Semiconductor device

Abstract

This semiconductor device comprises: a semiconductor chip having a main surface facing one side in a thickness direction, and a main surface electrode disposed on the main surface; a lead (conducting object) that is separated from the semiconductor chip and conductive with the main surface electrode; a plate-shaped conduction member including a joined part joined to the main surface electrode, a joined part joined to the lead (conducting object), and a suspension part connecting the joined part and the other joined part; a conductive joining layer joining the joined part and the main surface electrode; and a sealing resin covering the semiconductor chip, a portion of the lead (conducting object), the plate-shaped conduction member, and the joining layer. The plate-shaped conduction member includes an eaves part different from the suspension part. The eaves part does not contact the joining layer, and overlaps the outer periphery of the semiconductor chip as viewed in the thickness direction.

Description

Semiconductor Devices

[0001] The present disclosure relates to semiconductor devices.

[0002] Conventionally, semiconductor devices in which a semiconductor element such as a diode or transistor is covered with a resin package are known (see, for example, Patent Document 1). The semiconductor device (semiconductor device) described in Patent Document 1 includes a semiconductor element, a lead frame, bonding wires, and a resin package. The lead frame includes multiple leads, one of which includes a die bonding pad. The semiconductor element is mounted on the die bonding pad. Another of the multiple leads is electrically connected to the semiconductor element via a bonding wire. The resin package covers the semiconductor element and the bonding wires and also covers a portion of each of the multiple leads. The portion of each lead exposed from the resin package is a terminal of the semiconductor device. Such semiconductor devices are installed in electronic devices, automobiles, etc.

[0003] JP 2011-82523 A

[0004] 2. Description of the Related Art In recent years, with growing awareness of energy conservation and power saving, there has been an increasing demand for semiconductor devices that can minimize wasted power consumption.

[0005] An object of the present disclosure is to provide an improved semiconductor device compared to conventional semiconductor devices. In particular, in view of the above circumstances, an object of the present disclosure is to provide a semiconductor device that reduces power consumption.

[0006] A semiconductor device according to one aspect of the present disclosure includes a semiconductor chip having a main surface facing one side in a thickness direction and a first main surface electrode disposed on the main surface, a conduction target spaced from the semiconductor chip and electrically connected to the first main surface electrode, a plate-shaped conductive member including a first bonding portion bonded to the first main surface electrode, a second bonding portion bonded to the conduction target, and a suspension portion connecting the first bonding portion and the second bonding portion, a conductive bond joining the first bonding portion and the first main surface electrode, and a sealing resin covering the semiconductor chip, a portion of the conduction target, the plate-shaped conductive member, and the bonding layer. The plate-shaped conductive member includes a canopy portion different from the suspension portion. The canopy portion is not in contact with the bonding layer and overlaps the outer periphery of the semiconductor chip when viewed in the thickness direction.

[0007] According to the above configuration, it is possible to reduce power consumption.

[0008] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment. FIG. 2 is a plan view showing the semiconductor device according to the first embodiment. FIG. 3 is a view showing the sealing resin in the plan view of FIG. 2, with the sealing resin indicated by imaginary lines. FIG. 4 is a partially enlarged view of a portion of FIG. 3. FIG. 5 is a bottom view showing the semiconductor device according to the first embodiment. FIG. 6 is a front view showing the semiconductor device according to the first embodiment. FIG. 7 is a side view (right side view) showing the semiconductor device according to the first embodiment. FIG. 8 is a view showing the sealing resin in the side view of FIG. 7, with the sealing resin indicated by imaginary lines. FIG. 9 is a cross-sectional view taken along line IX-IX of FIG. 3. FIG. 10 is a partially enlarged view of a portion of FIG. 9. FIG. 11 is a partially enlarged view of a portion of FIG. 9. FIG. 12 is a partially enlarged view of a portion of FIG. 9. FIG. 13 is a cross-sectional view taken along line XIII-XIII of FIG. 3. FIG. 14 is a partially enlarged view of a portion of FIG. 13. FIG. 15 is a cross-sectional view taken along line XV-XV of FIG. 3. FIG. 16 is a partially enlarged view of a portion of FIG. 15 . FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 3 . FIG. 18 is a partially enlarged view of a portion of FIG. 17 . FIG. 19 is a diagram showing an example of a circuit configuration of a semiconductor device according to the first embodiment. FIG. 20 is a plan view showing a semiconductor device according to a first modified example of the first embodiment, with the sealing resin indicated by imaginary lines. FIG. 21 is a diagram showing an example of a circuit configuration of a semiconductor device according to a first modified example of the first embodiment. FIG. 22 is a plan view showing a semiconductor device according to a second modified example of the first embodiment, with the sealing resin indicated by imaginary lines. FIG. 23 is a diagram showing an example of a circuit configuration of a semiconductor device according to a second modified example of the first embodiment. FIG. 24 is a plan view showing a semiconductor device according to a third modified example of the first embodiment, with the sealing resin indicated by imaginary lines. FIG. 25 is a diagram showing an example of a circuit configuration of a semiconductor device according to a third modified example of the first embodiment. FIG. 26 is an enlarged plan view of a main portion of a semiconductor device according to the second embodiment. FIG. 27 is an enlarged cross-sectional view of a main portion of a semiconductor device according to the second embodiment. Fig. 28 is an enlarged cross-sectional view of a main part of a semiconductor device according to a second embodiment, Fig. 29 is an enlarged cross-sectional view of a main part of a semiconductor device according to a modification of the second embodiment, and Fig. 30 is a cross-sectional view of a semiconductor device according to a third embodiment.Fig. 31 is an enlarged cross-sectional view of a main portion of a semiconductor device according to a third embodiment. Fig. 32 is an enlarged cross-sectional view of a main portion of a semiconductor device according to the third embodiment. Fig. 33 is an enlarged plan view of a main portion of a semiconductor device according to a fourth embodiment. Fig. 34 is an enlarged plan view of a main portion of a semiconductor device according to a first modified example of the fourth embodiment. Fig. 35 is an enlarged plan view of a main portion of a semiconductor device according to a second modified example of the fourth embodiment. Fig. 36 is an enlarged plan view of a main portion of a semiconductor device according to a fifth embodiment. Fig. 37 is a plan view of a semiconductor device according to a sixth embodiment, in which a sealing resin is indicated by imaginary lines.

[0009] Preferred embodiments of the semiconductor device of the present disclosure will be described below with reference to the drawings. Hereinafter, identical or similar components will be designated by the same reference numerals, and redundant explanations will be omitted. Terms such as "first," "second," etc., used in this disclosure are merely used as labels and are not necessarily intended to assign any order to their objects.

[0010] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an) object B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an) object B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on (an) object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an) object B" includes "a certain object A is in contact with a certain object B and is located on (an) object B" and "a certain object A is located on (an) object B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, "when viewed from a certain direction, an object A overlaps an object B" includes "an object A overlaps the entire object B" and "an object A overlaps a part of an object B." Furthermore, "an object A (is made of) a certain material C" includes "an object A (is made of) a certain material C" and "an object A (is made of) a certain material C as its main component."

[0011] 1 to 19 show a semiconductor device A10 according to a first embodiment. The semiconductor device A10 includes two die pads 10A, 10B, a plurality of terminal leads 13, two semiconductor chips 21, 22, two plate-shaped conductive members 31, 32, a plurality of connecting members 41A, 41B, 42A, 42B, and a sealing resin 50. In the illustrated example, the plurality of terminal leads 13 includes a plurality of leads 14, 15, 16, 171, 172, 181, and 182.

[0012] For ease of explanation, the thickness direction of the semiconductor device A10 will be referred to as the "thickness direction z." In the following explanation, one side of the thickness direction z may be referred to as the upper side, and the other side as the lower side. Note that terms such as "upper," "lower," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component, etc. in the thickness direction z, and do not necessarily define the relationship with the direction of gravity. Furthermore, "plan view" refers to the view in the thickness direction z. An example of a direction perpendicular to the thickness direction z is referred to as the "first direction x." The direction perpendicular to the thickness direction z and the first direction x is referred to as the "second direction y."

[0013] The semiconductor device A10 converts a DC power supply voltage applied between two leads 14 and 15 of a plurality of terminal leads 13 into an AC voltage using two semiconductor chips 21 and 22. The converted AC voltage is input to a power supply target such as a motor from lead 16 of the plurality of terminal leads 13. The semiconductor device A10 is used in a power conversion circuit such as an inverter.

[0014] As shown in FIGS. 3 and 9 , the two die pads 10A, 10B are spaced apart from each other in the first direction x. The two die pads 10A, 10B, together with the plurality of terminal leads 13, are configured from the same lead frame. The lead frame is made of copper (Cu) or a copper alloy. Therefore, the two die pads 10A, 10B and the plurality of terminal leads 13 each contain copper. Note that the two die pads 10A, 10B and the plurality of terminal leads 13 may each contain another metal other than copper. Each of the two die pads 10A, 10B is, for example, rectangular in plan view.

[0015] As shown in FIG. 9 , the two die pads 10A and 10B each have a main surface 101 and a back surface 102. The main surface 101 and the back surface 102 described below are common to the two die pads 10A and 10B unless otherwise specified. The main surface 101 faces the thickness direction z (upward). The main surface 101 is covered with a sealing resin 50. A semiconductor chip 21 is mounted on the main surface 101 of the die pad 10A. The back surface 102 of the die pad 10A faces the opposite side in the thickness direction z from the side on which the semiconductor chip 21 is located. A semiconductor chip 22 is mounted on the main surface 101 of the die pad 10B. The back surface 102 of the die pad 10B faces the opposite side in the thickness direction z from the side on which the semiconductor chip 22 is located. The back surface 102 is exposed from the sealing resin 50. The back surface 102 is plated with, for example, tin (Sn).

[0016] As shown in FIGS. 3 , 5 to 9 , 13 , 15 , and 17 , the sealing resin 50 covers the two semiconductor chips 21 and 22, the two plate-shaped conductive members 31 and 32, and a portion of each of the two die pads 10A and 10B. The sealing resin 50 also covers a portion of each of the multiple terminal leads 13. The sealing resin 50 has electrical insulation properties. The sealing resin 50 includes, for example, a black epoxy resin. As shown in FIG. 2 , the dimension L1 of the sealing resin 50 in the first direction x is longer than the dimension L2 of the sealing resin 50 in the second direction y. The sealing resin 50 has a resin main surface 51, a resin back surface 52, multiple side surfaces 53, 54, and 55, multiple recesses 56, a groove 57, and multiple recesses 581 and 582.

[0017] 9, the resin main surface 51 faces the same side as the main surfaces 101 of the two die pads 10A and 10B in the thickness direction z. As shown in FIGS. 9, 13, and 17, the resin back surface 52 faces the opposite side to the resin main surface 51 in the thickness direction z. As shown in FIG. 5, the back surfaces 102 of the two die pads 10A and 10B are exposed from the resin back surface 52.

[0018] 2 , 5 , and 6 , the pair of side surfaces 53 are spaced apart from each other in the first direction x. The pair of side surfaces 53 face the first direction x and extend in the second direction y. The pair of side surfaces 53 are connected to the resin main surface 51 and the resin back surface 52.

[0019] 2, 5, and 7, the two side surfaces 54, 55 are spaced apart from each other in the second direction y. The two side surfaces 54, 55 face opposite each other in the second direction y and extend in the first direction x. The two side surfaces 54, 55 are connected to the resin main surface 51 and the resin back surface 52. As shown in FIG. 6, a plurality of terminal leads 13 are exposed from the side surfaces 55.

[0020] 2, 5, and 6, the recesses 56 are recessed from the side surface 55 in the second direction y, and extend in the thickness direction z from the resin main surface 51 to the resin rear surface 52. In the first direction x, the recesses 56 are located individually between the lead 182 and the lead 16, between the lead 16 and the lead 14, between the lead 14 and the lead 15, and between the lead 15 and the lead 181.

[0021] 5 , 6 , 9 , and 15 , the groove 57 is recessed from the resin rear surface 52 in the thickness direction z and extends along the second direction y. Both sides of the groove 57 in the second direction y are connected to the two side surfaces 54, 55, respectively. When viewed in the thickness direction z, the groove 57 separates the rear surface 102 of the die pad 10A from the rear surface 102 of the die pad 10B.

[0022] As shown in FIGS. 6 , 7 , 9 , 13 , 15 , and 17 , each of the multiple recesses 581, 582 is recessed from the resin main surface 51 in the thickness direction z. The planar shape of each of the multiple recesses 581, 582 is not particularly limited, but is circular in the illustrated example. Each of the multiple recesses 581 overlaps the die pad 10A in the planar view. In the illustrated example, the multiple recesses 581 are individually located near the four corners of the die pad 10A in the planar view. Each of the multiple recesses 582 overlaps the die pad 10B in the planar view. In the illustrated example, the multiple recesses 582 are individually located near the four corners of the die pad 10B in the planar view. As shown in FIG. 3 , each of the multiple recesses 581, 582 does not overlap either of the two plate-shaped conductive members 31, 32 in the planar view. Furthermore, as shown in FIG. 3 , each of the multiple recesses 581 and 582 does not overlap any of the multiple connection members 41A, 41B, 42A, and 42B in a plan view. The multiple recesses 581 are formed by pins for fixing the die pad 10A during the manufacture of the semiconductor device A10. The pins are pressed against the die pad 10A to fix the die pad 10A before the sealing resin 50 is formed. In this state, the formation of the sealing resin 50 begins. The pins are then pulled out before the formation of the sealing resin 50 is completed. As a result, the sealing resin 50 is formed in at least a portion of the area where the pins were located, so that the main surface 101 of the die pad 10A is covered with the sealing resin 50. The multiple recesses 581 are marks formed during the molding process of the sealing resin 50. Similarly, the multiple recesses 582 are formed by pins for fixing the die pad 10B during the manufacture of the semiconductor device A10. The recesses 582 are marks formed during the molding process of the sealing resin 50 .

[0023] As shown in FIGS. 3 and 5 , the two die pads 10A, 10B each have a plurality of end faces 111 to 114. The plurality of end faces 111 to 114 are covered with the sealing resin 50. The end face 111 faces in the first direction x and extends in the second direction y. The end face 111 is located closest to a pair of side faces 53 of the sealing resin 50. The end face 112 faces in the second direction y and extends in the first direction x. The end face 112 is located closest to the side face 54 of the sealing resin 50. The end face 113 faces in the opposite direction to the end face 112 in the second direction y and extends in the first direction x. The end face 113 is located closest to the side face 55 of the sealing resin 50. The end face 114 faces in the opposite direction to the end face 111 in the first direction x and extends in the second direction y. As shown in FIG. 9, a groove 57 is located between the end surface 114 of the die pad 10A and the end surface 114 of the die pad 10B.

[0024] As shown in FIGS. 5 and 8, the distance P2 between the end face 113 and the side face 55 is longer than the distance P1 between the end face 112 and the side face 54.

[0025] As shown in FIGS. 3 , 5 , and 8 , the two die pads 10A and 10B each have a corner end face 121. The corner end face 121 is located between the two end faces 111 and 112 and at a corner of one of the two die pads 10A and 10B. The corner end face 121 is covered with the sealing resin 50 and is a flat surface inclined with respect to the two end faces 111 and 112. Either the inclination angle of the corner end face 121 with respect to the end face 111 or the inclination angle of the corner end face 121 with respect to the end face 112 is, for example, between 60° and 85°. One of the multiple recesses 581 is located near the corner end face 121 of the die pad 10A in a plan view, and one of the multiple recesses 582 is located near the corner end face 121 of the die pad 10B in a plan view.

[0026] Furthermore, the longest normal to the corner end face 121 is set as follows: The longest normal is the maximum value of the normal to the corner end face 121 from the corner end face 121 of either of the two die pads 10A, 10B to the side face 53 of the pair of side faces 53 of the sealing resin 50 that is located closest to the corner end face 121. The longest normal is 1.0 to 1.5 times the length of the intersection line between the corner end face 121 and an imaginary plane having the first direction x and the second direction y as in-plane directions.

[0027] As shown in FIGS. 3 , 5 , and 8 , the two die pads 10A and 10B each have a corner end face 122. The corner end face 122 is located between the two end faces 111 and 113 and at a corner of one of the two die pads 10A and 10B. The corner end face 122 is covered with the sealing resin 50 and is a flat surface inclined with respect to the two end faces 111 and 113. Either the inclination angle of the corner end face 122 with respect to the end face 111 or the inclination angle of the corner end face 122 with respect to the end face 113 is, for example, between 60° and 85°. One of the multiple recesses 581 is located near the corner end face 122 of the die pad 10A in a plan view, and one of the multiple recesses 582 is located near the corner end face 122 of the die pad 10B in a plan view.

[0028] 3 and 5 , the two die pads 10A and 10B each have a corner end face 123. The corner end face 123 is located between the two end faces 112 and 114 and at a corner of one of the two die pads 10A and 10B. The corner end face 123 is covered with the sealing resin 50 and is a flat surface inclined with respect to the two end faces 112 and 114. Either the inclination angle of the corner end face 123 with respect to the end face 114 or the inclination angle of the corner end face 123 with respect to the end face 112 is, for example, between 60° and 85°. One of the multiple recesses 581 is located near the corner end face 123 of the die pad 10A in a plan view, and one of the multiple recesses 582 is located near the corner end face 123 of the die pad 10B in a plan view.

[0029] 3 and 5 , the two die pads 10A and 10B each have a corner end surface 124. The corner end surface 124 is located between the two end surfaces 113 and 114 and at a corner of one of the two die pads 10A and 10B. The corner end surface 124 is covered with the sealing resin 50 and is a flat surface inclined with respect to the two end surfaces 113 and 114. Either the inclination angle of the corner end surface 124 with respect to the end surface 114 or the inclination angle of the corner end surface 124 with respect to the end surface 113 is, for example, between 60° and 85°. One of the multiple recesses 581 is located near the corner end surface 124 of the die pad 10A in a plan view, and one of the multiple recesses 582 is located near the corner end surface 124 of the die pad 10B in a plan view.

[0030] 12 , the die pad 10B has a seating surface 103 and an upright surface 104. The seating surface 103 faces the same side as the main surface 101 in the thickness direction z, and is located between the main surface 101 and the back surface 102 in the thickness direction z. The seating surface 103 is connected to an end surface 114. The upright surface 104 faces a direction perpendicular to the thickness direction z, and is connected to the seating surface 103 and the main surface 101. The seating surface 103 and the upright surface 104 form a step in the die pad 10B.

[0031] Each of the two semiconductor chips 21 and 22 is, for example, a transistor. As shown in FIG. 19 , the transistor in the semiconductor device A10 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), but may also be a bipolar transistor or an IGBT (Insulated Gate Bipolar Transistor). The circuit in FIG. 19 also illustrates a parasitic diode component built into each of the two semiconductor chips 21 and 22. Each of the two semiconductor chips 21 and 22 is, for example, an n-channel type, but may also be a p-channel type. Each of the two semiconductor chips 21 and 22 includes a compound semiconductor substrate. The compound semiconductor substrate contains silicon (Si) or silicon carbide (SiC).

[0032] The semiconductor chip 21 is mounted on the die pad 10A as shown in Figures 3, 4, and 9. Preferably, the center of gravity of the semiconductor chip 21 overlaps the center of the die pad 10A in a plan view. The center of the die pad 10A is the center when the die pad 10A is divided into Nx (Nx is a positive odd number) parts in the first direction x, and is also a region corresponding to the center when the die pad 10A is divided into Ny (Ny is a positive odd number) parts in the second direction y. Nx and Ny are not limited to any particular value, but may be, for example, 3 or 5.

[0033] The semiconductor chip 21 has a main surface 21a and a back surface 21b. As shown in Figure 10, the main surface 21a and the back surface 21b are spaced apart from each other in the thickness direction z. The main surface 21a faces the same direction as the main surface 101 of the die pad 10A. The back surface 21b faces the opposite side to the main surface 21a in the thickness direction z and faces the main surface 101 of the die pad 10A.

[0034] As shown in Figures 3 and 4, the semiconductor chip 21 is rectangular in plan view. Therefore, an outer periphery 219 (see Figure 4) of the semiconductor chip 21 in plan view is rectangular. The outer periphery 219 has a pair of edges 219a and a pair of edges 219b. As shown in Figure 4, the pair of edges 219a are spaced apart in the second direction y and extend in the first direction x in plan view. The pair of edges 219a are parallel to each other. The pair of edges 219b are spaced apart in the first direction x and extend in the second direction y in plan view. The pair of edges 219b are parallel to each other.

[0035] The semiconductor chip 21 is mounted on the die pad 10A as shown in Figures 3, 4 and 9. The semiconductor chip 21 has a plurality of main surface electrodes 211, 212, 214 and a back surface electrode 213 as shown in Figures 4 and 10.

[0036] The principal surface electrode 211 is disposed on the principal surface 21a. A current corresponding to the power converted by the semiconductor chip 21 flows through the principal surface electrode 211. In an example in which the semiconductor chip 21 is a MOSFET, the principal surface electrode 211 is, for example, a source electrode. The principal surface electrode 211 includes multiple metal plating layers. The principal surface electrode 211 includes a nickel (Ni) plating layer and a gold (Au) plating layer laminated on the nickel plating layer. Alternatively, the principal surface electrode 211 may include a nickel plating layer, a palladium (Pd) plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer.

[0037] The main surface electrode 212 is disposed on the main surface 21a. A drive signal (gate voltage) for driving the semiconductor chip 21 is applied to the main surface electrode 212. In an example in which the semiconductor chip 21 is a MOSFET, the main surface electrode 212 is, for example, a gate electrode. In a plan view, the area of ​​the main surface electrode 212 is smaller than the area of ​​the main surface electrode 211. The main surface electrode 212 is located closer to the end surface 111 of the die pad 10A than the main surface electrode 211 in the first direction x.

[0038] Each of the pair of principal surface electrodes 214 is disposed on the principal surface 21a. Each of the pair of principal surface electrodes 214 has the same potential as the principal surface electrode 211. In an example in which the semiconductor chip 21 is a MOSFET, each of the pair of principal surface electrodes 214 is a source sense electrode. As shown in FIG. 4 , the pair of principal surface electrodes 214 are disposed on both sides of the principal surface electrode 212 in the second direction y in a plan view. In a plan view, the area of ​​the principal surface electrode 214 is smaller than the area of ​​the principal surface electrode 211. Each of the pair of principal surface electrodes 214 is located closer to the end surface 111 of the die pad 10A than the principal surface electrode 211 in the first direction x. Note that the semiconductor chip 21 may have only one of the pair of principal surface electrodes 214, or may have neither of the pair of principal surface electrodes 214.

[0039] The back surface electrode 213 is disposed on the back surface 21b. The back surface electrode 213 is provided opposite to the main surface 101 of the die pad 10A. A current corresponding to the power before being converted by the semiconductor chip 21 flows through the back surface electrode 213. In an example in which the semiconductor chip 21 is a MOSFET, the back surface electrode 213 is, for example, a drain electrode.

[0040] 3, 4, and 9, the semiconductor chip 22 is mounted on the main surface 101 of the die pad 10B. Preferably, in a plan view, the center of gravity of the semiconductor chip 22 overlaps with the center of the die pad 10B. The center of the die pad 10B is the center when the die pad 10B is divided into Lx (Lx is a positive odd number) in the first direction x, and is a region corresponding to the center when the die pad 10B is divided into Ly (Ly is a positive odd number) in the second direction y. Lx and Ly are not limited to any particular value, but may be, for example, 3 or 5.

[0041] The semiconductor chip 22 has a main surface 22a and a back surface 22b. As shown in Figure 11, the main surface 22a and the back surface 22b are spaced apart from each other in the thickness direction z. The main surface 22a faces the same direction as the main surface 101 of the die pad 10B. The back surface 22b faces the opposite side to the main surface 22a in the thickness direction z and faces the main surface 101 of the die pad 10B.

[0042] 3 and 4, the semiconductor chip 22 is rectangular in plan view. Therefore, an outer periphery 229 (see FIG. 4) of the semiconductor chip 22 in plan view is rectangular. The outer periphery 229 has a pair of edges 229a and a pair of edges 229b. As shown in FIG. 4, the pair of edges 229a are spaced apart in the second direction y and extend in the first direction x in plan view. The pair of edges 229a are parallel to each other. The pair of edges 229b are spaced apart in the first direction x and extend in the second direction y in plan view. The pair of edges 229b are parallel to each other.

[0043] The semiconductor chip 22 is mounted on the die pad 10B as shown in Figures 3, 4 and 9. The semiconductor chip 22 has a plurality of main surface electrodes 221, 222, 224 and a back surface electrode 223 as shown in Figures 4 and 11.

[0044] The principal surface electrode 221 is disposed on the principal surface 22a. A current corresponding to the power converted by the semiconductor chip 22 flows through the principal surface electrode 221. In an example in which the semiconductor chip 22 is a MOSFET, the principal surface electrode 221 is, for example, a source electrode. Like the principal surface electrode 211, the principal surface electrode 221 includes multiple metal plating layers. The principal surface electrode 221 includes a nickel (Ni) plating layer and a gold (Au) plating layer laminated on the nickel plating layer. Alternatively, the principal surface electrode 221 may include a nickel plating layer, a palladium (Pd) plating layer laminated on the nickel plating layer, and a gold plating layer laminated on the palladium plating layer.

[0045] The main surface electrode 222 is disposed on the main surface 22 a. A drive signal (gate voltage) for driving the semiconductor chip 22 is applied to the main surface electrode 222. In an example in which the semiconductor chip 22 is a MOSFET, the main surface electrode 222 is, for example, a gate electrode. In a plan view, the area of ​​the main surface electrode 222 is smaller than the area of ​​the main surface electrode 221. The main surface electrode 222 is located closer to the end surface 111 of the die pad 10B than the main surface electrode 221 in the first direction x.

[0046] Each of the pair of principal surface electrodes 224 is disposed on the principal surface 22a. Each of the pair of principal surface electrodes 224 has the same potential as the principal surface electrode 211. In an example in which the semiconductor chip 22 is a MOSFET, each of the pair of principal surface electrodes 224 is a source sense electrode. As shown in FIG. 4 , the pair of principal surface electrodes 224 are disposed on both sides of the principal surface electrode 222 in the second direction y in plan view. In plan view, the area of ​​the principal surface electrode 224 is smaller than the area of ​​the principal surface electrode 221. Each of the pair of principal surface electrodes 224 is located closer to the end surface 111 of the die pad 10B than the principal surface electrode 221 in the first direction x. Note that the semiconductor chip 22 may have only one of the pair of principal surface electrodes 224, or may have neither of the pair of principal surface electrodes 224.

[0047] The back surface electrode 223 is disposed on the back surface 22b. The back surface electrode 223 is provided opposite to the main surface 101 of the die pad 10B. A current corresponding to the power before being converted by the semiconductor chip 22 flows through the back surface electrode 223. In an example in which the semiconductor chip 22 is a MOSFET, the back surface electrode 223 is, for example, a drain electrode.

[0048] The semiconductor device A10 further includes two die bonding layers 231 and 232. Each of the two die bonding layers 231 and 232 is electrically conductive. Each of the die bonding layers 231 and 232 is made of, for example, solder. Alternatively, each of the die bonding layers 231 and 232 may be made of sintered metal.

[0049] 9, 10, and 13, the die bonding layer 231 is interposed between the main surface 101 of the die pad 10A and the back electrode 213 of the semiconductor chip 21. The die bonding layer 231 joins the main surface 101 of the die pad 10A and the back electrode 213 of the semiconductor chip 21. This establishes electrical continuity between the back electrode 213 of the semiconductor chip 21 and the die pad 10A.

[0050] 9, 11, and 17, the die bonding layer 232 is interposed between the main surface 101 of the die pad 10B and the back surface electrode 223 of the semiconductor chip 22. The die bonding layer 232 joins the main surface 101 of the die pad 10B and the back surface electrode 223 of the semiconductor chip 22. This establishes electrical conduction between the back surface electrode 223 of the semiconductor chip 22 and the die pad 10B.

[0051] 3 , the multiple terminal leads 13 are located on the side opposite to the side where the end face 112 faces the two die pads 10A, 10B in the second direction y. At least one of the multiple terminal leads 13 is electrically connected to one of the two semiconductor chips 21, 22. The multiple terminal leads 13 are arranged along the first direction x. As described above, the multiple terminal leads 13 include the multiple leads 14, 15, 16, 171, 172, 181, and 182.

[0052] As shown in FIG. 3 , the lead 14 is located away from the two die pads 10A, 10B in the second direction y and between the leads 15 and 16 in the first direction x. The lead 14 extends along the second direction y. The lead 14 is electrically connected to a main surface electrode 221 of the semiconductor chip 22. The lead 14 is an N terminal (negative electrode) to which a DC power supply voltage to be converted is applied. The lead 14 includes a covering portion 14A and an exposed portion 14B. As shown in FIGS. 3 and 15 , the covering portion 14A is covered with a sealing resin 50. As shown in FIGS. 2 , 3 , 5 , and 6 , the exposed portion 14B is connected to the covering portion 14A and exposed from a side surface 55 of the sealing resin 50. The exposed portion 14B extends away from the two die pads 10A, 10B in the second direction y. The surface of the exposed portion 14B is, for example, tin-plated.

[0053] 16 , the covering portion 14A of the lead 14 has a seating surface 14C and an upstanding surface 14D. The seating surface 14C faces the same side as the main surfaces 101 of the two die pads 10A and 10B in the thickness direction z, and is located lower in the thickness direction z than the upper surface of the covering portion 14A (the surface facing upward in the thickness direction z). The upstanding surface 14D faces in a direction perpendicular to the thickness direction z, and is connected to the seating surface 14C and the upper surface of the covering portion 14A. The seating surface 14C and the upstanding surface 14D form a step in the covering portion 14A of the lead 14.

[0054] As shown in FIG. 3 , the lead 15 includes a portion extending in the second direction y and is connected to the die pad 10A. Therefore, the lead 15 is electrically connected to the back electrode 213 of the semiconductor chip 21 via the die pad 10A. The lead 15 is a P terminal (positive electrode) to which a DC power supply voltage to be converted is applied. The lead 15 includes a covering portion 15A and an exposed portion 15B. As shown in FIGS. 3 and 13 , the covering portion 15A is connected to the end surface 113 of the die pad 10A and is covered with the sealing resin 50. When viewed in the first direction x, the covering portion 15A is bent. As shown in FIGS. 2 , 3 , 5 , and 6 , the exposed portion 15B is connected to the covering portion 15A and exposed from the side surface 55 of the sealing resin 50. The exposed portion 15B extends away from the die pad 10A in the second direction y. The surface of the exposed portion 15B is, for example, tin-plated.

[0055] As shown in FIG. 3 , the lead 16 includes a portion extending in the second direction y and is connected to the die pad 10B. Therefore, the lead 16 is electrically connected to the back electrode 223 of the semiconductor chip 22 via the die pad 10B. AC power converted by the two semiconductor chips 21 and 22 is output from the lead 16. The lead 16 includes a covering portion 16A and an exposed portion 16B. As shown in FIGS. 3 and 17 , the covering portion 16A is connected to the end surface 113 of the die pad 10B and is covered with the sealing resin 50. When viewed in the first direction x, the covering portion 16A is bent in the same manner as the covering portion 15A of the lead 15. As shown in FIGS. 2 , 3 , 5 , and 6 , the exposed portion 16B is connected to the covering portion 16A and exposed from the side surface 55 of the sealing resin 50. The exposed portion 16B extends away from the die pad 10B in the second direction y. The surface of the exposed portion 16B is plated with, for example, tin.

[0056] As shown in FIG. 3 , the lead 171 is located away from the die pad 10A in the second direction y and is located on one side of the lead 15 in the first direction x. As shown in FIG. 3 , the lead 172 is located away from the die pad 10B in the second direction y and is located on the other side of the lead 16 in the first direction x. The lead 171 is electrically connected to a main surface electrode 212 (gate electrode) of the semiconductor chip 21. A drive signal (gate voltage) for driving the semiconductor chip 21 is applied to the lead 171. The lead 172 is electrically connected to a main surface electrode 222 (gate electrode) of the semiconductor chip 22. A drive signal (gate voltage) for driving the semiconductor chip 22 is applied to the lead 172.

[0057] As shown in Fig. 3, the lead 171 includes a covering portion 171A and an exposed portion 171B. As shown in Fig. 3, the covering portion 171A is covered with the sealing resin 50. As shown in Figs. 2, 3, 5, and 6, the exposed portion 171B is connected to the covering portion 171A and is exposed from a side surface 55 of the sealing resin 50. The exposed portion 171B extends in the second direction y away from the die pad 10A. The surface of the exposed portion 171B is plated with, for example, tin.

[0058] As shown in Fig. 3, the lead 172 includes a covering portion 172A and an exposed portion 172B. As shown in Fig. 3, the covering portion 172A is covered with the sealing resin 50. As shown in Figs. 2, 3, 5, and 6, the exposed portion 172B is connected to the covering portion 172A and exposed from the sealing resin 50. The exposed portion 172B extends in the second direction y away from the die pad 10B. The surface of the exposed portion 172B is plated with, for example, tin.

[0059] As shown in FIG. 3 , the lead 181 is located away from the die pad 10A in the second direction y and is located between the leads 15 and 171 in the first direction x. As shown in FIG. 3 , the lead 182 is located away from the die pad 10B in the second direction y and is located between the leads 16 and 172 in the first direction x. The lead 181 is electrically connected to the main surface electrode 214 (source sense electrode) of the semiconductor chip 21. A voltage corresponding to the current flowing through the main surface electrode 211 (source electrode) of the semiconductor chip 21 is applied to the lead 181. The lead 182 is electrically connected to the main surface electrode 224 (source sense electrode) of the semiconductor chip 22. A voltage corresponding to the current flowing through the main surface electrode 221 (source electrode) of the semiconductor chip 22 is applied to the lead 182.

[0060] As shown in Fig. 3, the lead 181 includes a covering portion 181A and an exposed portion 181B. As shown in Fig. 3, the covering portion 181A is covered with the sealing resin 50. As shown in Figs. 2, 3, 5, and 6, the exposed portion 181B is connected to the covering portion 181A and is exposed from a side surface 55 of the sealing resin 50. The exposed portion 181B extends in the second direction y away from the die pad 10A. The surface of the exposed portion 181B is plated with, for example, tin.

[0061] As shown in Fig. 3, the lead 182 includes a covering portion 182A and an exposed portion 182B. As shown in Fig. 3, the covering portion 182A is covered with the sealing resin 50. As shown in Figs. 2, 3, 5, and 6, the exposed portion 182B is connected to the covering portion 182A and is exposed from the side surface 55 of the sealing resin 50. The exposed portion 182B extends in the second direction y away from the die pad 10B. The surface of the exposed portion 182B is plated with, for example, tin.

[0062] 6, in the semiconductor device A10, the heights h of the exposed portions 14B of the leads 14, 15B of the leads 15, and 16B of the leads 16 are all the same (or approximately the same). Furthermore, the thicknesses of these portions are all the same (or approximately the same). Therefore, when viewed in the first direction x, at least a portion of the lead 14 (exposed portion 14B) overlaps with each of the leads 15 and 16 (see FIG. 7).

[0063] As shown in Figures 3 and 4, the plate-shaped conductive member 31 is bonded to the principal surface electrode 211 of the semiconductor chip 21 and the die pad 10B. This electrically connects the principal surface electrode 211 to the die pad 10B and the back surface electrode 223 of the semiconductor chip 22. The plate-shaped conductive member 31 contains copper. The plate-shaped conductive member 31 may contain metals other than copper. In the semiconductor device A10, the plate-shaped conductive member 31 is a metal clip. In this embodiment, the plate-shaped conductive member 31 is formed by subjecting a metal plate of uniform thickness to processes such as cutting and bending. The plate-shaped conductive member 31 includes a suspension portion 311, two bonding portions 312 and 313, and a canopy portion 314.

[0064] The suspension portion 311 forms a main portion of the plate-shaped conductive member 31. As shown in FIG. 3 , the suspension portion 311 is connected to each of the two bonding portions 312, 313 and connects them. The suspension portion 311 extends in the first direction x. In the illustrated example, the suspension portion 311 extends linearly between the two semiconductor chips 21, 22 in a plan view. As shown in FIGS. 4 and 9 , the suspension portion 311 straddles the two die pads 10A, 10B. In the illustrated example, the end of the suspension portion 311 connected to the bonding portion 312 is bifurcated. As shown in FIG. 4 , in a plan view, the suspension portion 311 intersects one of a pair of edges 219b of the semiconductor chip 21 (the edge 219b closer to the semiconductor chip 22).

[0065] As shown in Figures 3, 4, 9, 10, 13, and 14, the bonding portion 312 is bonded to the main surface electrode 211 of the semiconductor chip 21. In the illustrated example, the bonding portion 312 includes two strip-shaped portions 312a. As shown in Figures 3, 4, 13, and 14, the two strip-shaped portions 312a are spaced apart from each other in the second direction y. The longitudinal direction of each of the two strip-shaped portions 312a is the first direction x. The two strip-shaped portions 312a are arranged parallel to each other in a plan view. In the illustrated example, the end of the suspension portion 311 connected to the bonding portion 312 is bifurcated and each bifurcated is connected to a corresponding one of the two strip-shaped portions 312a. Unlike this example, the end of the suspension portion 311 connected to the joint portion 312 may not be bifurcated, and the joint portion 312 may be a single rectangular portion (a configuration in which two strip-shaped portions 312a are connected). The area of ​​the joint portion 312 in a plan view (the total area of ​​the two strip-shaped portions 312a) is, for example, 10% to 100% of the area of ​​the principal surface electrode 211 in a plan view.

[0066] 3 and 12, the bonding portion 313 is bonded to the seating surface 103 of the die pad 10B. As shown in Fig. 3, the bonding portion 313 extends in the second direction y. As shown in Fig. 12, at least a portion of the bonding portion 313 is contained in an area defined by the seating surface 103 and the standing surface 104 of the die pad 10B. The bonding portion 313 is connected to the suspension portion 311. The bonding portion 313 is located on the opposite side of the suspension portion 311 from the bonding portion 312.

[0067] As shown in Figures 4, 9, 10, 13, and 14, the semiconductor device A10 further includes a bonding layer 33. The bonding layer 33 is interposed between the main surface electrode 211 of the semiconductor chip 21 and the two strip-shaped portions 312a of the bonding portion 312. The bonding layer 33 bonds the main surface electrode 211 to the bonding portion 312 (the two strip-shaped portions 312a). The bonding layer 33 is conductive. The bonding layer 33 is, for example, solder. Alternatively, the bonding layer 33 may be a sintered metal.

[0068] The thickness t31a (see FIG. 9) of the bonding portion 312 (each of the two strip-shaped portions 312a) is not limited in any way, but is, for example, 0.1 mm or more and not more than twice the maximum thickness T1max (see FIG. 10) of the bonding layer 33. The maximum thickness T1max of the bonding layer 33 is greater than the thickness of the semiconductor chip 21.

[0069] As shown in Figures 4, 9, and 12, the semiconductor device A10 further includes a bonding layer 34. The bonding layer 34 is interposed between the seating surface 103 of the die pad 10B and the bonding portion 313. The bonding layer 34 bonds the die pad 10B and the bonding portion 313. The bonding layer 34 is conductive. The bonding layer 34 is made of, for example, solder. Alternatively, the bonding layer 34 may be made of sintered metal.

[0070] The overhanging portion 314 is a different portion from the suspension portion 311 and is spaced apart from the suspension portion 311. The overhanging portion 314 is not in contact with the bonding layer 33. The overhanging portion 314 overlaps the outer periphery 219 of the semiconductor chip 21 in a plan view. In this embodiment, the overhanging portion 314 extends from the bonding portion 312. In a plan view, the overhanging portion 314 protrudes from the principal surface electrode 211. In this embodiment, as shown in FIGS. 4, 13, and 14, the overhanging portion 314 includes a pair of main body portions 314a and a pair of connecting portions 314b.

[0071] As shown in FIG. 4 , each of the pair of body portions 314a overlaps the outer periphery 219 of the semiconductor chip 21. The pair of body portions 314a are spaced apart in the second direction y. The pair of body portions 314a are arranged on opposite sides of the joint portion 312 in the second direction y. Each of the pair of body portions 314a has a strip shape extending in the first direction x. In the illustrated example, the pair of body portions 314a individually overlap the pair of edge portions 219a in a planar view. In this embodiment, as shown in FIG. 4 , the pair of body portions 314a overlap the entire pair of edge portions 219a in a planar view. Therefore, the pair of body portions 314a overlap the four corners of the semiconductor chip 21 in a planar view. Each of the body portions 314a does not contact any of the plurality of principal surface electrodes 211, 212, 214. In this embodiment, each main body portion 314a is spaced apart from the main surface 21a, and as shown in FIG. 14, a sealing resin 50 is interposed between each main body portion 314a and the main surface 21a in the thickness direction z.

[0072] As shown in FIGS. 4 and 14 , the pair of connecting portions 314b individually connect the joint portion 312 and the pair of main body portions 314a. Each of the pair of connecting portions 314b extends from the joint portion 312 in the second direction y. In this embodiment, one of the pair of connecting portions 314b connects to the one of the two strip-shaped portions 312a that is located furthest in the second direction y, and the other of the pair of connecting portions 314b connects to the one of the two strip-shaped portions 312a that is located furthest in the other direction y. As shown in FIG. 4 , in a plan view, the dimension of the pair of connecting portions 314b along the first direction x is smaller than the dimension of the pair of main body portions 314a along the first direction x. With this configuration, in a plan view, the multiple principal surface electrodes 212, 214 are exposed from the plate-shaped conductive member 31. Each of the connecting portions 314b is spaced apart from the main surface 21a, and as shown in FIG. 14, the sealing resin 50 is interposed between each of the connecting portions 314b and each of the main surfaces 21a in the thickness direction z.

[0073] In this embodiment, the thickness t31c (see FIG. 14 ) of the eave portion 314 (each of the pair of main body portions 314a and each of the pair of connecting portions 314b) and the thickness t31b (see FIGS. 9 and 10 ) of the joint portion 312 are the same (or approximately the same). Furthermore, the thickness t31c of the eave portion 314 and the thickness t31a (see FIG. 9 ) of the suspension portion 311 are the same (or approximately the same). In the present disclosure, the thickness t31c of the eave portion 314 is the plate thickness of the eave portion 314 and is the dimension along the vertical direction of the eave portion 314 (corresponding to the thickness direction z in the illustrated example). Similarly, the thickness t31b of the joint portion 312 is the plate thickness of the joint portion 312 and is the dimension along the vertical direction of the joint portion 312 (corresponding to the thickness direction z in the illustrated example). The thickness t31a of the suspension portion 311 is the plate thickness of the suspension portion 311, and is the dimension of the suspension portion 311 along the vertical direction.

[0074] 14 , the position of each of the pair of main body portions 314a and the position of the joint portion 312 (each of the pair of strip-shaped portions 312a) in the thickness direction z are the same (or approximately the same). Therefore, in this embodiment, each of the pair of main body portions 314a and the joint portion 312 are not misaligned in the thickness direction z. In the present disclosure, the position of each of the pair of main body portions 314a in the thickness direction z and the position of the joint portion 312 (each of the pair of strip-shaped portions 312a) in the thickness direction z are each based on a surface facing downward in the thickness direction z.

[0075] As shown in FIGS. 3 and 4 , the plate-shaped conductive member 32 is bonded to the principal surface electrode 221 of the semiconductor chip 22 and the covering portion 14A of the lead 14. This establishes electrical continuity between the principal surface electrode 221 and the lead 14. The plate-shaped conductive member 32 contains copper. However, the plate-shaped conductive member 32 may contain metals other than copper. In the semiconductor device A10, the plate-shaped conductive member 32 is a metal clip. In this embodiment, the plate-shaped conductive member 32 is formed by subjecting a metal plate of uniform thickness to processes such as cutting and bending. The plate-shaped conductive member 32 includes a suspension portion 321, two joining portions 322 and 323, and a canopy portion 324.

[0076] The suspension portion 321 forms a main portion of the plate-shaped conductive member 32. As shown in FIGS. 3 and 4 , the suspension portion 321 is connected to each of the two joining portions 322, 323 and connects them. When viewed in the thickness direction z, the suspension portion 321 is bent in a hook shape. When viewed in the thickness direction z, the suspension portion 321 overlaps the main surface 101 of the die pad 10B. As shown in FIG. 4 , in a plan view, the suspension portion 321 intersects one of a pair of edges 229b of the semiconductor chip 22 (the edge 229b closer to the semiconductor chip 21).

[0077] As shown in FIG. 4 , the suspension portion 321 includes a plurality of extending portions 321a, 321c, and 321e. The extending portion 321a has a base end 321b. The base end 321b is an edge connected to the bonding portion 323. The extending portion 321a extends from the base end 321b in the second direction y. In this embodiment, a portion of the extending portion 321a (an end portion including the base end 321b) is bent in the thickness direction z. The extending portion 321c has a base end 321d. The base end 321d is an edge connected to the extending portion 321a. The extending portion 321c extends from the base end 321d in the first direction x. As shown in FIG. 4 , the extending portion 321c intersects with the end surface 114 of the die pad 10B in a plan view. With this configuration, the plate-shaped conductive member 32 does not overlap the corner end surface 124 of the die pad 10B in a plan view. The extending portion 321e has a base end 321f. The base end 321f is an edge connected to the extending portion 321e. The extending portion 321e extends from the base end 321f in the second direction y. In this embodiment, a portion of the extending portion 321e (the end opposite the base end 321f) is bent in the thickness direction z.

[0078] As shown in FIGS. 3 , 4 , 9 , 11 , 17 , and 18 , the bonding portion 322 is bonded to the main surface electrode 221 of the semiconductor chip 22. In the illustrated example, the bonding portion 322 includes two strip-shaped portions 322 a. As shown in FIGS. 4 , 17 , and 18 , the two strip-shaped portions 322 a are spaced apart from each other in the second direction y. The longitudinal direction of each of the two strip-shaped portions 322 a is the first direction x. The two strip-shaped portions 322 a are arranged parallel to each other in a plan view. In the illustrated example, the end of the suspension portion 321 connected to the bonding portion 322 is bifurcated and each is connected to a corresponding one of the two strip-shaped portions 322 a. Alternatively, the end of the suspension portion 321 connected to the bonding portion 322 may not be bifurcated, and the bonding portion 322 may be a single rectangular portion (a configuration in which two strip-shaped portions 322 a are connected). The area of ​​the joint portion 322 in plan view (the total area of ​​the two strip portions 322a) is, for example, 10% to 100% of the area of ​​the principal surface electrode 221 in plan view.

[0079] 3 , 15 , and 16 , the joint portion 323 is joined to the seating surface 14C of the lead 14. The joint portion 323 extends in the first direction x. At least a portion of the joint portion 323 is contained in an area defined by the seating surface 14C and the standing surface 14D of the lead 14. The joint portion 323 is connected to the suspension portion 321 (extension portion 321 a). The joint portion 323 is located on the opposite side of the joint portion 322 with the suspension portion 321 in between.

[0080] As shown in Figures 4, 9, 11, 17, and 18, the semiconductor device A10 further includes a bonding layer 35. The bonding layer 35 is interposed between the main surface electrode 221 of the semiconductor chip 22 and the two strip-shaped portions 322a of the bonding portion 322. The bonding layer 35 bonds the main surface electrode 221 of the semiconductor chip 22 to the bonding portion 322 (each of the two strip-shaped portions 322a). The bonding layer 35 is conductive. The bonding layer 35 is, for example, solder. Alternatively, the bonding layer 35 may be a sintered metal.

[0081] The thickness t32b (see FIG. 9) of the bonding portion 322 (each of the two strip-shaped portions 322a) is not limited in any way, but is, for example, 0.1 mm or more and not more than twice the maximum thickness T2max (see FIG. 11) of the bonding layer 35. The maximum thickness T2max of the bonding layer 35 is greater than the thickness of the semiconductor chip 22.

[0082] As shown in Figures 4, 15, and 16, the semiconductor device A10 further includes a bonding layer 36. The bonding layer 36 is interposed between the seating surface 14C of the lead 14 and the bonding portion 323. The bonding layer 36 bonds the coating portion 14A of the lead 14 to the bonding portion 323. The bonding layer 36 is conductive. The bonding layer 36 is, for example, solder. Alternatively, the bonding layer 36 may be a sintered metal.

[0083] The overhanging portion 324 is a different portion from the suspension portion 321 and is spaced apart from the suspension portion 321. The overhanging portion 324 is not in contact with the bonding layer 35. The overhanging portion 324 overlaps the outer periphery 229 of the semiconductor chip 22 in a plan view. In this embodiment, the overhanging portion 324 extends from the bonding portion 322. In a plan view, the overhanging portion 324 protrudes from the principal surface electrode 221. In this embodiment, the overhanging portion 324 includes a pair of main body portions 324a and a pair of connecting portions 324b, as shown in FIGS. 4, 17, and 18 .

[0084] As shown in FIG. 4 , each of the pair of body portions 324a overlaps the outer periphery 229 of the semiconductor chip 22. The pair of body portions 324a are spaced apart in the second direction y. The pair of body portions 324a are arranged on opposite sides of the joint portion 322 in the second direction y. Each of the pair of body portions 324a has a strip shape extending in the first direction x. In the illustrated example, the pair of body portions 324a individually overlap the pair of edge portions 229a in a planar view. In this embodiment, as shown in FIG. 4 , the pair of body portions 324a overlap the entire pair of edge portions 229a in a planar view. Therefore, the pair of body portions 324a overlap the four corners of the semiconductor chip 22 in a planar view. Each of the body portions 324a does not contact any of the plurality of principal surface electrodes 221, 222, 224. In this embodiment, each main body portion 324a is spaced apart from the main surface 22a, and as shown in FIG. 18, a sealing resin 50 is interposed between each main body portion 324a and the main surface 22a in the thickness direction z.

[0085] As shown in FIGS. 4 and 18 , the pair of connecting portions 324b individually connect the joint portion 322 and the pair of main body portions 324a. Each of the pair of connecting portions 324b extends from the joint portion 322 in the second direction y. In this embodiment, one of the pair of connecting portions 324b connects to the one of the two strip-shaped portions 322a that is located furthest in the second direction y, and the other of the pair of connecting portions 324b connects to the one of the two strip-shaped portions 322a that is located furthest in the other direction y. As shown in FIG. 4 , in a plan view, the dimension of the pair of connecting portions 324b along the first direction x is smaller than the dimension of the pair of main body portions 324a along the first direction x. With this configuration, in a plan view, the multiple principal surface electrodes 222, 224 are exposed from the plate-shaped conductive member 32. Each of the connecting portions 324b is spaced apart from the main surface 22a, and as shown in FIG. 18, the sealing resin 50 is interposed between each of the connecting portions 324b and each of the main surfaces 22a in the thickness direction z.

[0086] In the present embodiment, the thickness t32c (see FIG. 18 ) of the eave portion 324 (each of the pair of main body portions 324a and each of the pair of connecting portions 324b) and the thickness t32b (see FIGS. 9 and 11 ) of the joint portion 322 are the same (or approximately the same). Furthermore, the thickness t32c of the eave portion 324 and the thickness t32a (see FIG. 9 ) of the suspension portion 321 are the same (or approximately the same). In the present disclosure, the thickness t32c of the eave portion 324 is the plate thickness of the eave portion 324 and is the dimension along the direction perpendicular to the eave portion 324 (corresponding to the thickness direction z in the illustrated example). Similarly, the thickness t32b of the joint portion 322 is the plate thickness of the joint portion 322 and is the dimension along the direction perpendicular to the joint portion 322 (corresponding to the thickness direction z in the illustrated example). The thickness t32a of the suspension portion 321 is the plate thickness of the suspension portion 321 and is the dimension along the direction perpendicular to the suspension portion 321.

[0087] 18 , the position of each of the pair of main body portions 324a and the position of the joint portion 322 (each of the pair of strip-shaped portions 322a) in the thickness direction z are the same (or approximately the same). Therefore, in this embodiment, each of the pair of main body portions 324a and the joint portion 322 are not misaligned in the thickness direction z. In the present disclosure, the position of each of the pair of main body portions 324a in the thickness direction z and the position of the joint portion 322 (each of the pair of strip-shaped portions 322a) in the thickness direction z are each based on a surface facing downward in the thickness direction z.

[0088] Each of the plurality of connection members 41A, 41B, 42A, and 42B is, for example, a bonding wire. Each of the plurality of connection members 41A, 41B, 42A, and 42B contains gold. Alternatively, each of the plurality of connection members 41A, 41B, 42A, and 42B may contain copper or aluminum (Al).

[0089] 3, the connecting member 41A is bonded to the main surface electrode 212 of the semiconductor chip 21 and the covering portion 171A of the lead 171. This provides electrical continuity between the lead 171 and the main surface electrode 212 of the semiconductor chip 21. The connecting member 41B is bonded to the main surface electrode 222 of the semiconductor chip 22 and the covering portion 172A of the lead 172. This provides electrical continuity between the lead 172 and the main surface electrode 222 of the semiconductor chip 22.

[0090] As shown in FIG. 3 , the connection member 42A is bonded to one of the pair of principal surface electrodes 214 of the semiconductor chip 21 and the covering portion 181A of the lead 181. As a result, the lead 181 is electrically connected to one of the pair of principal surface electrodes 214 of the semiconductor chip 21. In an example where the semiconductor chip 21 does not have either of the pair of principal surface electrodes 214, the connection member 42A is bonded to the principal surface electrode 211 instead of the principal surface electrode 214. As shown in FIG. 3 , the connection member 42B is bonded to one of the pair of principal surface electrodes 224 of the semiconductor chip 22 and the covering portion 182A of the lead 182. As a result, the lead 182 is electrically connected to one of the pair of principal surface electrodes 224 of the semiconductor chip 22. In an example where the semiconductor chip 22 does not have either of the pair of principal surface electrodes 224, the connection member 42B is bonded to the principal surface electrode 221 instead of the principal surface electrode 224.

[0091] 19, in the semiconductor device A10 configured as described above, the main surface electrode 211 of the semiconductor chip 21 and the back surface electrode 223 of the semiconductor chip 22 are electrically connected to each other. Therefore, the semiconductor device A10 configures a half-bridge circuit using two transistors (two semiconductor chips 21 and 22).

[0092] The functions and effects of the semiconductor device A10 according to the first embodiment are as follows.

[0093] In the semiconductor device A10, the principal surface electrodes 221 of the semiconductor chip 22 and the leads 14 (conduction objects) are electrically connected via the plate-shaped conductive members 32. This configuration reduces the wiring resistance between the principal surface electrodes 221 and the leads 14 (conduction objects) compared to a configuration in which the principal surface electrodes 221 and the leads 14 are connected by bonding wires. Therefore, the semiconductor device A10 can reduce power loss.

[0094] In the semiconductor device A10, the main surface electrodes 211 of the semiconductor chip 21 and the die pad 10B (conduction object) are electrically connected via the plate-shaped conductive member 31. This configuration reduces the wiring resistance between the main surface electrodes 211 and the die pad 10B (conduction object) compared to a configuration in which the main surface electrodes 211 and the die pad 10B (conduction object) are connected by bonding wires. Therefore, the semiconductor device A10 can reduce power loss.

[0095] In the semiconductor device A10, the plate-shaped conductive member 32 includes a canopy portion 324 different from the suspension portion 321. The canopy portion 324 is not in contact with the bonding layer 33 and overlaps the outer periphery 229 of the semiconductor chip 22 in the thickness direction z. When current is applied to the semiconductor chip 22, the semiconductor chip 22 generates heat. This heat generation applies thermal stress to the semiconductor chip 22. When the plate-shaped conductive member 32 (metal plate) is used to electrically connect the main surface electrodes 221 to the conductive objects (leads 14 in this embodiment), the thermal stress applied to the semiconductor chip 22 is greater than when bonding wires are used. This greater thermal stress may cause interfacial peeling between the semiconductor chip 22 and the sealing resin 50. Furthermore, because the thermal stress is greater near the outer periphery 229 of the semiconductor chip 22 in a planar view than toward the inside, the aforementioned interfacial peeling occurs from the outer periphery 229 of the semiconductor chip 22 in a planar view. According to research by the present inventors, it has been found that providing the plate-shaped conductive member 32 with an eave portion 324 that overlaps the outer periphery 229 of the semiconductor chip 22 when viewed in the thickness direction z can reduce thermal stress applied to the semiconductor chip 22 more than when the eave portion 324 is not provided. Therefore, the semiconductor device A10 can reduce thermal stress applied to the semiconductor chip 22 and suppress interfacial peeling between the semiconductor chip 22 and the sealing resin 50. This improves the reliability of the semiconductor device A10. The same applies to the plate-shaped conductive member 31. In other words, by including the eave portion 314 in the plate-shaped conductive member 31, the semiconductor device A10 can reduce thermal stress applied to the semiconductor chip 22 and suppress interfacial peeling between the semiconductor chip 22 and the sealing resin 50.

[0096] In the semiconductor device A10, the eave portion 324 of the plate-shaped conductive member 32 overlaps at least one of the four corners of the semiconductor chip 22 when viewed in the thickness direction z. Thermal stress applied to the semiconductor chip 22 is particularly large at the four corners of the outer periphery 229. Therefore, by overlapping the eave portion 324 with at least one of the four corners of the semiconductor chip 22 when viewed in the thickness direction z, the effect of alleviating the thermal stress applied to the semiconductor chip 22 is obtained. In other words, the semiconductor device A10 can further alleviate the thermal stress applied to the semiconductor chip 22. In particular, in the semiconductor device A10, the eave portion 324 of the plate-shaped conductive member 32 overlaps all four corners of the semiconductor chip 22 when viewed in the thickness direction z. Therefore, the semiconductor device A10 has a preferable structure for alleviating the thermal stress of the semiconductor chip 22. The same applies to the eave portion 314 of the plate-shaped conductive member 31. That is, the overhanging portion 314 of the plate-shaped conductive member 31 overlaps at least one of the four corners of the semiconductor chip 22 as viewed in the thickness direction z, so that the semiconductor device A10 can further alleviate the thermal stress applied to the semiconductor chip 21. In particular, in the semiconductor device A10, the overhanging portion 314 of the plate-shaped conductive member 31 overlaps all four corners of the semiconductor chip 21 as viewed in the thickness direction z. Therefore, the semiconductor device A10 has a preferable structure for alleviating the thermal stress of the semiconductor chip 21.

[0097] The semiconductor device A10 includes a semiconductor chip 21, a semiconductor chip 22, and a sealing resin 50. The sealing resin 50 covers the two semiconductor chips 21 and 22. According to this configuration, the semiconductor device A10 has two semiconductor elements (two semiconductor chips 21 and 22) packaged in one sealing resin 50. Therefore, the semiconductor device A10 can reduce the mounting area on the circuit board on which the semiconductor device A10 is mounted.

[0098] In the semiconductor device A10, the sealing resin 50 has multiple recesses 581. Each of the multiple recesses 581 is recessed from the resin main surface 51 in the thickness direction z. The multiple recesses 581 overlap the die pad 10A in a plan view. As described above, the multiple recesses 581 are marks formed by fixing the die pad 10A with multiple pins during the manufacturing of the semiconductor device A10. Therefore, since the die pad 10A is held down by multiple pins during the manufacturing of the semiconductor device A10, it is possible to prevent the die pad 10A from wobbling during the manufacturing process. This prevents a gap from being generated between the back surface 102 of the die pad 10A and the mold used to form the sealing resin 50, thereby preventing resin burrs from being generated in the sealing resin 50. The same applies to the multiple recesses 582. In other words, it is possible to prevent a gap from being generated between the back surface 102 of the die pad 10B and the mold used to form the sealing resin 50, so the semiconductor device A10 prevents resin burrs from being generated in the sealing resin 50.

[0099] In the semiconductor device A10, the plate-shaped conductive member 32 includes a suspension portion 321 connecting two joints 322, 323. The suspension portion 321 is bent in a planar view. As can be seen from FIG. 3 , if the two joints 322, 323 were connected linearly, the suspension portion 321 would overlap one of the four corners of the die pad 10B (the corner end surface 124 of the die pad 10B) in a planar view. In this case, it would be difficult for the pins that secure the die pad 10B during manufacturing of the semiconductor device A10 to press the four corners of the die pad 10B. Note that pressing the four corners of the die pad 10B with the pins is preferable for suppressing the formation of resin burrs and for suppressing the wobble of the die pad 10B. On the other hand, in the semiconductor device A10, by bending the suspension portion 321, it is possible to prevent the suspension portion 321 from overlapping one of the four corners of the die pad 10B (corner end surface 124 of the die pad 10B) in a plan view. In other words, the semiconductor device A10 is preferable in terms of suppressing the shaking of the die pad 10B during manufacturing.

[0100] In the semiconductor device A10, the suspension portion 321 of the plate-shaped conductive member 32 includes a plurality of extending portions 321a, 321c, and 321e. The extending portion 321a extends from the joint portion 323 in the second direction y, the extending portion 321c extends from the extending portion 321a in the first direction x, and the extending portion 321e extends from the extending portion 321c in the second direction y. In the semiconductor device A10, by bending the suspension portion 321 multiple times in a plan view in this manner, as described above, it becomes possible to fix the four corners of the die pad 10B with a plurality of pins during manufacturing, and it also becomes possible to form the suspension portion 311 linearly between the semiconductor chip 21 and the semiconductor chip 22.

[0101] Other embodiments and modifications of the semiconductor device of the present disclosure will be described below. The configurations of the components in each embodiment and each modification can be combined with each other as long as no technical contradiction occurs.

[0102] 20 and 21 show a semiconductor device A11 according to a first modification of the first embodiment. The semiconductor device A11 differs from the semiconductor device A10 in the following respect: the semiconductor chip 21 of the semiconductor device A11 is a diode rather than a transistor.

[0103] The semiconductor chip 21 of the semiconductor device A11 has a main surface electrode 211 and a back surface electrode 213. As shown in Fig. 20, the semiconductor chip 21 of the semiconductor device A11 does not have a plurality of main surface electrodes 212, 214. As shown in Fig. 21, the main surface electrode 211 is, for example, an anode electrode, and the back surface electrode 213 is, for example, a cathode electrode.

[0104] As shown in FIG. 20 , the semiconductor device A11 does not include any of the multiple connecting members 41A, 42A, and 42B. In this configuration, as shown in FIGS. 20 and 21 , each of the leads 171, 181, and 182 is not electrically connected to either of the two semiconductor chips 21 and 22. Therefore, in the semiconductor device A11, each of the leads 171, 181, and 182 is a non-connect terminal. Note that in the example shown in FIG. 20 , the semiconductor device A11 does not include any of the pair of connecting members 42A and 42B, but in a configuration different from this example, the semiconductor device A11 may include a pair of connecting members 42A and 42B similar to the semiconductor device A10.

[0105] 21 , in the semiconductor device A11, the main surface electrode 211 (anode electrode) of the semiconductor chip 21 and the back surface electrode 223 (drain electrode) of the semiconductor chip 22 are electrically connected. In the semiconductor device A11, with respect to the power supply voltage (DC voltage) applied between the two leads 14 and 15, the high-voltage side serves as a diode and the low-voltage side serves as a transistor. The semiconductor device A11 is used, for example, as a boost chopper circuit.

[0106] 22 and 23 show a semiconductor device A12 according to a second modification of the first embodiment. The semiconductor device A12 differs from the semiconductor device A10 in the following respect: the semiconductor chip 22 of the semiconductor device A12 is a diode rather than a transistor.

[0107] The semiconductor chip 22 of the semiconductor device A12 has a main surface electrode 221 and a back surface electrode 223. As shown in Fig. 22, the semiconductor chip 22 of the semiconductor device A12 does not have a plurality of main surface electrodes 222, 224. As shown in Fig. 23, the main surface electrode 221 is, for example, an anode electrode, and the back surface electrode 223 is, for example, a cathode electrode.

[0108] As shown in FIG. 22 , the semiconductor device A12 does not include any of the multiple connection members 41B, 42A, and 42B. In this configuration, as shown in FIGS. 22 and 23 , each of the leads 172, 181, and 182 is not electrically connected to either of the two semiconductor chips 21 and 22. Therefore, in the semiconductor device A12, each of the leads 172, 181, and 182 is a non-connect terminal. Note that in the example shown in FIG. 22 , the semiconductor device A12 does not include any of the pair of connection members 42A and 42B, but in a configuration different from this example, the semiconductor device A12 may include a pair of connection members 42A and 42B similar to that of the semiconductor device A10.

[0109] 23, in the semiconductor device A12, the main surface electrode 211 (source electrode) of the semiconductor chip 21 and the back surface electrode 223 (cathode electrode) of the semiconductor chip 22 are electrically connected. In the semiconductor device A12, with respect to the DC voltage applied between the two leads 14 and 15, the high-voltage side serves as a transistor and the low-voltage side serves as a diode. The semiconductor device A12 is used, for example, as a step-down chopper circuit.

[0110] 24 and 25 show a semiconductor device A13 according to a third modification of the first embodiment. The semiconductor device A13 differs from the semiconductor device A10 in the following respect: each of the two semiconductor chips 21 and 22 of the semiconductor device A13 is a diode rather than a transistor.

[0111] The semiconductor chip 21 of the semiconductor device A13 is a diode, similar to the semiconductor chip 21 of the semiconductor device A11. The semiconductor chip 22 of the semiconductor device A13 is a diode, similar to the semiconductor chip 22 of the semiconductor device A12.

[0112] As shown in FIG. 24 , the semiconductor device A13 does not include any of the multiple connecting members 41A, 41B, 42A, and 42B. In this configuration, as shown in FIGS. 24 and 25 , the leads 171, 172, 181, and 182 are not electrically connected to either of the two semiconductor chips 21 and 22. Therefore, in the semiconductor device A13, the leads 171, 172, 181, and 182 are non-connect terminals. Note that in the example shown in FIG. 24 , the semiconductor device A13 does not include any of the pair of connecting members 42A and 42B, but in a configuration different from this example, the semiconductor device A13 may include a pair of connecting members 42A and 42B similar to the semiconductor device A10.

[0113] 25, in the semiconductor device A13, the main surface electrode 211 (anode electrode) of the semiconductor chip 21 and the back surface electrode 223 (cathode electrode) of the semiconductor chip 22 are electrically connected. In the semiconductor device A13, both the high-voltage side and the low-voltage side are diodes with respect to the power supply voltage (DC voltage) applied between the two leads 14 and 15. The semiconductor device A13 is a diode bridge circuit.

[0114] Like the semiconductor device A10, the semiconductor devices A11 to A13 according to the modifications of the first embodiment each have two semiconductor elements (two semiconductor chips 21, 22) packaged in one sealing resin 50. Therefore, like the semiconductor device A10, each of the semiconductor devices A11 to A13 can reduce the mounting area on the circuit board on which the semiconductor devices A11 to A13 are mounted. In addition, each of the semiconductor devices A11 to A13 has a common configuration with the semiconductor device A10, and therefore achieves the same effects as the semiconductor device A10.

[0115] As can be seen from the above semiconductor devices A10 to A13, the semiconductor device of the present disclosure can configure four types of power conversion circuits (a transistor bridge circuit, a step-up chopper circuit, a step-down chopper circuit, and a diode bridge circuit) by combining two semiconductor chips 21 and 22. Meanwhile, the configurations of the terminal leads 13 and the sealing resin 50 are common to the semiconductor devices A10 to A13. Therefore, the semiconductor device of the present disclosure can configure any of the four types of power conversion circuits while maintaining the same package appearance. Furthermore, the semiconductor device of the present disclosure can utilize the same configurations of the terminal leads 13 and the sealing resin 50 even if the two semiconductor chips 21 and 22 are transistors or diodes. This allows the semiconductor device of the present disclosure to use a common package structure for any of the four types of power conversion circuits described above, which is advantageous in terms of improving productivity.

[0116] As can be seen from the above semiconductor devices A10 to A13, the semiconductor devices of the present disclosure are arranged so that the center of gravity of the semiconductor chip 21 overlaps the center of the die pad 10A in a plan view. This configuration is preferable for sharing the plate-shaped conductive member 31. Similarly, the semiconductor devices of the present disclosure are arranged so that the center of gravity of the semiconductor chip 22 overlaps the center of the die pad 10B in a plan view. This configuration is preferable for sharing the plate-shaped conductive member 32.

[0117] 26 to 28 show a semiconductor device A20 according to a second embodiment. The semiconductor device A20 differs from the semiconductor device A10 in the following respects. Each main body 314a of the eave portion 314 of the semiconductor device A20 is offset upward in the thickness direction z with respect to the joint 312. Furthermore, each main body 324a of the eave portion 324 of the semiconductor device A20 is offset upward in the thickness direction z with respect to the joint 322.

[0118] 27 , in the semiconductor device A20, each main body portion 314a is positioned above the joint portion 312 in the thickness direction z. Therefore, as shown in FIG. 27 , the end of each connecting portion 314b connected to the main body portion 314a is bent upward in the thickness direction z. The amount of misalignment Δz1 (see FIG. 27 ) in the thickness direction z between each main body portion 314a and the joint portion 312 (each strip-shaped portion 312a) is 20% to 300% of the thickness t31a of the suspension portion 311. In one example, the amount of misalignment Δz1 is 50 μm to 500 μm. In the present disclosure, the misalignment amount Δz1 is defined as a positive value when the lower surface (the surface facing downward in the thickness direction z) of each main body portion 314a is located above the lower surface (the surface facing downward in the thickness direction z) of the joint portion 312 (each strip portion 312a) in the thickness direction z, and a negative value when the lower surface of each main body portion 314a is located below the lower surface in the thickness direction z. In the semiconductor device A10, the misalignment amount Δz1 is 0.

[0119] As shown in FIG. 28 , in the semiconductor device A20, each main body portion 324a is positioned above the joint portion 322 in the thickness direction z. Therefore, as shown in FIG. 28 , the end of each connecting portion 324b connected to the main body portion 324a is bent upward in the thickness direction z. The misalignment Δz2 (see FIG. 28 ) in the thickness direction z between each main body portion 324a and the joint portion 322 (each strip portion 322a) is 20% to 300% of the thickness t32a of the suspension portion 321. In one example, the misalignment Δz2 is greater than 50 μm and less than 500 μm. In this embodiment, the misalignment Δz1 and the misalignment Δz2 are the same (or approximately the same), but they may be different. In the present disclosure, the misalignment amount Δz2 is defined as a positive value when the lower surface (the surface facing downward in the thickness direction z) of each main body portion 324a is located above the lower surface (the surface facing downward in the thickness direction z) of the joint portion 322 (each strip portion 322a) in the thickness direction z, and a negative value when the lower surface of each main body portion 324a is located below the lower surface in the thickness direction z. In the semiconductor device A10, the misalignment amount Δz2 is 0.

[0120] Like the semiconductor device A10, the semiconductor device A20 can reduce the wiring resistance between the principal surface electrode 221 and the lead 14 (the conductive object for the principal surface electrode 221) using the plate-shaped conductive member 32, thereby reducing power loss. Also, like the semiconductor device A10, the semiconductor device A20 can reduce the wiring resistance between the principal surface electrode 211 and the die pad 10B (the conductive object for the principal surface electrode 211) using the plate-shaped conductive member 31, thereby reducing power loss. Also, like the semiconductor device A10, the semiconductor device A20 can alleviate thermal stress applied to the semiconductor chip 22 using the overhanging portion 324 of the plate-shaped conductive member 32. Also, like the semiconductor device A10, the semiconductor device A20 can alleviate thermal stress applied to the semiconductor chip 21 using the overhanging portion 314 of the plate-shaped conductive member 31. Furthermore, the semiconductor device A20 achieves similar effects to the semiconductor device A10 due to the configuration common to the semiconductor device A10.

[0121] In the semiconductor device A20, each main body portion 324a of the overhanging portion 324 of the plate-shaped conductive member 32 is positioned above the joints 322 in the thickness direction z. Research by the present inventors has revealed that displacing each main body portion 324a above the joints 322 in the thickness direction z can further reduce thermal stress on the semiconductor chip 22 compared to the semiconductor device A10, where the main body portions 324a are not displaced. Therefore, the semiconductor device A20 can further reduce thermal stress on the semiconductor chip 22 than the semiconductor device A10. In particular, in the semiconductor device A20, the offset Δz2 (see FIG. 28 ) between each main body portion 324a and the joints 322 in the thickness direction z is greater than 20% and less than 300% of the thickness t32a of the suspension portion 321. This configuration reduces thermal stress on the semiconductor chip 22 more than when the offset Δz2 is outside the upper limit of this range. In other words, a configuration in which the misalignment amount Δz2 is within the aforementioned range is preferable in terms of alleviating thermal stress on the semiconductor chip 22. The same applies to the overhanging portion 314 of the plate-shaped conductive member 31. In other words, because each main body portion 314a of the overhanging portion 314 is located above the joint portion 312 in the thickness direction z, the semiconductor device A20 can further alleviate thermal stress applied to the semiconductor chip 21 than the semiconductor device A10. In particular, in the semiconductor device A20, the misalignment amount Δz1 (see FIG. 27 ) between each main body portion 314a and the joint portion 312 in the thickness direction z is greater than 20% and less than 300% of the thickness t31a of the suspension portion 311. With this configuration, the thermal stress applied to the semiconductor chip 21 is alleviated more than when the misalignment amount Δz1 is outside the upper limit of this range. In other words, a configuration in which the misalignment amount Δz1 is within the aforementioned range is preferable in terms of alleviating thermal stress on the semiconductor chip 21.

[0122] 29 shows a semiconductor device A21 according to a modification of the second embodiment. The semiconductor device A21 differs from the semiconductor device A20 in the following respects. First, each main body portion 314a of the eave portion 314 of the semiconductor device A21 is shifted downward in the thickness direction z, rather than upward, relative to the joint portion 312. Second, each main body portion 324a of the eave portion 324 of the semiconductor device A21 is shifted downward in the thickness direction z, rather than upward, relative to the joint portion 322.

[0123] As shown in FIG. 29 , in the semiconductor device A21, each main body portion 314a is positioned below the bonding portion 312 in the thickness direction z. Therefore, as shown in FIG. 29 , the end of each connecting portion 324b connected to the main body portion 324a is bent downward in the thickness direction z. For example, the aforementioned deviation amount Δz1 (see FIG. 29 ) is equal to or greater than the negative value (−T1max) of the maximum thickness T1max of the bonding layer 33 and less than 0 (zero). When the deviation amount Δz1 is the negative value (−T1max) of the maximum thickness T1max of the bonding layer 33, each main body portion 314a contacts the main surface 21a. Note that FIG. 29 illustrates a case in which each main body portion 314a is spaced apart from the main surface 21a in the thickness direction z.

[0124] In the semiconductor device A21, the positional relationship between each main body portion 324a and the bonding portion 322 is the same (or approximately the same) as the positional relationship between each main body portion 314a and the bonding portion 312. In other words, each main body portion 324a is located below the bonding portion 322 in the thickness direction z. Therefore, the end of each connecting portion 324b connected to the main body portion 324a is bent downward in the thickness direction z. For example, the aforementioned deviation amount Δz2 is equal to or greater than the negative value (−T2max) of the maximum thickness T2max of the bonding layer 34 and less than 0 (zero). When the deviation amount Δz2 is the negative value (−T2max) of the maximum thickness T2max of the bonding layer 34, each main body portion 324a contacts the main surface 22a.

[0125] In semiconductor device A21, as in semiconductor device A20, it is possible to reduce power loss through plate-shaped conductive member 32, reduce power loss through plate-shaped conductive member 31, alleviate thermal stress through eave portion 324 of plate-shaped conductive member 32, and alleviate thermal stress through eave portion 314 of plate-shaped conductive member 31.

[0126] As can be understood from the above-described first and second embodiments (including modified examples), in the semiconductor device of the present disclosure, each main body portion 314 a and the joint portion 312 may be offset upward in the thickness direction z, may be offset downward in the thickness direction z, or may not be offset at all. In other words, as long as the plate-shaped conductive member 31 includes the eave portion 314, the semiconductor device of the present disclosure is not limited in any way to whether each main body portion 314 a is offset relative to the joint portion 312, or whether the offset is upward or downward in the thickness direction z. However, according to the findings of the present inventors' research, a configuration in which each main body portion 314 a is offset upward in the thickness direction z relative to the joint portion 312 is preferable in terms of alleviating thermal stress in the semiconductor chip 21. Similarly, in the semiconductor device of the present disclosure, each main body portion 324 a and the joint portion 322 may be offset upward in the thickness direction z, may be offset downward in the thickness direction z, or may not be offset at all. In other words, in the semiconductor device of the present disclosure, as long as the plate-shaped conductive member 32 includes the overhanging portion 324, there are no limitations on whether each main body portion 324a is misaligned with respect to the joint portion 322 or whether the main body portion 324a is misaligned upward or downward in the thickness direction z. However, according to the findings of the research of the present inventors, in terms of alleviating thermal stress in the semiconductor chip 22, a configuration in which each main body portion 324a is misaligned upward in the thickness direction z with respect to the joint portion 322 is preferable.

[0127] 30 to 32 show a semiconductor device A30 according to a third embodiment. The semiconductor device A30 differs from the semiconductor device A10 in the following respects. First, the overhanging portion 314 of the semiconductor device A30 is thicker than the suspension portion 311. Second, the overhanging portion 324 of the semiconductor device A30 is thicker than the suspension portion 321.

[0128] As shown in Figure 30, the thickness t31b of the bonding portion 312 is greater than the thickness t31a of the suspension portion 311. As can be seen from Figure 31, the thickness t31b of the bonding portion 312 and the thickness t31c of the overhanging portion 314 are the same (or approximately the same). Therefore, the thickness t31c of the overhanging portion 314 is greater than the thickness t31a of the suspension portion 311. For example, the thickness t31c of the overhanging portion 314 is greater than 100% and less than 300% of the thickness of the suspension portion 311. Furthermore, the thickness t31c of the overhanging portion 314 is greater than 50% and less than 300% of the maximum thickness T1max of the bonding layer 33. In one example, the thickness t31c of the overhanging portion 314 is greater than 125 µm and less than 500 µm. In the example shown in Figure 30, the suspension portion 311 is connected to the lower end of the joint 312 (each band-shaped portion 312a) in the thickness direction z, but unlike this example, it may be connected to the upper end of the joint 312 (each band-shaped portion 312a) in the thickness direction z.

[0129] As shown in Figure 30, the thickness t32b of the bonding portion 322 is greater than the thickness t32a of the suspension portion 321. As can be seen from Figure 32, the thickness t32b of the bonding portion 322 and the thickness t32c of the overhanging portion 324 are the same (or approximately the same). Therefore, the thickness t32c of the overhanging portion 324 is greater than the thickness t32a of the suspension portion 321. For example, the thickness t32c of the overhanging portion 324 is greater than 100% and less than 300% of the thickness t32a of the suspension portion 321. Furthermore, the thickness t32c of the overhanging portion 324 is greater than 50% and less than 300% of the maximum thickness T2max of the bonding layer 35. In one example, the thickness t32c of the overhanging portion 324 is greater than 125 µm and less than 500 µm. In the example shown in Figure 30, the suspension portion 321 is connected to the lower end of the joint 322 (each band-shaped portion 322a) in the thickness direction z, but unlike this example, it may be connected to the upper end of the joint 322 (each band-shaped portion 322a) in the thickness direction z.

[0130] Like the semiconductor device A10, the semiconductor device A30 can reduce the wiring resistance between the principal surface electrode 221 and the lead 14 (the conductive object relative to the principal surface electrode 221) using the plate-shaped conductive member 32, thereby reducing power loss. Also, like the semiconductor device A10, the semiconductor device A30 can reduce the wiring resistance between the principal surface electrode 211 and the die pad 10B (the conductive object relative to the principal surface electrode 211) using the plate-shaped conductive member 31, thereby reducing power loss. Also, like the semiconductor device A10, the semiconductor device A30 can alleviate thermal stress applied to the semiconductor chip 22 using the overhanging portion 324 of the plate-shaped conductive member 32. Also, like the semiconductor device A10, the semiconductor device A30 can alleviate thermal stress applied to the semiconductor chip 21 using the overhanging portion 314 of the plate-shaped conductive member 31. Furthermore, the semiconductor device A30 achieves similar effects to the semiconductor device A10 due to the configuration common to the semiconductor device A10.

[0131] In the semiconductor device A30, the eave portion 324 of the plate-shaped conductive member 32 is thicker than the suspension portion 321. For example, the thickness t32c of the eave portion 324 is greater than 100% and less than 300% of the thickness t32a of the suspension portion 321. Even if the eave portion 324 is thicker than the suspension portion 321, thermal stress applied to the semiconductor chip 22 can be alleviated. On the other hand, if the eave portion 324 is thicker than the suspension portion 321, the joining portion 322 also becomes thicker, which requires a larger pressing force when joining the plate-shaped conductive member 32 to the principal surface electrode 221. This may result in damage to the principal surface electrode 221. Therefore, by setting the thickness t32c of the eave portion 324 to be greater than 100% and less than 300% of the thickness t32a of the suspension portion 321, the semiconductor device A30 can alleviate thermal stress applied to the semiconductor chip 22 and suppress damage to the principal surface electrode 221. The thickness t32c of the overhanging portion 324 may be set to 50% to 300% of the maximum thickness T2max of the bonding layer 35, instead of the thickness t32a of the suspension portion 321. In this case, the thermal stress applied to the semiconductor chip 22 can be reduced and damage to the principal surface electrodes 221 can be suppressed. The same applies to the plate-shaped conductive member 31. That is, by setting the thickness t31c of the overhanging portion 314 of the plate-shaped conductive member 31 to be greater than 100% and less than 300% of the thickness t31a of the suspension portion 311, the thermal stress applied to the semiconductor chip 21 can be reduced and damage to the principal surface electrodes 211 can be suppressed. The thickness t31c of the overhanging portion 314 may be set to 50% to 300% of the maximum thickness T1max of the bonding layer 33, instead of the thickness t31a of the suspension portion 311. In this case, the thermal stress applied to the semiconductor chip 21 can be similarly alleviated, and damage to the main surface electrodes 211 can be suppressed.

[0132] In an example different from the semiconductor device A30, the eave portion 314 may be thinner than the suspension portion 311. In this example, the thickness t31c of the plate-shaped conductive member 31 is 50% or more but less than 100% of the thickness t31a of the suspension portion 311. Even if the eave portion 314 is thinner than the suspension portion 311, the thermal stress applied to the semiconductor chip 21 can be alleviated. On the other hand, if the eave portion 314 is thinner than the suspension portion 311, the joint portion 312 also becomes thinner, resulting in increased wiring resistance at the joint portion 312. Therefore, in an example where the eave portion 314 is thinner than the suspension portion 311, setting the thickness t31c of the eave portion 314 to 50% or more of the thickness t31a of the suspension portion 311 can alleviate the thermal stress applied to the semiconductor chip 21 and suppress an increase in wiring resistance at the joint portion 312. Similarly, in an example different from the semiconductor device A30, the eave portion 324 may be thinner than the suspension portion 321. In this example, the thickness t32c of the plate-shaped conductive member 32 is 50% or more and less than 100% of the thickness t32a of the suspension portion 321. According to this configuration, by making the thickness t32c of the eave portion 324 50% or more of the thickness t32a of the suspension portion 321, it is possible to alleviate the thermal stress applied to the semiconductor chip 22 and suppress an increase in the wiring resistance at the bonding portion 322.

[0133] As can be understood from the above-described first and third embodiments (including modified examples), in the semiconductor device of the present disclosure, the thickness t31c of the overhanging portion 314 may be greater than, smaller than, or the same as the thickness t31a of the suspension portion 311. In other words, in the semiconductor device of the present disclosure, as long as the plate-shaped conductive member 31 includes the overhanging portion 314, the relative thickness relationship between the overhanging portion 314 and the suspension portion 311 is not limited in any way. However, according to the findings of the inventors' research, in order to alleviate thermal stress in the semiconductor chip 21, it is preferable to have the thickness t31c of the overhanging portion 314 and the thickness t31a of the suspension portion 311 be the same (or approximately the same). Similarly, in the semiconductor device of the present disclosure, the thickness t32c of the overhanging portion 324 may be greater than, smaller than, or the same as the thickness t32a of the suspension portion 321. That is, in the semiconductor device of the present disclosure, as long as the plate-shaped conductive member 32 includes the overhanging portion 324, there is no limitation on the relative thickness relationship between the overhanging portion 324 and the suspension portion 321. However, according to the findings of the research of the present inventors, in terms of alleviating thermal stress in the semiconductor chip 22, it is preferable to configure the thickness t32c of the overhanging portion 324 and the thickness t32a of the suspension portion 321 to be the same (or approximately the same).

[0134] 33 shows a semiconductor device A40 according to a fourth embodiment. The semiconductor device A40 differs from the semiconductor device A10 in the following respects. First, the area of ​​the overhanging portion 314 of the semiconductor device A40 that overlaps with the outer periphery 219 is different. Second, the area of ​​the overhanging portion 314 of the semiconductor device A40 that overlaps with the outer periphery 229 is different.

[0135] The eave portion 314 (each main body portion 314a and each connecting portion 314b) of the semiconductor device A40 does not entirely overlap each edge 219a of the outer periphery 219, but overlaps a portion of each edge 219a. In this embodiment, the eave portion 314 does not overlap any of the four corners of the semiconductor chip 21 in a planar view. In the illustrated example, in the eave portion 314, the dimension of each main body portion 314a along the first direction x and the dimension of each connecting portion 314b along the first direction x are the same (or approximately the same), but the dimension of each main body portion 314a along the first direction x may be larger or smaller than the dimension of each connecting portion 314b along the first direction x. As shown in FIG. 33 , the configuration of the eave portion 314 is similar for the eave portion 324. That is, the canopy portions 324 (main body portions 324a and connecting portions 324b) of the semiconductor device A40 do not overlap the entire edges 229a of the outer periphery 229, but overlap only a portion of each edge 229a.

[0136] Like the semiconductor device A10, the semiconductor device A40 can reduce the wiring resistance between the principal surface electrode 221 and the lead 14 (the conductive object relative to the principal surface electrode 221) using the plate-shaped conductive member 32, thereby reducing power loss. Also, like the semiconductor device A10, the semiconductor device A40 can reduce the wiring resistance between the principal surface electrode 211 and the die pad 10B (the conductive object relative to the principal surface electrode 211) using the plate-shaped conductive member 31, thereby reducing power loss. Also, like the semiconductor device A10, the semiconductor device A40 can alleviate thermal stress applied to the semiconductor chip 22 using the overhanging portion 324 of the plate-shaped conductive member 32. Also, like the semiconductor device A10, the semiconductor device A40 can alleviate thermal stress applied to the semiconductor chip 21 using the overhanging portion 314 of the plate-shaped conductive member 31. Furthermore, the semiconductor device A40 achieves similar effects to the semiconductor device A10 due to the configuration common to the semiconductor device A10.

[0137] 34 shows a semiconductor device A41 according to a first modified example of the fourth embodiment. The semiconductor device A41 differs from the semiconductor device A40 in the following respects. First, in a plan view, each main body portion 314a overlaps two of the four corners of the semiconductor chip 21 that are farther from the suspension portion 311. Second, in a plan view, each main body portion 324a overlaps two of the four corners of the semiconductor chip 22 that are farther from the suspension portion 321.

[0138] 35 shows a semiconductor device A42 according to a second modified example of the fourth embodiment. The semiconductor device A42 differs from the semiconductor device A40 in the following respects. First, in a plan view, each main body portion 314a overlaps two of the four corners of the semiconductor chip 21 that are closer to the suspension portion 321. Second, in a plan view, each main body portion 324a overlaps two of the four corners of the semiconductor chip 22 that are closer to the suspension portion 321.

[0139] In each of the semiconductor devices A41 and A42, as in the semiconductor device A40, it is possible to reduce power loss by the plate-shaped conductive member 32, reduce power loss by the plate-shaped conductive member 31, alleviate thermal stress by the eave portion 324 of the plate-shaped conductive member 32, and alleviate thermal stress by the eave portion 314 of the plate-shaped conductive member 31.

[0140] As can be understood from the above-described first and fourth embodiments (including modified examples), in the semiconductor device of the present disclosure, the overhanging portion 314 is not limited to a specific area as long as it overlaps the outer periphery 219 of the semiconductor chip 21 in a planar view. However, according to the findings of the inventors' research, in order to alleviate thermal stress in the semiconductor chip 21, a configuration in which the overhanging portion 314 overlaps the four corners of the semiconductor chip 21 in a planar view, as in the first embodiment, is preferable. Note that, in the pair of main body portions 314a, the area that overlaps the outer periphery 219 of one main body portion 314a may be different from the area that overlaps the outer periphery 219 of the other main body portion 314a. Similarly, in the semiconductor device of the present disclosure, the overhanging portion 324 is not limited to a specific area as long as it overlaps the outer periphery 229 of the semiconductor chip 22 in a planar view. However, according to the findings of the inventors' research, a configuration in which the overhanging portions 324 overlap the four corners of the semiconductor chip 22 in a plan view, as in the first embodiment, is preferable in terms of alleviating thermal stress in the semiconductor chip 22. Note that, in the pair of main body portions 324a, the region that overlaps the outer periphery 229 of one main body portion 324a may be different from the region that overlaps the outer periphery 229 of the other main body portion 324a.

[0141] 36 shows a semiconductor device A50 according to a fifth embodiment. The semiconductor device A50 differs from the semiconductor device A10 in the following respects. First, the overhanging portion 314 does not extend from the bonding portion 312 but extends from the suspension portion 311. Second, the overhanging portion 324 does not extend from the bonding portion 322 but extends from the suspension portion 321.

[0142] 36, the eave portion 314 of the semiconductor device A50 extends from the suspension portion 311 and is not directly connected to the joint portion 312. Also, as shown in FIG. 36, the eave portion 324 of the semiconductor device A50 extends from the suspension portion 321 and is not directly connected to the joint portion 322.

[0143] Like the semiconductor device A10, the semiconductor device A50 can reduce the wiring resistance between the principal surface electrode 221 and the lead 14 (the conductive object relative to the principal surface electrode 221) using the plate-shaped conductive member 32, thereby reducing power loss. Also, like the semiconductor device A10, the semiconductor device A50 can reduce the wiring resistance between the principal surface electrode 211 and the die pad 10B (the conductive object relative to the principal surface electrode 211) using the plate-shaped conductive member 31, thereby reducing power loss. Also, like the semiconductor device A10, the semiconductor device A50 can alleviate thermal stress applied to the semiconductor chip 22 using the overhanging portion 324 of the plate-shaped conductive member 32. Also, like the semiconductor device A10, the semiconductor device A50 can alleviate thermal stress applied to the semiconductor chip 21 using the overhanging portion 314 of the plate-shaped conductive member 31. Furthermore, the semiconductor device A50 achieves similar effects to the semiconductor device A10 due to the configuration common to the semiconductor device A10.

[0144] As can be understood from the above-described first and fifth embodiments, in the semiconductor device of the present disclosure, the overhanging portion 314 may extend from any portion of the plate-shaped conductive member 31. Similarly, in the semiconductor device of the present disclosure, the overhanging portion 324 may extend from any portion of the plate-shaped conductive member 32.

[0145] In the first to fifth embodiments (including their modified examples), the eave portion 314 of the plate-shaped conductive member 31 includes a pair of main body portions 314a, but the eave portion 314 may include only one of the pair of main body portions 314a. In this case, the eave portion 314 does not need to include the connecting portion 314b corresponding to one of the pair of main body portions 314a.

[0146] 37 shows a semiconductor device A60 according to a sixth embodiment. The semiconductor device A60 differs from the semiconductor device A10 in the following respects: The semiconductor device A60 does not include the semiconductor chip 22.

[0147] The semiconductor device A60 has a TO (Transistor Outline) type package structure. In the illustrated example, the package structure of the semiconductor device A60 is a lead insertion type TO package, but it may also be a surface mount type TO package.

[0148] 37 , a semiconductor device A60 includes a die pad 10A, three terminal leads 13, a semiconductor chip 21, a plate-shaped conductive member 31, a connection member 41A, and a sealing resin 50. The three terminal leads 13 include three leads 14, 15, and 171. As shown in FIG. 37 , in the semiconductor device A60, the plate-shaped conductive member 31 is bonded to the main surface electrodes 211 of the semiconductor chip 21 and the leads 14, establishing electrical continuity between them.

[0149] In the semiconductor device A60, the principal surface electrodes 211 of the semiconductor chip 21 and the leads 14 serving as conduction targets are electrically connected via the plate-shaped conductive member 31. This configuration reduces the wiring resistance between the principal surface electrodes 211 and the leads 14 compared to a configuration in which the principal surface electrodes 211 and the leads 14 are connected by bonding wires. Therefore, the semiconductor device A60 can reduce power loss. Furthermore, in the semiconductor device A60, the plate-shaped conductive member 31 includes a canopy portion 314. This configuration can reduce stress applied to the semiconductor chip 21.

[0150] As can be understood from the first and sixth embodiments, the package structure of the semiconductor device of the present disclosure is not limited to a specific configuration, and may be, for example, a small outline package (SOP), a quad flat package (QFP), a ball grid array (BGA), a land grid array (LGA), a dual flatpack no-leaded (DFN), or a quad flatpack no-leaded (QFN).

[0151] In the first to sixth embodiments, examples have been shown in which the semiconductor devices A10, A20, A30, A40, A50, and A60 have package structures formed from lead frames. That is, in the semiconductor devices A10, A20, A30, A40, A50, and A60, the semiconductor chip 21 (and the semiconductor chip 22) are supported by the die pad 10A (and the die pad 10B) formed from the lead frame. In package structures different from these examples, the semiconductor chip 21 (and the semiconductor chip 22) may be supported by a semiconductor substrate, a glass substrate, a metal base substrate, or the like.

[0152] The semiconductor device according to the present disclosure is not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present disclosure can be freely modified in various ways. For example, the semiconductor device according to the present disclosure includes embodiments according to the following supplementary notes. Supplementary Note 1. A semiconductor device comprising: a semiconductor chip having a main surface facing one side in a thickness direction and a first main surface electrode arranged on the main surface; a conduction target spaced from the semiconductor chip and conducting to the first main surface electrode; a plate-shaped conductive member including a first bonding portion bonded to the first main surface electrode, a second bonding portion bonded to the conduction target, and a suspension portion connecting the first bonding portion and the second bonding portion; a conductive bonding layer bonding the first bonding portion and the first main surface electrode; and a sealing resin covering the semiconductor chip, a portion of the conduction target, the plate-shaped conductive member, and the bonding layer, wherein the plate-shaped conductive member includes an overhang portion different from the suspension portion, and the overhang portion is not in contact with the bonding layer and overlaps the outer periphery of the semiconductor chip when viewed in the thickness direction. Appendix 2. The semiconductor device according to Appendix 1, wherein the overhang portion extends from the first bonding portion. Appendix 3. The semiconductor device according to Supplementary Note 2, wherein the overhanging portion includes at least one main body portion overlapping the outer periphery of the semiconductor chip when viewed in the thickness direction, and at least one connecting portion connecting the first bonding portion and the at least one main body portion, the first bonding portion being connected to the suspension portion from one side in a first direction perpendicular to the thickness direction, the at least one connecting portion extending from the first bonding portion in a second direction perpendicular to the thickness direction and the first direction, and the at least one main body portion extending in the first direction.Supplementary Note 4. The semiconductor device according to Supplementary Note 3, wherein the at least one main body portion overlaps at least one of four corners of the semiconductor chip.Appendix 5. The semiconductor device according to Appendix 3 or Appendix 4, wherein the at least one main body portion includes a pair of main body portions spaced apart in the second direction, the pair of main body portions are arranged in the second direction with the first joint portion sandwiched between them, the at least one connecting portion includes a pair of connecting portions spaced apart in the second direction, one of the pair of connecting portions extends from the first joint portion in one direction in the second direction and is connected to one of the pair of main body portions, and the other of the pair of connecting portions extends from the first joint portion in the other direction in the second direction and is connected to the other of the pair of main body portions. Appendix 6. The semiconductor device according to Appendix 5, wherein the periphery of the semiconductor chip has a pair of edges spaced apart in the second direction and extending in the first direction in the thickness direction when viewed in the thickness direction, and the pair of main body portions entirely overlap the pair of edges when viewed in the thickness direction. Appendix 7. The semiconductor device according to Supplementary Note 5 or Supplementary Note 6, wherein the first bonding portion includes a plurality of strip-shaped portions arranged in the second direction, and the one of the pair of connecting portions is connected to a strip-shaped portion of the plurality of strip-shaped portions that is located furthest on the one side in the second direction, and the other of the pair of connecting portions is connected to a strip-shaped portion of the plurality of strip-shaped portions that is furthest on the other side in the second direction. Supplementary Note 8. The semiconductor device according to any of Supplementary Note 3 to Supplementary Note 7, wherein a position of the at least one body portion in the thickness direction and a position of the first bonding portion are offset from each other. Supplementary Note 9. The semiconductor device according to Supplementary Note 8, wherein an end of the at least one connecting portion that is connected to the at least one body portion is bent in the thickness direction. Supplementary Note 10. The semiconductor device according to Supplementary Note 9, wherein the at least one body portion is separated from the semiconductor chip in the thickness direction. Supplementary Note 11. The semiconductor device according to Supplementary Note 10, wherein the at least one body portion is located on the one side in the thickness direction with respect to the first bonding portion. Supplementary Note 12. The semiconductor device according to claim 11, wherein the amount of misalignment between the at least one main body portion and the first joint portion in the thickness direction is 50% to 300% of the thickness of the suspension portion. The semiconductor device according to claim 9, wherein the thickness of the plate-shaped conductive member is uniform throughout the plate-shaped conductive member.Appendix 14. The semiconductor device according to any one of Appendix 1 to Appendix 12, wherein the thickness of the overhanging portion is 50% or more and 300% or less of the thickness of the suspension portion. Appendix 15. The semiconductor device according to any one of Appendix 1 to Appendix 14, wherein the semiconductor chip includes a second main surface electrode arranged on the main surface, and the plate-shaped conductive member does not overlap the second main surface electrode when viewed in the thickness direction. Appendix 16. The semiconductor device according to any one of Appendix 1 to Appendix 15, further comprising a die pad to which the semiconductor chip is bonded, wherein the conduction target is a first lead spaced from the die pad, and the first lead includes a covering portion covered with the sealing resin and to which the second bonding portion is bonded, and an exposed portion connected to the covering portion and exposed from the sealing resin. Appendix 17. 16. The semiconductor device according to claim 15, further comprising: a second lead spaced apart from the first lead and connected to the die pad; the semiconductor chip has a back surface facing opposite to the main surface in the thickness direction and a back surface electrode disposed on the back surface, the back surface electrode being conductively joined to the die pad; and the second lead including a second covered portion covered with the sealing resin and a second exposed portion connected to the second covered portion and exposed from the sealing resin. 17. The semiconductor device according to claim 15, further comprising: a second semiconductor chip electrically connected to the first semiconductor chip, the second semiconductor chip being covered with the sealing resin. 18. The semiconductor device according to any one of claims 1 to 17, wherein the semiconductor chip is a first semiconductor chip, and the second semiconductor chip is covered with the sealing resin. 19. The semiconductor device according to claim 15, wherein the first semiconductor chip is either a transistor or a diode, and the second semiconductor chip is either a transistor or a diode.

[0153] A10 to A13, A20, A21, A30, A40 to A42, A50, A60: semiconductor device 10A, 10B: die pad 101: main surface 102: back surface 103: seating surface 104: standing surface 111 to 114: end surface 121 to 124: corner end surface 13: terminal lead 14, 15, 16, 171, 172, 181, 182: lead 14A, 15A, 16A, 171A, 172A, 181A, 182A: coating portion 14B, 15B, 16B, 171B, 172B, 181B, 182B: exposed portion 14C: seating surface 14D: standing surface 21: semiconductor chip 21a: main surface 21b: back surface 211, 212, 214: Principal surface electrodes 213: Back surface electrode 219: Outer periphery 219a, 219b: Edge 22: Semiconductor chip 22a: Principal surface 22b: Back surface 221, 222, 224: Principal surface electrodes 223: Back surface electrode 229: Outer periphery 229a, 229b: Edge 231: Die bonding layer 232: Die bonding layer 31: Plate-shaped conductive member 311: Suspension portion 312: Bonding portion 312a: Strip-shaped portion 313: Bonding portion 314: Eaves portion 314a: Main body portion 314b: Connecting portion 32: Plate-shaped conductive member 321: Suspension portion 321a: Extension portion 321b: Base end 321c: Extension portion 321d: Base end 321e: Extension portion 321f: Base end 322: Bonding portion 322a: Strip portion 323: Bonding portion 324: Eaves portion 324a: Main body portion 324b: Linking portion 33 to 36: Bonding layer 41A, 41B, 42A, 42B: Connection member 50: Sealing resin 51: Resin main surface 52: Resin back surface 53, 54, 55: Side surface 56: Recess 57: Groove portion 581: Recess 582: Recess

Claims

1. a semiconductor chip having a main surface facing one side in a thickness direction and a first main surface electrode disposed on the main surface; a conduction target spaced apart from the semiconductor chip and electrically connected to the first principal surface electrode; a plate-shaped conductive member including a first bonding portion bonded to the first principal surface electrode, a second bonding portion bonded to the conduction target, and a suspension portion connecting the first bonding portion and the second bonding portion; a conductive bonding layer that bonds the first bonding portion and the first principal surface electrode; a sealing resin that covers the semiconductor chip, a portion of the conduction target, the plate-shaped conductive member, and the bonding layer; Equipped with the plate-shaped conductive member includes an eave portion different from the suspension portion, The semiconductor device, wherein the overhanging portion is not in contact with the bonding layer and overlaps the outer periphery of the semiconductor chip when viewed in the thickness direction.

2. The semiconductor device according to claim 1 , wherein the overhanging portion extends from the first bonding portion.

3. the overhanging portion includes at least one main body portion overlapping the outer periphery of the semiconductor chip when viewed in the thickness direction, and at least one connecting portion connecting the first bonding portion and the at least one main body portion; the first joint portion is connected to the suspension portion from one side in a first direction perpendicular to the thickness direction, the at least one connecting portion extends from the first joint portion in a second direction perpendicular to the thickness direction and the first direction; The semiconductor device according to claim 2 , wherein the at least one body portion extends in the first direction.

4. The semiconductor device according to claim 3 , wherein the at least one main body portion overlaps at least one of four corners of the semiconductor chip.

5. the at least one body portion includes a pair of body portions spaced apart in the second direction; the pair of main body portions are arranged to sandwich the first joint portion in the second direction, the at least one connecting portion includes a pair of connecting portions spaced apart in the second direction, one of the pair of connecting portions extends from the first joint portion in one of the second directions and is connected to one of the pair of main body portions; The semiconductor device according to claim 3 , wherein the other of the pair of connecting portions extends from the first joint portion in the other of the second direction and is connected to the other of the pair of main body portions.

6. the outer periphery of the semiconductor chip has a pair of edges spaced apart in the second direction when viewed in the thickness direction and extending in the first direction when viewed in the thickness direction; The semiconductor device according to claim 5 , wherein the pair of main body portions overlap the entire pair of end edges when viewed in the thickness direction.

7. the first joint portion includes a plurality of strip portions arranged in the second direction, the one of the pair of connecting portions is connected to the band-shaped portion among the plurality of band-shaped portions that is located furthest in the one direction in the second direction, The semiconductor device according to claim 5 , wherein the other of the pair of connecting portions is connected to a strip portion of the plurality of strip portions that is located furthest from the other in the second direction.

8. 8 . The semiconductor device according to claim 3 , wherein a position of the at least one body portion in the thickness direction and a position of the first joint portion in the thickness direction are offset from each other.

9. The semiconductor device according to claim 8 , wherein an end of said at least one connecting portion that is connected to said at least one main body portion is bent in said thickness direction.

10. The semiconductor device according to claim 9 , wherein the at least one body portion is spaced apart from the semiconductor chip in the thickness direction.

11. The semiconductor device according to claim 10 , wherein the at least one body portion is located on the one side in the thickness direction relative to the first joint portion.

12. 12 . The semiconductor device according to claim 11 , wherein the amount of misalignment between the at least one main body portion and the first joint portion in the thickness direction is 50% to 300% of the thickness of the suspension portion.

13. The semiconductor device according to claim 9 , wherein the thickness of said plate-shaped conductive member is uniform over the entirety of said plate-shaped conductive member.

14. 8. The semiconductor device according to claim 1, wherein the thickness of the overhanging portion is 50% to 300% of the thickness of the suspension portion.

15. the semiconductor chip includes a second principal surface electrode disposed on the principal surface; 8. The semiconductor device according to claim 1, wherein the plate-shaped conductive member does not overlap the second principal surface electrode when viewed in the thickness direction.

16. further comprising a die pad to which the semiconductor chip is bonded; the conduction object is a first lead spaced apart from the die pad, 8. The semiconductor device according to claim 1, wherein the first lead includes a covering portion that is covered with the sealing resin and to which the second bonding portion is bonded, and an exposed portion that is connected to the covering portion and is exposed from the sealing resin.

17. a second lead spaced apart from the first lead and connected to the die pad; the semiconductor chip has a back surface facing the opposite side to the main surface in the thickness direction, and a back surface electrode disposed on the back surface; the back surface electrode is electrically connected to the die pad; 17. The semiconductor device according to claim 16, wherein the second lead includes a second covered portion covered with the sealing resin, and a second exposed portion connected to the second covered portion and exposed from the sealing resin.

18. The semiconductor chip is a first semiconductor chip, and a second semiconductor chip is electrically connected to the first semiconductor chip, The semiconductor device according to claim 1 , wherein the second semiconductor chip is covered with the sealing resin.

19. the first semiconductor chip is either a transistor or a diode; 20. The semiconductor device according to claim 18, wherein the second semiconductor chip is either a transistor or a diode.