Silicon nitride substrate and silicon nitride circuit board using same

Abstract

The present invention provides: a silicon nitride substrate which is capable of reducing bonding failure; and a silicon nitride circuit board which uses the silicon nitride substrate. When recesses and projections in a 6 mm × 6 mm area of at least one surface of a silicon nitride substrate according to one embodiment are observed, the maximum roughness height that is the difference between the height of the maximum projection and the depth of the maximum recess is 50 µm or less. The area comprises: a first region, the height ratio of which to the maximum roughness height is 0.8 to 1.0; a second region, the height ratio of which to the maximum roughness height is not less than 0.5 but less than 0.8; a third region, the height ratio of which to the maximum roughness height is not less than 0.3 but less than 0.5; and a fourth region, the height ratio of which to the maximum roughness height is not less than 0 but less than 0.3. The ratio of the area of the first region to the total area of the first to fourth regions is 1% to 10%, the ratio of the area of the second region to the total area is 10% to 50%, the ratio of the area of the third region to the total area is 20% to 50%, and the ratio of the area of the fourth region to the total area is 10% to 60%.

Description

Silicon nitride substrate and silicon nitride circuit board using the same

[0001] The embodiments described below relate to a silicon nitride substrate and a silicon nitride circuit substrate using the same.

[0002] In recent years, as industrial equipment has become more sophisticated, the power modules installed in them have become increasingly powerful. This has led to an increase in the power output of semiconductor elements. The guaranteed operating temperature for semiconductor elements is 125°C to 150°C, but this may rise to 175°C or higher in the future. As the amount of heat generated by semiconductor elements increases, silicon nitride substrates are increasingly being used.

[0003] For example, Japanese Patent No. 6293772 (Patent Document 1) discloses a silicon nitride substrate having a thermal conductivity of 50 W / m·K or more and a three-point bending strength of 600 MPa or more. In the manufacturing process of a silicon nitride substrate, α-type silicon nitride powder contained in the raw material powder undergoes grain growth into β-type silicon nitride crystal particles during the sintering process. The grain-grown β-type silicon nitride crystal particles become intricately intertwined, thereby increasing the strength of the silicon nitride substrate.

[0004] The three-point bending strength of aluminum nitride substrates and aluminum oxide substrates is approximately 300 to 450 MPa. As shown in Patent Document 1, silicon nitride substrates with thermal conductivities of 50 W / m·K or higher, and even 80 W / m·K or higher, have been developed. As such, silicon nitride substrates combine high strength with heat dissipation properties.

[0005] On the other hand, surface irregularities pose a problem for silicon nitride substrates. Because β-type silicon nitride crystal particles are elongated crystal particles, irregularities are likely to occur on the surface of silicon nitride substrates. Silicon nitride substrates are bonded to metal plates and used as silicon nitride circuit substrates. For example, in Japanese Patent No. 6789955 (Patent Document 2), metal plates are bonded using an active metal bonding method. The active metal method is a bonding method that uses a bonding brazing material containing an active metal such as titanium. Large surface irregularities on silicon nitride substrates have been a cause of poor bonding.

[0006] Regarding surface irregularities, for example, Japanese Patent No. 3539634 (Patent Document 3) discloses a silicon nitride substrate in which the difference in height between the peaks and valleys on the substrate surface is set to 1.5 to 15 μm.

[0007] Patent No. 6293772 Patent No. 6789955 Patent No. 3539634

[0008] By reducing the surface roughness of silicon nitride substrates, improvements in bonding strength were observed. However, further improvement in TCT characteristics was required. When TCT (thermal cycle test) was performed, cracks occurred in the bonding layer. Investigation into the cause of this problem revealed that the distribution of surface roughness was related. The present embodiment is intended to address these issues and to provide a silicon nitride substrate with a controlled distribution of surface roughness.

[0009] When the unevenness of a 6 mm × 6 mm portion on at least one surface of the silicon nitride substrate according to the embodiment is observed, the maximum unevenness height, which is the difference between the height of the largest convex portion and the depth of the largest concave portion, is 50 μm or less. The portion includes a first region having a height ratio to the maximum unevenness height of 0.8 to 1.0, a second region having the height ratio of 0.5 to less than 0.8, a third region having the height ratio of 0.3 to less than 0.5, and a fourth region having the height ratio of 0 to less than 0.3. The ratio of the area of ​​the first region to the total area of ​​the first to fourth regions is 1% to 10%, the ratio of the area of ​​the second region to the total area is 10% to 50%, the ratio of the area of ​​the third region to the total area is 20% to 50%, and the ratio of the area of ​​the fourth region to the total area is 10% to 60%.

[0010] 1 is a perspective view showing an example of a silicon nitride substrate according to an embodiment; a schematic diagram showing an example of a maximum unevenness height; a plan view showing an example of an unevenness distribution on the surface of a silicon nitride substrate; a side view showing an example of a silicon nitride circuit substrate according to an embodiment; and a side view showing an example of a semiconductor device according to an embodiment.

[0011] When the unevenness of a 6 mm × 6 mm portion on at least one surface of the silicon nitride substrate according to the embodiment is observed, the maximum unevenness height, which is the difference between the height of the largest convex portion and the depth of the largest concave portion, is 50 μm or less. The portion includes a first region having a height ratio to the maximum unevenness height of 0.8 to 1.0, a second region having the height ratio of 0.5 to less than 0.8, a third region having the height ratio of 0.3 to less than 0.5, and a fourth region having the height ratio of 0 to less than 0.3. The ratio of the area of ​​the first region to the total area of ​​the first to fourth regions is 1% to 10%, the ratio of the area of ​​the second region to the total area is 10% to 50%, the ratio of the area of ​​the third region to the total area is 20% to 50%, and the ratio of the area of ​​the fourth region to the total area is 10% to 60%.

[0012] Fig. 1 is a perspective view showing an example of a silicon nitride substrate according to an embodiment. In Fig. 1, reference numeral 1 denotes a silicon nitride substrate, and reference numeral 2 denotes a surface. Fig. 1 illustrates a silicon nitride substrate 1 having a rectangular surface 2. The shape of the surface 2 is not limited to a rectangle, and may be various shapes such as a square, a circle, a pentagon, an L-shape, or a U-shape. As will be described later, the surface 2 of the silicon nitride substrate 1 can be used as a surface on which a circuit portion is provided.

[0013] When the irregularities on at least one surface 2 of a silicon nitride substrate 1 are observed in a 6 mm × 6 mm area, the maximum irregularity height, which is the difference in height between the largest convex portion and the largest concave portion, is 50 μm or less. Figure 2 is a schematic diagram showing an example of the maximum irregularity height. In Figure 2, reference numeral 2 denotes the surface, reference numeral 3 denotes the largest convex portion, reference numeral 4 denotes the largest concave portion, and reference numeral 5 denotes the maximum irregularity height.

[0014] First, the unevenness of an arbitrary 6 mm x 6 mm portion on surface 2 is observed. A three-dimensional shape measuring device is used to observe the unevenness. The three-dimensional shape measuring device used is a VR-3000 manufactured by Keyence Corporation or a device with performance equivalent to or better than that.

[0015] When measured with a three-dimensional shape measuring device, the highest point in a 6 mm x 6 mm area is defined as maximum convexity 3. The lowest point is defined as maximum concavity 44. The difference in height between maximum convexity 3 and maximum concavity 4 is defined as maximum irregularity height 5. The position of the highest point in the 6 mm x 6 mm area in the perpendicular direction to the surface is maximum convexity 3. The position of the lowest point in the 6 mm x 6 mm area in the perpendicular direction to the surface is maximum concavity depth 4. Maximum irregularity height 5 is expressed as the distance in the perpendicular direction between maximum convexity 3 and maximum concavity depth 4. The perpendicular direction to the surface is the direction perpendicular to surface 2 when surface 2 is viewed macroscopically.

[0016] In the silicon nitride substrate according to the embodiment, the maximum irregularity height 5 is 50 μm or less. If the maximum irregularity height 5 exceeds 50 μm, it can cause poor bonding. Furthermore, in any 6 mm × 6 mm portion of the surface 2, the maximum irregularity height 5 is 50 μm or less. In other words, no matter which 6 mm × 6 mm portion is observed, the maximum irregularity height 5 is 50 μm or less.

[0017] The size of the area to be observed is set to 6 mm x 6 mm because it provides good measurement accuracy. If the size is larger than 6 mm x 6 mm, undulations in the board may be detected, which may reduce measurement accuracy. If the size is smaller than 6 mm x 6 mm, the number of measurements may increase, which may reduce inspection efficiency.

[0018] Furthermore, in the silicon nitride substrate 1 according to the embodiment, when a 6 mm x 6 mm area is observed, first to fourth regions are present. The first region is a region where the height ratio to the maximum irregularity height 5 is 0.8 or more and 1.0 or less. The second region is a region where the height ratio to the maximum irregularity height 5 is 0.5 or more and less than 0.8. The third region is a region where the height ratio to the maximum irregularity height 5 is 0.3 or more and less than 0.5. The fourth region is a region where the height ratio to the maximum irregularity height 5 is 0 or more and less than 0.3.

[0019] After observing the 6 mm x 6 mm area, image analysis of this area is performed. First, the maximum irregularity height 5 in the 6 mm x 6 mm area is measured. Next, the height of each measurement area in the 6 mm x 6 mm area is measured. The "measurement area" corresponds to the laser spot diameter of the 3D shape measuring instrument. The "height" is the position of each measurement area in the perpendicular direction to the surface when the maximum recess depth 4 is used as the reference. The height of the measurement area / maximum irregularity height = height ratio.

[0020] For example, assume that the maximum irregularity height 5 is 30 μm. In this case, the first region having a height ratio of 0.8 or more and 1.0 or less to the maximum irregularity height 5 refers to a region having a height in the range of 24 μm or more and 30 μm or less. The second region having a height ratio of 0.5 or more and less than 0.8 to the maximum irregularity height 5 refers to a region having a height in the range of 15 μm or more and less than 24 μm. The third region having a height ratio of 0.3 or more and less than 0.5 to the maximum irregularity height 5 refers to a region having a height in the range of 9 μm or more and less than 15 μm. The fourth region having a height ratio of 0 or more and less than 0.3 to the maximum irregularity height 5 refers to a region having a height in the range of 0 μm or more and less than 9 μm.

[0021] In a 6 mm x 6 mm portion, the total area of ​​the first to fourth regions is 100%. In this case, the area ratio of the first region to the total area is 1% or more and 10% or less. The area ratio of the second region to the total area is 10% or more and 50% or less. The area ratio of the third region to the total area is 20% or more and 50% or less. The area ratio of the fourth region to the total area is 10% or more and 60% or less.

[0022] When using a Keyence VR-3000, for example, the first region can be displayed in red, the second region in orange or yellow, the third region in yellow-green, and the fourth region in light blue or blue. By calculating the area of ​​the region displayed in each color, the area ratio of each of the first to fourth regions can be calculated. It is also effective to use the color mapping function of a 3D shape measuring instrument to measure the area ratio.

[0023] 3 is a plan view showing an example of the unevenness distribution on the surface of a silicon nitride substrate, in which reference numeral 2 denotes a surface, reference numeral 6 denotes a first region, reference numeral 7 denotes a second region, reference numeral 8 denotes a third region, and reference numeral 9 denotes a fourth region.

[0024] In the silicon nitride substrate 1 according to the embodiment, the area ratio of the first region 6 is 1% or more and 10% or less. The height ratio of the first region 6 is 0.8 or more and 1.0 or less, and the first region 6 includes the highest point. In other words, the area ratio of the most convex region to the maximum recess depth 4 is controlled to 1% or more and 10% or less. In order to suppress the occurrence of bonding defects, it is effective to control the distribution of the unevenness rather than controlling local unevenness as in the conventional method. If the area ratio of the first region 6 exceeds 10%, the area of ​​the most convex region to the maximum recess depth 4 becomes large, which can cause bonding defects.

[0025] It is also important that the second region 7, the third region 8, and the fourth region 9 are present in a predetermined proportion. This can mitigate the impact of unevenness on the bond in a narrow area of ​​6 mm x 6 mm. Specifically, the area ratio of the fourth region is 10% or more and 60% or less. The height ratio of the fourth region 9 is 0 or more and less than 0.3, and the fourth region 9 includes the lowest point. If the area ratio of the fourth region is less than 10%, the proportion of localized depressions increases, causing bond failure. The area ratio of the second region is 10% or more and 50% or less. The area ratio of the third region is 20% or more and 50% or less. By having the second region and the third region present in these proportions, abrupt changes in the unevenness on the surface 2 can be suppressed, and the bond strength can be increased.

[0026] Here, the area of ​​the first region 6 is defined as A1, the area of ​​the second region 7 as A2, the area of ​​the third region 8 as A3, and the area of ​​the fourth region 9 as A4. The ratio of the area of ​​the second region 7 to the area of ​​the first region 6 is preferably within the range of 2≦A2 / A1≦30. In other words, the area of ​​the second region 7 is within the range of 2 to 30 times the area of ​​the first region 6. By providing a larger number of second regions 7 than the first region 6, it is possible to prevent the first region 6 from protruding convexly.

[0027] The area ratios of the second region 7, the third region 8, and the fourth region 9 preferably satisfy the relationship 3≦(A3+A4) / A2. In other words, the total area of ​​the third region 8 and the fourth region 9 is at least three times the area of ​​the second region 7. By providing more third region 8 and fourth region 9 than the second region 7, the influence of unevenness caused by the second region 7 can be alleviated. Furthermore, by combining this with the relationship 2≦A2 / A1≦30, an even greater effect can be obtained.

[0028] When the maximum unevenness height is 5 μm or more and 25 μm or less, it is preferable to satisfy 0.3≦(A2+A3) / (A1+A2+A3+A4)≦0.6. A maximum unevenness height 5 of 5 μm or more and 25 μm or less indicates that the maximum unevenness height 5 is at a medium level (medium unevenness). In this case, it is preferable that the ratio of the total area of ​​the second region 7 and the third region 8 within a 6 mm × 6 mm area is in the range of 30% to 60%. Since the area ratio of the first region 6 is 1% to 10%, the remainder excluding the second region 7 and the third region 8 is the fourth region 9. In other words, when the maximum unevenness height 5 is 5 μm or more and 25 μm or less, it is effective to increase the ratio of the fourth region 9. The condition 0.3≦(A2+A3) / (A1+A2+A3+A4)≦0.6 may be combined with one or more conditions selected from 2≦A2 / A1≦30 and 3≦(A3+A4) / A2.

[0029] When the maximum unevenness height is greater than 25 μm and less than or equal to 50 μm, it is preferable to satisfy the condition 0.5≦(A2+A3) / (A1+A2+A3+A4)≦0.8. A maximum unevenness height 5 of greater than 25 μm and less than or equal to 50 μm indicates that the maximum unevenness height 5 is high (large unevenness). In this case, it is preferable that the total area of ​​the second region 7 and the third region 8 in a 6 mm × 6 mm area is in the range of 50% to 80%. In other words, it is effective to increase the total area of ​​the second region 7 and the third region 8 compared to when the maximum unevenness height 5 is medium (5 μm to 25 μm). The condition 0.5≦(A2+A3) / (A1+A2+A3+A4)≦0.8 may be combined with one or more conditions selected from 2≦A2 / A1≦30 and 3≦(A3+A4) / A2.

[0030] In the 6 mm × 6 mm portion, it is preferable that both the second region 7 and the third region 8 exist between the first region 6 and the fourth region 9. More specifically, when a line is drawn connecting the largest convex portion 3 and the largest concave portion 4 in the 6 mm × 6 mm portion, it is preferable that both the second region 7 and the third region 8 exist on that line.

[0031] For example, in the 6 mm × 6 mm portion shown in Figure 3, the largest convex portion 3 and the largest concave portion 4 are present in the first region 6 and the fourth region 9, respectively, which are located near the center. If the largest convex portion 3 and the largest concave portion 4 are connected by a straight line L, then both the second region 7 and the third region 8 are present on the straight line L.

[0032] The first region 6 is a region whose height ratio to the maximum unevenness height 5 is 0.8 or more and 1.0 or less. The fourth region 9 is a region whose height ratio to the maximum unevenness height 5 is 0 or more and less than 0.3. The presence of both the second region 7 and the third region 8 between the maximum convex portion 3 and the maximum concave portion 4 makes it possible to make the slope from the highest maximum convex portion 3 to the lowest maximum concave portion 4 gentler. This makes it possible to reduce the effect of the unevenness.

[0033] In the 6 mm x 6 mm portion, the influence of unevenness can be alleviated by controlling the distribution of the first to fourth regions. In other words, even if a certain amount of unevenness exists, it is possible to reduce defects by controlling the distribution of the first to fourth regions.

[0034] The thickness of the silicon nitride substrate 1 is preferably in the range of 0.2 mm to 3 mm. If the substrate thickness is less than 0.2 mm, the insulating properties may be reduced. As mentioned above, the surface 2 of the silicon nitride substrate 1 according to the embodiment has irregularities. If the substrate is too thin, the influence of the irregularities becomes greater, and the insulating properties may be reduced. If the substrate is thicker than 3 mm, the insulating properties will be improved, but the substrate may become a thermal resistor and the heat dissipation properties may be reduced. For this reason, the thickness of the silicon nitride substrate 1 is preferably in the range of 0.2 mm to 3 mm, and more preferably in the range of 0.2 mm to 1 mm.

[0035] The specific size of the silicon nitride substrate 1 is arbitrary. For example, the size of the silicon nitride substrate 1 may be 50 mm or more in length and 50 mm or more in width. For a silicon nitride substrate 1 larger than 50 mm in length and 50 mm in width, controlling the unevenness in the 6 mm x 6 mm portion can provide better results. A large-sized silicon nitride substrate can be produced in multiple pieces. Multi-piece production means scribing the silicon nitride substrate to divide it into smaller pieces. This improves mass productivity. The scribing may be performed before or after bonding the metal plate. Bonding defects in a large-sized silicon nitride substrate have a significant impact on yield. For this reason, controlling the unevenness is more effective.

[0036] The thermal conductivity of the silicon nitride substrate 1 is preferably 50 W / m·K or more, and more preferably 80 W / m·K or more. The thermal conductivity is measured by a flash method. The thermal conductivity is measured in accordance with JIS-R-1611. JIS-R-1611 corresponds to ISO 18755. The three-point bending strength of the silicon nitride substrate is preferably 500 MPa or more, and more preferably 600 MPa or more. The three-point bending strength is measured in accordance with JIS-R-1601. JIS-R-1601 corresponds to ISO 14704.

[0037] The silicon nitride substrate 1 described above can be used as a silicon nitride circuit board provided with a circuit portion, which can be a metal plate, a metallized layer, a thin film, or the like.

[0038] Examples of the metal plate include a copper plate (including a copper alloy) and an aluminum plate (including an aluminum alloy). If necessary, the metal plate may be bonded to the silicon nitride substrate 1 via a bonding layer. Examples of bonding methods include an active metal bonding method using an active metal. When bonding a copper plate, the active metal bonding method uses an active metal brazing material containing an active metal such as Ti. When bonding an aluminum plate, an active metal brazing material containing an active metal such as Si is used.

[0039] The metallized layer is formed by applying a metal paste to the silicon nitride substrate 1 and firing it. The metallized layer contains, for example, one selected from Ag (silver), Cu (copper), Mo (molybdenum), and W (tungsten) as a main component. The thin film is a conductive film formed by sputtering or vapor deposition.

[0040] FIG. 4 is a side view showing an example of a silicon nitride circuit substrate according to an embodiment. In FIG. 4, 1 denotes a silicon nitride substrate, 10 denotes a silicon nitride circuit substrate, 11 denotes a circuit portion, 12 denotes a bonding layer, and 13 denotes a heat dissipation portion. The silicon nitride circuit substrate 10 includes a silicon nitride substrate 1 and a circuit portion 11 provided on at least one surface of the silicon nitride substrate 1. In the example shown in FIG. 4, the circuit portion 11 is provided on the front surface of the silicon nitride substrate 1, and a heat dissipation portion 13 is provided on the back surface. The circuit portion 11 and the heat dissipation portion 13 are each bonded to the silicon nitride substrate 1 via a bonding layer 12. For example, the circuit portion 11 made of a metal plate can be provided on the front surface, and the heat dissipation portion 13 made of a metal plate can be provided on the back surface. If necessary, the circuit portions 11 may be provided on both surfaces of the silicon nitride substrate 1. Furthermore, the number of circuit portions 11 provided on the front surface is arbitrary. Not limited to the illustrated example, one circuit portion 11, or three or more circuit portions 11 may be provided on the front surface.

[0041] The silicon nitride circuit substrate 10 according to the embodiment can suppress bonding defects between the surface 2 and the circuit portion 11. Bonding defects after a TCT test can also be reduced. Because the effect of surface irregularities on the silicon nitride substrate 1 is mitigated, the occurrence of minute gaps at the bonding interface between the silicon nitride substrate 1 and the circuit portion 11 can be suppressed. If minute gaps exist at the bonding interface between the silicon nitride substrate 1 and the circuit portion 11, the gaps may become larger after a TCT test, potentially causing bonding defects. Bonding defects can be measured by ultrasonic testing (SAT).

[0042] When metal plates are to be joined, an active metal joining method is used. In this method, an active metal brazing material containing an active metal is applied and fired to join the silicon nitride substrate 1 and the metal plate. A joining layer 12 is formed by firing the brazing material layer.

[0043] If the unevenness difference on the surface 2 of the silicon nitride substrate 1 is large, gaps are likely to form between the silicon nitride substrate 1 and the brazing material layer when an active metal brazing material is applied. If there is a gap between the silicon nitride substrate 1 and the brazing material layer, gaps are also likely to form between the silicon nitride substrate 1 and the bonding layer 12. For example, an active metal brazing material containing Ti reacts with the silicon nitride substrate 1 to form a titanium nitride layer. The formation of the titanium nitride layer firmly bonds the silicon nitride substrate 1 to the metal plate. The formation of a gap between the silicon nitride substrate 1 and the bonding layer 12 adversely affects the strong bond. In other words, the embodiment of the present invention is suitable for a silicon nitride circuit substrate 10 to which a metal plate is bonded using an active metal bonding method. By controlling the maximum unevenness height 5 and the respective proportions of the first region 6 to the fourth region 9 on the surface 2 of the silicon nitride substrate 1, gaps are less likely to form between the silicon nitride substrate 1 and the bonding layer 12. As a result, the bonding strength between the silicon nitride substrate 1 and the metal plate can be increased.

[0044] The silicon nitride circuit substrate 10 can be used in a semiconductor device on which a semiconductor element is mounted. Fig. 5 is a side view showing an example of a semiconductor device according to an embodiment. In Fig. 5, reference numeral 10 denotes a silicon nitride circuit substrate, reference numeral 14 denotes a semiconductor element, and reference numeral 20 denotes a semiconductor device. While Fig. 5 shows an example in which one semiconductor element 14 is mounted, multiple semiconductor elements 14 may also be mounted. Furthermore, a lead frame or wire bonding (not shown) may be provided. Sealing with resin may also be performed.

[0045] Next, a method for manufacturing the silicon nitride substrate 1 according to the embodiment will be described. The method for manufacturing the silicon nitride substrate 1 according to the embodiment is not particularly limited as long as it has the above-mentioned properties. Here, an example of a method for obtaining the silicon nitride substrate 1 with a good yield will be described.

[0046] The manufacturing process for silicon nitride substrates includes a raw material mixing process, a molding process, a degreasing process, and a sintering process. In the raw material mixing process, a raw material powder is prepared by mixing silicon nitride powder, the main component, with a sintering aid powder. An organic binder is mixed with the raw material powder to prepare a raw material paste. Either direct nitride powder or powder obtained by the imide decomposition method can be used as the silicon nitride powder. In the molding process, a silicon nitride sheet is prepared from the raw material paste. Methods for preparing a silicon nitride sheet include the doctor blade method, mold molding, and injection molding.

[0047] Next, a degreasing step and a sintering step are performed. The degreasing step and the sintering step are preferably performed by placing a sheet-shaped silicon nitride molded body on a boron nitride plate. It is preferable that the surface of the boron nitride plate does not have any recesses with a depth of 40 μm or more. Furthermore, it is preferable that the maximum height roughness Rz of the surface of the boron nitride plate is 40 μm or less. The amount of warping of the boron nitride plate is preferably 0.1 mm or less. The warping of the boron nitride plate is defined as the greatest distance between the boron nitride plate and a straight line connecting one end of the boron nitride plate to the opposite end. It is preferable that the amount of warping of the boron nitride plate in the long side direction, short side direction, and diagonal direction is 0.2 mm or less.

[0048] In the degreasing process, the binder is removed from the sheet-shaped silicon nitride molded body. The sheet-shaped silicon nitride molded body is called a silicon nitride molded body. The silicon nitride molded body is placed on a boron nitride plate. A single layer of silicon nitride molded body may be placed, or multiple silicon nitride molded bodies may be stacked. A weight plate may be placed on the silicon nitride molded body. A layered structure of boron nitride plate and silicon nitride molded body may be used, such as boron nitride plate / silicon nitride molded body / boron nitride plate / silicon nitride molded body. When silicon nitride molded bodies are stacked, a layering powder may be used between the silicon nitride molded bodies. The layering powder is preferably boron nitride powder with an average particle size of 10 μm or less. A layering powder with a small particle size can reduce the surface unevenness of the silicon nitride substrate 1. For this reason, the average particle size of the layering powder is preferably 10 μm or less, and more preferably 6 μm or less. The use of a weight plate also has the effect of suppressing warping of the silicon nitride substrate 1. Similarly, by adopting a laminated structure of a boron nitride plate and a silicon nitride molded body, the effect of suppressing warpage of the silicon nitride substrate 1 can be obtained.

[0049] The degreasing step is preferably carried out within a temperature range of 350° C. to 600° C. The degreasing step removes the organic binder from the silicon nitride molded body, and a silicon nitride degreased body is obtained by the degreasing step.

[0050] In the sintering step, the silicon nitride degreased body is sintered. The sintering step is preferably carried out within a temperature range of 1600°C to 2000°C. The sintering step may be carried out in a vacuum, in the air, in an inert atmosphere, or the like. The pressure in the sintering step is set to normal pressure or applied pressure.

[0051] The above steps can produce the silicon nitride substrate 1. If necessary, steps such as a step of removing the powder, a cleaning step, and a step of correcting warping may be performed. The surface of the silicon nitride substrate 1 may be inspected, and only the silicon nitride substrate 1 included in the embodiment may be selected.

[0052] Examples (Examples 1-7, Comparative Examples 1-2) A raw material powder was prepared by mixing silicon nitride powder and a sintering aid. A binder and other additives were added to the raw material powder, and a silicon nitride sheet was produced by the doctor blade method. A boron nitride plate and boron nitride bedding powder were used to carry out a degreasing process and a sintering process for the silicon nitride sheet. The degreasing process was carried out at a temperature range of 350°C to 600°C. The sintering process was carried out at a temperature range of 1600°C to 2000°C. A silicon nitride substrate was thus obtained. The size of the silicon nitride substrate was 120 mm long x 100 mm wide. The boron nitride plate and boron nitride bedding powder used are as shown in Table 1.

[0053]

[0054] In the examples, the preferred manufacturing conditions are met. In comparative example 1, the boron nitride plate has small warpage but large irregularities. In comparative example 1, the average particle size of the powder is larger than in the examples. In comparative example 2, the boron nitride plate has small irregularities but large warpage.

[0055] The surface unevenness of the obtained silicon nitride substrate was inspected. Multiple 6 mm x 6 mm sections were randomly selected on the surface of the silicon nitride substrate, and the unevenness of each section was observed. A three-dimensional shape measuring machine (VR-3000 manufactured by Keyence Corporation) was used to observe the unevenness. The method for measuring the maximum unevenness height and the area ratios of the first to fourth regions was as described above. The area ratios of each of the first to fourth regions were calculated assuming that the sum of the areas of the first to fourth regions was 100%. The results are shown in Table 2. In Table 2, "YES" indicates that the area ratio of each region was within the specified range. "NO" indicates that the area ratio of each region was outside the specified range.

[0056]

[0057] In the examples, the maximum unevenness height was 50 μm or less in all 6 mm × 6 mm portions, and the area ratio of each region was within a predetermined range. In the examples, the preferred conditions for the maximum unevenness height and area ratio were met. In Example 1, there was a mixture of regions where the maximum unevenness height was 5 μm or more and 25 μm or less, and regions where it was more than 25 μm and less than 50 μm. In Comparative Example 1, there was a portion where the maximum unevenness height was 83 μm. In other words, in Comparative Example 1, the area ratio of each region was within the predetermined range, but there was a portion where the maximum unevenness height exceeded 50 μm. In Comparative Example 2, the area ratio of the first region was 15%, and the area ratio of the second region was 5%. In other words, in Comparative Example 2, the maximum unevenness height was 50 μm, but there were portions where the area ratio of the first region and the area ratio of the second region were outside the range.

[0058] Next, the silicon nitride substrates according to Example 1 were classified according to the area ratios of the respective regions. Specifically, the area of ​​the first region 6 was defined as A1, the area of ​​the second region 7 as A2, the area of ​​the third region 8 as A3, and the area of ​​the fourth region 9 as A4. Each substrate was then evaluated to determine whether it satisfied the following conditions: 2≦A2 / A1≦30, 3≦(A3+A4) / A2, 0.3≦(A2+A3) / (A1+A2+A3+A4)≦0.6, and 0.5≦(A2+A3) / (A1+A2+A3+A4)≦0.8. It was also determined whether both the second region and the third region were present between the maximum convex portion and the maximum concave portion. Example 1 was classified into Examples 2 to 7 according to whether each condition was satisfied. The results are shown in Table 3. In Table 3, "YES" indicates that the condition was satisfied, and "NO" indicates that the condition was not satisfied. The condition 0.3≦(A2+A3) / (A1+A2+A3+A4)≦0.6 was determined for Examples 2 to 4, in which the maximum irregularity height was 5 μm or more and 25 μm or less. The condition 0.5≦(A2+A3) / (A1+A2+A3+A4)≦0.8 was determined for Examples 5 to 7, in which the maximum irregularity height was more than 25 μm and 50 μm or less.

[0059]

[0060] Table 4 also shows the results of measuring the maximum irregularity height and the area ratios of the first to fourth regions in any 6 mm×6 mm area of ​​the silicon nitride substrates according to Examples 2 to 7.

[0061]

[0062] Next, metal plates were bonded to the front and back surfaces of the silicon nitride substrate using an active metal bonding method. A 0.8 mm thick copper plate was bonded to the front surface to form a circuit section. A 0.8 mm thick copper plate was bonded to the back surface as a heat sink. A brazing filler metal containing Ti as the active metal was used. The copper plate on the front surface was etched to give it a circuit shape, forming the circuit section. A silicon nitride circuit substrate was produced through these processes.

[0063] The silicon nitride circuit boards according to the examples and comparative examples were examined for the presence or absence of bonding defects. Bonding defects were examined by ultrasonic testing (SAT). Examples in which the area ratio of bonding defects in the circuit section was 0% or more and 1% or less were rated "excellent." Examples in which the area ratio of bonding defects was more than 1% and 3% or less were rated "good." Examples in which the area ratio of bonding defects was more than 3% and 5% or less were rated "passable." Examples in which the area ratio of bonding defects exceeded 5% were rated "unacceptable." The area ratio of bonding defects was measured for 10 silicon nitride circuit boards for each example and comparative example, and the result with the largest area ratio of bonding defects was recorded.

[0064] In addition, bonding failures were examined after the TCT test. In the TCT test, one cycle consisted of 30 minutes at -40°C, 10 minutes at room temperature, 30 minutes at 150°C, and 10 minutes at room temperature, and the area ratio of bonding failures was measured after 4,000 cycles. The area ratio of bonding failures was measured for 10 silicon nitride circuit boards for each example and comparative example, and the result with the largest area ratio of bonding failures was recorded. The results are shown in Table 5.

[0065]

[0066] As can be seen from Table 5, bonding defects were reduced in the silicon nitride circuit boards according to the examples. In particular, in Examples 2 and 5, which satisfied all of the preferred conditions, the area ratio of bonding defects was small even after the TCT test, and the decrease in bonding strength due to TCT was suppressed. In contrast, in Comparative Example 1, the maximum unevenness height was large, so the area ratio of bonding defects was large before the TCT test. In Comparative Example 2, although the maximum unevenness height was small, the ratios of the first and second regions were outside the preferred range. Therefore, the area ratio of bonding defects was relatively large before the TCT test, and the area ratio further increased after the TCT test.

[0067] Embodiments of the present invention include the following features: (Feature 1) A silicon nitride substrate, wherein, when unevenness is observed in a 6 mm x 6 mm area on at least one surface of the silicon nitride substrate, a maximum unevenness height, which is the difference between the height of the largest convex portion and the depth of the largest concave portion, is 50 μm or less, the area comprising: a first region having a height ratio to the maximum unevenness height of 0.8 to 1.0, a second region having the height ratio of 0.5 to less than 0.8, a third region having the height ratio of 0.3 to less than 0.5, and a fourth region having the height ratio of 0 to less than 0.3, wherein a ratio of the area of ​​the first region to a total area of ​​the first to fourth regions is 1% to 10%, a ratio of the area of ​​the second region to the total area is 10% to 50%, a ratio of the area of ​​the third region to the total area is 20% to 50%, and a ratio of the area of ​​the fourth region to the total area is 10% to 60%. (Feature 2) The silicon nitride substrate according to Feature 1, which satisfies 2≦the area of ​​the second region / the area of ​​the first region≦30. (Feature 3) The silicon nitride substrate according to Feature 1 or Feature 2, which satisfies 3≦(the area of ​​the third region+the area of ​​the fourth region) / the area of ​​the second region. (Feature 4) The silicon nitride substrate according to any one of Features 1 to 3, wherein the maximum unevenness height is 5 μm or more and 25 μm or less, and satisfies 0.3≦(the area of ​​the second region+the area of ​​the third region) / the total area≦0.6. (Feature 5) The silicon nitride substrate according to any one of Features 1 to 3, wherein the maximum unevenness height is more than 25 μm and 50 μm or less, and satisfies 0.5≦(the area of ​​the second region+the area of ​​the third region) / the total area≦0.8. (Feature 6) The silicon nitride substrate according to any one of Features 1 to 5, wherein, in the portion, when the maximum convex portion and the maximum concave portion are connected by a straight line, both the second region and the third region are present on the straight line. (Feature 7) The silicon nitride substrate according to any one of Features 1 to 6, wherein the substrate thickness is 0.2 mm or more and 3 mm or less. (Feature 8) The silicon nitride substrate according to Feature 7, wherein the vertical dimension is 50 mm or more and the horizontal dimension is 50 mm or more.(Feature 9) A silicon nitride circuit board comprising: the silicon nitride substrate according to any one of Features 1 to 8; and a circuit portion provided on the silicon nitride substrate.

[0068] Although several embodiments of the present invention have been described above, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. Furthermore, the above-described embodiments can be implemented in combination with each other.

[0069] DESCRIPTION OF SYMBOLS 1... Silicon nitride substrate 2... Surface 3... Maximum convex portion 4... Maximum concave portion 5... Maximum concave-convex height 6... First region 7... Second region 8... Third region 9... Fourth region 10... Silicon nitride circuit substrate 11... Circuit portion 12... Bonding layer 13... Heat dissipation portion 14... Semiconductor element 20... Semiconductor device

Claims

1. A silicon nitride substrate, wherein, when unevenness is observed in a 6 mm x 6 mm portion on at least one surface of the silicon nitride substrate, a maximum unevenness height, which is the difference between the height of the largest convexity and the depth of the largest concaveity, is 50 μm or less, said portion including: a first region having a height ratio to said maximum unevenness height of 0.8 or more and 1.0 or less, a second region having said height ratio of 0.5 or more and less than 0.8, a third region having said height ratio of 0.3 or more and less than 0.5, and a fourth region having said height ratio of 0 or more and less than 0.3, wherein a ratio of an area of ​​the first region to a total area of ​​said first to fourth regions is 1% or more and 10% or less, a ratio of an area of ​​the second region to said total area is 10% or more and 50% or less, a ratio of an area of ​​the third region to said total area is 20% or more and 50% or less, and a ratio of an area of ​​the fourth region to said total area is 10% or more and 60% or less.

2. A silicon nitride substrate according to claim 1, which satisfies the following condition: 2≦the area of ​​said second region / the area of ​​said first region≦30.

3. A silicon nitride substrate according to claim 1 or 2, which satisfies 3≦(the area of ​​the third region+the area of ​​the fourth region) / the area of ​​the second region.

4. A silicon nitride substrate according to claim 1 or 2, wherein the maximum unevenness height is 5 μm or more and 25 μm or less, and 0.3≦(the area of ​​the second region+the area of ​​the third region) / the total area≦0.6 is satisfied.

5. The silicon nitride substrate according to claim 3, wherein the maximum unevenness height is 5 μm or more and 25 μm or less, and 0.3≦(the area of ​​the second region+the area of ​​the third region) / the total area≦0.6 is satisfied.

6. A silicon nitride substrate according to claim 1 or 2, wherein the maximum unevenness height is greater than 25 μm and not greater than 50 μm, and 0.5≦(the area of ​​the second region+the area of ​​the third region) / the total area≦0.8 is satisfied.

7. The silicon nitride substrate according to claim 3, wherein the maximum unevenness height is greater than 25 μm and not greater than 50 μm, and 0.5≦(the area of ​​the second region+the area of ​​the third region) / the total area≦0.8 is satisfied.

8. A silicon nitride substrate according to claim 1 or claim 2, wherein, in said portion, when a straight line is drawn between said maximum convex portion and said maximum concave portion, both said second region and said third region are present on said straight line.

9. A silicon nitride substrate according to claim 5, wherein, in said portion, when said maximum convex portion and said maximum concave portion are connected by a straight line, both said second region and said third region are present on said straight line.

10. A silicon nitride substrate according to claim 7, wherein, in said portion, when said maximum convex portion and said maximum concave portion are connected by a straight line, both said second region and said third region are present on said straight line.

11. The silicon nitride substrate according to claim 1 or 2, wherein the thickness of the substrate is 0.2 mm or more and 3 mm or less.

12. The silicon nitride substrate according to claim 5, wherein the thickness of the substrate is 0.2 mm or more and 3 mm or less.

13. The silicon nitride substrate according to claim 8, wherein the substrate has a thickness of 0.2 mm or more and 3 mm or less.

14. The silicon nitride substrate according to claim 11, having a vertical dimension of 50 mm or more and a horizontal dimension of 50 mm or more.

15. The silicon nitride substrate according to claim 12, having a vertical dimension of 50 mm or more and a horizontal dimension of 50 mm or more.

16. The silicon nitride substrate according to claim 13, having a vertical dimension of 50 mm or more and a horizontal dimension of 50 mm or more.

17. A silicon nitride circuit board comprising: the silicon nitride substrate according to claim 1 or 2; and a circuit portion provided on the silicon nitride substrate.

18. A silicon nitride circuit board comprising: the silicon nitride substrate according to claim 12; and a circuit portion provided on the silicon nitride substrate.

19. A silicon nitride circuit board comprising: the silicon nitride substrate according to claim 13; and a circuit portion provided on the silicon nitride substrate.

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