Signal generation circuit

Abstract

A control voltage source circuit (11) generates, in accordance with a control signal (k) that has been input, a control voltage (Vc) which has one voltage value from among a predetermined plurality of voltage values. A reference voltage source circuit (12) generates a predetermined plurality of reference voltages (Vr). Folding circuits (13, 14) generate, on the basis of the difference between the control voltage (Vc) and the plurality of reference voltages (Vr), output signals having a signal level corresponding to a prescribed phase of a sine wave and cosine wave. The control voltage source circuit (11) is provided with a parallel circuit of a plurality of constant current sources (62) respectively turned on or off in accordance with the control signal (k).

Description

signal generation circuit

[0001] The present disclosure relates to a signal generating circuit, a phase shifter, an array antenna device, and a wireless communication device.

[0002] In wireless communication systems beyond the fifth generation mobile communication system (Beyond 5G), the use of high frequency bands such as millimeter waves and terahertz waves is being considered to increase communication capacity. Furthermore, to increase communication capacity, the use of a phased array antenna device to focus a radio wave beam on a communication partner is being considered. The use of a phased array antenna device makes it possible to perform, for example, beamforming (directing a beam in a specific direction), beam steering (directing a beam at a communication partner), and beam tracking (continuously directing a beam at a communication partner that is moving at high speed).

[0003] To realize a phased array antenna device, a phase shifter capable of freely controlling the phase of a local signal is required. For example, Patent Document 1 discloses a vector sum type analog phase shifter used in communication devices and radar devices.

[0004] Japanese Patent Application Laid-Open No. 2003-133906

[0005] Japanese Patent Application Laid-Open No. 2006-129999 discloses a technique for reading and setting gain settings and bias voltage values ​​for four differential variable gain amplifiers from a storage device, and then synthesizing the output signals of the four differential variable gain amplifiers. However, storing such gain settings and bias voltage values ​​and processing signals based on the gain settings and bias voltage values ​​increases the circuit size and power consumption. Furthermore, it takes a certain amount of time to process the signals. Therefore, there is a need for a technique for shifting the phase of a signal faster than conventional techniques, with a smaller circuit size and power consumption than conventional techniques.

[0006] The phase shifter is also required to have a certain tolerance to process, voltage, and temperature variations (PVT variations), and may be required to have a linear control characteristic with respect to the control signal.

[0007] An object of the present disclosure is to provide a signal generation circuit that generates a signal that can be used to control a phase shifter, the signal generation circuit having a smaller circuit size and power consumption than conventional circuits, being capable of operating at higher speeds than conventional circuits, being tolerant to PVT fluctuations, and having linear control characteristics with respect to a control signal. Another object of the present disclosure is to provide a phase shifter, an array antenna device, and a wireless communication device that include such a signal generation circuit.

[0008] A signal generating circuit according to a first aspect of the present disclosure comprises: at least one control voltage source circuit that generates a control voltage having one of a plurality of predetermined voltage values ​​in response to an input control signal; at least one reference voltage source circuit that generates a plurality of predetermined reference voltages; and at least one folding circuit that generates an output signal having a signal level corresponding to a predetermined phase of a sine wave or cosine wave based on the difference between the control voltage and the plurality of reference voltages, wherein the control voltage source circuit comprises a parallel circuit of a plurality of first constant current sources that are each turned on or off in response to the control signal.

[0009] According to a signal generation circuit of a second aspect of the present disclosure, in the signal generation circuit of the first aspect, the signal generation circuit includes: a first folding circuit that generates a first output signal having a signal level corresponding to a predetermined phase of a sine wave; and a second folding circuit that generates a second output signal having a signal level corresponding to a predetermined phase of a cosine wave.

[0010] According to a third aspect of the present disclosure, there is provided a signal generation circuit according to the second aspect, wherein the first folding circuit comprises: a first differential amplifier that compares the control voltage with a first reference voltage to generate a first differential output signal; a second differential amplifier that compares the control voltage with a second reference voltage that is higher than the first reference voltage to generate a second differential output signal; and a third differential amplifier that compares the control voltage with a third reference voltage that is higher than the second reference voltage to generate a third differential output signal; and the second folding circuit comprises: a fourth differential amplifier that compares the control voltage with a fourth reference voltage to generate a fourth differential output signal; a fifth differential amplifier that compares the control voltage with a fifth reference voltage that is higher than the fourth reference voltage to generate a fifth differential output signal; and a sixth differential amplifier that compares the control voltage with a sixth reference voltage that is higher than the fifth reference voltage to generate a sixth differential output signal; The first output signal is the sum of the first and third differential output signals and an inverted signal of the second differential output signal, and the second output signal is the sum of the fourth and sixth differential output signals and an inverted signal of the fifth differential output signal.

[0011] According to a fourth aspect of the present disclosure, in the signal generation circuit of the third aspect, the control voltage source circuit supplies one common control voltage to the first to sixth differential amplifiers, and the first to sixth reference voltages are different from one another.

[0012] According to a signal generation circuit according to a fifth aspect of the present disclosure, in the signal generation circuit according to the fourth aspect, the reference voltage source circuit includes a plurality of resistors and a plurality of taps, and generates the first to sixth reference voltages from the plurality of taps, respectively.

[0013] According to a signal generation circuit according to a sixth aspect of the present disclosure, in the signal generation circuit according to the fourth aspect, the signal generation circuit includes first to sixth reference voltage source circuits, each of which generates one of the first to sixth reference voltages, each of which includes a parallel circuit of a plurality of second constant current sources that are turned on or off depending on the reference voltage to be generated, and each of which has components and a layout that are at least partially the same as the components and a layout of the control voltage source circuit.

[0014] According to a seventh aspect of the present disclosure, there is provided a signal generation circuit according to the fourth aspect, comprising: a first reference voltage source circuit that generates the first and sixth reference voltages; a second reference voltage source circuit that generates the second and fifth reference voltages; and a third reference voltage source circuit that generates the third and fourth reference voltages; the first reference voltage source circuit comprises a parallel circuit of a plurality of second constant current sources that are connected to one of the first and sixth differential amplifiers respectively in accordance with the reference voltage to be generated; the second reference voltage source circuit comprises a parallel circuit of a plurality of third constant current sources that are connected to one of the second and fifth differential amplifiers respectively in accordance with the reference voltage to be generated; and the third reference voltage source circuit comprises a parallel circuit of a plurality of fourth constant current sources that are connected to one of the third and fourth differential amplifiers respectively in accordance with the reference voltage to be generated; and each of the first to third reference voltage source circuits has components and a layout that are at least partially the same as the components and layout of the control voltage source circuit.

[0015] According to a signal generation circuit of an eighth aspect of the present disclosure, in the signal generation circuit of the third aspect, the signal generation circuit comprises: a first control voltage source circuit that generates a first control voltage and supplies it to the first to third differential amplifiers; and a second control voltage source circuit that generates a second control voltage having a constant potential difference with respect to the first control voltage, modulo the difference between the maximum and minimum values ​​of the first control voltage, and supplies it to the fourth to sixth differential amplifiers, and the fourth to sixth reference voltages are equal to the first to third reference voltages, respectively.

[0016] According to a ninth aspect of the present disclosure, in the signal generation circuit of the eighth aspect, the reference voltage source circuit includes a plurality of resistors and a plurality of taps, and generates the first to third reference voltages from the plurality of taps, respectively.

[0017] According to a signal generation circuit according to a tenth aspect of the present disclosure, in the signal generation circuit according to the eighth aspect, the signal generation circuit includes first to third reference voltage source circuits each generating one of the first to third reference voltages, each of the first to third reference voltage source circuits including a parallel circuit of a plurality of second constant current sources that are respectively turned on or off depending on the reference voltage to be generated, and each of the first to third reference voltage source circuits has components and a layout that are at least partially the same as the components and layout of the control voltage source circuit.

[0018] According to the signal generation circuit of the eleventh aspect of the present disclosure, in the signal generation circuit of one of the eighth to tenth aspects, the first control voltage source circuit generates the first control voltage in response to the control signal, and the second control voltage source circuit generates the second control voltage in response to a signal obtained by adding a predetermined value to the control signal.

[0019] According to a signal generation circuit according to a twelfth aspect of the present disclosure, in the signal generation circuit according to one of the eighth to tenth aspects, the second control voltage source circuit further includes a second constant current source that constantly generates a current corresponding to the potential difference between the first and second control voltages.

[0020] According to a signal generation circuit according to a thirteenth aspect of the present disclosure, in the signal generation circuit according to one of the third to twelfth aspects, each of the first to sixth differential amplifiers includes a pair of bipolar transistors or a pair of field-effect transistors.

[0021] A phase shifter according to a fourteenth aspect of the present disclosure includes a signal generating circuit according to any one of the second to thirteenth aspects; a quadrature divider that separates an input signal into an in-phase signal and a quadrature-phase signal; a first multiplier that multiplies the in-phase signal by a second output signal of the signal generating circuit to generate a first multiplied signal; a second multiplier that multiplies the quadrature-phase signal by the first output signal of the signal generating circuit to generate a second multiplied signal; and a combiner that combines the first and second multiplied signals together.

[0022] A phase shifter according to a fifteenth aspect of the present disclosure is the phase shifter according to the fourteenth aspect, further comprising a low-pass filter that reduces signal components having frequencies higher than a predetermined frequency in the first and second output signals of the signal generating circuit.

[0023] An array antenna apparatus according to a sixteenth aspect of the present disclosure includes: a plurality of antenna elements; a plurality of mixers; and a plurality of phase shifters according to the fourteenth or fifteenth aspect.

[0024] A wireless communication device according to a seventeenth aspect of the present disclosure includes the array antenna device according to the sixteenth aspect and a communication circuit.

[0025] According to one aspect of the present disclosure, it is possible to provide a signal generation circuit that has a smaller circuit size and power consumption than conventional circuits, is capable of operating at higher speeds than conventional circuits, is resistant to PVT fluctuations, and has linear control characteristics with respect to control signals.

[0026] 1 is a block diagram showing the configuration of a phase shifter 1 including a signal generation circuit 10 according to a first embodiment. It is a circuit diagram showing the configuration of the signal generation circuit 10 of FIG. 1. It is a circuit diagram showing the configuration of the controlled voltage source circuit 11 of FIG. 1. It is a diagram explaining the operation of the controlled voltage source circuit 11 of FIG. 1. It is a circuit diagram showing an example of the configuration of the differential amplifiers 31-33, 41-43 of FIG. 2. It is a circuit diagram showing another example of the configuration of the differential amplifiers 31-33, 41-43 of FIG. 2. It is a graph showing a schematic diagram of the operating characteristics of each of the differential amplifiers 31-33, 41-43 of FIG. 2. It is a graph showing a schematic diagram of changes in the operating characteristics when different reference voltages Vr2, Vr4 are set for the pair of differential amplifiers 31, 32 of FIG. 2. It is a graph explaining that a signal having a waveform similar to a sine wave can be generated by the pair of differential amplifiers 31, 32 of FIG. 2. It is a diagram explaining the relationship between the control voltage Vc(k), the reference voltage Vr, and the output signals Vsin(k) and Vcos(k) of FIG. 1. It is a block diagram showing the configuration of a phase shifter 1A including a signal generation circuit 10A according to a second embodiment. 15. A circuit diagram showing the configuration of a signal generating circuit 10A of FIG. 11. A diagram explaining the operation of the control voltage source circuits 11a and 11b of FIG. 11. A diagram explaining the relationship between the control voltages Vca(k), Vcb(k), reference voltage Vr, and output signals Vsin(k) and Vcos(k) of FIG. 11. A block diagram showing the configuration of a phase shifter 1B including a signal generating circuit 10B according to a third embodiment. A circuit diagram showing the configuration of the signal generating circuit 10B of FIG. 15. A diagram explaining the operation of the control voltage source circuits 11a and 11Bb of FIG. 15. A diagram explaining the relationship between the control voltages Vca(k), Vcb(k), reference voltage Vr, and output signals Vsin(k) and Vcos(k) of FIG. 15. A block diagram showing the configuration of a phase shifter 1C including a signal generating circuit 10C according to a fourth embodiment. A circuit diagram showing the configuration of the signal generating circuit 10C of FIG. 19. A circuit diagram showing the configuration of a signal generating circuit 10D according to a modified example of the fourth embodiment. A block diagram showing the configuration of a phase shifter 1E including a signal generating circuit 10E according to a fifth embodiment. It is a circuit diagram showing the configuration of a signal generating circuit 10E of Fig. 22. It is a diagram explaining the operation of reference voltage source circuits 12E-1 to 12E-6 of Fig. 22. It is a block diagram showing the configuration of a phase shifter 1F including a signal generating circuit 10F according to a sixth embodiment.FIG. 26 is a circuit diagram showing the configuration of a signal generating circuit 10F of FIG. 25. FIG. 27 is a diagram explaining the operation of reference voltage source circuits 12F-1 to 12F-3 of FIG. 25. FIG. 28 is a block diagram showing the configuration of a phase shifter 1G including a signal generating circuit 10 according to a seventh embodiment. FIG. 29 is a block diagram showing the configuration of a wireless communication device 100 according to an eighth embodiment.

[0027] Hereinafter, a signal generating circuit, a phase shifter, an array antenna device, and a wireless communication device according to embodiments of the present disclosure will be described with reference to the drawings. The same reference numerals denote the same components throughout the drawings.

[0028] 1 is a block diagram showing the configuration of a phase shifter 1 including a signal generation circuit 10 according to a first embodiment. The phase shifter 1 includes the signal generation circuit 10 and a quadrature modulation circuit 20.

[0029] The signal generating circuit 10 includes a control voltage source circuit 11, a reference voltage source circuit 12, and folding circuits 13 and 14. The control voltage source circuit 11 generates a control voltage Vc(k) having one of a predetermined number of voltage values ​​N in response to an input control signal k. The control signal k is a digital signal that takes any integer value among k={0, 1, ..., N-1}. The control signal k is expressed as log ２ The input signal has a size of N bits. The reference voltage source circuit 12 generates a predetermined plurality of 2M reference voltages Vr1, ..., Vr2M. The folding circuit 13 generates an output signal Vsin(k) having a signal level corresponding to a predetermined phase of a sine wave based on the difference between the control voltage Vc(k) and the plurality of reference voltages Vr2, Vr4, ..., Vr2M. The folding circuit 14 generates an output signal Vcos(k) having a signal level corresponding to a predetermined phase of a cosine wave based on the difference between the control voltage Vc(k) and the plurality of reference voltages Vr1, Vr3, ..., Vr(2M-1).

[0030] The quadrature modulation circuit 20 includes a quadrature divider 21, multipliers 22 and 23, and a combiner 24. The quadrature divider 21 divides the input original frequency signal Vin into an I-component signal VinI and a Q-component signal VinQ. The multiplier 22 multiplies the I-component signal VinI by a signal Vcos(k) output from the folding circuit 14. The multiplier 23 multiplies the Q-component signal VinQ by a signal Vsin(k) output from the folding circuit 13. When two analog signals are input, each of the multipliers 22 and 23 outputs the product thereof. The multipliers 22 and 23 may be, for example, four-quadrant multipliers or variable gain amplifiers. The combiner 24 combines the output signals of the multipliers 22 and 23 and outputs a phase-shifted frequency signal Vout.

[0031] Here, the operating principle of the quadrature modulation circuit 20 will be explained. The original frequency signal Vin is expressed as Vin = sin(ωt) as a sine wave having an angular frequency ω. Furthermore, the following signals Vsin(k) and Vcos(k) are input from the signal generation circuit 10.

[0032]

[0033] The quadrature divider 21 generates two signals VinI=sin(ωt) and VinQ=cos(ωt) having a phase difference of 90 degrees. Next, multipliers 22 and 23 multiply the signals VinI and VinQ by the signals Vcos(k) and Vsin(k) input from the signal generating circuit 10, respectively. The combiner 24 combines the output signals of the multipliers 22 and 23 and outputs a phase-shifted frequency signal Vout. Therefore, the phase-shifted frequency signal Vout can be expressed as follows:

[0034]

[0035] Comparing the original frequency signal Vin and the phase-shifted frequency signal Vout, it can be seen that the phase shifter 1 generates an output signal having a phase shift proportional to the value of the control signal k.

[0036] The signal generating circuit 10 operates as a control circuit for the quadrature modulation circuit 20 and controls the amount of phase shift of the signal Vin by the quadrature modulation circuit 20 .

[0037] FIG. 2 is a circuit diagram showing the configuration of the signal generating circuit 10 of FIG.

[0038] The controlled voltage source circuit 11 includes a resistor R0, a plurality of switches 61, and a plurality of constant current sources 62. Each of the plurality of constant current sources 62 is connected to the resistor R0 via a corresponding switch 61. In other words, a plurality of series circuits each including a switch 61 and a constant current source 62 are connected in parallel. The plurality of switches 61 have the same characteristics. The plurality of constant current sources 62 also have the same characteristics, and each generates a predetermined current I. By turning each switch 61 on or off in response to a control signal k, the current of the constant current source 62 corresponding to the turned-on switch 61 flows through the resistor R0. As a result, a control voltage Vc(k) having one of a plurality of predetermined voltage values ​​N is generated in response to the control signal k. Functionally, the controlled voltage source circuit 11 is a log ２ It has the same configuration as an N-bit current output type digital / analog converter.

[0039] 3 is a circuit diagram showing the configuration of the controlled voltage source circuit 11 in FIG. 1. The example in FIG. 3 shows the case where N=8, and the control signal k is log ２ It consists of N=3 bits b1 to b3, b1 is the least significant bit and b3 is the most significant bit. ３ It includes -1=7 switches 61 and 7 constant current sources 62. One switch 61 turns on / off in response to bit b1, two switches 61 turn on / off in conjunction with each other in response to bit b2, and four switches 61 turn on / off in conjunction with each other in response to bit b3.

[0040] Each switch 61 may be a single-pole, single-throw switch or a single-pole, double-throw switch.

[0041] FIG. 4 is a diagram illustrating the operation of the control voltage source circuit 11 of FIG. 1. The horizontal axis of FIG. 4 represents a code consisting of bits b3, b2, and b1 of the control signal k, and the vertical axis represents the control voltage Vc(k) corresponding to each code. When all switches 61 are off (i.e., when the control signal k is "000"), the control voltage Vc(k) is equal to the power supply voltage Vcc. Each time one switch 61 is turned on, the control voltage Vc(k) drops from the power supply voltage Vcc by I×R0. When all switches 61 are on (i.e., when the control signal k is "111"), the control voltage Vc(k) becomes Vcc-7×I×R0.

[0042] In this disclosure, for simplicity, the control voltage Vc(k) may also be simply referred to as the control voltage Vc.

[0043] Referring again to FIG. 2, the reference voltage source circuit 12 includes resistors R21 to R28 and a plurality of 2M taps. FIG. 2 shows the case where M=3. The resistors R21, R25 to R28 are connected in series between the positive power supply voltage Vcc terminal and the negative power supply voltage Vee terminal, and form a first voltage-dividing resistor that generates reference voltages Vr2, Vr4, and Vr6 from the power supply voltage. The reference voltages Vr2, Vr4, and Vr6 are generated at the M taps between the resistors R25 to R28. The resistors R21 to R24, and R28 are connected in series between the positive power supply voltage Vcc terminal and the negative power supply voltage Vee terminal, and form a second voltage-dividing resistor that generates reference voltages Vr1, Vr3, and Vr5 from the power supply voltage. The reference voltages Vr1, Vr3, and Vr5 are generated at the M taps between the resistors R21 to R24. The resistance values ​​of resistors R24 and R25 are set to be equal to each other. The resistance values ​​of resistors R22, R23, R26, and R27 are set to be equal to each other and twice the resistance values ​​of resistors R24 and R25. By setting the resistance values ​​of resistors R22 to R27 in this way, it is possible to generate reference voltages Vr1 to Vr6 for simultaneously generating sine waves and cosine waves.

[0044] In this disclosure, for the sake of simplicity, the reference voltages Vr1 to Vr6 may also be simply referred to as reference voltages Vr.

[0045] The folding circuit 13 includes differential amplifiers 31 to 33 and resistors R31 and R32. The differential amplifier 31 compares the control voltage Vc with a reference voltage Vr2 to generate a first differential output signal. The differential amplifier 32 compares the control voltage Vc with a reference voltage Vr4 that is higher than the reference voltage Vr2 to generate a second differential output signal. The differential amplifier 33 compares the control voltage Vc with a reference voltage Vr6 that is higher than the reference voltage Vr4 to generate a third differential output signal. The output terminals of the differential amplifiers 31 to 33 are connected to the terminal of the power supply voltage Vcc via the resistors R31 and R32. The first output signal Vsin(k) is the sum of the differential output signals of the differential amplifiers 31 and 33 and an inverted signal of the differential output signal of the differential amplifier 32.

[0046] The folding circuit 14 includes differential amplifiers 41 to 43 and resistors R41 and R42. The differential amplifier 41 compares the control voltage Vc with a reference voltage Vr1 to generate a fourth differential output signal. The differential amplifier 42 compares the control voltage Vc with a reference voltage Vr3 higher than the reference voltage Vr1 to generate a fifth differential output signal. The differential amplifier 43 compares the control voltage Vc with a reference voltage Vr5 higher than the reference voltage Vr3 to generate a sixth differential output signal. The output terminals of the differential amplifiers 41 to 43 are connected to the terminal of the power supply voltage Vcc via resistors R41 and R42. The second output signal Vcos(k) is the sum of the differential output signals of the differential amplifiers 41 and 43 and an inverted signal of the differential output signal of the differential amplifier 42.

[0047] 5 is a circuit diagram showing an example of the configuration of the differential amplifiers 31 to 33 and 41 to 43 shown in FIG. Each of the differential amplifiers 31 to 33 and 41 to 43 includes a pair of bipolar transistors Q1 and Q2, a constant current source 51, and resistors Ra to Rd. A control voltage Vc is applied to the base of the bipolar transistor Q1, and a reference voltage Vr (one of reference voltages Vr1 to Vr6) is applied to the base of the bipolar transistor Q2. An output current Ix flows through output terminals dout1 and dout2 in accordance with the potential difference between the control voltage Vc and the reference voltage Vr.

[0048] Fig. 6 is a circuit diagram showing another example of the configuration of the differential amplifiers 31 to 33 and 41 to 43 of Fig. 2. The folding circuits 13 and 14 may include differential amplifiers 31A to 33A and 41A to 43A of Fig. 6 instead of the differential amplifiers 31 to 33 and 41 to 43 of Fig. 5. Each of the differential amplifiers 31A to 33A and 41A to 43A includes a pair of field effect transistors Q1A and Q2A instead of the bipolar transistors Q1 and Q2 of Fig. 5.

[0049] The differential amplifier may have an emitter feedback resistor or may include a Darlington connection. Furthermore, the folding circuits 13 and 14 may include cascode-connected differential amplifiers or two-stage cascade-connected differential amplifiers.

[0050] 7 is a graph schematically illustrating the operating characteristics of each of the differential amplifiers 31 to 33 and 41 to 43 in FIG. The output current Ix of each differential amplifier 31 to 33 and 41 to 43 fluctuates approximately according to the transmission characteristic (solid line) of a hyperbolic sine function tanh(Vc) relative to the control voltage Vc or the transmission characteristic (dashed line) of its inverted signal. When the control voltage Vc is within a predetermined voltage range Vtran centered on the reference voltage Vr, the output current Ix fluctuates in response to the control voltage Vc. However, when the control voltage Vc is outside the voltage range Vtran, the output current Ix does not substantially fluctuate even when the control voltage Vc changes.

[0051] FIG. 8 is a graph schematically illustrating changes in operating characteristics when different reference voltages Vr2 and Vr4 are set for the pair of differential amplifiers 31 and 32 in FIG. 2 . The upper, middle, and lower sections of FIG. 8 show the current Isum′, which is the sum of the output currents of the differential amplifiers 31 and 32, with respect to changes in the control voltage Vc. The upper section of FIG. 8 shows the case where reference voltages Vr2 and Vr4 (shown as reference voltages Vr2a and Vr4a) with a large difference are set, the lower section of FIG. 8 shows the case where reference voltages Vr2 and Vr4 (shown as reference voltages Vr2c and Vr4c) with a small difference are set, and the middle section of FIG. 8 shows the case where reference voltages Vr2 and Vr4 (shown as reference voltages Vr2b and Vr4b) with an intermediate difference between them are set. By combining the differential amplifiers 31 and 32, each having a hyperbolic sine function characteristic, the current Isum′ fluctuates with respect to the control voltage Vc, exhibiting a characteristic that combines two hyperbolic sine functions. In the upper and lower figures of Fig. 8, the current Isum' deviates significantly from a sine wave waveform. On the other hand, in the middle figure of Fig. 8, it can be seen that by appropriately setting the difference between the reference voltages Vr2 and Vr4, the current Isum' can be made to closely approximate a sine wave waveform.

[0052] 9 is a graph illustrating that a signal having a waveform similar to a sine wave can be generated by the pair of differential amplifiers 31 and 32 in FIG. 2. Equation f1 shows the transmission characteristic of the differential amplifier 31, and equation f2 shows the transmission characteristic of the differential amplifier 32. Equation f3 shows the combined transmission characteristic of the adjacent differential amplifiers 31 and 32. Equation f4 shows an ideal sine wave. k Ｂ denotes the Boltzmann constant, T denotes temperature, and q denotes elementary charge. The plots of equations f1 to f4 show that the combined transmission characteristics of the differential amplifiers 31 and 32 can be well approximated to a sine wave in the range of control voltage Vc=2.1 to 2.5.

[0053] Similarly, by appropriately setting the difference between reference voltages Vr4 and Vr6, the sum of the output currents of differential amplifiers 32 and 33 can also be made to closely approximate a sine wave waveform. Furthermore, by appropriately setting the difference between reference voltages Vr1 and Vr3, the sum of the output currents of differential amplifiers 41 and 42 can also be made to closely approximate a sine wave waveform. Furthermore, by appropriately setting the difference between reference voltages Vr3 and Vr5, the sum of the output currents of differential amplifiers 42 and 43 can also be made to closely approximate a sine wave waveform.

[0054] The folding circuits 13 and 14 are analog circuits whose output voltages repeatedly increase and decrease multiple times in response to an increase or decrease in the input voltage.

[0055] FIG. 10 is a diagram illustrating the relationship between the control voltage Vc(k), reference voltage Vr, and output signals Vsin(k) and Vcos(k) of FIG. 1. The upper part of FIG. 10 shows the voltage values ​​Vc(0), ..., Vc(127) that the control voltage Vc(k) can take. The middle part of FIG. 10 shows the voltage values ​​Vr1 to Vr6 that the reference voltage Vr can take. The lower part of FIG. 10 shows how the magnitudes of the output signals Vsin(k) and Vcos(k) change depending on the control voltage Vc(k). FIG. 10 shows the case where N=128.

[0056] The total phase shift of the phase shifter 1 is ((M-1) / 4)2π radians. For example, when the control voltage Vc(k) varies across the potential difference Vr5-Vr1 (or the potential difference Vr6-Vr2), a phase shift of 2π is brought about in the quadrature modulation circuit 20.

[0057] The upper and lower limits of the control voltage Vc(k) may be set to match the upper and lower limits of the reference voltage Vr (Vc(127) = Vr1, Vc(0) = Vr6). In this case, when the kth voltage value is selected in the control voltage source circuit 11, the phase shift amount of the phase shifter 1 is expressed by the following equation:

[0058]

[0059] As described above, the parameter M determines the total phase shift amount of the phase shifter 1. If a wide phase shift amount is required, a large M is set when designing the phase shifter 1. Furthermore, the parameter N determines the resolution with which the control signal k can be set. If fine resolution is required, a large N is set when designing the phase shifter 1.

[0060] [Effects of the First Embodiment] As described above, the signal generating circuit 10 includes two folding circuits 13 and 14, and a control voltage source circuit 11 and a reference voltage source circuit 12 that generate the control voltage Vc and the reference voltage Vr used in the folding circuits 13 and 14, respectively. The folding circuits 13 and 14 generate output signals Vsin(k) and Vcos(k), which are sine or cosine waves with predetermined phases and have signal levels corresponding to phases that change in proportion to the value of the control signal k. The output signals Vsin(k) and Vcos(k) are applied as DC coefficients to two multipliers 22 and 23 of the quadrature modulation circuit 20. As a result, the phase of the original frequency signal input to the quadrature modulation circuit 20 is shifted by an amount proportional to the control signal k, and the signal is output as a phase-shifted frequency signal. According to this embodiment, it is possible to provide a signal generating circuit 10 and a phase shifter 1 that have a smaller circuit scale and power consumption than conventional ones, can operate at a higher speed than conventional ones, are resistant to PVT fluctuations, and have linear control characteristics with respect to a control signal.

[0061] The phase shifter 1 including the signal generating circuit 10 according to the embodiment has the following advantages compared to the case of referring to data stored in advance in a storage device (for example, using a look-up table) as in Patent Document 1.

[0062] The control circuit can be realized with a significantly fewer number of elements than conventional circuits, allowing for easier and lower-cost circuit design. Furthermore, the chip size can be reduced, enabling a low-cost phase shifter. When the phase shifter 1 is placed in the front-end circuit of a wireless terminal device, both the signal generation circuit 10 and the quadrature modulation circuit 20 are manufactured as high-frequency integrated circuits, enabling a highly integrated analog circuit with a small number of components. However, incorporating digital circuits into high-frequency integrated circuits is technically difficult. To achieve large-scale MIMO (Multiple-Input and Multiple-Output), the number of antenna elements in the array antenna device must be increased. However, when using high-frequency bands such as millimeter waves, the number of antenna elements in the array antenna device cannot be increased due to power consumption considerations. Therefore, a method of transmitting and receiving signals while changing the beam pattern at short time intervals (time-division multiple access massive MIMO or virtual massive MIMO) is being considered. When adopting such a method, the phase shifter must be controlled at high speed, and the signal generation circuit must operate at high speed. Therefore, it is particularly useful in terms of power consumption if the signal generating circuit 10 can be realized using an analog circuit with a small number of components.

[0063] By configuring the controlled voltage source circuit 11 as a current-output digital-to-analog converter, the controlled voltage source circuit 11 operates in current mode, allowing it to generate the control voltage Vc(k) faster than, for example, a resistor ladder configuration. Furthermore, by reducing the resistance value of resistor R0, the output impedance of the controlled voltage source circuit 11 can be reduced, allowing the controlled voltage source circuit 11 to operate at a higher speed. Furthermore, by configuring the controlled voltage source circuit 11 as a current-output digital-to-analog converter, the control voltage Vc(k) can be generated with high precision. Furthermore, by configuring the controlled voltage source circuit 11 as a current-output digital-to-analog converter, the parasitic capacitance of the subsequent folding circuits 13 and 14 can be charged quickly. As a result, a phase shifter 1 that is capable of high-speed switching and high precision can be realized.

[0064] Control voltage source circuit 11 can be realized by a plurality of switches 61 having the same characteristics and a plurality of constant current sources 62 having the same characteristics, so that manufacturing variations can be reduced when integrated. Also, reference voltage source circuit 12 can be realized by a plurality of resistors having the same resistance value, or a certain resistance value or twice that resistance value, so that manufacturing variations can be reduced when integrated.

[0065] As described above, this circuit has high tolerance to variations in the manufacturing process (P), power supply voltage (V), and temperature (T). By being resistant to PVT variations, it is possible to maintain the same performance in a variety of environments.

[0066] Since the differential amplifier has a large common-mode rejection ratio (CMRR), even if there is PVT fluctuation, if the same fluctuation is input to the two input signals of the differential amplifier, the fluctuation will be canceled out. Therefore, according to the first embodiment, it is possible to greatly improve PVT fluctuation tolerance.

[0067] When an externally input analog control voltage is used to generate the control voltage Vc instead of using the control voltage source circuit 11 as in this embodiment, the control voltage is generated by a mechanism separate from the folding circuit inside the phase shifter, which poses the problem of low resistance to PVT fluctuations. On the other hand, according to this embodiment, by using the control voltage source circuit 11 and reference voltage source circuit 12 that are integrated with each other, for example, it is possible to further improve resistance to PVT fluctuations.

[0068] According to the first embodiment, one control voltage Vc(k) is generated by the control voltage source circuit 11, and six reference voltages Vr1 to Vr6 are generated by the reference voltage source circuit 12. By supplying the reference voltages Vr1, Vr3, and Vr5 to the folding circuit 14 and supplying different reference voltages Vr2, Vr4, and Vr6 to the folding circuit 13, a phase difference occurs between the output signals Vsin(k) and Vcos(k).

[0069] Second Embodiment In the first embodiment, a common control voltage is supplied to the two folding circuits, and different reference voltages are supplied to each of the two folding circuits. In contrast, in the second embodiment, a common reference voltage is supplied to the two folding circuits, and different control voltages are supplied to each of the two folding circuits.

[0070] Fig. 11 is a block diagram showing the configuration of a phase shifter 1A including a signal generation circuit 10A according to the second embodiment. Fig. 12 is a circuit diagram showing the configuration of the signal generation circuit 10A of Fig. 11. The signal generation circuit 10A includes control voltage source circuits 11a and 11b, a reference voltage source circuit 12A, folding circuits 13 and 14, and an adder 15.

[0071] Control voltage source circuits 11a and 11b are each configured similarly to control voltage source circuit 11 in FIG. 2. However, control signal k is input directly to control voltage source circuit 11a, while a signal obtained by adding a predetermined value, for example, N / 4 to control signal k by adder 15 is input to control voltage source circuit 11b. Control voltage source circuit 11a generates control voltage Vca(k) in response to control signal k and supplies it to differential amplifiers 31 to 33 of folding circuit 13. Control voltage source circuit 11b generates control voltage Vcb(k) in response to control signal k+N / 4 and supplies it to differential amplifiers 41 to 43 of folding circuit 14.

[0072] 13 is a diagram illustrating the operation of the controlled voltage source circuits 11a and 11b of FIG. 11. Similar to the cases of FIGS. 3 and 4, FIG. 13 shows a case where N=8 and the controlled voltage source circuits 11a and 11b each include seven switches 61 and seven constant current sources 62. In this case, the adder 15 adds N / 4=8 / 4=2 to the control signal k and inputs the result to the controlled voltage source circuit 11b. Therefore, when the control signal k=0, 1, ..., 7 is input to the controlled voltage source circuit 11a, the corresponding control signal k+2=2, 3, ..., 9 is input to the controlled voltage source circuit 11b. However, if the control signal input to the controlled voltage source circuit 11b is N or more, an overflow occurs and N is subtracted from the control signal. 13, when control voltage source circuit 11a generates control voltage Vca(k) in response to control signal k=0, 1, ..., 7, control voltage source circuit 11a generates control voltage Vcb(k) in response to the corresponding control signal k=2, 3, ..., 7, 0, 1. Because control voltage source circuits 11a and 11b have the same configuration, control voltage Vcb(k) has a constant potential difference of 2·I·R0 with respect to control voltage Vca(k), modulo 7·I·R0, which is the difference between the maximum and minimum values ​​of control voltage Vca(k).

[0073] Vca (k) - Vcb (k) = 2・I・R0 (mod 7・I・R0)

[0074] 11 and 12, the reference voltage source circuit 12A includes resistors R21A to R24A and M taps. FIG. 12 shows the case where M=3. The resistors R21A to R24A are connected in series between the terminal for the positive power supply voltage Vcc and the terminal for the negative power supply voltage Vee, and are voltage-dividing resistors that generate reference voltages Vr11, Vr12, and Vr13 from the power supply voltage. The reference voltages Vr11, Vr12, and Vr13 are generated at the M taps between the resistors R21A to R24A. The resistance values ​​of the resistors R22A and R23A are set equal to each other. The reference voltage Vr11 is supplied to differential amplifiers 31 and 41, the reference voltage Vr12 is supplied to differential amplifiers 32 and 42, and the reference voltage Vr13 is supplied to differential amplifiers 33 and 43.

[0075] The folding circuits 13 and 14 in FIG. 11 are configured similarly to the folding circuits 13 and 14 in FIG.

[0076] FIG. 14 is a diagram illustrating the relationship between the control voltages Vca(k), Vcb(k), reference voltage Vr, and output signals Vsin(k) and Vcos(k) of FIG. 11. The first row of FIG. 14 shows the voltage values ​​Vca(0), ..., Vca(127) that the control voltage Vca(k) can take. The second row of FIG. 14 shows the voltage values ​​Vcb(0), ..., Vcb(127) that the control voltage Vcb(k) can take. The third row of FIG. 14 shows the voltage values ​​Vr11 to Vr13 that the reference voltage Vr can take. The fourth row of FIG. 14 shows how the magnitudes of the output signals Vsin(k) and Vcos(k) change depending on the control voltages Vca(k) and Vcb(k). FIG. 14 illustrates the case where N=128.

[0077] 14, when the control signal k varies from the minimum value 0 to the maximum value 127, the control voltages Vca(k) and Vcb(k) vary from the minimum value to the maximum value, and the phases of the output signals Vsin(k) and Vcos(k) vary over 2π. The value N / 4 added to the control signal k by the adder 15 corresponds to a phase difference of π / 2 between the output signals Vsin(k) and Vcos(k). According to the second embodiment, by supplying different control voltages Vca(k) and Vcb(k) to the folding circuits 13 and 14, respectively, the folding circuits 13 and 14 can operate using common reference voltages Vr11 to Vr13.

[0078] In the first embodiment, six differential amplifiers 31 to 33 and 41 to 43 are connected to control voltage source circuit 11. On the other hand, in the second embodiment, three differential amplifiers 31 to 33 are connected to control voltage source circuit 11a, and three differential amplifiers 41 to 43 are connected to control voltage source circuit 11b. Therefore, according to the second embodiment, the loads on each of control voltage source circuits 11a and 11b are reduced compared to that of control voltage source circuit 11 of the first embodiment, and as a result, control voltage source circuits 11a and 11b can be operated faster than control voltage source circuit 11.

[0079] The signal generation circuit 10 according to the first embodiment operates using six reference voltages Vr1 to Vr6. On the other hand, the signal generation circuit 10A according to the second embodiment can operate using three reference voltages Vr11 to Vr13. Therefore, according to the second embodiment, the configuration of the reference voltage source circuit 12A can be simplified compared to the reference voltage source circuit 12 according to the first embodiment.

[0080] According to the second embodiment, control voltages Vca(k) and Vcb(k) are generated by control voltage source circuits 11a and 11b, respectively, and three reference voltages Vr11 to Vr13 are generated by reference voltage source circuit 12A. By supplying control voltage Vca(k) to folding circuit 13 and a different control voltage Vcb(k) to folding circuit 14, a phase difference occurs between output signals Vsin(k) and Vcos(k).

[0081] [Third Embodiment] In the second embodiment, different control signals are input to two control voltage source circuits to generate different control voltages, whereas in the third embodiment, the control voltage generated by one of the two control voltage source circuits is shifted to generate different control voltages.

[0082] Fig. 15 is a block diagram showing the configuration of a phase shifter 1B including a signal generation circuit 10B according to the third embodiment. Fig. 16 is a circuit diagram showing the configuration of the signal generation circuit 10B of Fig. 15. The signal generation circuit 10B includes control voltage source circuits 11a and 11Bb, a reference voltage source circuit 12A, and folding circuits 13 and 14.

[0083] The controlled voltage source circuit 11a has a configuration similar to that of the controlled voltage source circuit 11 in FIG. 2. The controlled voltage source circuit 11Bb includes the controlled voltage source circuit 11b, which has a configuration similar to that of the controlled voltage source circuit 11 in FIG. 2, and additionally includes one or more switches 63 and one or more constant current sources 64. The switch 63 has the same characteristics as the switch 61 in the controlled voltage source circuits 11a and 11b. The constant current source 64 has the same characteristics as the constant current source 62 in the controlled voltage source circuits 11a and 11b, and generates a predetermined current I. The same control signal k is input to the controlled voltage source circuits 11a and 11b. The controlled voltage source circuit 11a generates a control voltage Vca(k) in response to the control signal k and supplies it to the differential amplifiers 31 to 33 of the folding circuit 13. The controlled voltage source circuit 11Bb generates a control voltage Vcb(k) in response to the control signal k and supplies it to the differential amplifiers 41 to 43 of the folding circuit 14. In the controlled voltage source circuit 11Bb, the switch 63 is always on, and therefore the constant current source 64 always generates a current corresponding to the potential difference between the control voltages Vca(k) and Vcb(k).

[0084] 17 is a diagram illustrating the operation of the controlled voltage source circuits 11a and 11Bb of FIG. 15. Similar to the cases of FIGS. 3 and 4, FIG. 17 shows a case where N=8 and the controlled voltage source circuits 11a and 11Bb include seven switches 61 and seven constant current sources 62. The controlled voltage source circuit 11Bb further includes two switches 63 and two constant current sources 64. As described above, the switches 63 are always on, and therefore the control voltage Vcb(k) has a constant potential difference of 2·I·R0 with respect to the control voltage Vca(k) due to the current 2·I generated by the constant current source 64.

[0085] The reference voltage source circuit 12A and folding circuits 13 and 14 in FIG. 15 are configured in the same manner as the corresponding components in FIG.

[0086] FIG. 18 is a diagram illustrating the relationship between the control voltages Vca(k), Vcb(k), reference voltage Vr, and output signals Vsin(k) and Vcos(k) of FIG. 15 . The first row of FIG. 18 shows the voltage values ​​Vca(0), ..., Vca(127) that the control voltage Vca(k) can take. The second row of FIG. 18 shows the voltage values ​​Vcb(0), ..., Vcb(127) that the control voltage Vcb(k) can take. The third row of FIG. 18 shows the voltage values ​​Vr11 to Vr13 that the reference voltage Vr can take. The fourth row of FIG. 18 shows how the magnitudes of the output signals Vsin(k) and Vcos(k) change depending on the control voltages Vca(k) and Vcb(k). FIG. 18 illustrates the case where N=128.

[0087] 18, as the control signal k varies from its minimum value of 0 to its maximum value of 127, the control voltages Vca(k) and Vcb(k) vary from their minimum value to their maximum value, and the phases of the output signals Vsin(k) and Vcos(k) vary over a 2π range. The potential difference between the control voltages Vca(k) and Vcb(k) resulting from the currents generated by the constant current sources 64 corresponds to a phase difference of π / 2 between the output signals Vsin(k) and Vcos(k). Therefore, the number of switches 63 and constant current sources 64 is determined so that the output signals Vsin(k) and Vcos(k) have a desired phase difference. In the example of FIG. 18, the controlled voltage source circuit 11Bb includes 32 switches 63 and 32 constant current sources 64. According to the third embodiment, by supplying different control voltages Vca(k) and Vcb(k) to the folding circuits 13 and 14, respectively, the folding circuits 13 and 14 can operate using common reference voltages Vr11 to Vr13.

[0088] According to the third embodiment, as in the second embodiment, the loads on each of control voltage source circuits 11a and 11Bb are reduced compared to that of control voltage source circuit 11 of the first embodiment, and as a result, control voltage source circuits 11a and 11Bb can be operated at a higher speed than control voltage source circuit 11. Furthermore, according to the third embodiment, as in the second embodiment, the configuration of reference voltage source circuit 12A can be simplified compared to that of reference voltage source circuit 12 of the first embodiment.

[0089] According to the third embodiment, control voltages Vca(k) and Vcb(k) are generated by control voltage source circuits 11a and 11Bb, respectively, and three reference voltages Vr11 to Vr13 are generated by reference voltage source circuit 12A. By supplying control voltage Vca(k) to folding circuit 13 and a different control voltage Vcb(k) to folding circuit 14, a phase difference occurs between output signals Vsin(k) and Vcos(k).

[0090] 19 is a block diagram showing the configuration of a phase shifter 1C including a signal generation circuit 10C according to a fourth embodiment. The signal generation circuit 10C includes reference voltage source circuits 12C1 to 12C-3 instead of the reference voltage source circuit 12A of FIG.

[0091] Reference voltage source circuits 12C1 to 12C-3 generate reference voltages Vr11 to Vr13, respectively. Reference voltage source circuits 12C1 to 12C-3 are replica circuits of control voltage source circuits 11a and 11Bb, having at least part of the same components and layout as those of control voltage source circuits 11a and 11Bb.

[0092] In the first to third embodiments, the control voltages Vc(k), Vca(k), and Vcb(k) are generated by a current-output digital-to-analog converter, and the reference voltages Vr1 to Vr6 or Vr11 to Vr13 are generated by voltage-dividing resistors. In other words, the control voltages and the reference voltages are generated by different mechanisms. As a result, variations in element characteristics due to manufacturing variations in elements such as transistors and resistors, fluctuations in power supply voltage, and temperature may occur, resulting in fluctuations in the output signals Vsin(k) and Vcos(k). In the fourth embodiment, the reference voltages Vr11 to Vr13 are generated by reference voltage source circuits 12C-1 to 12C-3, which are replica circuits of the control voltage source circuits 11a and 11Bb, thereby improving resistance to PVT (process, power supply voltage, and temperature) variations.

[0093] FIG. 20 is a circuit diagram showing the configuration of the signal generating circuit 10C of FIG. 19. The example of FIG. 20 shows the case where n=3 bits, and the controlled voltage source circuits 11a and 11Bb each include seven switches 61 and seven constant current sources 62. The reference voltage source circuits 12C-2 and 12C-3 each include a resistor R70, multiple switches 71, and multiple constant current sources 72. Each of the reference voltage source circuits 12C-2 and 12C-3 may include the same seven switches 71 and seven constant current sources 72 as those in the controlled voltage source circuits 11a and 11Bb. The reference voltage source circuit 12C-1 includes a resistor R70, multiple switches 71, multiple constant current sources 72, an additional switch 73, and an additional constant current source 74. The reference voltage source circuit 12C-1 may include the same seven switches 71 and seven constant current sources 72 as those in the controlled voltage source circuits 11a and 11Bb (shown by circuit portion 12C-0). The additional switch 73 and the additional constant current source 74 have the same characteristics as those of the switch 71 and the constant current source 72. The switch 73 and the constant current source 74 are provided to generate a reference voltage corresponding to the control signal k=N.

[0094] In the reference voltage source circuit 12C-1, all of the switches 71 and 73 are preset to be on, thereby generating a reference voltage Vr11. In the reference voltage source circuit 12C-2, four of the switches 71 are preset to be on and the remaining three switches 71 are preset to be off, thereby generating a reference voltage Vr12. In the reference voltage source circuit 12C-3, all of the switches 71 are preset to be off, thereby generating a reference voltage Vr13.

[0095] The circuit portion 12C-0 of the reference voltage source circuit 12C-1 and the reference voltage source circuits 12C-2 and 12C-3 have at least part of the same components and layout as those of the control voltage source circuits 11a and 11Bb. This makes them less susceptible to manufacturing variations in the elements and fluctuations in the power supply voltage. Furthermore, to reduce the effects of temperature-related variations in element characteristics, the control voltage source circuits 11a and 11Bb and the reference voltage source circuits 12C-1 to 12C-3 may be arranged close to one another.

[0096] In order to improve the symmetry of the control voltage source circuits 11a, 11Bb and the reference voltage source circuits 12C-1 to 12C-3, a switch 73 and a constant current source 74 similar to those in the reference voltage source circuit 12C-1 may be added to the control voltage source circuits 11a, 11Bb and the reference voltage source circuits 12C-2, 12C-3.

[0097] The control voltage source circuits 11a, 11Bb and the reference voltage source circuits 12C-1 to 12C-3 can be implemented using multiple switches 61, 63, 71, and 73 with the same characteristics and multiple constant current sources 62, 64, 72, and 74 with the same characteristics. Therefore, when integrated, manufacturing variations can be reduced. Furthermore, when the control voltage source circuits 11a, 11Bb and the reference voltage source circuits 12C-1 to 12C-3 are implemented using the same types of circuit elements, the control voltages Vca(k), Vcb(k) and the reference voltages Vr11 to Vr13 shift in the same direction in response to fluctuations in power supply voltage and temperature. Because the control voltages Vca(k), Vcb(k) and the reference voltages Vr11 to Vr13 are input to differential amplifiers 31 to 33 and 41 to 43, the high common-mode rejection ratios (CMRRs) of the differential amplifiers cancel out this voltage shift in the same direction.

[0098] By configuring both the control voltage source circuits 11a, 11Bb and the reference voltage source circuits 12C-1 to 12C-3 as current output type digital / analog converters, it becomes possible to easily determine design parameters related to the voltages supplied to the folding circuits 13, 14.

[0099] FIG. 21 is a circuit diagram showing the configuration of a signal generation circuit 10D according to a modification of the fourth embodiment. The signal generation circuit 10D may include reference voltage source circuits 12D-2 and 12D-3 shown in FIG. 21 instead of the reference voltage source circuits 12C-2 and 12C-3 shown in FIG. 20. The reference voltage source circuits 12D-2 and 12D-3 have a configuration in which the switch 71 turned off and the constant current source 72 connected thereto are removed from the reference voltage source circuits 12C-2 and 12C-3 shown in FIG. 20. The reference voltage source circuits 12C-1, 12D-2, and 12D-3 have the same components and layout as the control voltage source circuits 11a and 11Bb, with respect to elements through which current flows. Furthermore, by removing elements through which no current flows from the reference voltage source circuits, it is possible to reduce the circuit size while improving PVT variation resistance.

[0100] According to the fourth embodiment, control voltages Vca(k) and Vcb(k) are generated by control voltage source circuits 11a and 11Bb, respectively, and three reference voltages Vr11 to Vr13 are generated by reference voltage source circuits 12C-1 to 12C-3, respectively. By supplying control voltage Vca(k) to folding circuit 13 and a different control voltage Vcb(k) to folding circuit 14, a phase difference is generated between output signals Vsin(k) and Vcos(k).

[0101] [Fifth Embodiment] Fig. 22 is a block diagram showing the configuration of a phase shifter 1E including a signal generation circuit 10E according to a fifth embodiment. Fig. 23 is a circuit diagram showing the configuration of the signal generation circuit 10E of Fig. 22. The signal generation circuit 10E includes reference voltage source circuits 12E-1 to 12E-6 instead of the reference voltage source circuit 12 of Fig. 1.

[0102] Reference voltage source circuits 12E-1 to 12E-6 generate reference voltages Vr1 to Vr6, respectively. Reference voltage source circuits 12E-1 to 12E-6 are replica circuits of controlled voltage source circuit 11, having at least part of the same components and layout as those of controlled voltage source circuit 11.

[0103] Each of the reference voltage source circuits 12E-1 to 12E-6 includes a resistor R70, five switches 71, and five constant current sources 72, each configured similarly to the resistor R0, switch 61, and constant current source 62 of the control voltage source circuit 11. Five sets of series circuits, each including a switch 71 and a constant current source 72, are connected in parallel. Each switch 71 (and equivalently, each constant current source 72) is turned on or off depending on the reference voltage to be generated. In the reference voltage source circuit 12E-1, five switches 71 are preset to be turned on, thereby generating a control voltage Vr1. In the reference voltage source circuit 12E-2, four switches 71 are preset to be turned on, thereby generating a control voltage Vr2. In the reference voltage source circuit 12E-3, three switches 71 are preset to be turned on, thereby generating a control voltage Vr3. In reference voltage source circuit 12E-4, two switches 71 are preset to be turned on, thereby generating control voltage Vr4. In reference voltage source circuit 12E-5, one switch 71 is preset to be turned on, thereby generating control voltage Vr5. In reference voltage source circuit 12E-6, all five switches 71 are preset to be turned off, thereby generating control voltage Vr6.

[0104] 24 is a diagram illustrating the operation of reference voltage source circuits 12E-1 to 12E-6 in FIG. 22. When all switches 71 are off, reference voltage Vr is equal to power supply voltage Vcc. Each time one switch 71 is turned on, reference voltage Vr drops from power supply voltage Vcc by I×R0. When all switches 71 are on, reference voltage Vr becomes Vcc-5×I×R70.

[0105] Reference voltage source circuits 12E-1 to 12E-6 have at least part of the same components and layout as control voltage source circuit 11. This makes them less susceptible to manufacturing variations in elements and fluctuations in power supply voltage. Furthermore, control voltage source circuit 11 and reference voltage source circuits 12E-1 to 12E-6 may be arranged close to each other to reduce the influence of temperature-related variations in element characteristics.

[0106] To improve the symmetry of control voltage source circuit 11 and reference voltage source circuits 12E-1 to 12E-6, each of reference voltage source circuits 12E-1 to 12E-6 may include the same number of switches 71 and constant current sources 72 (for example, seven when n=3 bits) as the number of switches 61 and constant current sources 62 of control voltage source circuit 11. In this case, the extra switches 71 (and equivalently, constant current sources 72) in reference voltage source circuits 12E-1 to 12E-6 are always turned off.

[0107] As in the case described with reference to FIG. 21, in the reference voltage source circuits 12E-1 to 12E-6, the switch 71 that is always turned off and the constant current source 72 connected thereto may be removed.

[0108] Control voltage source circuit 11 and reference voltage source circuits 12E-1 to 12E-6 can be implemented using multiple switches 61, 71 with the same characteristics and multiple constant current sources 62, 72 with the same characteristics, which reduces manufacturing variations when integrated. Furthermore, when control voltage source circuit 11 and reference voltage source circuits 12E-1 to 12E-6 are implemented using the same types of circuit elements, control voltage Vc(k) and reference voltages Vr1 to Vr6 shift in the same direction in response to fluctuations in power supply voltage and temperature. Because control voltage Vc(k) and reference voltages Vr1 to Vr6 are input to differential amplifiers 31 to 33 and 41 to 43, the high common-mode rejection ratio (CMRR) of the differential amplifiers cancels out this voltage shift in the same direction.

[0109] By configuring both the control voltage source circuit 11 and the reference voltage source circuits 12E-1 to 12E-6 as current output type digital / analog converters, it becomes possible to easily determine design parameters related to the voltages supplied to the folding circuits 13 and 14.

[0110] According to the fifth embodiment, one control voltage Vc(k) is generated by control voltage source circuit 11, and six reference voltages Vr1 to Vr6 are generated by reference voltage source circuits 12E-1 to 12E-6, respectively. Reference voltages Vr1, Vr3, and Vr5 are supplied to folding circuit 14, and different reference voltages Vr2, Vr4, and Vr6 are supplied to folding circuit 13, thereby generating a phase difference between output signals Vsin(k) and Vcos(k).

[0111] [Sixth Embodiment] Fig. 25 is a block diagram showing the configuration of a phase shifter 1F including a signal generation circuit 10F according to a sixth embodiment. Fig. 26 is a circuit diagram showing the configuration of the signal generation circuit 10F of Fig. 25. The signal generation circuit 10F includes a control voltage source circuit 11F and reference voltage source circuits 12F-1 to 12F-3 instead of the control voltage source circuit 11 and reference voltage source circuit 12 of Fig. 1.

[0112] Similar to the controlled voltage source circuit 11 of FIG. 1, the controlled voltage source circuit 11F generates a control voltage Vc(k) having one of a predetermined plurality of voltage values ​​N in response to an input control signal k.

[0113] Reference voltage source circuit 12F-1 generates reference voltages Vr1 and Vr6, reference voltage source circuit 12F-2 generates reference voltages Vr2 and Vr5, and reference voltage source circuit 12F-3 generates reference voltages Vr3 and Vr4. Reference voltage source circuits 12F-1 to 12F-3 are replica circuits of control voltage source circuit 11F, having at least part of the same components and layout as those of control voltage source circuit 11F.

[0114] The controlled voltage source circuit 11 includes resistors R81 and R82, multiple switches 81, and multiple constant current sources 82. The resistors R81 and R82 have the same resistance value R80. Each switch 81 is a single-pole, double-throw switch. Each of the multiple constant current sources 82 is connected to one of the output terminals t and c via a corresponding switch 81. The output terminals t and c are further connected to resistors R81 and R82, respectively. This results in multiple series circuits, each including a switch 81 and a constant current source 82, being connected in parallel. The multiple switches 81 have the same characteristics. The multiple constant current sources 82 also have the same characteristics and each generate a predetermined current I. By controlling each switch 81 to connect each constant current source 82 to either the output terminal t or c in response to a control signal k, the current from the constant current source 82 connected to the output terminal t flows through the resistor R81. Equivalently, each constant current source 82 is turned on or off in response to the control signal k. As a result, a control voltage Vc(k) having one of a plurality of predetermined voltage values ​​N is generated at the output terminal t in response to the control signal k. ２ It has the same configuration as an N-bit current output type digital / analog converter.

[0115] Each of the reference voltage source circuits 12F-1 to 12F-3 includes resistors R91 and R92, five switches 91, and five constant current sources 92, each configured similarly to the resistors R81 and R82, switch 81, and constant current source 82 of the control voltage source circuit 11F. The resistors R91 and R92 have the same resistance value R90. Each switch 91 is a single-pole, double-throw switch. Five sets of series circuits, each including a switch 91 and a constant current source 92, are connected in parallel. Each switch 91 is controlled to connect the corresponding constant current source 92 to one of the output terminals t and c depending on the reference voltage to be generated. In the reference voltage source circuit 12F-1, the switches 91 are preset to connect the five constant current sources 92 to the output terminal t, thereby generating a control voltage Vr1 at the output terminal t and a control voltage Vr6 at the output terminal c. In reference voltage source circuit 12F-2, switches 91 are set in advance so that four constant current sources 92 are connected to output terminal t, thereby generating control voltage Vr2 at output terminal t and control voltage Vr5 at output terminal c. In reference voltage source circuit 12F-3, switches 91 are set in advance so that three constant current sources 92 are connected to output terminal t, thereby generating control voltage Vr3 at output terminal t and control voltage Vr4 at output terminal c.

[0116] 27 is a diagram illustrating the operation of the reference voltage source circuits 12F-1 to 12F-3 of FIG. 25. When all constant current sources 92 are connected to output terminal c, the voltage at output terminal t is equal to the power supply voltage Vcc, and the voltage at output terminal c is equal to Vcc-5×I×R80. Each time the number of constant current sources 92 connected to output terminal t is increased, the voltage at output terminal t decreases by I×R90, and the voltage at output terminal c increases by I×R90. When all constant current sources 92 are connected to output terminal t, the voltage at output terminal t is equal to Vcc-5×I×R80, and the voltage at output terminal c is equal to the power supply voltage Vcc. Thus, in each of the reference voltage source circuits 12F-1 to 12F-3, the voltages at output terminals t and c change complementarily. Therefore, in the reference voltage source circuits 12F-1 to 12F-3, by connecting different numbers of constant current sources 92 to the output terminal t, six reference voltages Vr1 to Vr6 can be generated.

[0117] According to the sixth embodiment, by outputting two reference voltages from one reference voltage source circuit, the number of reference voltage source circuits can be reduced to half of that in the fifth embodiment, thereby making it possible to reduce the circuit size and power consumption of the phase shifter 1F compared to the phase shifter 1E.

[0118] Reference voltage source circuits 12F-1 to 12F-3 have at least part of the same components and layout as control voltage source circuit 11F. This makes them less susceptible to manufacturing variations in elements and fluctuations in power supply voltage. Furthermore, to reduce the effects of temperature-related variations in element characteristics, control voltage source circuit 11F and reference voltage source circuits 12F-1 to 12F-3 may be located close to each other.

[0119] The control voltage source circuit 11F and the reference voltage source circuits 12F-1 to 12F-3 can be realized using multiple switches 81 and 91 with the same characteristics and multiple constant current sources 82 and 92 with the same characteristics, which reduces manufacturing variations when integrated. Furthermore, when the control voltage source circuit 11F and the reference voltage source circuits 12F-1 to 12F-3 are realized using the same types of circuit elements, the control voltage Vc(k) and the reference voltages Vr1 to Vr6 shift in the same direction in response to fluctuations in the power supply voltage and temperature. Because the control voltage Vc(k) and the reference voltages Vr1 to Vr6 are input to the differential amplifiers 31 to 33 and 41 to 43, the high common-mode rejection ratios (CMRRs) of the differential amplifiers cancel out this voltage shift in the same direction.

[0120] By configuring both the control voltage source circuit 11 and the reference voltage source circuits 12F-1 to 12F-3 as current output type digital / analog converters, it becomes possible to easily determine design parameters related to the voltages supplied to the folding circuits 13 and 14.

[0121] According to the sixth embodiment, one control voltage Vc(k) is generated by the control voltage source circuit 11F, and six reference voltages Vr1 to Vr6 are generated by three reference voltage source circuits 12F-1 to 12F-3. By supplying reference voltages Vr1, Vr3, and Vr5 to the folding circuit 14 and different reference voltages Vr2, Vr4, and Vr6 to the folding circuit 13, a phase difference occurs between the output signals Vsin(k) and Vcos(k).

[0122] Seventh Embodiment FIG. 28 is a block diagram showing the configuration of a phase shifter 1G including a signal generation circuit 10 according to a seventh embodiment. In addition to the components of the phase shifter 1 shown in FIG. 1 , the phase shifter 1G includes low-pass filters (LPFs) F1 and F2 inserted between the signal generation circuit 10 and the quadrature modulation circuit 20. The low-pass filters F1 and F2 reduce signal components having frequencies higher than a predetermined frequency in the output signals Vsin(k) and Vcos(k) of the signal generation circuit 10. In a phased array antenna device using a phase shifter, high-speed control of the phase shifter can result in the generation of spurious frequencies (unwanted waves) in the output signal of the phased array antenna device. Inserting the low-pass filters F1 and F2 between the signal generation circuit 10 and the quadrature modulation circuit 20 enables smooth phase switching of the phase shifter 1G, thereby preventing spurious signals from occurring.

[0123] 29 is a block diagram showing the configuration of a wireless communication device 100 according to an eighth embodiment. The wireless communication device 100 includes a transmission circuit 101, mixers 102-1 to 102-4, amplifiers 103-1 to 103-4, antenna elements 104-1 to 104-4, a frequency synthesizer 105, a frequency multiplier 106, phase shifters 107-1 to 107-4, frequency multipliers 108-1 to 108-4, and a control circuit 109.

[0124] The transmitting circuit 101 sends a baseband signal containing data to be transmitted to the mixers 102-1 to 102-4.

[0125] Frequency synthesizer 105 generates a high-frequency signal having a predetermined frequency. Frequency multiplier 106 multiplies the frequency of the high-frequency signal generated by frequency synthesizer 105 and sends the multiplied signal to phase shifters 107-1 to 107-4.

[0126] Each of the phase shifters 107-1 to 107-4 has the same configuration as the phase shifters 1, 1A to 1C, and 1G according to the first to fourth embodiments. Control signals k1 to k4 are input to each of the phase shifters 107-1 to 107-4 from a control circuit 109. The phase shifters 107-1 to 107-4 change the phase of the high-frequency signal input from the frequency multiplier 106 in accordance with the control signals k1 to k4. The control circuit 109 uses the control signals k1 to k4 to arbitrarily change the phase of the high-frequency signal independently of one another.

[0127] Frequency multipliers 108-1 to 108-4 multiply the frequencies of the high frequency signals output from phase shifters 107-1 to 107-4 and send the multiplied signals to mixers 102-1 to 102-4.

[0128] Mixers 102-1 to 102-4 modulate the high-frequency signals (radio frequency signals) input from frequency multipliers 108-1 to 108-4 with the baseband signals input from transmission circuit 101. The output signals of mixers 102-1 to 102-4 are amplified by amplifiers 103-1 to 103-4, respectively, and then radiated from antenna elements 104-1 to 104-4, respectively.

[0129] The antenna elements 104-1 to 104-4 operate as a phased array antenna device by changing the phase of the radio frequency signal to be transmitted by the phase shifters 107-1 to 107-4. By changing the phase of the radio frequency signal with high precision using the phase shifters 107-1 to 107-4, the directivity of the antenna device can be further increased.

[0130] 29 shows a wireless communication device 100 including a transmission circuit 101, but the phase shifters 1, 1A to 1C, and 1G according to the first to seventh embodiments are also applicable to wireless communication devices including a reception circuit. When the wireless communication device includes a reception circuit, the arrival direction may be estimated based on the received signal, or a beam may be directed toward the arrival direction using a phase shifter.

[0131] According to the eighth embodiment, it is possible to provide a wireless communication device that utilizes high frequency bands such as millimeter waves and terahertz waves.

[0132] Other Embodiments The embodiments and modifications described above may be combined in any manner.

[0133] In the example of FIG. 2, the reference voltages Vr1 to Vr6 for the differential amplifiers 31 to 33 and 41 to 43 are set in the order Vr1<Vr2<Vr3<Vr4<Vr5<Vr6, but they may also be set in another order, for example, Vr2<Vr1<Vr4<Vr3<Vr6<Vr5.

[0134] 1 and other figures illustrate a case in which the signal generation circuit 10 generates both a sine wave and a cosine wave, but the techniques described in this disclosure are also applicable to a case in which only one of a sine wave and a cosine wave is generated. In this case, the signal generation circuit includes only one of the folding circuits 13 and 14. The output signal of the signal generation circuit may be supplied to any circuit that utilizes a signal level corresponding to a predetermined phase of a sine wave or a cosine wave, for example, a direct digital synthesizer that digitally generates a sine wave signal or a cosine wave signal.

[0135] A signal generating circuit, a phase shifter, an array antenna device, and a wireless communication device according to an aspect of the present disclosure may be applied to, for example, a base station or a mobile station of a wireless communication system. The signal generating circuit, the phase shifter, the array antenna device, and the wireless communication device according to an aspect of the present disclosure may be applied to, for example, a phase shifter portion of a phased array antenna device that is being considered for use in satellite communications and weather radar.

[0136] 1, 1A to 1C, 1E to 1G Phase shifter 10, 10A to 10F Signal generation circuit 11, 11a, 11b, 11Bb, 11F Control voltage source circuit 12, 12A, 12C1 to 12C-3, 12D-2 to 12D-3, 12E-1 to 12E-6, 12F-1 to 12F-3 Reference voltage source circuit 13, 14 Folding circuit 15 Adder 20 Quadrature modulation circuit 21 Quadrature distributor 22, 23 Multiplier 24 Combiner 31 to 33 Differential amplifiers 41 to 43 Differential amplifiers 51 Constant current source 61, 63 Switch 62, 64 Constant current source 71, 73 Switch 72, 74 Constant current source 81 Switch 82 Constant current source 91 Switch 92 Constant current source 100 Wireless communication device 101 Transmitting circuit 102-1 to 102-4 Mixers 103-1 to 103-4 Amplifiers 104-1 to 104-4 Antenna elements 105 Frequency synthesizer 106 Frequency multipliers 107-1 to 107-4 Phase shifters 108-1 to 108-4 Frequency multipliers 109 Control circuit F1, F2 Low pass filters (LPF) R0, R21 to R28, R21A to R24A, R31, R32, R41, R42, Ra to Rd Resistors Q1, Q2 Bipolar transistors Q1A, Q2A Field effect transistors

Claims

1. At least one control voltage source circuit that generates a control voltage having one of a plurality of predetermined voltage values ​​in response to an input control signal; at least one reference voltage source circuit for generating a plurality of predetermined reference voltages; a first folding circuit that generates a first output signal having a signal level corresponding to a predetermined phase of a sine wave based on a difference between the control voltage and the plurality of reference voltages; a second folding circuit that generates a second output signal having a signal level corresponding to a predetermined phase of a cosine wave based on a difference between the control voltage and the plurality of reference voltages; the controlled voltage source circuit includes a parallel circuit of a plurality of first constant current sources, each of which is turned on or off in response to the control signal; The first folding circuit comprises: a first differential amplifier that compares the control voltage against a first reference voltage to generate a first differential output signal; a second differential amplifier that compares the control voltage to a second reference voltage higher than the first reference voltage to generate a second differential output signal; a third differential amplifier that compares the control voltage to a third reference voltage higher than the second reference voltage to generate a third differential output signal; The second folding circuit includes: a fourth differential amplifier that compares the control voltage against a fourth reference voltage to generate a fourth differential output signal; a fifth differential amplifier that compares the control voltage to a fifth reference voltage higher than the fourth reference voltage to generate a fifth differential output signal; a sixth differential amplifier that compares the control voltage to a sixth reference voltage higher than the fifth reference voltage to generate a sixth differential output signal; the first output signal is a sum of the first and third differential output signals and an inverted signal of the second differential output signal; the second output signal is a sum of the fourth and sixth differential output signals and an inverted signal of the fifth differential output signal; The at least one controlled voltage source circuit comprises: a first control voltage source circuit that generates a first control voltage and supplies it to the first to third differential amplifiers; a second control voltage source circuit that generates a second control voltage having a fixed potential difference with respect to the first control voltage, modulo the difference between the maximum value and the minimum value of the first control voltage, and supplies the second control voltage to the fourth to sixth differential amplifiers; the fourth to sixth reference voltages are equal to the first to third reference voltages, respectively; Signal generation circuit.

2. the reference voltage source circuit includes a plurality of resistors and a plurality of taps, and generates the first to third reference voltages from the plurality of taps, respectively; 2. The signal generating circuit according to claim 1.

3. the signal generating circuit includes first to third reference voltage source circuits that generate one of the first to third reference voltages, each of the first to third reference voltage source circuits includes a parallel circuit of a plurality of second constant current sources that are turned on or off according to a reference voltage to be generated; each of the first to third reference voltage source circuits has components and a layout at least partially identical to the components and a layout of the control voltage source circuit; 2. The signal generating circuit according to claim 1.

4. the first control voltage source circuit generates the first control voltage in response to the control signal; the second control voltage source circuit generates the second control voltage in response to a signal obtained by adding a predetermined value to the control signal; A signal generating circuit according to any one of claims 1 to 3.

5. the second control voltage source circuit further includes a third constant current source that constantly generates a current corresponding to a potential difference between the first and second control voltages; A signal generating circuit according to any one of claims 1 to 3.

6. each of the first to sixth differential amplifiers includes a pair of bipolar transistors or a pair of field effect transistors; 2. The signal generating circuit according to claim 1.

7. A control voltage source circuit that generates a control voltage having one of a plurality of predetermined voltage values ​​in response to an input control signal; at least one reference voltage source circuit for generating a plurality of predetermined reference voltages; a first folding circuit that generates a first output signal having a signal level corresponding to a predetermined phase of a sine wave based on a difference between the control voltage and the plurality of reference voltages; a second folding circuit that generates a second output signal having a signal level corresponding to a predetermined phase of a cosine wave based on a difference between the control voltage and the plurality of reference voltages; the controlled voltage source circuit includes a parallel circuit of a plurality of first constant current sources, each of which is turned on or off in response to the control signal; The first folding circuit comprises: a first differential amplifier that compares the control voltage against a first reference voltage to generate a first differential output signal; a second differential amplifier that compares the control voltage to a second reference voltage higher than the first reference voltage to generate a second differential output signal; a third differential amplifier that compares the control voltage to a third reference voltage higher than the second reference voltage to generate a third differential output signal; The second folding circuit includes: a fourth differential amplifier that compares the control voltage against a fourth reference voltage to generate a fourth differential output signal; a fifth differential amplifier that compares the control voltage to a fifth reference voltage higher than the fourth reference voltage to generate a fifth differential output signal; a sixth differential amplifier that compares the control voltage to a sixth reference voltage higher than the fifth reference voltage to generate a sixth differential output signal; the first output signal is a sum of the first and third differential output signals and an inverted signal of the second differential output signal; the second output signal is a sum of the fourth and sixth differential output signals and an inverted signal of the fifth differential output signal; the control voltage source circuit supplies one common control voltage to the first to sixth differential amplifiers; the first to sixth reference voltages are different from one another, The at least one reference voltage source circuit a first reference voltage source circuit that generates the first and sixth reference voltages; a second reference voltage source circuit that generates the second and fifth reference voltages; a third reference voltage source circuit that generates the third and fourth reference voltages; the first reference voltage source circuit includes a parallel circuit of a plurality of second constant current sources, each connected to one of the first and sixth differential amplifiers in accordance with a reference voltage to be generated; the second reference voltage source circuit includes a parallel circuit of a plurality of third constant current sources, each connected to one of the second and fifth differential amplifiers in accordance with a reference voltage to be generated; the third reference voltage source circuit comprises a parallel circuit of a plurality of fourth constant current sources, each connected to one of the third and fourth differential amplifiers in accordance with a reference voltage to be generated; each of the first to third reference voltage source circuits has components and a layout at least partially identical to the components and a layout of the control voltage source circuit; Signal generation circuit.

8. a signal generating circuit according to claim 1 or 7; a quadrature splitter that splits an input signal into an in-phase signal and a quadrature-phase signal; a first multiplier that multiplies the in-phase signal by the second output signal of the signal generating circuit to generate a first multiplied signal; a second multiplier that multiplies the quadrature phase signal by the first output signal of the signal generating circuit to generate a second multiplied signal; a combiner for combining the first and second multiplied signals together; Phase shifter.

9. a low-pass filter for reducing signal components having frequencies higher than a predetermined frequency in the first and second output signals of the signal generating circuit; 9. The phase shifter according to claim 8.

10. a plurality of antenna elements; a plurality of mixers; and a plurality of phase shifters according to claim 8. Array antenna device.

11. an array antenna device according to claim 10; a communication circuit; Wireless communication device.