Circuit board

Abstract

This circuit board comprises a first multilayer ceramic electronic component and a second multilayer ceramic electronic component. The multilayer ceramic electronic components each have a height dimension that is at least 1.3 times the width dimension thereof. The first multilayer ceramic electronic component and the second multilayer ceramic electronic component have mutually orthogonal length directions, and are disposed on a mounting surface so as to be adjacent to each other in a state such that a region, in which a range covering the width direction of the first multilayer ceramic electronic component is extended in the length direction of the first multilayer ceramic electronic component, overlaps with one of a first outer electrode and a second outer electrode provided to the second multilayer ceramic electronic component.

Description

circuit board

[0001] The present invention relates to a circuit board.

[0002] In recent years, various electronic devices have become smaller and more functional, leading to a trend toward a reduction in the mounting area of ​​electronic components, including multilayer ceramic electronic components, on circuit boards. Meanwhile, there is a demand for even higher capacitance for multilayer ceramic electronic components. To meet this demand, component structures aimed at achieving higher density mounting and larger capacitance have been proposed (see, for example, Patent Document 1). For multilayer ceramic electronic components, the mounting area on a circuit board can be determined by the length and width dimensions of the multilayer ceramic electronic component. Patent Document 1 proposes a high-profile multilayer ceramic electronic component in which the height dimension, i.e., the dimension perpendicular to the mounting surface of the circuit board, is larger than the length or width dimension. A high-profile multilayer ceramic electronic component is suitable for achieving higher capacitance.

[0003] Japanese Patent Application Laid-Open No. 2020-031152

[0004] However, if a multilayer ceramic electronic component that is large in height and densely mounted is tilted, it may come into contact with other electronic components mounted around it, potentially causing a short circuit.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to prevent the occurrence of short circuits when tall multilayer ceramic electronic components are tilted in a circuit board on which the high-profile multilayer ceramic electronic components are densely mounted.

[0006] In order to achieve the above object, the circuit board disclosed in this specification includes a substrate having a first axis perpendicular to a mounting surface, and second and third axes orthogonal to the first axis and orthogonal to each other, and a plurality of multilayer ceramic electronic components mounted on the mounting surface, wherein a first multilayer ceramic electronic component included in the plurality of multilayer ceramic electronic components is mounted on the mounting surface with its height direction aligned with the first axis, its width direction aligned with the second axis, and its length direction aligned with the third axis direction, and has a first external electrode at one end in the length direction and having a predetermined length along the length direction, and a second external electrode at the other end in the length direction, and a second multilayer ceramic electronic component included in the plurality of multilayer ceramic electronic components has its height direction aligned with the first axis, its length direction aligned with the second axis, and its width direction aligned with the third axis direction. the height dimension of the first multilayer ceramic electronic component is 1.3 times or more the width or length dimension of the first multilayer ceramic electronic component, and the height dimension of the second multilayer ceramic electronic component is 1.3 times or more the width dimension of the second multilayer ceramic electronic component; and the first and second multilayer ceramic electronic components are arranged adjacent to each other on the mounting surface such that their length directions are orthogonal to each other and one of the first external electrode and the second external electrode of the second multilayer ceramic electronic component overlaps with a virtual region obtained by extending a region of the first multilayer ceramic electronic component in the width direction along the length direction of the first multilayer ceramic electronic component.

[0007] In the circuit board having the above configuration, the distance along the second axis between the first external electrode and the second external electrode of the first multilayer ceramic electronic component and the other of the first external electrode and the second external electrode of the second multilayer ceramic electronic component can be greater than 0.5 times the height dimension of the first multilayer ceramic electronic component.

[0008] In the circuit board having the above configuration, another electronic component covered with an insulating coating may be mounted adjacent to the first and second multilayer ceramic electronic components in a region that is to the side of the first multilayer ceramic electronic component along the second axis direction and that is along the third axis direction of the second multilayer ceramic electronic component.

[0009] Furthermore, in the circuit board having the above configuration, another electronic component covered with an insulating coating may be mounted in a region that is adjacent to the first and second multilayer ceramic electronic components and that is located to the side of the first multilayer ceramic electronic component along the third axis direction and that is located along the second axis direction of the second multilayer ceramic electronic component.

[0010] Furthermore, in the circuit board having the above configuration, at least one of the height dimension of the first multilayer ceramic electronic component and the height dimension of the second multilayer ceramic electronic component may be 1.5 times or more the width dimension or length dimension of the respective component.

[0011] In the circuit board having the above configuration, at least one of the internal electrodes provided in the ceramic body of the first multilayer ceramic electronic component and the internal electrodes provided in the ceramic body of the second multilayer ceramic electronic component may be laminated so as to face each other in a direction along the height direction of the respective internal electrodes.

[0012] Furthermore, in the circuit board having the above configuration, the internal electrodes stacked in the height direction include a first internal electrode connected to the first external electrode and a second internal electrode connected to the second external electrode, the first internal electrode having a connection end connected to the first external electrode and an open end located opposite the connection end, the connection end having a narrow portion whose dimension in the width direction is smaller than the dimension of the open end along the width direction, and the second internal electrode having a connection end connected to the second external electrode and an open end located opposite the connection end, the connection end having a narrow portion whose dimension in the width direction is smaller than the dimension of the open end along the width direction.

[0013] Furthermore, in the circuit board having the above configuration, at least one of the internal electrodes provided in the ceramic body of the first multilayer ceramic electronic component and the internal electrodes provided in the ceramic body of the second multilayer ceramic electronic component may be laminated so as to face each other in a direction along the width direction of the respective electrodes.

[0014] Furthermore, in the circuit board having the above configuration, the internal electrodes stacked in the direction along the width direction include a first internal electrode connected to the first external electrode and a second internal electrode connected to the second external electrode, the first internal electrode having a connection end connected to the first external electrode and an open end located opposite the connection end, the connection end having a narrow portion whose dimension in the height direction is smaller than the dimension of the open end along the height direction, and the second internal electrode having a connection end connected to the second external electrode and an open end located opposite the connection end, the connection end having a narrow portion whose dimension in the height direction is smaller than the dimension of the open end along the height direction.

[0015] In the circuit board having the above configuration, a low-melting-point metal may be contained in the internal electrodes or in the dielectric layers formed between the internal electrodes.

[0016] According to the invention disclosed in this specification, in a circuit board on which high-profile multilayer ceramic electronic components are densely mounted, it is possible to suppress the occurrence of short circuits when the multilayer ceramic electronic components are tilted.

[0017] FIG. 1(A) is a front view of the circuit board of the first embodiment, and FIG. 1(B) is a plan view thereof. FIG. 1(C) is an equivalent circuit diagram of the circuit board shown in FIGS. 1(A) and 1(B). FIG. 2 is a perspective view of first and second multilayer ceramic capacitors used in the circuit board of the first embodiment. FIG. 3 is a four-side view of the first and second multilayer ceramic capacitors used in the circuit board of the first embodiment. FIG. 3(A) is a plan view, FIG. 3(B) is a bottom view, FIG. 3(C) is a front view, and FIG. 3(D) is a rear view. FIG. 4 is a cross-sectional view of the first multilayer ceramic capacitor used in the circuit board of the first embodiment, taken along line A1-A1 in FIG. 2. FIG. 5(A) is a cross-sectional view of the first multilayer ceramic capacitor used in the circuit board of the first embodiment, taken along line A2-A2 in FIG. 2. FIG. 5(B) is a cross-sectional view of the first multilayer ceramic capacitor used in the circuit board of the first embodiment, taken along line A3-A3 in FIG. 2. FIG. 6(A) is an explanatory diagram showing the positional relationship between the first multilayer ceramic capacitor and the second multilayer ceramic capacitor in the first embodiment, and FIG. 6(B) is an explanatory diagram showing the positional relationship between the first multilayer ceramic capacitor and the second multilayer ceramic capacitor in a first modified example of the first embodiment. FIG. 6(C) is an explanatory diagram showing the positional relationship between the first multilayer ceramic capacitor and the second multilayer ceramic capacitor in a second modified example of the first embodiment, and FIG. 6(D) is an explanatory diagram showing the positional relationship between the first multilayer ceramic capacitor and the second multilayer ceramic capacitor in a third modified example of the first embodiment. FIG. 7(A) is a side view of a circuit board according to the second embodiment, and FIG. 7(B) is a plan view of the circuit board according to the second embodiment. FIG. 7(C) is a plan view of a circuit board according to the third embodiment. FIG. 8 is a cross-sectional view of a first multilayer ceramic capacitor used in a circuit board according to a fourth embodiment, taken along a line corresponding to line A1-A1 in FIG. 2. 9A is a cross-sectional view of the first multilayer ceramic capacitor used in the circuit board of the fourth embodiment, taken along a line segment corresponding to the A2-A2 line in FIG. 2, and FIG. 9B is a cross-sectional view of the first multilayer ceramic capacitor used in the circuit board of the fourth embodiment, taken along a line segment corresponding to the A3-A3 line in FIG. 2.Fig. 10 is a partially exploded view showing a ceramic body included in the first multilayer ceramic capacitor according to the fifth embodiment. Fig. 11 is a partially exploded view showing a ceramic body included in the first multilayer ceramic capacitor according to a modification of the fifth embodiment. Fig. 12 is a perspective view of a circuit board showing a partial cross section of the first multilayer ceramic capacitor according to a modification of the fifth embodiment. Fig. 13(A) is a side view of a circuit board according to a comparative example, and Fig. 13(B) is a plan view thereof. Fig. 14 is a schematic view showing how the first multilayer ceramic capacitor according to the comparative example tilts, with Fig. 14(A) being a side view and Fig. 14(B) being a plan view.

[0018] Hereinafter, a circuit board according to an embodiment of the present invention will be described with reference to the accompanying drawings. The dimensions, ratios, and the like of each part in the drawings may not be exactly the same as those in reality. Furthermore, for convenience of illustration, some details or components may be omitted in some drawings. The drawings also show mutually orthogonal X-, Y-, and Z-axes as appropriate. The X-, Y-, and Z-axes define a fixed coordinate system fixed with respect to the circuit board 110. In the following description, the Z-axis direction corresponds to the direction along the first axis, the Y-axis direction corresponds to the direction along the second axis, and the X-axis direction corresponds to the direction along the third axis.

[0019] First Embodiment [Circuit Board] First, a schematic configuration of a circuit board 110 according to a first embodiment will be described with reference to FIGS. 1A to 1C. FIG. 1A is a front view of the circuit board 110 according to the first embodiment. FIG. 1B is a plan view of the circuit board 110. FIG. 1C is an equivalent circuit diagram of the circuit board 110 according to the first embodiment. The circuit board 110 includes a printed wiring board 1 as a substrate, a first multilayer ceramic capacitor (MLCC: Multi Layered Ceramic Capacitor) 10, and a second multilayer ceramic capacitor 30. In this embodiment, the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are identical but are assigned different reference numerals for convenience of explanation. The first multilayer ceramic capacitor 10 includes a first external electrode 14 and a second external electrode 15. Similarly, the second multilayer ceramic capacitor 30 also includes a first external electrode 34 and a second external electrode 35 .

[0020] In the circuit board 110, it is necessary to avoid a short circuit between the first external electrode 14 or the second external electrode 15 of the first multilayer ceramic capacitor 10 and the first external electrode 34 and the second external electrode 35 of the second multilayer ceramic capacitor 30. Specifically, for example, it is necessary to avoid a short circuit between the first external electrode 34 and the second external electrode 35 of the second multilayer ceramic capacitor 30 by the second external electrode 15 of the first multilayer ceramic capacitor 10.

[0021] 1C , in the circuit configuration of this embodiment, one external electrode of the first multilayer ceramic capacitor 10 is grounded, and the other external electrode is input via the first terminal 4a. Furthermore, one external electrode of the second multilayer ceramic capacitor 30 is grounded, and the other external electrode is input via the second terminal 4b. Therefore, in this embodiment, it is necessary to avoid contact between any of the external electrodes of the first multilayer ceramic capacitor 10 and the two external electrodes of the second multilayer ceramic capacitor 30. However, this circuit configuration is merely an example, and the combination of external electrodes that should be avoided from contacting differs depending on the circuit configuration.

[0022] A first land 2a, a second land 2b, a third land 2c, and a fourth land 2d are provided on the printed wiring board 1. The second land 2b and the fourth land 2d are grounded. A first terminal 4a is provided on the first land 2a. A second terminal 4b is provided on the third land 2c.

[0023] The first external electrode 14 of the first multilayer ceramic capacitor 10 is disposed on the first land 2a on which the first terminal 4a is provided. The second external electrode 15 of the first multilayer ceramic capacitor 10 is disposed on the second land 2b, which is grounded. The second external electrode 35 of the second multilayer ceramic capacitor 30 is disposed on the third land 2c on which the second terminal 4b is provided. The first external electrode 34 of the second multilayer ceramic capacitor 30 is disposed on the fourth land 2d, which is grounded.

[0024] For this reason, in this embodiment, it is necessary to avoid contact between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the first external electrode 34 and second external electrode 35 of the second multilayer ceramic capacitor 30 .

[0025] Each external electrode is fixed to its corresponding land by a solder fillet 3. In this way, the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are mounted on the mounting surface 1a of the printed wiring board 1.

[0026] The first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are mounted on the substrate 1 so that their respective height directions are perpendicular to the mounting surface 1a.

[0027] The first multilayer ceramic capacitor 10 is mounted on the mounting surface 1a with its width direction aligned with the Y-axis direction and its length direction aligned with the X-axis direction. The first external electrode 14 is provided at one end of the first multilayer ceramic capacitor 10 along the X-axis direction, and the second external electrode 15 is provided at the other end.

[0028] The second multilayer ceramic capacitor 30 is mounted on the mounting surface 1a with its length aligned along the Y-axis direction and its width aligned along the X-axis direction. The first external electrode 34 is provided at one end of the second multilayer ceramic capacitor 30 along the Y-axis direction, and the second external electrode 35 is provided at the other end.

[0029] 1B, the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are arranged so that their respective length directions intersect at right angles. The first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are arranged adjacent to each other, with the region Ar shown in FIG. 1B overlapping the first external electrode 34 of the second multilayer ceramic capacitor 30. Here, the region Ar, as indicated by hatching in FIG. 1B, is an area obtained by extending the range of the first multilayer ceramic capacitor 10 in the width direction in the length direction of the first multilayer ceramic capacitor 10. In this specification, the adjacent state refers to a state in which no other components are mounted between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30.

[0030] The first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 may be mounted in a state rotated by 180°. The positional relationship between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 will be described in more detail later.

[0031] <Dimensional Notation of First and Second Multilayer Ceramic Capacitors> Here, the notation of dimensions of each part of the first multilayer ceramic capacitor 10 will be described with reference to FIG. 2 , which is a perspective view of the first multilayer ceramic capacitor 10. The X-axis dimension of the first multilayer ceramic capacitor 10, i.e., its length, is denoted as L

[10] , and its Y-axis dimension, i.e., its width, is denoted as W

[10] . The Z-axis dimension, i.e., its height, is denoted as T

[10] . The X-axis dimension of the first external electrode 14, i.e., its length, is denoted as L

[14] . Similarly, the X-axis dimension of the second external electrode 15, i.e., its length, is denoted as L

[15] . Furthermore, the gap between the first external electrode 14 and the second external electrode 15 along the X-axis direction is denoted as G

[10] . Note that the ceramic body 11, which will be described later, is exposed between the first external electrode 14 and the second external electrode 15.

[0032] The second multilayer ceramic capacitor 30 is similarly represented. However, the length directions of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are perpendicular to each other. Therefore, in the second multilayer ceramic capacitor 30, the Y-axis dimension is the length dimension and is represented as L

[30] , and the X-axis dimension is the width dimension and is represented as W

[30] . As with the first multilayer ceramic capacitor 10, the Z-axis dimension is the height dimension and is represented as T

[30] . The Y-axis dimension of the first external electrode 34, i.e., the length, is represented as L

[34] . Similarly, the Y-axis dimension of the second external electrode 35, i.e., the length, is represented as L

[35] . Furthermore, the gap along the Y-axis direction between the first external electrode 34 and the second external electrode 35 is represented as G

[30] . Note that the ceramic body 31, which will be described later, is exposed between the first external electrode 34 and the second external electrode 35.

[0033] <First Multilayer Ceramic Capacitor> Next, the first multilayer ceramic capacitor 10 will be described in detail with reference to FIG. 2 and FIGS. 3A to 3D. FIGS. 3A to 3D are four-sided views of the first multilayer ceramic capacitor 10. The first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are identical and generally share the same external shape. For this reason, reference numerals indicating the components of both are used in FIGS. 2 and 3A to 3D. In the following description, the X-axis, Y-axis, and Z-axis are used based on the state in which the first multilayer ceramic capacitor 10 is mounted on the substrate 1. In other words, the description is based on a coordinate system set on the substrate.

[0034] <External Shape> First, the external shape of the first multilayer ceramic capacitor 10 will be described.

[0035] The first multilayer ceramic capacitor 10 includes a ceramic body 11, a first external electrode 14, and a second external electrode 15. The ceramic body 11 is configured as a hexahedron having first and second main surfaces M11, M12 orthogonal to the Z axis, first and second end faces E11, E12 orthogonal to the X axis, and first and second side surfaces S11, S12 orthogonal to the Y axis. Note that the term "hexahedron" refers to any shape that is substantially hexahedral, and for example, the edges connecting the faces of the ceramic body 11 may be rounded.

[0036] The main surfaces M11, M12, end surfaces E11, E12, and side surfaces S11, S12 of the ceramic body 11 are all flat surfaces. According to this embodiment, the flat surfaces do not necessarily have to be strictly planar as long as they are recognized as flat when viewed overall, and include, for example, surfaces with minute irregularities or gently curved shapes within a predetermined range.

[0037] The first multilayer ceramic capacitor 10 is a tall type having a height T

[10] that is 1.3 times or more the width W

[10] . In the first multilayer ceramic capacitor 10, a large capacitance is achieved by increasing the height T

[10] . It is desirable that the height T

[10] be 1.5 times or more the width W

[10] . The height T

[10] can be, for example, 1.6 times or 1.7 times the width W

[10] , or even higher. This allows the capacitance of the first multilayer ceramic capacitor 10 to be further increased.

[0038] In this embodiment, the condition for the height T

[10] is defined by the ratio to the width W

[10] , but the condition for the height T

[10] may be set based on the relationship with the length L

[10] instead of the width W

[10] . That is, the first multilayer ceramic capacitor 10 may be a tall type in which the height T

[10] is 1.3 times or more the length W

[10] . Also, the height T

[10] may be 1.5 times or more the length L

[10] .

[0039] In the first multilayer ceramic capacitor 10, the dimension of the ceramic body 11 in the X-axis direction only needs to be larger than the dimension in the Y-axis direction, and may be smaller than the dimension in the Z-axis direction. In the first multilayer ceramic capacitor 10, the dimensions of the ceramic body 11 in the three axial directions can be determined arbitrarily within a range that satisfies the above conditions.

[0040] In the first multilayer ceramic capacitor 10 of this embodiment, for example, the length L

[10] can be set to 0.2 mm or more and 1.2 mm or less, and the width W

[10] can be set to 0.1 mm or more and 0.7 mm or less. Also, the height T

[10] can be set to 0.15 mm or more and 1.0 mm or less. The height T

[10] , width W

[10] , and length L

[10] are all the maximum dimensions of the first multilayer ceramic capacitor 10 in each direction.

[0041] The first external electrode 14 has a first surface portion 14a covering the end face E11 of the ceramic body 11. The first external electrode 14 has a second surface portion 14b extending from the first surface portion 14a to the side surface S11 and a third surface portion 14c extending to the side surface S12. Furthermore, the first external electrode 14 has a fourth surface portion 14d extending from the first surface portion 14a to the main surface M11 and a fifth surface portion 14e extending to the main surface M12.

[0042] The second external electrode 15 has a first surface portion 15a covering the end face E12 of the ceramic body 11. The second external electrode 15 has a second surface portion 15b extending from the first surface portion 15a to the side surface S11 and a third surface portion 15c extending to the side surface S12. Furthermore, the second external electrode 15 has a fourth surface portion 15d extending from the first surface portion 15a to the main surface M11 and a fifth surface portion 15e extending to the main surface M12.

[0043] Here, the second surface portions 14b, 15b, the third surface portions 14c, 15c, the fourth surface portions 14d, 15d, and the fifth surface portions 14e, 15e correspond to the extension portions.

[0044] In the external electrodes 14, 15, both the cross section parallel to the XZ plane and the cross section parallel to the XY plane are U-shaped. The shapes of the external electrodes 14, 15 are not limited to the examples shown in the drawings.

[0045] The external electrodes 14, 15 contain a metal material as a main component. Examples of the metal material constituting the external electrodes 14, 15 include copper (Cu), nickel (Ni), tin (Sn), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof. In this embodiment, the term "main component" refers to the component with the highest content.

[0046] <Internal Structure> Next, the internal structure of the first multilayer ceramic capacitor 10 will be described with reference to Fig. 4 to Fig. 5(B). Fig. 4 is a cross-sectional view of the first multilayer ceramic capacitor 10 taken along line A1-A1 in Fig. 2. Fig. 5(A) is a cross-sectional view of the first multilayer ceramic capacitor 10 taken along line A2-A2 in Fig. 2. Fig. 5(B) is a cross-sectional view of the first multilayer ceramic capacitor 10 taken along line A3-A3 in Fig. 2. Note that the second external electrode 15 is omitted in Fig. 5(B).

[0047] The ceramic body 11 has a laminated portion 20 and a pair of margin portions 18. The laminated portion 20 has a capacitance forming portion 16 and a pair of cover portions 17. The capacitance forming portion 16 includes a plurality of first and second internal electrodes 12, 13 alternately laminated with a plurality of ceramic layers 19 along the Z-axis direction. In this embodiment, the first internal electrodes 12, the second internal electrodes 13, and the ceramic layers 19 are each configured in a sheet shape extending along the X-Y plane. Note that the number of layers of the first and second internal electrodes 12, 13 in each drawing does not represent the actual number of layers.

[0048] The first and second internal electrodes 12, 13 are alternately arranged along the Z-axis direction so as to face each other in the Z-axis direction. The first and second internal electrodes 12, 13 face each other in the Z-axis direction in a facing region at the center of the X-axis and Y-axis directions. The first internal electrode 12 corresponds to a first group, is drawn from the facing region to one end face E11, and is connected to the first external electrode 14. The second internal electrode 13 corresponds to a second group, is drawn from the facing region to the other end face E12, and is connected to the second external electrode 15.

[0049] The first and second internal electrodes 12, 13 contain a metal material as a main component. Typical examples of the metal material include nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof. The metal material forming the internal electrodes 12, 13 may contain a low-melting-point metal as an additive element, the low-melting-point metal having a melting point lower than that of the main component, nickel (Ni). Examples of such low-melting-point metals include tin (Sn), zinc (Zn), aluminum (Al), gallium (Ga), and germanium (Ge). The internal electrodes 12, 13 may contain at least one of these low-melting-point metals. Adding such a low-melting-point metal can improve the sinterability within the ceramic body 11 and the insulation between the internal electrodes 12, 13.

[0050] With this configuration, when a voltage is applied between the external electrodes 14 and 15 in the first multilayer ceramic capacitor 10, the voltage is applied to the plurality of ceramic layers 19 between the internal electrodes 12 and 13 in the opposing region. As a result, a charge corresponding to the voltage between the external electrodes 14 and 15 is stored in the first multilayer ceramic capacitor 10.

[0051] In the laminated portion 20, a dielectric ceramic having a high dielectric constant is used to increase the electrostatic capacitance of each ceramic layer 19 between the first and second internal electrodes 12, 13. As the dielectric ceramic having a high dielectric constant, for example, barium titanate (BaTiO ３ Examples of suitable perovskite materials include materials with a perovskite structure containing barium (Ba) and titanium (Ti), such as ZnO, ZnO, and ZnO.

[0052] The dielectric ceramic is strontium titanate (SrTiO ３ ), calcium titanate (CaTiO ３ ), magnesium titanate (MgTiO ３ ), calcium zirconate (CaZrO ３ ), calcium zirconate titanate (Ca(Zr,Ti)O ３ ), barium calcium zirconate titanate ((Ba,Ca)(Zr,Ti)O ３ ), barium zirconate (BaZrO３ ), titanium oxide (TiO ２ ) or other compositions may be used. Here, a low-melting point metal may be added to the dielectric ceramic instead of or in addition to the addition of a low-melting point metal to the first and second internal electrodes 12, 13. The content of the low-melting point metal and the effect of adding the low-melting point metal are as described above, and therefore a detailed description thereof will be omitted here.

[0053] The pair of cover portions 17 cover the capacitance forming portion 16 from both sides in the Z-axis direction, which is the stacking direction. The cover portion 17 is sometimes referred to as a protective layer in the height direction. The cover portion 17 is formed, for example, by a laminate of ceramic sheets extending along the XY plane. From the viewpoint of suppressing internal stress, it is preferable that the dielectric ceramic forming the cover portion 17 has the same composition as the ceramic layer 19.

[0054] The pair of margin portions 18 are formed along the Z-axis direction and cover the laminated portion 20 from the Y-axis direction. The margin portions 18 are sometimes referred to as widthwise protective layers. The margin portions 18 are attached to the surfaces of the laminated portion 20 that are perpendicular to the Y-axis. For example, the margin portions 18 are formed from ceramic sheets and configured in the shape of sheets extending along the X-Z plane. From the viewpoint of suppressing internal stress, etc., it is preferable that the dielectric ceramic that constitutes the margin portions 18 has the same composition as the ceramic layers 19.

[0055] <Second Multilayer Ceramic Capacitor> The second multilayer ceramic capacitor 30 is identical to the first multilayer ceramic capacitor 10. Therefore, the above description of the first multilayer ceramic capacitor 10 generally applies to the description of the second multilayer ceramic capacitor 30. However, the X-axis, Y-axis, and Z-axis in the above description of the first multilayer ceramic capacitor 10 are based on the state in which the first multilayer ceramic capacitor 10 is mounted on the substrate 1. In other words, the description is based on a coordinate system set on the substrate. Therefore, in the description of the second multilayer ceramic capacitor 30, the X-axis will be read as the Y-axis.

[0056] The second multilayer ceramic capacitor 30 includes a ceramic body 31, a first external electrode 34, and a second external electrode 35. The ceramic body 31 is configured as a hexahedron having first and second main surfaces M31, M32 orthogonal to the Z axis, first and second end surfaces E31, E32 orthogonal to the Y axis, and first and second side surfaces S31, S32 orthogonal to the X axis.

[0057] Furthermore, although no reference numerals are assigned to any of the components of the ceramic body 31, the ceramic body 31 has a laminated portion and a pair of margin portions, similar to the ceramic body 11. The laminated portion has a capacitance forming portion and a pair of cover portions 17. The capacitance forming portion includes a plurality of first and second internal electrodes alternately laminated with a plurality of ceramic layers along the Z-axis direction. Since the components of the second multilayer ceramic capacitor 30 are the same as the components of the first multilayer ceramic capacitor 10 with the same names, detailed description thereof will be omitted here.

[0058] <Dimensional and Positional Relationship Between First and Second Multilayer Ceramic Capacitors> Returning to FIGS. 1A and 1B, the positional relationship between the first and second multilayer ceramic capacitors 10 and 30 will now be described.

[0059] The first multilayer ceramic capacitor 10 is mounted on the substrate 1 with its length direction aligned with the X-axis direction of the substrate 1. On the other hand, the second multilayer ceramic capacitor 30 is mounted on the substrate 1 with its length direction aligned with the Y-axis direction of the substrate 1. The second multilayer ceramic capacitor 30 is mounted so that its first external electrode 34 overlaps the region Ar.

[0060] Here, a gap S1 is provided between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the first external electrode 34 of the second multilayer ceramic capacitor 30. The gap S1 is the shortest distance along the X-axis direction of the substrate 1 between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the first external electrode 34 of the second multilayer ceramic capacitor 30. No other components are mounted between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30. Therefore, from the viewpoint of high-density mounting, the gap S1 is preferably set to 0.3 mm or less, more preferably 0.2 mm or less.

[0061] Furthermore, a gap S2 is set between the first external electrode 14 and the second external electrode 15 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30. The gap S2 is set to be larger than 0.5 times the height T

[10] of the first multilayer ceramic capacitor 10. The gap S2 can be set in consideration of the manner in which the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 may be tilted.

[0062] As shown in FIG. 1A , the first multilayer ceramic capacitor 10 may be tilted in the Y-axis direction, i.e., the width direction. For example, it is assumed that the upper edge of the first multilayer ceramic capacitor 10 is tilted so as to approach the second external electrode 35 of the second multilayer ceramic capacitor 30. Assume that the maximum tilt angle is 30°. In this case, as shown in FIG. 1A , the angle θ between the mounting surface 1a and the side surface S11 (see FIG. 2 ) of the first multilayer ceramic capacitor 10 is 60°. When θ = 60°, the upper edge of the first multilayer ceramic capacitor 10 approaches the second external electrode 35 of the second multilayer ceramic capacitor 30 by T

[10] × cos 60°. When the upper edge of the first multilayer ceramic capacitor 10 approaches the second external electrode 35 of the second multilayer ceramic capacitor 30, contact between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30 must be avoided. Therefore, the interval S2 is set to be larger than cos 60°=0.5 times the height T

[10] of the first multilayer ceramic capacitor 10.

[0063] Therefore, the gap S2 is set to be greater than 0.2 mm when T

[10] is 0.4 mm, and greater than 0.3 mm when T

[10] is 0.6 mm. Furthermore, the gap S2 is set to be greater than 0.4 mm when T

[10] is 0.8 mm. As described above, in this embodiment, it is necessary to avoid contact between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the first external electrode 34 and second external electrode 35 of the second multilayer ceramic capacitor 30. If an appropriate gap S2 is not set and the first multilayer ceramic capacitor 10 tilts to the right in FIG. 1B and the second multilayer ceramic capacitor 30 tilts downward in FIG. 1B, the above-described contact may occur. However, in this embodiment, an appropriate gap S2 is set. Therefore, even if both multilayer ceramic capacitors tilt, contact between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the first external electrode 34 and second external electrode 35 of the second multilayer ceramic capacitor 30 is avoided.

[0064] Here, variations in the positional relationship between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitors 30, 40, 40' will be described with reference to FIGS. 6(A) to 6(D).

[0065] 6A shows the positional relationship between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 of the first embodiment. The distance S2 between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30 is greater than 0.5×T

[10] .

[0066] (First Modification) FIG. 6B is an explanatory diagram showing the positional relationship between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 in a first modification of the first embodiment. The left-right position of the second multilayer ceramic capacitor 30 in FIG. 6A is such that the inner edge of the first external electrode 34 of the second multilayer ceramic capacitor 30 roughly coincides with the right edge of the region Ar. In contrast, the second multilayer ceramic capacitor 30 may be disposed at a position relatively shifted within a range where the first external electrode 34 of the second multilayer ceramic capacitor 30 overlaps with the region Ar, as indicated by arrow 6a in FIG. 6B. As a result, the distance between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30 is equal to or greater than the distance S2 shown in FIG. 6A, thereby avoiding contact between them.

[0067] (Second Modification) FIG. 6C is an explanatory diagram showing the positional relationship between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 40 in a second modification of the first embodiment. In the second modification, a second multilayer ceramic capacitor 40 is used instead of the second multilayer ceramic capacitor 30. The second multilayer ceramic capacitor 40 includes a first external electrode 44 and a second external electrode 45, but is longer than the second multilayer ceramic capacitor 30. The first external electrode 44 in the second modification has moved in the direction indicated by arrow 6b compared to the first external electrode 34 shown in FIG. 6A and is accommodated within the region Ar. However, in the second modification, the length of the second multilayer ceramic capacitor 40 is increased to ensure a gap S between the second external electrode 15 and the second external electrode 45 of the first multilayer ceramic capacitor 10.

[0068] (Third Modification) FIG. 6D is an explanatory diagram showing the positional relationship between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 40′ in a third modification of the first embodiment. In the third modification, a second multilayer ceramic capacitor 40′ is used instead of the second multilayer ceramic capacitor 30. The second multilayer ceramic capacitor 40′ has a first external electrode 44′ and a second external electrode 45′, but is longer than the second multilayer ceramic capacitor 30. The second multilayer ceramic capacitor 40′ is also longer than the second multilayer ceramic capacitor 40 of the second modification. This prevents short circuits from occurring.

[0069] 6C , the first external electrode 44′ of the third modified example is further shifted in the direction indicated by the arrow 6c, and its outer edge is located to the left of the left edge of the region Ar. However, in the third modified example, the length of the second multilayer ceramic capacitor 40′ is increased to ensure the interval S between the second external electrode 15 of the first multilayer ceramic capacitor 10 and the second external electrode 45′, thereby preventing the occurrence of a short circuit.

[0070] In the third and fourth modifications, the spacing S2 is ensured by increasing the length of the second multilayer ceramic capacitor, but the spacing S2 may also be ensured by shortening the length of the external electrodes.

[0071] [Effect] In this embodiment, even if the first multilayer ceramic capacitor 10 is tilted in any direction along the Y-axis direction or the second multilayer ceramic capacitor 30 is tilted in any direction along the X-axis direction, contact between the two is avoided.

[0072] This allows the height T

[10] of the first multilayer ceramic capacitor 10 and the height T

[30] of the second multilayer ceramic capacitor 30 to be set large. Furthermore, the heights of the second multilayer ceramic capacitor 40 of the third modified example and the second multilayer ceramic capacitor 40' of the fourth modified example can be set large.

[0073] In this embodiment, the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are the same, but they do not necessarily have to be the same.

[0074] Second Embodiment Next, a second embodiment will be described with reference to Figures 7A and 7B. A circuit board 120 of the second embodiment includes a first multilayer ceramic capacitor 10, a second multilayer ceramic capacitor 30, and a flip-mounted electronic component 70. In the second embodiment, two second multilayer ceramic capacitors 30 are provided. The two second multilayer ceramic capacitors 30 are arranged side by side in the longitudinal direction.

[0075] The electronic component 70 is disposed on a side of the first multilayer ceramic capacitor 10 in the width direction (Y-axis direction) and in a region along the width direction (X-axis direction) of the second multilayer ceramic capacitor 30. The electronic component 70 is disposed adjacent to the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30.

[0076] The electronic component 70 is covered with an insulating coating. Therefore, even if the first multilayer ceramic capacitor 10 or the second multilayer ceramic capacitor 30 is tilted toward the electronic component 70 located on its side, a short circuit will not occur between the first multilayer ceramic capacitor 10 or the second multilayer ceramic capacitor 30 and the electronic component 70.

[0077] This makes it possible to narrow the gap S3 between the first multilayer ceramic capacitor 10 and the electronic component 70, and the gap S4 between the second multilayer ceramic capacitor 30 and the electronic component 70. Furthermore, it is possible to set the height of the first multilayer ceramic capacitor 10 and the height of the second multilayer ceramic capacitor 30 to be large. From the viewpoint of high-density mounting, it is preferable that the gaps S3 and S4 be 0.3 mm or less, and more preferably 0.2 mm or less.

[0078] Third Embodiment Next, a third embodiment will be described with reference to FIG. 7C . A circuit board 130 of the third embodiment includes a first multilayer ceramic capacitor 10, a second multilayer ceramic capacitor 30, and electronic components 71, 72, and 73. This embodiment is similar to the second embodiment in that it includes two second multilayer ceramic capacitors 30 arranged in a row in the longitudinal direction. The electronic component 71 replaces the electronic component 70 of the second embodiment. The electronic component 72 is located in a region separated from the first multilayer ceramic capacitor 10 and one second multilayer ceramic capacitor 30 by the electronic component 71, i.e., in the region to the upper left of the electronic component 71 in FIG. 7C . The electronic component 73 is located in a region separated from the electronic component 71 by the first multilayer ceramic capacitor 10 by the electronic component 71, i.e., in the region to the left of the first multilayer ceramic capacitor 10 in FIG. 7C .

[0079] The electronic components 71, 72, and 73 are covered with an insulating coating, similar to the electronic component 70 of the embodiment. Therefore, even if the first multilayer ceramic capacitor 10 or the second multilayer ceramic capacitor 30 is tilted toward the electronic component 71, the electronic component 72, and the electronic component 73 located on its lateral side, a short circuit will not occur between the first multilayer ceramic capacitor 10 or the second multilayer ceramic capacitor 30 and the electronic components 71, 72, and 73.

[0080] 7C , it is possible to narrow the distance S5 between the external electrode of the second multilayer ceramic capacitor 30 located on the left side and the electronic component 72, and the distance S6 between the two second multilayer ceramic capacitors 30 and the electronic component 71. It is also possible to narrow the distance S7 between the first multilayer ceramic capacitor 10 and the electronic component 71, the distance S8 between the first multilayer ceramic capacitor 10 and the electronic component 73, and the distance S9 between the first multilayer ceramic capacitor 10 and the electronic component 72. It is also possible to set the height of the first multilayer ceramic capacitor 10 and the height of the second multilayer ceramic capacitor 30 to be large.

[0081] In addition, similarly to the spacings S3 and S4 in the second embodiment, from the viewpoint of high-density mounting, it is preferable that the spacings S6 to S9 be 0.3 mm or less, more preferably 0.2 mm or less.

[0082] Fourth Embodiment Next, a fourth embodiment will be described with reference to FIGS. 8 and 9. In the fourth embodiment, a first multilayer ceramic capacitor 50 is provided instead of the first multilayer ceramic capacitor 10 of the first embodiment. Although not shown, the second multilayer ceramic capacitor 30 is also changed to a multilayer ceramic capacitor similar to the first multilayer ceramic capacitor 50. The following description will mainly focus on the first multilayer ceramic capacitor 50.

[0083] FIG. 8 is a cross-sectional view of the first multilayer ceramic capacitor 50 taken along a line corresponding to line A1-A1 in FIG. 2. That is, it is a view equivalent to the cross-sectional view of the first multilayer ceramic capacitor 10 of the first embodiment taken along line A1-A1. FIG. 9A is a cross-sectional view of the first multilayer ceramic capacitor 50 taken along a line corresponding to line A2-A2 in FIG. 2. That is, it is a cross-sectional view equivalent to the A2-A2 cross-sectional view of the first multilayer ceramic capacitor 10 of the first embodiment. FIG. 9B is a cross-sectional view of the first multilayer ceramic capacitor 50 taken along a line corresponding to line A3-A3 in FIG. 2. That is, it is a cross-sectional view equivalent to the A3-A3 cross-sectional view of the first multilayer ceramic capacitor 10 of the first embodiment. Note that the second external electrode 55 is omitted in FIG. 9B.

[0084] <External Shape> The external shape of the first multilayer ceramic capacitor 50 is generally the same as that of the first multilayer ceramic capacitor 10 of the first embodiment. That is, the first multilayer ceramic capacitor 50 includes a ceramic body 51, a first external electrode 54, and a second external electrode 55. The first external electrode 54 includes a first surface portion 54a, a second surface portion (not shown), a third surface portion (not shown), a fourth surface portion 54d, and a fifth surface portion 54e. The second external electrode 55 includes a first surface portion 55a, a second surface portion (not shown), a third surface portion (not shown), a fourth surface portion 55d, and a fifth surface portion 55e. The first multilayer ceramic capacitor 50 also includes a first main surface M51, a first side surface S51, and the like. Because these components are common to the corresponding parts of the first multilayer ceramic capacitor 10 of the first embodiment, detailed description thereof will be omitted here.

[0085] The length, width, and height of the first multilayer ceramic capacitor 50 are not shown, but are represented as length L

[50] , width W

[50] , and height T

[50] , respectively, similar to the first multilayer ceramic capacitor 10 of the first embodiment. The first multilayer ceramic capacitor 50 is a tall type in which the height T

[50] is 1.3 times or more the width W

[50] . This is also similar to the first multilayer ceramic capacitor 10 of the first embodiment.

[0086] <Internal Structure> Next, the internal structure of the first multilayer ceramic capacitor 50 according to the second embodiment will be described with reference to FIGS. 8 to 9B.

[0087] The ceramic body 51 includes a laminated portion 56 and a pair of cover portions 57. The laminated portion 56 includes a capacitance-forming portion 60 and a pair of margin portions 58. The capacitance-forming portion 60 includes a plurality of first and second internal electrodes 52, 53 alternately stacked with a plurality of ceramic layers 59 along the Y-axis direction. In this embodiment, the internal electrodes 52, 53 and the ceramic layers 59 are each configured as sheets extending along the X-Z plane. The internal electrodes 52, 53 are stacked along the Y-axis direction and face each other in a direction parallel to the mounting surface 1a. This allows for a large bonding area between each first internal electrode 52 and the first external electrode 54, and a large bonding area between each second internal electrode 53 and the second external electrode 55. This prevents capacitance loss due to poor contact, or so-called capacitance loss. Note that the number of layers of the first and second internal electrodes 52, 53 in each figure does not represent the actual number of layers.

[0088] The internal electrodes 52, 53 are alternately arranged along the Y-axis direction so as to face each other in the Y-axis direction. The internal electrodes 52, 53 face each other in the Y-axis direction in a facing region in the center of the X-axis direction and the Z-axis direction. The first internal electrode 52 corresponds to a first group, is drawn from the facing region to one end face E51, and is connected to the first external electrode 54. The second internal electrode 53 corresponds to a second group, is drawn from the facing region to the other end face E52, and is connected to the second external electrode 55.

[0089] The internal electrodes 52, 53 contain a metal material as a main component. Typical examples of the metal material include nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), and alloys thereof. The internal electrodes 52, 53 may contain a low-melting-point metal, similar to the internal electrodes 12, 13 in the first embodiment.

[0090] With this configuration, when a voltage is applied between the external electrodes 54, 55 in the first multilayer ceramic capacitor 50, the voltage is applied to the plurality of ceramic layers 59 between the internal electrodes 52, 53 in the opposing region. As a result, a charge corresponding to the voltage between the external electrodes 54, 55 is stored in the second multilayer ceramic capacitor 30.

[0091] In the laminated portion 56, a dielectric ceramic having a high dielectric constant is used to increase the electrostatic capacitance of each ceramic layer 59 between the internal electrodes 52 and 53. As a dielectric ceramic having a high dielectric constant, for example, barium titanate (BaTiO ３ Examples of suitable perovskite materials include materials with a perovskite structure containing barium (Ba) and titanium (Ti), such as ZnO, ZnO, and ZnO.

[0092] The dielectric ceramic is strontium titanate (SrTiO ３ ), calcium titanate (CaTiO ３ ), magnesium titanate (MgTiO ３ ), calcium zirconate (CaZrO3), calcium titanate zirconate (Ca(Zr,Ti)O ３ ), barium calcium zirconate titanate ((Ba,Ca)(Zr,Ti)O ３ ), barium zirconate (BaZrO ３ ), titanium oxide (TiO ２ ) or other compositions may also be used. As in the first embodiment, a low melting point metal may be added to the dielectric ceramic.

[0093] The pair of cover portions 57 are formed along the Y-axis direction and cover the laminate portion 56 from the Z-axis direction. The cover portions 57 are sometimes referred to as protective layers in the height direction. The cover portions 57 are attached to the surfaces of the laminate portion 56 that are perpendicular to the Z-axis. The cover portions 57 are formed, for example, by a laminate of ceramic sheets extending along the X-Y plane. From the viewpoint of suppressing internal stress, the dielectric ceramic that forms the cover portions 57 preferably has the same composition as the ceramic layer 59.

[0094] The pair of margin portions 58 are formed along the Z-axis direction and cover the capacitance forming portion 60 from the Y-axis direction. The margin portions 58 are sometimes referred to as widthwise protective layers. The margin portions 58 are formed, for example, from a ceramic sheet and configured in a sheet shape extending along the X-Z plane. From the viewpoint of suppressing internal stress, the dielectric ceramic that forms the margin portions 58 preferably has the same composition as the ceramic layer 59.

[0095] The second multilayer ceramic capacitor employed in place of the second multilayer ceramic capacitor 30 is the same as the first multilayer ceramic capacitor 50, and therefore a detailed description thereof will be omitted.

[0096] These first multilayer ceramic capacitor 50 and second multilayer ceramic capacitor (not shown) are mounted on the substrate 1 in the same manner as the first multilayer ceramic capacitor 10 and second multilayer ceramic capacitor 30 of the first embodiment shown in FIGS. 1A and 1B.

[0097] This prevents the external electrodes from coming into contact with each other even if the tall first multilayer ceramic capacitor 50 or the second multilayer ceramic capacitor is tilted.

[0098] Note that electrostriction may occur in the first multilayer ceramic capacitor 50. The electrostriction may cause so-called acoustic noise. However, the lamination direction of the internal electrodes 52, 53 in the first multilayer ceramic capacitor 50 is the width direction, which is the mounting direction, i.e., a direction perpendicular to the Z-axis direction. This suppresses acoustic noise in the first multilayer ceramic capacitor 50. Acoustic noise caused by electrostriction is similarly suppressed in the second multilayer ceramic capacitor.

[0099] In this embodiment, the first multilayer ceramic capacitor 50 and the second multilayer ceramic capacitor are identical, but one of them may be replaced with, for example, the first multilayer ceramic capacitor 10 of the first embodiment.

[0100] Fifth Embodiment Next, a fifth embodiment will be described. The fifth embodiment differs from the first embodiment in the following respects. Referring to FIG. 10 , a partially exploded state of a ceramic body included in the first multilayer ceramic capacitor 10 is shown. The fifth embodiment includes first internal electrodes 12 and second internal electrodes 13, as in the first embodiment, but the shapes of the electrodes are different. Note that the fifth embodiment is otherwise the same as the first embodiment, and therefore, in the following description, the fifth embodiment will be described with appropriate reference to the drawings used to describe the first embodiment. Furthermore, in the description, the same reference numerals will be used for components common to the first embodiment.

[0101] As shown in FIG. 5A, the first internal electrodes 12 included in the first group are connected to the first external electrodes 14, and the second internal electrodes 13 included in the second group are connected to the second external electrodes 15.

[0102] 10 , the first internal electrode 12 of this embodiment has a connection end 12a connected to the first external electrode 14 and an open end 12b located on the opposite side of the connection end 12a. A notch 12a2 is provided in the connection end 12a, thereby forming a narrow portion 12a1. The width of the narrow portion 12a1 is narrower than the width of the portion closer to the open end 12b than the connection end 12a. In other words, the dimension of the narrow portion 12a1 in the width direction of the first multilayer ceramic capacitor 10 is smaller than the dimension of the open end 12b in the width direction of the first multilayer ceramic capacitor 10. This is also true for the second multilayer ceramic capacitor 30.

[0103] Similarly, the second internal electrode 13 of this embodiment has a connection end 13a connected to the second external electrode 15 and an open end 13b located opposite the connection end 13a. A notch 13a2 is provided in the connection end 13a, thereby forming a narrow portion 13a1. The width of the narrow portion 13a1 is narrower than the width dimension of the side closer to the open end 13b than the connection end 13a. In other words, the dimension of the narrow portion 13a1 in the width direction of the first multilayer ceramic capacitor 10 is smaller than the dimension of the open end 13b in the width direction of the first multilayer ceramic capacitor 10. This is also true for the second multilayer ceramic capacitor 30.

[0104] With this configuration, for example, when the internal electrodes 12, 13 are made of Ni and the external electrodes 14, 15 are made of Cu, it is possible to prevent cracks from occurring at the corners of the first multilayer ceramic capacitor due to expansion of the internal electrodes 12, 13 caused by diffusion of Cu from the external electrodes 14, 15. In particular, as described in the first embodiment, even when a low-melting-point metal is added to the internal electrodes 12, 13 or the dielectric ceramic, it is possible to avoid expansion of the internal electrodes 12, 13 and prevent cracks from occurring.

[0105] In the fifth embodiment, the external shapes of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30, and the dimensional and positional relationships therebetween are maintained as in the first embodiment. Therefore, in the fifth embodiment, as in the first embodiment, short circuits between the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are suppressed.

[0106] In this embodiment, the first multilayer ceramic capacitor and the second multilayer ceramic capacitor are the same. That is, the internal electrodes of both ceramic capacitors have narrow portions. However, an embodiment in which only the internal electrodes of one of the first multilayer ceramic capacitor and the second multilayer ceramic capacitor have narrow portions may also be used.

[0107] ((Modification)) Next, a modification of the fifth embodiment will be described. The fifth embodiment maintains the basic configuration of the first embodiment while changing the shapes of the internal electrodes 12, 13. In contrast, this modification maintains the basic configuration of the fourth embodiment while changing the shapes of the internal electrodes 52, 53.

[0108] 11 shows a partially exploded state of a ceramic body included in a first multilayer ceramic capacitor 80 (see FIG. 12). The first multilayer ceramic capacitor 80 corresponds to the first multilayer ceramic capacitor 50 in the fourth embodiment. In this modification, a multilayer ceramic capacitor similar to the first multilayer ceramic capacitor 80 is used as the second multilayer ceramic capacitor.

[0109] The modified example includes a first internal electrode 52 and a second internal electrode 53, similar to the fourth embodiment, but has a different shape. Since the other parts are the same as those of the fourth embodiment, the following description will explain the modified example of the fifth embodiment while referring to the drawings for explaining the fourth embodiment as appropriate. In addition, the same reference numerals will be used for components common to the fourth embodiment.

[0110] Although not shown, the first internal electrodes 52 included in the first group are connected to the first external electrodes 54. Furthermore, as shown in Fig. 9(A) , the second internal electrodes 53 included in the second group are connected to the second external electrodes 55.

[0111] 11 , the first internal electrode 52 of this modified example has a connection end 52a connected to the first external electrode 54 and an open end 52b located opposite the connection end 52a. A notch 52a2 is provided in the connection end 52a, thereby forming a narrow portion 52a1. The width of the narrow portion 52a1 is narrower than the width of the portion closer to the open end 52b than the connection end 52a. In other words, the dimension of the narrow portion 52a1 in the height direction of the first multilayer ceramic capacitor 80 is smaller than the dimension of the open end 52b in the height direction of the first multilayer ceramic capacitor 80. The width of the first internal electrode 52 is the dimension along the Z-axis direction.

[0112] Similarly, the second internal electrode 53 of this modified example has a connection end 53a connected to the second external electrode 55 and an open end 53b located opposite the connection end 53a. A notch 53a2 is provided in the connection end 53a, thereby forming a narrow portion 53a1. The width of the narrow portion 53a1 is narrower than the width of the side closer to the open end 53b than the connection end 53a. In other words, the dimension of the narrow portion 53a1 in the height direction of the first multilayer ceramic capacitor 80 is smaller than the dimension of the open end 53b in the height direction of the first multilayer ceramic capacitor 80. The width of the second internal electrode 53 is also the dimension along the Z-axis direction.

[0113] With this configuration, for example, when the internal electrodes 52, 53 are made of Ni and the external electrodes 54, 55 are made of Cu, it is possible to prevent the internal electrodes 52, 53 from expanding due to diffusion of Cu from the external electrodes 54, 55, and to prevent cracks from occurring at the corners of the first multilayer ceramic capacitor 90. In particular, as described in the third embodiment, even when a low-melting-point metal is added to the internal electrodes 52, 53 or the dielectric ceramic, it is possible to avoid expansion of the internal electrodes 12, 13 and to prevent cracks from occurring.

[0114] In this modified example, the external shape of the first multilayer ceramic capacitor 50 and the dimensional and positional relationships therebetween in the fourth embodiment are maintained, so that, similar to the fourth embodiment, short circuits between the first multilayer ceramic capacitor and the second multilayer ceramic capacitor are suppressed in the modified example.

[0115] In this embodiment, the first multilayer ceramic capacitor and the second multilayer ceramic capacitor are the same. That is, the internal electrodes of both ceramic capacitors have narrow portions. However, an embodiment in which only the internal electrodes of one of the first multilayer ceramic capacitor and the second multilayer ceramic capacitor have narrow portions may also be used.

[0116] This specification also discloses a variety of multilayer ceramic capacitors having different internal electrode lamination directions and shapes, and these multilayer ceramic capacitors can be used in appropriate combinations.

[0117] Examples Next, examples will be described together with comparative examples. In the examples, the dimensions of each part of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 in the circuit board 110 of the first embodiment were set to the values ​​shown below. Five types of combinations of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30, patterns 1 to 5, were prepared.

[0118] 13A and 13B , the comparative example has a configuration in which the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 are arranged along the Y-axis direction. In this case, the positions of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 along the X-axis direction are the same. That is, the first external electrode 14 of the first multilayer ceramic capacitor 10 and the first external electrode 34 of the second multilayer ceramic capacitor 30 are adjacent to each other along the Y-axis direction. The second external electrode 15 of the first multilayer ceramic capacitor 10 and the second external electrode 35 of the second multilayer ceramic capacitor 30 are adjacent to each other along the Y-axis direction. A gap S is provided between the first external electrode 14 and the first external electrode 34, and between the second external electrode 15 and the second external electrode 35.

[0119] <Pattern 1> First multilayer ceramic capacitor 10: Length L

[10] : 0.6 mm, width W

[10] : 0.3 mm, height T

[10] : 0.4 mm Second multilayer ceramic capacitor 30: Same as the first multilayer ceramic, and all dimensions are also the same Spacing S1: 0.1 mm The distance by which the upper edge of the first multilayer ceramic capacitor 10 approaches the second external electrode 35 of the second multilayer ceramic capacitor 30 when tilted at 30°: Height T

[10] × cos 60° = 0.4 mm × 0.5 = 0.2 mm Spacing S2: 0.3 mm

[0120] In pattern 1, T

[10] / W

[10] is approximately 1.33, which satisfies the condition for the first multilayer ceramic capacitor 10 of the first embodiment that T

[10] is 1.3 times or more W

[10] . The second multilayer ceramic capacitor 30 similarly satisfies this condition. In addition, the spacing S2 is greater than the height T

[10] ×cos 60°=0.2 mm.

[0121] <Pattern 2> First multilayer ceramic capacitor 10: Length L

[10] : 0.4 mm, width W

[10] : 0.2 mm, height T

[10] : 0.3 mm Second multilayer ceramic capacitor 30: Same as pattern 1. Spacing S1: Same as pattern 1. Distance at which the upper edge of the first multilayer ceramic capacitor 10 approaches the second external electrode 35 of the second multilayer ceramic capacitor 30 when tilted at 30°: Height T

[10] × cos 60° = 0.3 mm × 0.5 = 0.15 mm Spacing S2: 0.2 mm.

[0122] In pattern 2, T

[10] / W

[10] is 1.5, which satisfies the condition of the first multilayer ceramic capacitor 10 that T

[10] is 1.3 times or more, and even 1.5 times or more, of W

[10] . The second multilayer ceramic capacitor 30 satisfies the condition of the second multilayer ceramic capacitor 30 of the first embodiment that T

[30] is 1.3 times or more than W

[30] . In addition, the spacing S2 is greater than the height T

[10] ×cos 60°=0.15 mm.

[0123] <Pattern 3> First multilayer ceramic capacitor 10: Length L

[10] : 0.6 mm, width W

[10] : 0.3 mm, height T

[10] : 0.5 mm Second multilayer ceramic capacitor 30: Same as pattern 1. Spacing S1: Same as pattern 1. Distance at which the upper edge of the first multilayer ceramic capacitor 10 approaches the second external electrode 35 of the second multilayer ceramic capacitor 30 when the first multilayer ceramic capacitor 10 is tilted at 30°: Height T

[10] × cos 60° = 0.5 mm × 0.5 = 0.25 mm Spacing S2: Same as pattern 1.

[0124] In pattern 3, T

[10] / W

[10] is approximately 1.67, which satisfies the condition of the first multilayer ceramic capacitor 10 that T

[10] is 1.3 times or more, and even 1.5 times or more, of W

[10] . The second multilayer ceramic capacitor 30 satisfies the condition of the second multilayer ceramic capacitor 30 of the first embodiment that T

[30] is 1.3 times or more of W

[30] . In addition, the spacing S2 is greater than the height T

[10] ×cos 60°=0.25 mm.

[0125] <Pattern 4> First multilayer ceramic capacitor 10: Length L

[10] : 1.0 mm, width W

[10] : 0.5 mm, height T

[10] : 0.7 mm Second multilayer ceramic capacitor 30: Same as pattern 1. Spacing S1: Same as pattern 1. Distance at which the upper edge of the first multilayer ceramic capacitor 10 approaches the second external electrode 35 of the second multilayer ceramic capacitor 30 when tilted at 30°: Height T

[10] x cos 60° = 0.7 mm x 0.5 = 0.35 mm Spacing S2: 0.5 mm

[0126] In pattern 4, T

[10] / W

[10] is approximately 1.4, which satisfies the condition of the first multilayer ceramic capacitor 10 that T

[10] is 1.3 times or more than W

[10] . The second multilayer ceramic capacitor 30 satisfies the condition of the second multilayer ceramic capacitor 30 of the first embodiment that T

[30] is 1.3 times or more than W

[30] . In addition, the spacing S2 is greater than the height T

[10] ×cos 60°=0.35 mm.

[0127] <Pattern 5> First multilayer ceramic capacitor 10: Length L

[10] : 1.0 mm, width W

[10] : 0.5 mm, height T

[10] : 0.8 mm Second multilayer ceramic capacitor 30: Same as the first multilayer ceramic, and all dimensions are also the same Spacing S1: Same as pattern 1. When the first multilayer ceramic capacitor 10 is tilted at 30°, the distance by which its upper edge approaches the second external electrode 35 of the second multilayer ceramic capacitor 30: Height T

[10] x cos 60° = 0.8 mm x 0.5 = 0.4 mm Spacing S2: 0.5 mm

[0128] In pattern 4, T

[10] / W

[10] is 1.6, which satisfies the condition of the first multilayer ceramic capacitor 10 that T

[10] is 1.3 times or more, and even 1.5 times or more, of W

[10] . The second multilayer ceramic capacitor 30 satisfies the condition of the second multilayer ceramic capacitor 30 of the first embodiment that T

[30] is 1.3 times or more than W

[30] . In addition, the spacing S2 is greater than the height T

[10] ×cos 60°=0.4 mm.

[0129] Comparative Example First multilayer ceramic capacitor 10: Length L

[10] : 0.6 mm, width W

[10] : 0.3 mm, height T

[10] : 0.4 mm, spacing S: 0.1 mm

[0130] In the comparative example, T

[10] / W

[10] is approximately 1.33, which satisfies the condition of the first multilayer ceramic capacitor 10 of the first embodiment that T

[10] is 1.3 times or more W

[10] .

[0131] [Test Method] A predetermined number of samples were prepared for each of the example patterns 1 to 5 and the comparative example. From these, samples in which the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 were determined to be tilted were extracted. A voltage was applied between the first test terminal 4a and the second test terminal 4b of each extracted sample to check for the occurrence of a short circuit.

[0132] [Test Results] In the patterns 1 to 4 of the example, no short circuit was observed in any of the samples.

[0133] In the comparative example, the presence of samples in which short circuits occurred was confirmed. In such samples, tilting of the first multilayer ceramic capacitor 10 was confirmed. In the comparative example, as shown in Figures 14(A) and 14(B), when at least one of the first multilayer ceramic capacitor 10 and the second multilayer ceramic capacitor 30 tilts so as to approach each other, the first external electrode 14 comes into contact with the first external electrode 34, and the second external electrode 15 comes into contact with the second external electrode 35. This causes a short circuit.

[0134] Thus, according to this embodiment, the occurrence of a short circuit can be suppressed even when T

[10] is 1.3 times or more than W

[10] , and even when T

[10] is 1.5 times or more than W

[10] .

[0135] In the second to fifth embodiments and their modifications, the external shape of the first multilayer ceramic capacitor 10 and the dimensional and positional relationships with the second multilayer ceramic capacitor 30 in the first embodiment are maintained. Therefore, it is considered that the occurrence of short circuits can be similarly suppressed in all the embodiments.

[0136] Although the above embodiments have been described with reference to a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component, the present invention is not limited thereto. For example, the configurations of the above embodiments can be applied to other multilayer ceramic electronic components such as varistors and thermistors.

[0137] The above-described embodiments are merely examples for implementing the present invention, and the present invention is not limited to these. Various modifications of these embodiments are within the scope of the present invention. Furthermore, it is obvious from the above description that various other embodiments are possible within the scope of the present invention.

[0138] REFERENCE SIGNS LIST 1...printed wiring board, 2a...first land, 2b...second land, 2c...third land, 2d...fourth land, 3...solder fillet, 10, 50, 80...first multilayer ceramic capacitor, 11, 31, 51...ceramic body, M11, M51...first main surface, M12...second main surface, E11...first end face, E12...second end face, S11, S51...first side face, S12...second Two side surfaces, 12, 13, 52, 53, 92, 93... internal electrodes, 14, 34, 54... first external electrodes, 15, 35, 55... second external electrodes, 16, 60... capacitance forming portions, 17, 57... cover portions, 18, 58... margin portions, 19, 59... ceramic layers, 20, 56... laminated portions, 30, 40, 40'... second laminated ceramic capacitor, 110, 120, 130... circuit board

Claims

1. a substrate on which a first axis perpendicular to a mounting surface, and a second axis and a third axis perpendicular to the first axis and perpendicular to each other are set; a plurality of multilayer ceramic electronic components mounted on the mounting surface, a first multilayer ceramic electronic component included in the plurality of multilayer ceramic electronic components is mounted on the mounting surface with its height direction aligned with the direction along the first axis, its width direction aligned with the direction along the second axis, and its length direction aligned with the third axis direction, and has a first external electrode at one end in the length direction and having a predetermined length along the length direction, and a second external electrode at the other end in the length direction and having a predetermined length along the length direction; a second multilayer ceramic electronic component included in the plurality of multilayer ceramic electronic components is mounted on the mounting surface with its height direction aligned with the direction along the first axis, its length direction aligned with the direction along the second axis, and its width direction aligned with the third axis direction, and has a first external electrode at one end in the length direction and having a predetermined length along the length direction, and a second external electrode at the other end in the length direction and having a predetermined length along the length direction, a height dimension of the first multilayer ceramic electronic component is 1.3 times or more the width dimension or length dimension of the first multilayer ceramic electronic component, and a height dimension of the second multilayer ceramic electronic component is 1.3 times or more the width dimension of the second multilayer ceramic electronic component; the first and second multilayer ceramic electronic components are arranged adjacent to each other on the mounting surface in a manner that their respective length directions are perpendicular to each other, and a region obtained by extending a range of the first multilayer ceramic electronic component in the width direction thereof in the length direction of the first multilayer ceramic electronic component overlaps with one of the first external electrode and the second external electrode of the second multilayer ceramic electronic component; Circuit board.

2. a distance in a direction along the second axis between the first external electrode and the second external electrode of the first multilayer ceramic electronic component and the other of the first external electrode and the second external electrode of the second multilayer ceramic electronic component is greater than 0.5 times a height dimension of the first multilayer ceramic electronic component; The circuit board according to claim 1 .

3. another electronic component covered with an insulating coating is mounted adjacent to the first and second multilayer ceramic electronic components in a region that is on the side of the first multilayer ceramic electronic component along the second axis direction and that is along the third axis direction of the second multilayer ceramic electronic component; The circuit board according to claim 1 .

4. another electronic component covered with an insulating coating is mounted adjacent to the first and second multilayer ceramic electronic components in a region that is on the side of the first multilayer ceramic electronic component along the third axis direction and that is along the second axis direction of the second multilayer ceramic electronic component; The circuit board according to claim 1 .

5. At least one of the height dimension of the first multilayer ceramic electronic component and the height dimension of the second multilayer ceramic electronic component is 1.5 times or more the width dimension or length dimension of the first multilayer ceramic electronic component or the second multilayer ceramic electronic component, The circuit board according to claim 1 .

6. at least one of the internal electrodes provided in the ceramic body of the first multilayer ceramic electronic component and the internal electrodes provided in the ceramic body of the second multilayer ceramic electronic component is laminated so as to face each other in a direction along the height direction of the respective electrodes; The circuit board according to claim 1 .

7. the internal electrodes stacked in the height direction include a first internal electrode connected to the first external electrode and a second internal electrode connected to the second external electrode, the first internal electrode has a connection end connected to the first external electrode and an open end located opposite to the connection end, the connection end having a narrow portion whose dimension along the width direction is smaller than the dimension of the open end along the width direction, the second internal electrode has a connection end connected to the second external electrode and an open end located opposite to the connection end, and the connection end has a narrow portion whose dimension along the width direction is smaller than the dimension of the open end along the width direction; The circuit board according to claim 6.

8. at least one of the internal electrodes provided in the ceramic body of the first multilayer ceramic electronic component and the internal electrodes provided in the ceramic body of the second multilayer ceramic electronic component is laminated so as to face each other in a direction along the width direction of the respective electrodes; The circuit board according to claim 1 .

9. the internal electrodes stacked in the width direction include a first internal electrode connected to the first external electrode and a second internal electrode connected to the second external electrode, the first internal electrode has a connection end connected to the first external electrode and an open end located opposite to the connection end, the connection end having a narrow portion whose dimension in the height direction is smaller than the dimension of the open end along the height direction, the second internal electrode has a connection end connected to the second external electrode and an open end located opposite to the connection end, and the connection end has a narrow portion whose dimension in the height direction is smaller than the dimension of the open end along the height direction; The circuit board according to claim 8 .

10. The internal electrodes or the dielectric layers formed between the internal electrodes contain a low-melting point metal. The circuit board according to claim 7 or 9.

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