Semiconductor device

Abstract

The present invention suppresses the occurrence of damage to a bonding member for bonding a semiconductor chip to a wiring board.　A semiconductor device comprises: a semiconductor chip (12); and an insulating circuit board (11) that has a wiring board (11b2) on a front surface, has a rear surface facing downward, and is bent to protrude downward, with the semiconductor chip (12) being bonded via a bonding member (14a) to a bonding region on an upper surface of the wiring board (11b2) which is inclined on the front surface due to the bending. The semiconductor chip (12) is bonded to the bonding region, with an end of the rear surface of the semiconductor chip (12) on the side of an apex (16b) of the bent section of the insulating circuit board (11) being supported by a support part (15) provided in the bonding region. Therein, the semiconductor chip (12) is made substantially parallel to the bonding region of the wiring board (11b2) by the support part (15), and the thickness of the bonding member (14a) is substantially uniform. Due to this configuration, the occurrence of cracks in the bonding member (14a) is reduced.

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] The first semiconductor chip and the second semiconductor chip are bonded to the wiring portion via the first solder portion and the second solder portion, respectively. The thickness of the first solder portion is smaller than the thickness of the second solder portion. As a result, if the insulating substrate including the second semiconductor chip and the wiring portion deforms due to thermal fluctuations, the second solder portion has difficulty absorbing this deformation, making it more likely to crack (see, for example, Patent Document 1). Furthermore, when the semiconductor chip is bonded to the circuit pattern via the bonding material, a smooth protrusion without corners is formed in the area of ​​the circuit pattern facing the semiconductor chip. This improves the fatigue resistance of the bonding material (see, for example, Patent Document 2).

[0003] The semiconductor device includes a conductor layer and a semiconductor element bonded to the conductor layer via a solder layer, and the solder layer includes wire bumps. This allows the solder layer to have a uniform thickness and prevents voids from occurring in the solder layer (see, for example, Patent Document 3). Furthermore, in a mounting member in which a semiconductor chip is bonded to a mounting surface with solder, two regions with different wettability are provided around the semiconductor chip. This prevents misalignment, including rotation, of the semiconductor chip (see, for example, Patent Document 4).

[0004] JP 2022-174923 A JP 2020-009995 A JP 2019-110317 A JP 2009-218280 A

[0005] An object of the present invention is to provide a semiconductor device in which damage to a bonding member that bonds a semiconductor chip to a wiring board is suppressed.

[0006] According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor chip; and a substrate that includes a wiring board on its front surface, that is warped convexly downward with its back surface facing downward, and that is bonded via a first bonding member to a bonding area on the upper surface of the wiring board that is inclined at the front surface due to the warping; wherein the semiconductor chip is bonded to the bonding area by a support portion provided in the bonding area, with the end of the back surface of the semiconductor chip that is on the apex side of the warp of the substrate being supported by a support portion provided in the bonding area.

[0007] The semiconductor chip may be substantially parallel to the bonding area of ​​the wiring board.

[0008] The support portion may be formed on the vertex side of the bonding region of the wiring board and have a protrusion shape. A plurality of the support portions may be formed on the vertex side of the bonding region of the wiring board.

[0009] The semiconductor chip may have a rectangular shape in a plan view, and the support portions may be formed in correspondence with two corners of the semiconductor chip on the apex side relative to the bonding region of the wiring board.

[0010] The support portion may be formed in the bonding region of the wiring board and may include an inclined surface that is inclined higher on a side closer to the apex than on a side farther from the apex in a side view. The semiconductor chip may be rectangular in a plan view, and the support portion may be formed along a side of the semiconductor chip that is closer to the apex than on the bonding region of the wiring board.

[0011] The support portion may be a roughened region in which the apex side of the bonding region of the wiring board is roughened. The support portion may include a plurality of the roughened regions.

[0012] The semiconductor chip may have a rectangular shape in a plan view, and the support portions may be formed in correspondence with two corners of the semiconductor chip on the apex side relative to the bonding region of the wiring board.

[0013] The support portion may be a wire formed on the vertex side of the bonding region of the wiring board. The semiconductor chip may be rectangular in plan view, and the support portion may be formed along the vertex side of the semiconductor chip with respect to the bonding region of the wiring board.

[0014] The support portions may be formed in the bonding region of the wiring board so as to correspond to two corners of the semiconductor chip on the vertex side. The wiring board may further include a wiring member having a flat bonding portion bonded to a main electrode on the front surface of the semiconductor chip via a second bonding member.

[0015] The bonding portion of the wiring member may be substantially parallel to the front surface of the semiconductor chip. A protrusion may be formed on the bonding surface of the bonding portion that is bonded to the main electrode of the semiconductor chip. Note that the above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also constitute inventions.

[0016] According to the disclosed technology, it is possible to suppress the occurrence of damage to the bonding member that bonds the semiconductor chip to the wiring board, and to prevent a decrease in the reliability of the semiconductor device.

[0017] The above and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings illustrating preferred embodiments of the present invention.

[0018] 1 is a plan view of a semiconductor device according to an embodiment; a side view of the semiconductor device according to an embodiment; a plan view of a semiconductor unit included in the semiconductor device according to an embodiment; a plan view of an insulating circuit board included in the semiconductor device according to an embodiment; a first side view of a semiconductor unit included in the semiconductor device according to an embodiment; a second side view of a semiconductor unit included in the semiconductor device according to an embodiment; a third side view of a semiconductor unit included in the semiconductor device according to an embodiment; a fourth side view of a semiconductor unit included in the semiconductor device according to an embodiment; a plan view (part 1) of an insulating circuit board included in the semiconductor device according to an embodiment, showing another warpage; a second side view (part 1) of a semiconductor unit included in the semiconductor device according to an embodiment, in which another warpage has occurred; a fourth side view (part 1) of a semiconductor unit included in the semiconductor device according to an embodiment, in which another warpage has occurred; a plan view (part 2) of an insulating circuit board included in the semiconductor device according to an embodiment, showing another warpage; a second side view (part 2) of a semiconductor unit included in the semiconductor device according to an embodiment, in which another warpage has occurred; a fourth side view (part 2) of a semiconductor unit included in the semiconductor device according to an embodiment, in which another warpage has occurred; a cross-sectional view of a semiconductor device according to an embodiment; a back view of a cooling device included in the semiconductor device according to an embodiment; and a flowchart showing a method for manufacturing a semiconductor device according to an embodiment. FIG. 1 is a diagram illustrating a state after a setting step included in the method for manufacturing a semiconductor device of an embodiment; FIG. 2 is a diagram illustrating a state after a setting step included in the method for manufacturing a semiconductor device of a reference example; FIG. 3 is a diagram illustrating a first bonding step included in the method for manufacturing a semiconductor device of a reference example; FIG. 4 is a diagram illustrating an insulating circuit board included in a semiconductor device of an embodiment (variation 1); FIG. 5 is a diagram illustrating an insulating circuit board included in a semiconductor device of an embodiment (variation 2); FIG. 6 is a diagram illustrating an insulating circuit board included in a semiconductor device of an embodiment (variation 3); and FIG. 7 is a diagram illustrating an insulating circuit board included in a semiconductor device of an embodiment (variation 4).

[0019] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "top surface" refer to the X-Y plane facing upward (+Z direction) in the semiconductor device 1 shown in the drawings. Similarly, "top" refers to the upward (+Z direction) direction in the semiconductor device 1 shown in the drawings. The terms "back surface" and "bottom surface" refer to the X-Y plane facing downward (-Z direction) in the semiconductor device 1 shown in the drawings. Similarly, "bottom" refers to the downward (-Z direction) direction in the semiconductor device 1 shown in the drawings. Similar orientations will be used in other drawings as necessary. The terms "front surface," "top surface," "top," "back surface," "bottom surface," "bottom," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "top" and "bottom" do not necessarily refer to the vertical direction relative to the ground. In other words, the "top" and "bottom" directions are not limited to the direction of gravity. In the following description, the term "main component" refers to a component containing 80 vol% or more of a component. Furthermore, "substantially the same" means within a range of ±10%, and "perpendicular" and "parallel" means within a range of ±10°.

[0020] [Embodiment] A semiconductor device 1 according to an embodiment will be described with reference to Figures 1 and 2. Figure 1 is a plan view of the semiconductor device according to the embodiment, and Figure 2 is a side view of the semiconductor device according to the embodiment. Note that Figure 2 is a side view of the XZ plane in Figure 1 as viewed in the +Y direction.

[0021] The semiconductor device 1 includes a semiconductor module 2 and a cooling device 3. The semiconductor module 2 includes semiconductor units 10a, 10b, and 10c and a housing 20 that houses the semiconductor units 10a, 10b, and 10c. The semiconductor units 10a, 10b, and 10c housed in the housing 20 are sealed with a sealing member (not shown). The semiconductor units 10a, 10b, and 10c all have the same configuration. When there is no need to distinguish between the semiconductor units 10a, 10b, and 10c, they will be described as the semiconductor unit 10. Details of the semiconductor unit 10 will be described later.

[0022] First, the housing 20 includes a frame portion 21, first connection terminals 22a, 22b, and 22c, second connection terminals 23a, 23b, and 23c, a U-phase output terminal 24a, a V-phase output terminal 24b, a W-phase output terminal 24c, and control terminals 25a, 25b, and 25c.

[0023] The frame 21 has a generally rectangular shape in plan view and is surrounded on all four sides by outer walls 21a, 21b, 21c, and 21d. The outer walls 21a and 21c correspond to the long sides of the frame 21 in plan view, and the outer walls 21b and 21d correspond to the short sides of the frame 21. In plan view, the corners at the connections between the outer walls 21a, 21b, 21c, and 21d do not necessarily have to be right angles. These corners may be rounded as shown in FIG. 1 . Fixing holes 21i penetrating the frame 21 are formed at the corners of the front surface of the frame 21. The fixing holes 21i formed at these corners of the frame 21 may be formed lower (in the −Z direction) than the front surface of the frame 21.

[0024] The frame 21 includes unit storage sections 21e, 21f, and 21g on its front surface along the outer walls 21a and 21c. The unit storage sections 21e, 21f, and 21g have rectangular openings in a plan view. The unit storage sections 21e, 21f, and 21g store the semiconductor units 10a, 10b, and 10c, respectively. As will be described in detail later, the semiconductor units 10a, 10b, and 10c are each joined to a top plate 31 of the cooling device 3, which will be described later. The frame 21 is attached to the top plate 31 of the cooling device 3. When attached, the unit storage sections 21e, 21f, and 21g of the frame 21 surround (store) the semiconductor units 10a, 10b, and 10c arranged in the cooling device 3, respectively. An inlet 33a and an outlet 33b are formed on a bottom surface 33d (the surface opposite to the top plate 31 on which the semiconductor unit 10 is attached) of the cooling device 3. Details of the cooling device 3 will be described later.

[0025] In a plan view, the frame 21 includes first connection terminals 22a, 22b, and 22c and second connection terminals 23a, 23b, and 23c along the outer wall 21a on the front surface facing the outer wall 21a. One outer end of each of the first connection terminals 22a, 22b, and 22c and the second connection terminals 23a, 23b, and 23c is exposed on the front surface facing the outer wall 21a. The other inner end is exposed inside the unit storage compartments 21e, 21f, and 21g and is electrically connected to the semiconductor units 10a, 10b, and 10c. Note that nuts facing the openings of the first connection terminals 22a, 22b, and 22c and the second connection terminals 23a, 23b, and 23c on the front surface of the frame 21 may be stored in areas facing the openings.

[0026] On the front surface facing the outer wall 21c, a U-phase output terminal 24a, a V-phase output terminal 24b, and a W-phase output terminal 24c are provided along the outer wall 21c. One outer end of each of the U-phase output terminal 24a, the V-phase output terminal 24b, and the W-phase output terminal 24c is exposed from the outer wall 21c. The other inner end is exposed inside the unit storage portions 21e, 21f, and 21g and is electrically connected to the semiconductor units 10a, 10b, and 10c.

[0027] Thus, in plan view, the front surface of the frame 21 is provided with the first and second connection terminals 22a, 23a, and the W-phase output terminal 24c, sandwiching the unit storage section 21e between them. Similarly, the first and second connection terminals 22b, 23b, and the V-phase output terminal 24b are provided with the unit storage section 21f between them. Similarly, the first and second connection terminals 22c, 23c, and the U-phase output terminal 24a are provided with the unit storage section 21g between them.

[0028] Furthermore, in a plan view, the frame 21 includes control terminals 25a, 25b, and 25c along the outer wall 21c on the +Y direction side of the unit storage sections 21e, 21f, and 21g. Each of the control terminals 25a, 25b, and 25c is provided in two parts. The control terminals 25a, 25b, and 25c are, for example, L-shaped and include an outer end and an inner end. The outer ends of the control terminals 25a, 25b, and 25c extend vertically upward (in the +Z direction) from the front surface of the frame 21. The other ends of the control terminals 25a, 25b, and 25c are exposed inside the unit storage sections 21e, 21f, and 21g. The shape and number of the control terminals 25a, 25b, and 25c are not limited to those described above and can be modified as appropriate.

[0029] The frame 21 includes first connection terminals 22a, 22b, and 22c, second connection terminals 23a, 23b, and 23c, a U-phase output terminal 24a, a V-phase output terminal 24b, a W-phase output terminal 24c, and control terminals 25a, 25b, and 25c, and is integrally molded by injection molding using a thermoplastic resin such as polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0030] The first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b, 25c are made of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy containing at least one of these as a main component. The surfaces of the first connection terminals 22a, 22b, 22c, the second connection terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b, 25c may be plated. Examples of plating materials used in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0031] The sealing member 27 (see FIG. 9 ) that seals the unit housing sections 21 e, 21 f, and 21 g of the housing 20 may be made of a thermosetting resin. Examples of the thermosetting resin include epoxy resin, phenol resin, maleimide resin, and polyester resin. Epoxy resin is preferable. Furthermore, a filler may be added to the sealing member 27. The filler may be an insulating ceramic with high thermal conductivity.

[0032] Next, the semiconductor units 10a, 10b, and 10c will be described with reference to Figures 3 and 4. Figure 3 is a plan view of a semiconductor unit included in a semiconductor device according to an embodiment. Figure 4 is a plan view of an insulating circuit board 11 of the semiconductor unit 10 in Figure 3.

[0033] The semiconductor unit 10 includes an insulating circuit board 11, two semiconductor chips 12, and lead frames 13a and 13b. The semiconductor chip 12 is joined to the insulating circuit board 11 by a joining member 14a (see FIGS. 5 to 8). The lead frames 13a and 13b are joined to main electrodes on the front surface of the semiconductor chip 12 by a joining member 14b (see FIGS. 5 to 8).

[0034] As shown in FIG. 4, the insulating circuit board 11 includes an insulating plate 11a, wiring boards 11b1, 11b2, and 11b3, and a metal plate 11c (see FIGS. 5 to 8). The insulating circuit board 11 also includes a support portion 15. The areas (vertices 16a to 16d) indicated by dashed lines in FIG. 4 indicate the positions of the vertices 16a to 16d of warpage that occur in the insulating circuit board 11 in a plan view. The support portion 15 is formed at these positions when the vertices 16b and 16d of warpage occur. The vertices 16a to 16d of warpage do not necessarily have to occur at the same time at these positions. At least one may occur. The positions of the vertices 16a to 16d of warpage shown in FIG. 4 are merely examples. Other examples of the positions of the vertices of warpage that occur in the insulating circuit board 11 in a plan view will be described later.

[0035] The insulating plate 11a and the metal plate 11c are rectangular in plan view. The corners of the insulating plate 11a and the metal plate 11c may be rounded or chamfered. The size of the metal plate 11c is smaller than the size of the insulating plate 11a in plan view, and the metal plate 11c is formed inside the insulating plate 11a.

[0036] The insulating plate 11a includes side surfaces 11a1 to 11a4 that surround the four sides of the front surface in order. The side surfaces 11a1 and 11a3 correspond to the short sides of the insulating plate 11a in a plan view. The side surfaces 11a2 and 11a4 correspond to the long sides of the insulating plate 11a in a plan view. The insulating plate 11a also includes four corners 11a5 to 11a8. The corner 11a5 is formed by the side surfaces 11a1 and 11a2. The corner 11a6 is formed by the side surfaces 11a2 and 11a3. The corner 11a7 is formed by the side surfaces 11a3 and 11a4. The corner 11a8 is formed by the side surfaces 11a4 and 11a1. The insulating plate 11a is made of a material that has insulating properties and excellent thermal conductivity. The insulating plate 11a is made of ceramics. The ceramic is, for example, aluminum oxide, aluminum nitride, or silicon nitride.

[0037] The wiring boards 11b1, 11b2, and 11b3 are formed on the front surface of the insulating plate 11a. The wiring boards 11b1, 11b2, and 11b3 are made of a metal with excellent conductivity. Such metals include, for example, copper, aluminum, or an alloy containing at least one of these as a main component. The thickness of the wiring boards 11b1, 11b2, and 11b3 is 0.1 mm or more and 2.0 mm or less. The surfaces of the wiring boards 11b1, 11b2, and 11b3 may be plated to improve corrosion resistance. Examples of plating materials used in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0038] The wiring board 11b1 occupies half of the area on the side surface 11a4 side of the front surface of the insulating plate 11a, occupying the entire area from side surface 11a1 to side surface 11a3. A bonding area 11d is defined on the top surface of the wiring board 11b1. The semiconductor chip 12 is bonded to the bonding area 11d, and the bonding area 11d corresponds to the shape of the semiconductor chip 12 in a plan view. The inner ends of the first connection terminals 22a, 22b, and 22c are bonded to the broken-line area shown on the edge of the front surface of the wiring board 11b1 in the -Y direction. This bonding may be achieved by means of a bonding material, laser welding, or ultrasonic bonding. Alternatively, the broken-line area shown on the wiring board 11b1 and the inner ends of the first connection terminals 22a, 22b, and 22c may be bonded via a conductive block.

[0039] The wiring board 11b2 occupies half of the front surface of the insulating board 11a on the side surface 11a2 side. Furthermore, the wiring board 11b2 occupies the front surface of the insulating board 11a from the side surface 11a3 to just before the side surface 11a1. A bonding area 11d is defined on the front surface of the wiring board 11b2. Furthermore, a support portion 15 is provided within the bonding area 11d of the wiring board 11b2.

[0040] The support portions 15 are protruding. Such support portions 15 may be, for example, columnar. The columnar shape may include a cylindrical shape, a rectangular prism shape, a triangular prism shape, and also a truncated cone shape. The support portions 15 are provided on the vertices 16b and 16d side of the bonding region 11d, respectively, at the corners of the bonding region 11d. A plurality of support portions 15 may be formed on the vertices 16b and 16d side of the bonding region 11d, as will be described later. The location of the support portions 15 depends on the position of the vertex of the warp, as will be described later. In the case of FIG. 4, the support portions 15 are formed on the vertices 16b and 16d side of the bonding region 11d. In addition, the support portions 15 may not be formed depending on the position of the vertex of the warp. The location of the support portions 15 formed depending on the position of the vertex of the warp will be described later.

[0041] Furthermore, the support portion 15 is preferably made of a conductive material. Such a metal is, for example, copper, aluminum, or an alloy containing at least one of these as a main component. Alternatively, the support portion 15 may be disposed on the wiring board 11b2 and bonded to the wiring board 11b2. This electrically connects the main electrode on the back surface of the semiconductor chip 12 to the wiring board 11b2. Furthermore, the support portion 15 may be sandwiched from the back surface of the semiconductor chip 12.

[0042] Furthermore, the dashed-line region shown on the +Y-direction side of the front surface of wiring board 11b2 is where the inner ends of U-phase output terminal 24a, V-phase output terminal 24b, and W-phase output terminal 24c are joined. This joining may be performed using a joining material, laser welding, or ultrasonic welding. Alternatively, the dashed-line region shown on wiring board 11b2 and the inner ends of U-phase output terminal 24a, V-phase output terminal 24b, and W-phase output terminal 24c may be joined via a conductive block.

[0043] Wiring board 11b3 occupies the area surrounded by wiring boards 11b1 and 11b2 on the front surface of insulating board 11a. The dashed-line area on wiring board 11b3 is where the ends of second connection terminals 23a, 23b, and 23c are joined. This joining may be achieved by using a joining material, laser welding, or ultrasonic welding. Alternatively, the dashed-line area on wiring board 11b3 and the ends of second connection terminals 23a, 23b, and 23c may be connected via a conductive block.

[0044] Such wiring boards 11b1, 11b2, and 11b3 are formed on the front surface of insulating plate 11a as follows. A metal layer is formed on the front surface of insulating plate 11a, and then the metal layer is subjected to etching or other processing to obtain wiring boards 11b1, 11b2, and 11b3 of a predetermined shape. Alternatively, wiring boards 11b1, 11b2, and 11b3 may be pre-cut from the metal layer and then pressure-bonded to the front surface of insulating plate 11a. The corners of wiring boards 11b1, 11b2, and 11b3 may be round-chamfered or chamfered. Note that wiring boards 11b1, 11b2, and 11b3 are merely examples. The number, shape, size, and position of wiring boards 11b1, 11b2, and 11b3 may be appropriately selected as needed.

[0045] As shown in FIGS. 5 to 8 , the metal plate 11c is formed on the back surface of the insulating plate 11a. The metal plate 11c is rectangular. The area of ​​the metal plate 11c in a plan view is smaller than that of the insulating plate 11a and larger than the area of ​​the region where the wiring boards 11b1, 11b2, and 11b3 are formed. The corners of the metal plate 11c may be round-chamfered or C-chamfered. The metal plate 11c is smaller than the insulating plate 11a and is formed on the entire surface of the insulating plate 11a except for the edges. The metal is, for example, copper, aluminum, or an alloy containing at least one of these. The surface of the metal plate 11c may be plated to improve corrosion resistance. Examples of plating materials used in this case include nickel, nickel-phosphorus alloys, and nickel-boron alloys.

[0046] For example, a DCB (Direct Copper Bonding) board or an AMB (Active Metal Brazed) board may be used as the insulating circuit board 11 having such a configuration. The insulating circuit board 11 may be attached to the front surface of the cooling device 3 via a bonding member (not shown). Heat generated in the semiconductor chip 12 can be conducted to the cooling device 3 via the wiring boards 11b1 and 11b2, the insulating plate 11a, and the metal plate 11c, and dissipated.

[0047] The joining members 14a and 14b are solder. Lead-free solder is used as the solder. Lead-free solder is mainly composed of an alloy containing at least two of tin, silver, copper, zinc, antimony, indium, and bismuth, for example. The solder may also contain additives. Examples of the additives include nickel, germanium, cobalt, and silicon. The addition of additives to the solder improves the wettability, gloss, and bonding strength, thereby improving reliability.

[0048] The joining member (not shown) joining the semiconductor unit 10 and the cooling device 3 may be solder, brazing filler metal, or thermal interface material. Lead-free solder is used as the solder. The brazing filler metal is primarily composed of at least one of an aluminum alloy, a titanium alloy, a magnesium alloy, a zirconium alloy, and a silicon alloy. The thermal interface material is, for example, an adhesive material containing an elastomer sheet, RTV (Room Temperature Vulcanization) rubber, a gel, a phase change material, or the like. Attaching the semiconductor unit 10 to the cooling device 3 via such brazing filler metal or thermal interface material can improve the heat dissipation of the semiconductor unit 10.

[0049] The semiconductor chip 12 includes a power device element made of silicon. The thickness of the semiconductor chip 12 is, for example, 40 μm or more and 250 μm or less. The power device element is an RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor). The RC-IGBT combines the functions of an IGBT, which is a switching element, and an FWD (Free Wheeling Diode), which is a diode element. The front surface of the semiconductor chip 12 includes a control electrode 12a (gate electrode) and a main electrode 12b, which is an output electrode (emitter electrode). The back surface of the semiconductor chip 12 includes an input electrode (collector electrode), which is a main electrode (not shown). The control electrode 12a may be provided along one edge of the front surface of the semiconductor chip 12 (or in the center of that edge). The output electrode is provided in the center of the front surface of the semiconductor chip 12. The input electrode is provided including the center of the back surface of the semiconductor chip.

[0050] The semiconductor chip 12 may also use a pair of switching elements and diode elements instead of the RC-IGBT. The switching elements are, for example, IGBTs and power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Such a semiconductor chip 12 has, for example, an input electrode (drain electrode or collector electrode) as a main electrode on the back surface, and a control electrode 12a (gate electrode) and an output electrode (source electrode or emitter electrode) as a main electrode 12b on the front surface. The diode elements are, for example, Schottky Barrier Diodes (SBDs) and P-intrinsic-N (PiN) diodes, which are used as FWDs. Such a semiconductor chip 12 has, for example, an output electrode (cathode electrode) as a main electrode on the back surface, and an input electrode (anode electrode) as a main electrode on the front surface.

[0051] The semiconductor chip 12 may also include a switching element made of a power MOSFET. This semiconductor chip 12 includes a FWD in addition to the power MOSFET. Such a semiconductor chip 12 includes a control electrode 12a (gate electrode) and an output electrode (source electrode) that is a main electrode 12b on the front surface. The semiconductor chip 12 includes an input electrode (drain electrode) that is a main electrode on the back surface. Such a semiconductor chip 12 may preferably be made of silicon carbide.

[0052] Lead frame 13a electrically connects main electrodes 12b of semiconductor chip 12 (on wiring board 11b2) to wiring board 11b3. Lead frame 13b electrically connects main electrodes 12b of semiconductor chip 12 (on wiring board 11b1) to wiring board 11b2. Semiconductor unit 10 may be a device that constitutes a one-phase inverter circuit.

[0053] The lead frames 13a and 13b integrally include main electrode joints 13a1 and 13b1, first vertical linkages 13a2 and 13b2, horizontal linkages 13a3 and 13b3, second vertical linkages 13a4 and 13b4, and wiring joints 13a5 and 13b5. The lead frames 13a and 13b have the same overall thickness and are flat. The lead frames 13a and 13b may be constructed by bending each of these parts. The lead frames 13a and 13b are made of a metal with excellent conductivity. Examples of such metals include copper, aluminum, or an alloy containing at least one of these as a main component. The thickness of the lead frames 13a and 13b is 0.1 mm or more and 2.0 mm or less. The surfaces of the lead frames 13a and 13b may be plated to improve corrosion resistance. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy.

[0054] The main electrode bonding portions 13a1 and 13b1 are flat and are bonded to the main electrode 12b of the semiconductor chip 12 (on the wiring boards 11b2 and 11b1) by bonding members 14a. The main electrode bonding portions 13a1 and 13b1 are rectangular in plan view, similar to the main electrode 12b. Bosses 13a6 and 13b6 are formed on the rear surfaces of the main electrode bonding portions 13a1 and 13b1, respectively (see FIGS. 5 to 8). The bosses 13a6 and 13b6 may be formed, for example, at the four corners of the rear surfaces of the rectangular main electrode bonding portions 13a1 and 13b1.

[0055] The first vertical linkages 13a2 and 13b2 have their lower ends integrally connected to the ends of the main electrode bonding portions 13a1 and 13b1, and their upper ends extending vertically upward (in the +Z direction) relative to the main electrode bonding portions 13a1 and 13b1. The first vertical linkage 13a2 is joined to the end of the main electrode bonding portion 13a1 on the wiring board 11b3 (-Y direction) side, which is bonded to the semiconductor chip 12 arranged on the wiring board 11b2. The first vertical linkage 13b2 is joined to the end of the main electrode bonding portion 13b1 on the wiring board 11b2 (-X direction) side, which is bonded to the semiconductor chip 12 arranged on the wiring board 11b1.

[0056] The horizontal linkages 13a3 and 13b3 are integrally connected to the upper ends of the first vertical linkages 13a2 and 13b2 and extend to the wiring boards 11b3 and 11b2, respectively. The horizontal linkages 13a3 and 13b3 are flat. The horizontal linkages 13a3 and 13b3 extend in the ±Y direction and the ±X direction, respectively. The horizontal linkages 13a3 and 13b3 may have one end misaligned with the other end. In this case, the horizontal linkages 13a3 and 13b3 span the gaps between the wiring boards 11b2 and 11b3 and the wiring boards 11b1 and 11b2. The horizontal linkages 13a3 and 13b3 are parallel to the insulating circuit board 11. The horizontal linkages 13a3 and 13b3 may be at the same height. In this way, the heights of the first vertical linkages 13a2, 13b2 and the second vertical linkages 13a4, 13b4 are appropriately selected so that the horizontal linkages 13a3, 13b3 are formed.

[0057] The second vertical linkages 13a4, 13b4 have their upper ends integrally connected to the ends of the horizontal linkages 13a3, 13b3, and their lower ends extend vertically downward (in the -Z direction) and are integrally connected to the wiring joints 13a5, 13b5.

[0058] The wiring joints 13a5 and 13b5 are joined to the wiring boards 11b3 and 11b2, respectively, and are integrally connected to the lower ends of the second vertical linking portions 13a4 and 13b4.

[0059] The first vertical linking portion 13a2, the horizontal linking portion 13a3 (excluding the bent portion), the second vertical linking portion 13a4, and the wiring joint portion 13a5 of the lead frame 13a have the same width. This width is the length in the direction (±X direction) perpendicular to the wiring direction (±Y direction) of the lead frame 13a.

[0060] The first vertical link 13b2, the horizontal link 13b3 (excluding the bent portion), and the second vertical link 13b4 of the lead frame 13b have the same width, which is the length in the direction (±Y direction) perpendicular to the wiring direction (±X direction) of the lead frame 13b.

[0061] Furthermore, the control electrodes 12a of the semiconductor chips 12 of the semiconductor units 10a, 10b, and 10c housed in the unit housings 21e, 21f, and 21g of the housing 20 are mechanically and electrically connected to the inner ends of the control terminals 25a, 25b, and 25c by wires 26 (see FIG. 1). The wires 26 are primarily made of a material with excellent conductivity. Such materials include, for example, gold, copper, aluminum, or an alloy containing at least one of these. Preferably, the wires 26 may be an aluminum alloy containing a trace amount of silicon. The diameter of the wires 26 is, for example, 100 μm or more and 400 μm or less.

[0062] The semiconductor unit 10 having such a configuration is not flat because heating during manufacturing, which will be described later, causes warping in the insulating circuit board 11. The warping depends, for example, on the volume and formation position of the wiring boards 11b1 to 11b3 and metal plate 11c of the insulating circuit board 11, the semiconductor chip 12, the lead frames 13a and 13b, and the heating temperature and time.

[0063] Here, an example of warpage occurring in insulating circuit board 11 will be described. In this example, warpage peaks 16a and 16c occur on side surfaces 11a1 and 11a3 of insulating circuit board 11. Furthermore, warpage peaks 16b and 16d occur on the side surfaces 11a2 and 11a4 of insulating circuit board 11, respectively, closer to side surface 11a3. These cases will be described with reference to FIGS. 5 to 8.

[0064] 5 to 8 are first to fourth side views of a semiconductor unit included in a semiconductor device according to an embodiment. Note that FIG. 5 is a side view of the semiconductor unit 10 of FIG. 3 as viewed in the −Y direction, and FIG. 6 is a side view of the semiconductor unit 10 of FIG. 3 as viewed in the −X direction. FIG. 7 is a side view of the semiconductor unit 10 of FIG. 3 as viewed in the +Y direction, and FIG. 8 is a side view of the semiconductor unit 10 of FIG. 3 as viewed in the +X direction. Note that the warpage in FIGS. 5 to 8 is shown only schematically. Although FIGS. 5 to 8 are side views, the support portion 15 and bosses 13a6 and 13b6 (these reference numerals may be omitted in some cases) are shown for ease of visual recognition. Some of the warpage in FIGS. 5 to 8 may appear larger than the actual warpage.

[0065] For example, in a side view of the semiconductor unit 10 looking in the -Y direction, as shown in Figure 5, the area where the wiring board 11b1 is formed is substantially flat. The area where the wiring board 11b2 is formed is more warped in the -Z direction than the area where the wiring board 11b1 is formed. Furthermore, at the vertex 16c near the center of the area where the wiring board 11b1 is formed, the insulating circuit board 11 is warped downward in a convex manner, with the bottom surface (-Z direction) of the insulating circuit board 11 facing downward. In this case, the semiconductor chip 12 is provided on the vertex 16c, and the semiconductor chip 12 is substantially parallel to the wiring board 11b2.

[0066] 6, in a side view of the semiconductor unit 10 looking in the −X direction, the semiconductor unit 10 is warped downwardly convexly from the vertex 16d of the region where the wiring board 11b1 is formed, as shown in Fig. 6. In this case, the back surface of the semiconductor chip 12 on the vertex 16d side is supported by the support portion 15, and the semiconductor chip 12 is approximately parallel to the wiring board 11b1.

[0067] 7, in a side view of the semiconductor unit 10 looking in the +Y direction, the region where the wiring board 11b1 is formed is substantially flat, while the region where the wiring board 11b3 is formed is warped downward at a vertex 16a that is slightly closer to the −X direction from the center of this region.

[0068] In a side view of the semiconductor unit 10 looking in the +X direction, as shown in Figure 8, the semiconductor unit 10 is warped downward and convexly from the vertex 16b of the region where the wiring board 11b2 is formed. In this case, the back surface of the semiconductor chip 12 on the vertex 16b side is supported by the support portion 15, and the semiconductor chip 12 is approximately parallel to the wiring board 11b2. Note that these warp vertices 16a, 16b, 16c, and 16d do not necessarily have to occur at the same time at these positions. At least one may occur.

[0069] Next, a case will be described in which the apex of the warp occurs at a position different from that shown in Fig. 4 on the side surfaces 11a2 and 11a4 of the insulating circuit board 11. Here, a case in which the apex of the warp 16b and 16d occurs at the center of the side surfaces 11a2 and 11a4 of the insulating circuit board 11 will be described with reference to Figs.

[0070] FIG. 9 is a plan view of an insulating circuit board showing another type of warpage included in a semiconductor device according to an embodiment. FIG. 10 is a second side view of a semiconductor unit having another type of warpage included in a semiconductor device according to an embodiment. FIG. 11 is a fourth side view of a semiconductor unit having another type of warpage included in a semiconductor device according to an embodiment. Note that FIG. 9 corresponds to FIG. 4 and illustrates a case in which the peak of the warpage occurs at a different position (the center of the side surfaces 11a2 and 11a4) relative to the side surfaces 11a2 and 11a4 of the insulating circuit board 11 shown in FIG. 4. FIG. 10 corresponds to FIG. 6 and illustrates a side view of the semiconductor unit 10 as viewed in the -X direction. FIG. 11 corresponds to FIG. 8 and illustrates a side view of the semiconductor unit 10 as viewed in the +X direction. Note that the warpage in FIGS. 10 and 11 is shown only schematically. Although FIGS. 10 and 11 are side views, the support portion 15 and bosses 13a6 and 13b6 (these reference numerals may be omitted in some cases) are illustrated for visual recognition. Some of the warpages in FIGS. 10 and 11 are shown to be larger than the actual warpage.

[0071] As shown in FIG. 9 , on the side surface 11a2 of the insulating circuit board 11 included in the semiconductor unit 10, a warpage peak 16b is generated in the center of the side surface 11a2 in the ±Y direction. On the side surface 11a4 of the insulating circuit board 11 included in the semiconductor unit 10, a warpage peak 16d is generated in the center of the side surface 11a4 in the ±Y direction. Note that the warpage peaks 16b and 16d do not necessarily have to occur at the same time at these positions. At least one may occur. Furthermore, in this example, the support portion 15 does not have to be formed in the bonding region 11d of the wiring board 11b2 of the insulating circuit board 11.

[0072] In a side view of the semiconductor unit 10 in the -X direction, the region where the wiring board 11b1 is formed is warped downward at the vertex 16d near the center of the region, as shown in Figure 10. In this case, the approximate center of the semiconductor chip 12 is located directly above the vertex 16d, and the semiconductor chip 12 is approximately parallel to the wiring board 11b1.

[0073] In a side view of the semiconductor unit 10 looking in the +X direction, the region where the wiring board 11b2 is formed is warped downward at the vertex 16b near the center of the region, as shown in Fig. 11. In this case, the approximate center of the semiconductor chip 12 is located directly above the vertex 16b, and the semiconductor chip 12 is approximately parallel to the wiring board 11b2.

[0074] 4 and 9 on the side surfaces 11a2 and 11a4 of the insulating circuit board 11. Here, a case where the warpage peaks 16b and 16d occur on the side surface 11a1 of the side surfaces 11a2 and 11a4 of the insulating circuit board 11 will be described with reference to FIGS.

[0075] FIG. 12 is a plan view of an insulating circuit board showing another type of warpage included in a semiconductor device according to an embodiment. FIG. 13 is a second side view of a semiconductor unit having another type of warpage included in a semiconductor device according to an embodiment. FIG. 14 is a fourth side view of a semiconductor unit having another type of warpage included in a semiconductor device according to an embodiment. Note that FIG. 12 corresponds to FIGS. 4 and 9 and illustrates a case in which the peak of the warpage occurs at a different position (the side 11a1 side of the side 11a2 and 11a4) from the side 11a2 and 11a4 sides of the insulating circuit board 11 shown in FIGS. 4 and 9. FIG. 13 corresponds to FIGS. 6 and 10 and illustrates a side view of the semiconductor unit 10 as viewed in the -X direction. FIG. 14 corresponds to FIGS. 8 and 11 and illustrates a side view of the semiconductor unit 10 as viewed in the +X direction. Note that the warpage in FIGS. 13 and 14 is shown only schematically. Although FIGS. 13 and 14 are side views, the support portion 15 and bosses 13a6 and 13b6 (these reference numerals may be omitted in some cases) are illustrated for visual recognition. Some of the warpages in FIGS. 13 and 14 are shown to be larger than the actual warpage.

[0076] 12, a warpage peak 16b is generated on the side surface 11a2 of the insulating circuit board 11 included in the semiconductor unit 10 between the wiring boards 11b2 and 11b3 on the side surface 11a2. Furthermore, a warpage peak 16d is generated on the side surface 11a4 of the insulating circuit board 11 included in the semiconductor unit 10 at a location on the side surface 11a4 opposite the peak 16b. Note that the warpage peaks 16b and 16d do not necessarily have to occur at the same time at these positions. At least one may occur.

[0077] A plurality of support portions 15 may be formed on the vertex 16b side of the bonding region 11d of the wiring board 11b2 of the insulating circuit board 11. In this case, the plurality of support portions 15 may be formed parallel to the side surface 11a1.

[0078] Furthermore, a plurality of support portions 15 may be formed on the vertex 16d side of the bonding region 11d of the wiring board 11b1 of the insulating circuit board 11. In this case, the plurality of support portions 15 may be formed parallel to the side surface 11a1.

[0079] In a side view of the semiconductor unit 10 looking in the −X direction, the semiconductor unit 10 is warped downwardly as a whole, with the vertex 16d of the region where the wiring board 11b1 is formed as the vertex, as shown in Fig. 13. In this case, the back surface of the semiconductor chip 12 on the vertex 16d side is supported by the support portion 15, and the semiconductor chip 12 is approximately parallel to the wiring board 11b1.

[0080] In a side view of semiconductor unit 10 looking in the +X direction, as shown in Fig. 14, semiconductor unit 10 is warped downwardly convexly from vertex 16b in the region between wiring boards 11b2 and 11b3 as an vertex. In this case, the back surface of semiconductor chip 12 on the vertex 16b side is supported by support portion 15, and semiconductor chip 12 is approximately parallel to wiring board 11b2.

[0081] Note that the warpage vertices 16b and 16d do not necessarily have to occur simultaneously at the positions of the side surfaces 11a2 and 11a4 of the insulating circuit board 11 shown in FIGS. 4, 9, and 12, but may occur separately. Furthermore, the support portions 15 can be arbitrarily combined depending on the warpage vertices 16b and 16d. For example, when only the vertex 16b occurs or when only the vertex 16d occurs, the support portions 15 are disposed on either the wiring boards 11b1 or 11b2 according to the positions of the vertices 16b and 16d. For example, when the vertices 16b and 16d occur simultaneously in a diagonal direction (the vertex 16c in FIG. 4 and the vertex 16d in FIG. 12, or the vertex 16b in FIG. 12 and the vertex 16d in FIG. 4), the support portions 15 in the bonding region 11d of the wiring boards 11b2 and 11b2 are disposed diagonally.

[0082] Next, the cooling device will be described with reference to FIGS. 15 and 16. FIG. 15 is a cross-sectional view of the semiconductor device of the embodiment. FIG. 16 is a rear view of the cooling device included in the semiconductor device of the embodiment. FIG. 15 is a cross-sectional view taken along the dashed dotted line X-X in FIG. 1. FIG. 16 is a rear view of the semiconductor device 1 of FIG. 1 rotated about a center line passing through the centers of the outer walls 21a and 21c.

[0083] The cooling device 3 includes an inlet 33a through which the refrigerant flows into the interior and an outlet 33b through which the refrigerant that has circulated inside flows out to the outside. The cooling device 3 cools the semiconductor unit 10 by discharging heat from the semiconductor unit 10 through the refrigerant. Examples of the refrigerant used here include water, antifreeze (ethylene glycol aqueous solution), and long-life coolant. The cooling device 3 may also include a pump and a heat dissipation device (radiator). The pump introduces the refrigerant into the inlet 33a of the cooling device 3 and circulates the refrigerant by allowing the refrigerant that flows out from the outlet 33b back into the inlet 33a. The heat dissipation device receives the refrigerant that flows out of the cooling device 3 and dissipates the heat of the refrigerant, which has conducted heat from the semiconductor unit 10, to the outside.

[0084] The cooling device 3 includes a top plate 31, a side wall 32 connected in a ring shape to the back surface of the top plate 31, and a cooling bottom plate 33 facing the top plate 31 and connected to the back surface of the side wall 32. The top plate 31 has a rectangular shape in plan view, surrounded by long and short sides, and fastening holes are formed at each of the four corners. The corners of the top plate 31 may be rounded in plan view. The semiconductor units 10a, 10b, and 10c are joined to the front surface of the top plate 31 along the ±X directions. The side wall 32 is formed in a ring shape and continuously on the back surface of the top plate 31. A plurality of heat dissipation fins 34 are formed in an area on the back surface of the top plate 31 corresponding to the area where the semiconductor units 10a, 10b, and 10c are arranged.

[0085] The cooling bottom plate 33 is flat and has the same shape as the top plate 31 in a plan view. The cooling bottom plate 33 has a rectangular shape surrounded by long sides 30a, 30c and short sides 30b, 30d in a plan view. Fastening holes 30e corresponding to the top plate 31 are formed at the four corners. The corners of the cooling bottom plate 33 may also be rounded. The front and bottom surfaces 33d of the cooling bottom plate 33 are parallel to each other. The bottom surface 33d of the cooling bottom plate 33 is flat and has no steps, forming the same plane. The bottom surface 33d of the cooling bottom plate 33 and the front surface of the top plate 31 may also be parallel to each other. The bottom surface 33d of the cooling bottom plate 33 has an inlet 33a and an outlet 33b through which the refrigerant flows in and out. Seal areas 33a1 and 33b1 are provided around the inlet 33a and outlet 33b on the bottom surface 33d of the cooling base plate 33. Water distribution heads are attached to the inlet 33a and outlet 33b via annular rubber packings in the seal areas 33a1 and 33b1 surrounding the periphery of the inlet 33a and outlet 33b. A water distribution pipe connected to a pump is attached to the water distribution heads.

[0086] Next, a method for manufacturing such a semiconductor device 1 will be described with reference to FIG. 17. FIG. 17 is a flowchart showing the method for manufacturing a semiconductor device according to the embodiment. First, a preparation step is performed to prepare the components of the semiconductor device 1 (step S1). The components include, for example, the semiconductor chip 12, the insulating circuit board 11, the lead frames 13a and 13b, the housing 20, the cooling device 3, and the sealing material of the sealing member 27. Other components necessary for manufacturing the semiconductor device 1 are also prepared. Furthermore, manufacturing equipment and manufacturing jigs necessary for manufacturing the semiconductor device 1 may be prepared.

[0087] Next, a setting step is performed in which semiconductor chip 12 is set on insulating circuit board 11, and lead frames 13a and 13b are set in that order (step S2). The state after this setting step will be described with reference to FIG. 18. FIG. 18 is a diagram illustrating the state after the setting step included in the semiconductor device manufacturing method of the embodiment. FIG. 18 shows a cross-sectional view of the set structure in which insulating circuit board 11, semiconductor chip 12, and lead frames 13a and 13b are set in that order. The cross-sectional location corresponds to the dashed-dotted line X-X in FIG. 3.

[0088] 18, the semiconductor chip 12 is placed on the wiring board 11b2 of the insulating circuit board 11 via the bonding material 14a. The bonding material 14a used here before hardening is, for example, solder paste or plate solder. At this time, a support portion 15 is placed between the rear surface of the semiconductor chip 12 on the +Y direction side and the wiring board 11b2. In other words, the rear surface of the semiconductor chip 12 is supported by the support portion 15.

[0089] Furthermore, main electrode bonding portions 13a1 of lead frame 13a are disposed on main electrodes 12b of semiconductor chip 12 via bonding material 14b. The bonding material 14b used here before hardening is, for example, solder paste or plate solder. In this case, main electrode bonding portions 13a1 are disposed on main electrodes 12b of semiconductor chip 12 via bosses 13a6 formed on the back surface thereof. Wiring bonding portions 13a5 of lead frame 13a are disposed on wiring board 11b3.

[0090] Next, the components set in step S2 are heated to bond the components together to form the semiconductor unit 10 in a first bonding step (step S3). Heating is performed in the state shown in FIG. 18 to melt and harden the bonding members 14a and 14b. This bonds the semiconductor chip 12 to the wiring board 11b2 of the insulating circuit board 11 via the bonding member 14a. Furthermore, the main electrode bonding portions 13a1 and 13b1 of the lead frames 13a and 13b are bonded to the main electrodes 12b of the semiconductor chip 12 via the bonding member 14b. The wiring bonding portions 13a5 and 13b5 of the lead frames 13a and 13b are bonded to the wiring boards 11b3 and 11b2, for example, by ultrasonic bonding. The heating in the first bonding step also causes warping of the insulating circuit board 11, as shown in FIGS. 5 to 8. The warping of the insulating circuit board 11 will be described later.

[0091] Next, a second bonding process is performed to bond the semiconductor unit 10 to the top plate 31 of the cooling device 3 (step S4). The semiconductor unit 10 is bonded to the top plate 31 of the cooling device 3 via a bonding material such as the brazing material or thermal interface material described above. Next, a housing attachment process is performed to attach the housing 20 to the cooling device 3 (step S5). The housing 20 is attached with an adhesive to the top plate 31 of the cooling device 3 to which the semiconductor unit 10 has been bonded, and the semiconductor units 10 are housed in the unit housing portions 21e, 21f, and 21g of the housing 20, respectively. Note that, for example, the first bonding process and the second bonding process may be performed simultaneously.

[0092] Next, a wiring and sealing process is performed in which wiring is performed on the semiconductor unit 10 and the unit housing portions 21e, 21f, and 21g are sealed with sealing material 27 (step S6). The inner ends of first connection terminals 22a, 22b, and 22c exposed from the housing 20 to the unit housing portions 21e, 21f, and 21g are joined to the wiring board 11b1 of the insulating circuit board 11 of the semiconductor unit 10, for example, by ultrasonic bonding. Similarly, the inner ends of second connection terminals 23a, 23b, and 23c are joined to the wiring board 11b3 of the insulating circuit board 11 of the semiconductor unit 10. Similarly, the inner ends of U-phase output terminal 24a, V-phase output terminal 24b, and W-phase output terminal 24c are joined to the wiring board 11b2 of the insulating circuit board 11 of the semiconductor unit 10. Furthermore, the inner ends of control terminals 25a, 25b, and 25c of the housing 20 are connected to the control electrode 12a of the semiconductor chip 12 by wires 26. The unit housing portions 21e, 21f, and 21g are filled with a sealing member 27 to seal the semiconductor unit 10. In this manner, the semiconductor device 1 shown in FIGS.

[0093] Here, a semiconductor device of a reference example will be described. The semiconductor device of the reference example is semiconductor device 1 minus support portion 15, and is otherwise configured with the same components as semiconductor device 1, and is manufactured by the same manufacturing method as semiconductor device 1, as in FIG. 17 . Here, the setting step (step S2) and first bonding step (step S3) of the manufacturing method for the reference example will be described with reference to FIGS. 19 and 20 . FIG. 19 is a diagram illustrating the state after the setting step included in the manufacturing method for a semiconductor device of the reference example. FIG. 20 is a diagram illustrating the first bonding step included in the manufacturing method for a semiconductor device of the reference example.

[0094] A setting step is performed (step S2) in which semiconductor chip 12 is set on insulating circuit board 11, and then lead frames 13a and 13b are set in that order. As a result, as shown in Fig. 18, semiconductor chip 12 is placed on wiring board 11b2 of insulating circuit board 11 via only bonding member 14a. Furthermore, main electrode bonding portion 13a1 of lead frame 13a is placed on main electrode 12b of semiconductor chip 12 via bonding member 14b.

[0095] After this, a first bonding step is performed in which these components are heated and bonded to form the semiconductor unit 10 (step S3). As previously described, the insulating circuit board 11 warps when heated. For example, the wiring boards 11b1-11b3 and the metal plate 11c have different linear expansion coefficients from the insulating plate 11a. Furthermore, the volumes of the wiring boards 11b1-11b3 and the metal plate 11c formed on the front and back surfaces of the insulating plate 11a are different. For this reason, in the reference example, as an example of warping, a case in which warping occurs around the vertices 16a-16d of the side surfaces 11a1-11a4 of the insulating circuit board 11 in FIG. 4, as shown in FIGS. 5-8, will be described.

[0096] For example, the semiconductor unit 10 along dashed line X-X in Figure 3 (corresponding to a side view viewed in the +X direction) warps as shown in Figure 20. That is, a downward convex warp occurs with the vertex 16b of the insulating circuit board 11 as the vertex. Furthermore, the bonding members 14a, 14b melt due to heating. At this time, the semiconductor chip 12, which is disposed in the bonding region 11d of the wiring board 11b2 that has tilted due to the warp, also tilts because the bonding member 14a has melted. Note that the main electrode bonding portion 13a1 of the lead frame 13a maintains a substantially parallel position to the semiconductor chip 12 because a boss 13a6 is formed on the back surface.

[0097] When the bonding material 14a is cured in this tilted state and the semiconductor chip 12 is bonded to the wiring board 11b2, the thickness of the bonding material 14a is not uniform, resulting in thin and thick areas. That is, the bonding material 14a is thinner on the side of the vertex 16b and thicker on the side away from the vertex 16b.

[0098] In the thin portions of the bonding member 14a, cracks are more likely to occur due to external stress. In addition, the thick portions of the bonding member 14a have poorer heat dissipation properties than the thinner portions. The inclusion of such bonding members 14a with uneven thickness leads to a decrease in the reliability of the semiconductor device.

[0099] 10, when the semiconductor unit 10 is viewed from the side in the −X direction, a vertex 16d is formed directly below the central region of the semiconductor chip 12. In this case, the semiconductor chip 12 is substantially parallel to the wiring board 11b1, and the thickness of the bonding member 14a is substantially uniform, making it difficult for cracks to occur.

[0100] Therefore, the semiconductor device 1 described above includes an insulating circuit substrate 11 having a semiconductor chip 12 and a wiring board 11b2 on its front surface, warping downward convexly with its back surface facing downward, and having the semiconductor chip 12 bonded to a bonding area 11d on the upper surface of the wiring board 11b2, which is tilted on the front surface due to the warping, via a bonding member 14a. In this case, the semiconductor chip 12 is bonded to the bonding area 11d by a support 15 provided in the bonding area 11d, with the end of the back surface of the semiconductor chip 12 on the side of the apex 16b of the warp of the insulating circuit substrate 11 being supported by the support 15. The semiconductor chip 12 is then aligned substantially parallel to the bonding area 11d of the wiring board 11b2 by the support 15, and the thickness of the bonding member 14a is substantially uniform. This reduces the occurrence of cracks in the bonding member 14a. Furthermore, the positional variation in the thermal conductivity of the bonding member 14a is also reduced. This prevents a decrease in the reliability of the semiconductor device 1. Furthermore, it is preferable that support portions 15 are formed in correspondence with two corners on the vertex 16b side of semiconductor chip 12 relative to bonding region 11d on the upper surface of wiring board 11b2. With this structure, support portions 15 allow semiconductor chip 12 to be approximately parallel to bonding region 11d of wiring board 11b2, and the posture approximately parallel to bonding region 11d can be more stabilized.

[0101] As shown in Fig. 4, warpage of the insulating circuit board 11 occurs not only at the vertex 16b but also at the vertices 16a, 16c, and 16d. Furthermore, warpage also occurs at the vertices 16b and 16d as shown in Fig. 12. As mentioned above, the vertices 16b and 16d in Fig. 9 occur directly below the center of the semiconductor chip 12 arranged on the bonding region 11d in side view, and therefore do not have much effect on the inclination of the semiconductor chip 12.

[0102] In Figure 4 of this embodiment, a support portion 15 is arranged to make the semiconductor chip 12, which is placed in the bonding area 11d on the upper surface of the wiring board 11b2, which is inclined due to a downward convex warp with vertex 16b as the vertex in a side view, approximately parallel to the wiring board 11b2.

[0103] 4, for wiring board 11b2 that is tilted due to downward convex warping with vertices 16a and 16c as vertices in side view, support portion 15 may be disposed on side surface 11a4 (vertices 16a and 16c) of bonding region 11d of wiring board 11b2. Support portion 15 may be appropriately disposed in bonding region 11d depending on the direction of warping of wiring board 11b2 so that semiconductor chip 12 is approximately parallel to wiring board 11b2.

[0104] In addition, in Figure 4 of this embodiment, a support portion 15 is arranged to make the semiconductor chip 12, which is placed in the bonding area 11d on the upper surface of the wiring board 11b1, which is inclined due to a downward convex warp with vertex 16d as the vertex in a side view, approximately parallel to the wiring board 11b1.

[0105] In addition, in Figure 12 of this embodiment, support portions 15 are arranged to make the semiconductor chip 12, which is placed in the bonding area 11d on the upper surface of the wiring boards 11b1 and 11b2, which are inclined due to downward convex warping with vertices 16b and 16d as vertices when viewed from the side, approximately parallel to the wiring boards 11b1 and 11b2.

[0106] Various modifications of the support portion 15 will be described below. Note that the following description will be given taking as an example a case where warpage occurs with the vertex 16b in Fig. 4 as its vertex. The following modifications of the support portion 15 can also be applied to a case where warpage occurs with the vertex 16b in Fig. 9 as its vertex, or a case where warpage occurs with the vertices 16b and 16d in Fig. 12 as its vertex.

[0107] (Variation 1) The support portion 15 of Variation 1 will be described with reference to FIG. 21 . FIG. 21 is a diagram showing an insulating circuit board included in a semiconductor device according to an embodiment (Variation 1). Note that FIG. 21A shows a plan view of the insulating circuit board 11 including the support portion 15, and FIG. 21B shows a cross-sectional view taken along the dashed-dotted line X-X in FIG. 21A. The insulating circuit board 11 in FIG. 21 shows a state before warpage occurs, and the location where the vertex 16b is expected to occur is indicated by a dashed circle in FIG. 21. Only the vertex 16b is shown here. Also, in FIG. 21B, the semiconductor chip 12, which is to be placed relative to the bonding region 11d where the support portion 15 is provided, is indicated by a dashed line.

[0108] In Modification 1, support portion 15 is provided on the side where vertex 16b occurs in a side view of bonding region 11d of wiring board 11b2 in the +X direction. Support portion 15 in Modification 1 is rod-shaped in a plan view. Such support portion 15 is disposed on the side surface 11a3 of bonding region 11d of wiring board 11b2, along side surface 11a3. The cross section of this support portion 15 in the Y-Z plane may be rectangular, triangular, or semicircular. Here, a rectangular shape is shown. The height of support portion 15 in the ±Z directions is set in advance depending on the warpage that occurs.

[0109] Even with this wiring board 11b2, when a downward convex warp occurs in the insulating circuit board 11 with vertex 16b as the vertex, the semiconductor chip 12 is approximately parallel to the wiring board 11b2. Note that here, a case where there is one support portion 15 is illustrated. The number of support portions 15 is not limited to one, but may be arranged in multiple rows parallel to the side surfaces 11a1 and 11a3. The support portions 15 are not limited to being continuous rod-shaped as shown in FIG. 21 . The support portions 15 may be arranged in one row or multiple rows in the form of a dashed line parallel to the side surfaces 11a1 and 11a3. Furthermore, depending on the warp occurrence situation, for example, in the case of a downward convex warp with vertex 16a or 16c as the vertex, the support portions 15 may be arranged along the side surface 11a4 of the bonding region 11d of the wiring board 11b2.

[0110] (Variation 2) Supporting portion 15 of Variation 2 will be described with reference to FIG. 22. FIG. 22 is a diagram showing an insulating circuit board included in a semiconductor device according to an embodiment (variation 2). Note that FIG. 22(A) shows a plan view of insulating circuit board 11 including supporting portion 15, and FIG. 22(B) shows a cross-sectional view taken along dashed line Y-Y in FIG. 22(A). In addition, insulating circuit board 11 in FIG. 22 is also before warpage occurs, and in FIG. 22, the location where vertex 16b is expected to occur is indicated by a dashed circle.

[0111] In Modification 2, support portion 15 is provided on the side where vertex 16b occurs in a side view of bonding region 11d of wiring board 11b2 in the +X direction. Support portion 15 in Modification 2 is configured with wire. Here, the wires are formed near the corners on the vertex 16b side of bonding region 11d of wiring board 11b2 in a side view. The example shows a case where the wires are arranged parallel to side surfaces 11a1 and 11a3. The height of support portion 15 in the ±Z directions is set in advance depending on the warpage that occurs.

[0112] Even with this wiring board 11b2, when the insulating circuit board 11 warps downward with the vertex 16b as the vertex, the semiconductor chip 12 remains substantially parallel to the wiring board 11b2. The support portions 15 are preferably formed along the edge of the semiconductor chip 12 on the vertex 16b side relative to the bonding region 11d of the wiring board 11b2. Furthermore, the support portions 15 are preferably formed corresponding to two corners of the semiconductor chip 12 on the vertex 16b side relative to the bonding region 11d on the upper surface of the wiring board 11b2. The support portions 15 allow the semiconductor chip 12 to remain substantially parallel to the bonding region 11d of the wiring board 11b2, further stabilizing its substantially parallel orientation with the bonding region 11d. Note that the example shown here illustrates a case where two support portions 15 are arranged in a row. The number of support portions 15 is not limited to two, and one, or three or more support portions 15 may connect the end of the bonding region 11d on the side surface 11a2 side to the end on the side surface 11a4 side. Furthermore, such support portions 15 may be formed in multiple rows closer to the side surface 11a3. In this case, the multiple rows of support portions 15 may be formed so that the height increases as they approach the side surface 11a3. Depending on the state of warping, the support portions 15 may be formed, for example, along the side surfaces 11a2 and 11a4, or on the diagonal of the bonding region 11d. Because they are wires, there is a high degree of freedom in their formation, and they can be formed wherever necessary.

[0113] (Variation 3) Supporting portion 15 of Variation 3 will be described with reference to FIG. 23. FIG. 23 is a diagram showing an insulating circuit board included in a semiconductor device according to an embodiment (variation 3). Note that FIG. 23(A) is a plan view of insulating circuit board 11 including supporting portion 15, and FIG. 23(B) is a cross-sectional view taken along dashed line Y-Y in FIG. 23(A). In addition, insulating circuit board 11 in FIG. 23 is also before warpage occurs, and the location where vertex 16b is expected to occur is indicated by a dashed circle in FIG.

[0114] In Modification 3, support portion 15 is provided on the side of bonding region 11d of wiring board 11b2 where vertex 16b occurs in a side view looking in the +X direction. Support portion 15 in Modification 3 is a region where the front surface of wiring board 11b2 is roughened. The roughening process may be performed by laser, blasting, or roughening plating, for example. The roughened support portion 15 is shown as being parallel to side surfaces 11a1 and 11a3 and located near the corners of bonding region 11d. The height of support portion 15 in the ±Z directions is preset depending on the warpage to be generated.

[0115] Even with this wiring board 11b2, when the insulating circuit board 11 warps downward with the vertex 16b as the vertex, the semiconductor chip 12 remains substantially parallel to the wiring board 11b2. Furthermore, the support portions 15 are preferably formed in correspondence with the two corners of the semiconductor chip 12 on the vertex 16b side of the bonding region 11d on the upper surface of the wiring board 11b2. With this structure, the support portions 15 allow the semiconductor chip 12 to remain substantially parallel to the bonding region 11d of the wiring board 11b2, thereby more stabilizing its substantially parallel orientation with the bonding region 11d. Note that the example shown here illustrates a case where the support portions 15 are arranged in two locations in a row. The number of such support portions 15 is not limited to two, but may be one or three or more, forming a linear shape from the end of the bonding region 11d on the side surface 11a2 side to the end on the side surface 11a4 side. Furthermore, such support portions 15 may be formed in multiple rows near the side surface 11a3 side of the bonding region 11d included in the wiring board 11b2. Depending on the occurrence of warping, the support portion 15 may be formed, for example, along the side surfaces 11a2 and 11a4 or on the diagonal of the bonding region 11d. Since the support portion 15 is formed by roughening the surface, there is a high degree of freedom in its formation, and it can be formed in any desired location.

[0116] (Variation 4) The support portion 15 of Variation 4 will be described with reference to FIG. 24. FIG. 24 is a diagram showing an insulating circuit board included in a semiconductor device according to an embodiment (Variation 4). Note that FIG. 24(A) is a plan view of the insulating circuit board 11 including the support portion 15, and FIG. 24(B) is a cross-sectional view taken along the dashed line X-X in FIG. 24(A). The insulating circuit board 11 in FIG. 24 is also before warpage occurs, and the location where the vertex 16b is expected to occur is indicated by a dashed circle in FIG. 24. Furthermore, FIG. 24(B) shows the semiconductor chip 12, which will be placed relative to the bonding region 11d where the support portion 15 is provided, indicated by a dashed line.

[0117] In Variation 4, support portion 15 is rectangular in plan view and is located halfway in the +Y direction of bonding region 11d of wiring board 11b2. The front surface of support portion 15 is inclined so that the height of the side where vertex 16b occurs is higher when viewed from the side of bonding region 11d of wiring board 11b2 in the +X direction. In other words, the front surface of support portion 15 is inclined so that the side closer to vertex 16b is higher than the side farther from vertex 16b when viewed from the side of bonding region 11d of wiring board 11b2 in the +X direction. Again, the inclination angle of support portion 15 is preset based on the warpage to be generated. The lengths of support portion 15 in the ±Y and ±X directions are also preset based on the warpage to be generated.

[0118] Even with this type of wiring board 11b2, when a downward convex warp occurs in the insulating circuit board 11 with vertex 16b as the vertex, the backside of the semiconductor chip 12 is supported by the support portion 15 and remains substantially parallel to the wiring board 11b2. Such support portion 15 stably supports the backside of the tilted semiconductor chip 12. Furthermore, it is preferable that the support portion 15 is formed along the edge of the semiconductor chip 12 on the vertex 16b side relative to the bonding region 11d of the wiring board 11b2. With this structure, the support portion 15 allows the semiconductor chip 12 to remain substantially parallel to the bonding region 11d of the wiring board 11b2, and the posture substantially parallel to the bonding region 11d can be more stabilized.

[0119] Here, the example shows a case where there is one support portion 15 along the side surfaces 11a1 and 11a3. The number of support portions 15 including an incline is not limited to one, and multiple support portions 15 may be arranged in a row along the side surfaces 11a1 and 11a3. When there are multiple support portions 15, the bonding member 14a penetrates between the support portions 15, increasing the contact area between the support portions 15 and the bonding member 14a, thereby enabling the bonding region 11d and the semiconductor chip 12 to be bonded more reliably.

[0120] The foregoing merely illustrates the principles of the present invention. Further, since numerous modifications and changes will be apparent to those skilled in the art, the present invention is not limited to the exact construction and application shown and described above, and all corresponding modifications and equivalents are deemed to be within the scope of the present invention as defined by the appended claims and their equivalents.

[0121] REFERENCE SIGNS LIST 1 semiconductor device 2 semiconductor module 3 cooling device 10, 10a, 10b, 10c semiconductor unit 11 insulated circuit board 11a insulating plate 11a1, 11a2, 11a3, 11a4 side surface 11a5, 11a6, 11a7, 11a8 corner portion 11b1, 11b2, 11b3 wiring board 11c metal plate 11d bonding area 12 semiconductor chip 12a control electrode 12b main electrode 13a, 13b lead frame 13a1, 13b1 main electrode bonding portion 13a2, 13b2 first vertical linking portion 13a3, 13b3 horizontal linking portion 13a4, 13b4 second vertical linking portion 13a5, 13b5 wiring bonding portion 13a6, 13b6 boss 14a, 14b Joining member 15 Support portion 16a, 16b, 16c, 16d Vertex 20 Housing 21 Frame portion 21a, 21b, 21c, 21d Outer wall 21e, 21f, 21g Unit storage portion 21i Fixing hole 22a, 22b, 22c First connection terminal 23a, 23b, 23c Second connection terminal 24a U-phase output terminal 24b V-phase output terminal 24c W-phase output terminal 25a, 25b, 25c Control terminal 26 Wire 27 Sealing member 30a, 30c Long side 30b, 30d Short side 30e Fastening hole 31 Top plate 32 Side wall 33 Cooling bottom plate 33a Inlet 33a1, 33b1 Sealing area 33b Outlet 33d Bottom surface 34 Heat dissipation fin

Claims

1. A semiconductor chip; a substrate including a wiring board on a front surface thereof, warping downwardly convexly with the back surface facing downward, and the semiconductor chip being bonded via a first bonding member to a bonding region on an upper surface of the wiring board that is inclined on the front surface due to the warping; Including, the semiconductor chip is supported at an end portion of the back surface of the semiconductor chip on the apex side of the warp of the substrate by a support portion provided in the bonding region; Semiconductor device.

2. The semiconductor chip is generally parallel to the bonding area of ​​the wiring board. The semiconductor device according to claim 1 .

3. The support portion is formed on the apex side of the bonding region of the wiring board and has a protruding shape. The semiconductor device according to claim 1 .

4. The support portion is formed in plurality. The semiconductor device according to claim 3 .

5. The semiconductor chip has a rectangular shape in a plan view, the support portions are formed in the bonding region of the wiring board in correspondence with two corner portions of the semiconductor chip on the apex side, The semiconductor device according to claim 4.

6. The support portion includes an inclined surface that is inclined higher on a side closer to the apex than on a side farther from the apex in a side view. The semiconductor device according to claim 1 .

7. The semiconductor chip has a rectangular shape in a plan view, the support portion is formed along a side of the semiconductor chip on the apex side with respect to the bonding region of the wiring board. The semiconductor device according to claim 6.

8. The support portion is a roughened region in which the apex side of the bonding region of the wiring board is roughened. The semiconductor device according to claim 1 .

9. The support portion includes a plurality of the roughened regions. The semiconductor device according to claim 8.

10. The semiconductor chip has a rectangular shape in a plan view, the support portions are formed in the bonding region of the wiring board in correspondence with two corner portions of the semiconductor chip on the apex side, The semiconductor device according to claim 9.

11. The support portion is a wire formed on the apex side of the bonding region of the wiring board. The semiconductor device according to claim 1 .

12. The semiconductor chip has a rectangular shape in a plan view, the support portion is formed along a side of the semiconductor chip on the apex side with respect to the bonding region of the wiring board. The semiconductor device according to claim 11.

13. the support portions are formed in the bonding region of the wiring board in correspondence with two corner portions of the semiconductor chip on the apex side, The semiconductor device according to claim 12.

14. The semiconductor chip further includes a wiring member having a flat joint portion that is joined to a main electrode on the front surface of the semiconductor chip via a second joint member. The semiconductor device according to claim 1 .

15. the joint portion of the wiring member is substantially parallel to the front surface of the semiconductor chip; The semiconductor device according to claim 14.

16. a protrusion is formed on a bonding surface of the bonding portion that is bonded to the main electrode of the semiconductor chip; The semiconductor device according to claim 14.

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