High frequency package and production method for high frequency package

Abstract

A high frequency package (1) comprises: a first wiring substrate (2); a semiconductor chip (3) that is disposed on the first wiring substrate (2) with first solder bumps (6) therebetween and that is electrically connected to the first wiring substrate (2); a second wiring substrate (4) that is disposed on the first wiring substrate (2) with second solder bumps (7) therebetween and that is electrically connected to the first wiring substrate (2), said second solder bumps (7) being disposed around the semiconductor chip (3) on the first wiring substrate (2); and a reinforcing material (5) that is filled between the first solder bumps (6) and the second solder bumps (7) and that is filled from above the first wiring substrate (2) to the second wiring substrate (4) and the semiconductor chip (3). Formed in the second wiring substrate (4) is a through hole (4c) that passes through the second wiring substrate (4) in a plate thickness direction. In a view along the plate thickness direction, at least part of the semiconductor chip (3) and at least part of the reinforcing material (5) are at a position overlapping with the through hole (4c).

Description

High frequency package and method of manufacturing the same

[0001] The present disclosure relates to a high frequency package including a semiconductor chip and a method for manufacturing the high frequency package.

[0002] Conventionally, high-frequency packages have been known that include a first wiring substrate, a semiconductor chip, and a second wiring substrate. In such high-frequency packages, the semiconductor chip is mounted to the first wiring substrate via solder bumps, and the first wiring substrate is mounted to the second wiring substrate via solder bumps arranged around the semiconductor chip. Hereinafter, when distinguishing between solder bumps connecting the first wiring substrate and the semiconductor chip and solder bumps connecting the first wiring substrate and the second wiring substrate, the former will be referred to as "first solder bumps" and the latter will be referred to as "second solder bumps."

[0003] In a high-frequency package, since the semiconductor chip is disposed between the second wiring substrate and the first solder bumps, it is necessary to avoid interference between the semiconductor chip and the second wiring substrate. Therefore, in a high-frequency package, as disclosed in Patent Document 1, a counterbore recessed in a direction away from the semiconductor chip is provided on the surface of the second wiring substrate facing the semiconductor chip.

[0004] International Publication No. 2012 / 140934

[0005] In the high-frequency package disclosed in Patent Document 1, the temperature of the high-frequency package rises and falls due to heat generation from electronic components such as semiconductor chips and changes in the ambient temperature. When the temperature of the high-frequency package changes, strain occurs in the first solder bumps arranged on the periphery of the semiconductor chip and the second solder bumps arranged around the recesses due to the difference in the linear expansion coefficients between the first wiring board and the semiconductor chip, the difference in the linear expansion coefficients between the first wiring board and the second wiring board, and the recesses in the second wiring board. When this strain occurs repeatedly, there is a problem that the first solder bumps and the second solder bumps may break.

[0006] In particular, when a waveguide plate is attached to the surface of the second wiring board facing away from the semiconductor chip and the first wiring board, the difference in the linear expansion coefficient between the second wiring board and the waveguide plate is also added, increasing the amount of strain in the first solder bumps and the amount of strain in the second solder bumps, which creates the problem of making the breakage of the first solder bumps and the second solder bumps more likely to progress.

[0007] A common approach to reducing distortion of the first solder bumps is to infiltrate an insulating underfill material into the gap between the first wiring substrate and the semiconductor chip, or to apply an insulating sidefill material between the first wiring substrate and the outer periphery of the semiconductor chip.

[0008] However, when the underfill material is allowed to penetrate, it comes into contact with all of the first solder bumps, which can degrade the electrical characteristics of the high-frequency package. On the other hand, when the side fill material is applied after mounting the semiconductor chip on the first wiring substrate via the first solder bumps, the area to which the side fill material is applied is small, so the side fill material may come into contact with both the first and second solder bumps. If the side fill material adheres to the first or second solder bumps, the first or second solder bumps may fly off during the secondary reflow process in which the first wiring substrate is mounted on the second wiring substrate, causing problems with the connection between the semiconductor chip and the first wiring substrate and the connection between the first wiring substrate and the second wiring substrate.

[0009] The present disclosure has been made in consideration of the above, and aims to obtain a high-frequency package that can reduce distortion of the solder bumps while preventing deterioration of the electrical characteristics of the high-frequency package and scattering of the solder bumps during the secondary reflow process.

[0010] In order to solve the above-mentioned problems and achieve the object, the high-frequency package according to the present disclosure includes a first wiring substrate, a semiconductor chip disposed on the first wiring substrate and electrically connected to the first wiring substrate via first solder bumps, a second wiring substrate disposed on the first wiring substrate and electrically connected to the first wiring substrate via second solder bumps disposed around the semiconductor chip on the first wiring substrate, and a reinforcing material filled between the first solder bumps and the second solder bumps and filling from the first wiring substrate to the second wiring substrate and the semiconductor chip. The second wiring substrate has a through hole formed therein that penetrates the second wiring substrate in a thickness direction. When viewed along the thickness direction, at least a portion of the semiconductor chip and at least a portion of the reinforcing material are positioned to overlap the through hole.

[0011] According to the present disclosure, it is possible to reduce distortion of the solder bumps while preventing deterioration of the electrical characteristics of the high frequency package and scattering of the solder bumps in the secondary reflow process.

[0012] FIG. 1 is a cross-sectional view showing a high-frequency package according to a first embodiment; FIG. 2 is a plan view showing a high-frequency package according to a first embodiment; FIG. 3 is a cross-sectional view showing a method of manufacturing a high-frequency package according to a first embodiment, showing a first reflow process; FIG. 4 is a cross-sectional view showing a method of manufacturing a high-frequency package according to a first embodiment, showing a second reflow process; FIG. 5 is a cross-sectional view showing a method of manufacturing a high-frequency package according to a first embodiment, showing a coating process;

[0013] Hereinafter, a high-frequency package and a method for manufacturing the high-frequency package according to an embodiment will be described in detail with reference to the drawings.

[0014] First Embodiment. FIG. 1 is a cross-sectional view showing a high-frequency package 1 according to a first embodiment. FIG. 2 is a plan view showing the high-frequency package 1 according to the first embodiment. As shown in FIG. 1, the high-frequency package 1 includes a first wiring board 2, a semiconductor chip 3, a second wiring board 4, and a reinforcing material 5. Hereinafter, when describing the directions of the components of the high-frequency package 1, the thickness direction of the first wiring board 2 and the second wiring board 4 is referred to as a first direction, and a direction perpendicular to the first direction is referred to as a second direction. In the following description, the direction from the outer periphery of the first wiring board 2 and the second wiring board 4 in the second direction toward the center of the first wiring board 2 and the second wiring board 4 in the second direction is referred to as an inward direction, and the side opposite the inward direction is referred to as an outward direction. In FIG. 2, the reinforcing material 5 is hatched with dots to clearly indicate the extent of the reinforcing material 5.

[0015] The first wiring board 2 has a rectangular shape in a plan view. The first wiring board 2 has a first front surface 2a and a first back surface 2b facing away from the first front surface 2a.

[0016] The semiconductor chip 3 is disposed on the first surface 2a of the first wiring substrate 2 via the first solder bumps 6. The semiconductor chip 3 is electrically connected to the first wiring substrate 2 via the first solder bumps 6. The semiconductor chip 3 is disposed between the second wiring substrate 4 and the first solder bumps 6. A portion of the semiconductor chip 3 is disposed in a through hole 4c (described later) of the second wiring substrate 4. The semiconductor chip 3 is an integrated circuit that processes high frequencies in the microwave and millimeter wave bands. A plurality of first solder bumps 6 are disposed at intervals from each other in the second direction. The outermost first solder bumps 6 are disposed on the periphery of the semiconductor chip 3. Hereinafter, the first solder bumps 6 disposed on the periphery of the semiconductor chip 3 will be referred to as first solder bumps 6a. As shown in FIG. 2 , the semiconductor chip 3 has a rectangular shape in a plan view.

[0017] As shown in FIG. 1 , the second wiring board 4 is disposed on the first surface 2a of the first wiring board 2 via the second solder bumps 7. The second wiring board 4 is electrically connected to the first wiring board 2 via the second solder bumps 7. The second wiring board 4 has a second surface 4a and a second back surface 4b facing away from the second surface 4a. The second back surface 4b and the first surface 2a are disposed with a gap in the first direction. The second wiring board 4 has a through hole 4c formed therein, which penetrates in the first direction. The through hole 4c penetrates from the second surface 4a to the second back surface 4b.

[0018] The second solder bumps 7 are arranged around the semiconductor chip 3 and the first solder bumps 6 on the first surface 2a of the first wiring substrate 2. The innermost second solder bump 7 is arranged around the portion of the through hole 4c that opens to the second back surface 4b. Hereinafter, the second solder bump 7 arranged around the portion of the through hole 4c that opens to the second back surface 4b will be referred to as the second solder bump 7a. The first solder bump 6a and the second solder bump 7a are arranged with a gap in the second direction. The outermost second solder bump 7 is arranged on the outer periphery of the first wiring substrate 2. Hereinafter, the second solder bump 7 arranged on the outer periphery of the first wiring substrate 2 will be referred to as the second solder bump 7b. As shown in FIG. 2 , the planar shape of the second wiring substrate 4 and the planar shape of the through hole 4c are rectangular.

[0019] As shown in FIG. 1 , the reinforcing material 5 is filled between the first solder bumps 6 a and the second solder bumps 7 a, and also fills from the first surface 2 a of the first wiring substrate 2 to the second wiring substrate 4 and the semiconductor chip 3. This reduces distortion of the first solder bumps 6 a arranged on the periphery of the semiconductor chip 3. It also reduces distortion of the second solder bumps 7 a arranged around the portions of the through holes 4 c that open to the second back surface 4 b. The reinforcing material 5 contacts the first solder bumps 6 a and the second solder bumps 7 a, but does not contact the remaining first solder bumps 6 and second solder bumps 7. In this embodiment, the reinforcing material 5 fills a portion of the through holes 4 c, but does not necessarily fill the through holes 4 c. It is sufficient for the reinforcing material 5 to reach from the first surface 2 a of the first wiring substrate 2 to the second back surface 4 b of the second wiring substrate 4. In this embodiment, the reinforcing material 5 extends from the first surface 2a of the first wiring substrate 2 to the outer periphery of the semiconductor chip 3, but it is sufficient if the reinforcing material 5 extends from the first surface 2a of the first wiring substrate 2 to the surface of the semiconductor chip 3 that faces the first wiring substrate 2. The reinforcing material 5 is, for example, a thermosetting resin.

[0020] 2, when viewed in a first direction, which is the plate thickness direction, at least a portion of the semiconductor chip 3 and at least a portion of the reinforcing material 5 are positioned to overlap with the through-hole 4c. In other words, when viewed in the first direction, at least a portion of the semiconductor chip 3 and at least a portion of the reinforcing material 5 are exposed through the through-hole 4c. In this embodiment, when viewed in the first direction, the entire semiconductor chip 3 is positioned to overlap with the through-hole 4c.

[0021] Next, a manufacturing method of the high-frequency package 1 according to this embodiment will be described with reference to FIGS. 3 to 6. The manufacturing method of the high-frequency package 1 includes a first reflow process, a second reflow process, a coating process, and a curing process. FIG. 3 is a cross-sectional view showing the manufacturing method of the high-frequency package 1 according to the first embodiment, illustrating the first reflow process. FIG. 4 is a cross-sectional view showing the manufacturing method of the high-frequency package 1 according to the first embodiment, illustrating the second reflow process. FIG. 5 is a cross-sectional view showing the manufacturing method of the high-frequency package 1 according to the first embodiment, illustrating the coating process. FIG. 6 is a cross-sectional view showing the manufacturing method of the high-frequency package 1 according to the first embodiment, illustrating the curing process.

[0022] 3 , the first reflow process is a process of mounting the semiconductor chip 3 on the first wiring board 2 via the first solder bumps 6. Prior to the first reflow process, the first solder bumps 6 and the second solder bumps 7 are formed in advance on the first wiring board 2. In the first reflow process, the semiconductor chip 3 is first placed on the first wiring board 2 via the first solder bumps 6. Next, the first solder bumps 6 are heated to their melting temperature for a reflow process, melting the first solder bumps 6. When the melted first solder bumps 6 harden, a structure is obtained in which the semiconductor chip 3 is mounted on the first wiring board 2 via the first solder bumps 6.

[0023] The second reflow process is a process of mounting the first wiring board 2 on the second wiring board 4 via the second solder bumps 7 so that at least a portion of the semiconductor chip 3 overlaps with the through-holes 4c when viewed in the first direction. In the second reflow process, the first wiring board 2 on which the semiconductor chip 3 is mounted is first placed on the second wiring board 4 via the second solder bumps 7. Next, the second solder bumps 7 are heated to their melting temperature for a reflow process, melting the second solder bumps 7. In the second reflow process, the first solder bumps 6 are remelted. As the melted first solder bumps 6 and second solder bumps 7 harden, a structure is obtained in which the semiconductor chip 3 is mounted on the first wiring board 2 via the first solder bumps 6 and the first wiring board 2 is mounted on the second wiring board 4 via the second solder bumps 7.

[0024] The coating process is a process of coating the material that will become the reinforcing material 5 between the first solder bump 6 a and the second solder bump 7 a through the through hole 4 c. In the coating process, a nozzle 8 is inserted into the through hole 4 c, and the material is coated between the first solder bump 6 a and the second solder bump 7 a. In the coating process, the material is coated from the first surface 2 a of the first wiring board 2 to the second wiring board 4 and the semiconductor chip 3.

[0025] The curing step is a step of curing the applied material. In the curing step, the applied material is heated to harden it. By performing the above steps, the high frequency package 1 is manufactured.

[0026] Next, the effects of the high-frequency package 1 and the method for manufacturing the high-frequency package 1 according to this embodiment will be described.

[0027] First, with reference to Figs. 7 to 9, a conventional high-frequency package 1D in which a through hole 4c is not formed in the second wiring substrate 4 but a counterbore 9 is formed in the second wiring substrate 4 will be described. Fig. 7 is a cross-sectional view showing the conventional high-frequency package 1D. Fig. 8 is a cross-sectional view showing the conventional high-frequency package 1D at a high temperature. Fig. 9 is a cross-sectional view showing the conventional high-frequency package 1D with a waveguide plate 10 attached thereto, showing the conventional high-frequency package 1D and the waveguide plate 10 at a high temperature.

[0028] As shown in FIG. 7 , in a high-frequency package 1D according to the prior art, in order to avoid interference between the semiconductor chip 3 and the second wiring board 4, a recess 9 recessed in a direction away from the semiconductor chip 3 is provided on the second back surface 4 b of the second wiring board 4.

[0029] 8 , where A is the linear expansion coefficient of the first wiring board 2, B is the linear expansion coefficient of the semiconductor chip 3, and C is the linear expansion coefficient of the second wiring board 4, the relationship generally satisfies B<C<A. When the temperature of the high-frequency package 1D changes, strain occurs in the first solder bumps 6 and the second solder bumps 7 due to the difference in the linear expansion coefficients between the first wiring board 2 and the semiconductor chip 3, the difference in the linear expansion coefficients between the first wiring board 2 and the second wiring board 4, and the counterbore 9 of the second wiring board 4. In particular, the strain occurring in the first solder bump 6a is larger than the strain occurring in the other first solder bumps 6. Furthermore, the strain occurring in the second solder bumps 7a and 7b is larger than the strain occurring in the other second solder bumps 7. If such distortion of the first solder bump 6a and the second solder bumps 7a and 7b are repeated, there is a problem that the first solder bump 6a and the second solder bumps 7a and 7b may break.

[0030] As shown in FIG. 9 , a conventional high-frequency package 1D employs a structure in which a waveguide plate 10 is attached to a second wiring board 4 with screws 11 from the viewpoint of electrical characteristics. The waveguide plate 10 is attached to the second surface 4a of the second wiring board 4. When the linear expansion coefficient of the waveguide plate 10 is D, the relationship B<C<A≦D generally holds. When the waveguide plate 10 is attached to the second surface 4a of the second wiring board 4, a temperature change in the high-frequency package 1D increases the strain of the first solder bump 6a and the second solder bumps 7a and 7b due to the difference in the linear expansion coefficients between the second wiring board 4 and the waveguide plate 10, in addition to the difference in the linear expansion coefficients between the components. This increases the strain of the first solder bump 6a and the second solder bumps 7a and 7b. This poses a problem of facilitating fracture of the first solder bump 6a and the second solder bumps 7a and 7b.

[0031] As a means for reducing the distortion of the first solder bumps 6 a, there are methods such as infiltrating an insulating underfill material into the gap between the first wiring substrate 2 and the semiconductor chip 3, or applying an insulating sidefill material between the first wiring substrate 2 and the outer periphery of the semiconductor chip 3. However, when the underfill material is infiltrated, the underfill material comes into contact with all of the first solder bumps 6, which causes a problem of degrading the electrical characteristics of the high-frequency package 1D. On the other hand, when the sidefill material is applied after the semiconductor chip 3 is mounted on the first wiring substrate 2 via the first solder bumps 6, the area to which the sidefill material is applied is small, so the sidefill material may come into contact with both the first solder bumps 6 and the second solder bumps 7. If the side fill material adheres to the first solder bumps 6 and the second solder bumps 7, the first solder bumps 6 and the second solder bumps 7 will scatter during the secondary reflow process in which the first wiring board 2 is mounted on the second wiring board 4, causing problems in the connection between the semiconductor chip 3 and the first wiring board 2 and the connection between the first wiring board 2 and the second wiring board 4.

[0032] 1 and 2, second wiring board 4 has through holes 4c formed therein that penetrate through second wiring board 4 in the thickness direction, and when viewed along the thickness direction, at least a portion of semiconductor chip 3 and at least a portion of reinforcing material 5 are positioned to overlap through holes 4c. With this configuration, after the second reflow step of mounting first wiring board 2 to second wiring board 4 via second solder bumps 7 is completed, material to become reinforcing material 5 can be applied through through holes 4c of second wiring board 4, thereby preventing scattering of first solder bumps 6 and second solder bumps 7 during the second reflow step.

[0033] 1, in this embodiment, the reinforcing material 5 is filled between the first solder bumps 6a and the second solder bumps 7a, and also fills from the first surface 2a of the first wiring board 2 to the second wiring board 4 and the semiconductor chip 3. This configuration can reduce distortion of the first solder bumps 6a arranged on the periphery of the semiconductor chip 3, and can also reduce distortion of the second solder bumps 7a arranged around the portions of the through holes 4c that open to the second back surface 4b. This makes it possible to prevent breakage of the first solder bumps 6a and the second solder bumps 7a.

[0034] 1, the reinforcing material 5 does not contact all of the first solder bumps 6. In other words, the reinforcing material 5 contacts only the first solder bumps 6 a. This configuration can prevent the electrical characteristics of the high-frequency package 1 from deteriorating.

[0035] As described above, in this embodiment, it is possible to reduce the distortion of the first solder bump 6a and the second solder bump 7a while preventing the deterioration of the electrical characteristics of the high-frequency package 1 and the scattering of the second solder bump 7 in the secondary reflow process.

[0036] Second Embodiment Next, a high-frequency package 1A according to a second embodiment will be described with reference to Fig. 10. Fig. 10 is a cross-sectional view showing a high-frequency package 1A according to the second embodiment. In this embodiment, the filling range of the reinforcing material 5 differs from that of the first embodiment. In the second embodiment, parts that overlap with those of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0037] The reinforcing material 5 fills the entire through hole 4c and is also in contact with the surface of the semiconductor chip 3 that faces away from the first wiring board 2.

[0038] In this embodiment, since the reinforcing material 5 is filled into the entire through hole 4c, the distortion of the second solder bump 7a can be further reduced, and therefore, the breakage of the second solder bump 7a can be further suppressed.

[0039] Third Embodiment Next, a high-frequency package 1B according to a third embodiment will be described with reference to Fig. 11. Fig. 11 is a cross-sectional view showing a high-frequency package 1B according to the third embodiment. This embodiment differs from the first embodiment in that the reinforcing member 5 includes a first reinforcing member 5a and a second reinforcing member 5b. In the third embodiment, parts that overlap with those in the first embodiment are denoted by the same reference numerals and will not be described again.

[0040] The reinforcing material 5 includes a first reinforcing material 5a and a second reinforcing material 5b. The first reinforcing material 5a is filled between the first solder bumps 6a and the second solder bumps 7a. The first reinforcing material 5a is filled from the first surface 2a of the first wiring board 2 to the second wiring board 4 and the semiconductor chip 3. The first reinforcing material 5a is in contact with the first solder bumps 6a and the second solder bumps 7a, but is not in contact with the other first solder bumps 6 and second solder bumps 7. In this embodiment, the first reinforcing material 5a is filled in a portion of the through hole 4c, but it does not have to be filled in the through hole 4c. It is sufficient that the first reinforcing material 5a extends from the first surface 2a of the first wiring board 2 to the second back surface 4b of the second wiring board 4. In this embodiment, the first reinforcing material 5a extends from the first surface 2a of the first wiring substrate 2 to the outer periphery of the semiconductor chip 3, but it is sufficient if the first reinforcing material 5a extends from the first surface 2a of the first wiring substrate 2 to the surface of the semiconductor chip 3 that faces the first wiring substrate 2. The first reinforcing material 5a is, for example, a thermosetting resin.

[0041] The second reinforcing material 5b is layered on the first reinforcing material 5a and fills the through hole 4c. The second reinforcing material 5b is disposed on the surface of the first reinforcing material 5a facing away from the first wiring board 2. In this embodiment, the second reinforcing material 5b fills a portion of the through hole 4c, but may fill the entire through hole 4c. In this embodiment, the second reinforcing material 5b extends from above the first reinforcing material 5a to the same position as the second surface 4a of the second wiring board 4, but may extend from above the first reinforcing material 5a to near the second surface 4a. The second reinforcing material 5b contacts the outer periphery of the semiconductor chip 3 and the surface of the semiconductor chip 3 facing away from the first wiring board 2. The second reinforcing material 5b is, for example, a thermosetting resin. The difference in linear expansion coefficient between the second reinforcing material 5b and the second wiring board 4 is smaller than the difference in linear expansion coefficient between the first reinforcing material 5a and the second wiring board 4. The difference in the linear expansion coefficient between the second reinforcing material 5b and the second wiring board 4 is smaller than the difference in the linear expansion coefficient between the second wiring board 4 and each component of the high-frequency package 1C other than the second reinforcing material 5b.

[0042] In this embodiment, the reinforcing material 5 includes a first reinforcing material 5a filled between the first solder bump 6a and the second solder bump 7a, and a second reinforcing material 5b laminated on the first reinforcing material 5a and filled in the through hole 4c. Furthermore, in this embodiment, the difference in the linear expansion coefficient between the second reinforcing material 5b and the second wiring board 4 is smaller than the difference in the linear expansion coefficient between the first reinforcing material 5a and the second wiring board 4. This configuration allows the first reinforcing material 5a to reduce distortion of the first solder bump 6a caused by the difference in the linear expansion coefficient between the first wiring board 2 and the semiconductor chip 3, and distortion of the second solder bump 7a caused by the difference in the linear expansion coefficient between the first wiring board 2 and the second wiring board 4. This configuration also allows the second reinforcing material 5b to reduce distortion of the second solder bump 7a caused by the provision of the through hole 4c in the second wiring board 4. This makes it possible to further prevent the first solder bumps 6a and the second solder bumps 7a from breaking.

[0043] Although the second reinforcing material 5b is a thermosetting resin, it may be a conductive adhesive. This can improve the heat dissipation effect of the second wiring board 4. Furthermore, by electrically connecting the second reinforcing material 5b, which is a conductive adhesive, to the ground layer of the second wiring board 4, an electromagnetic shielding effect can be obtained.

[0044] Fourth Embodiment Next, a high-frequency package 1C according to a fourth embodiment will be described with reference to FIGS. 12 and 13. FIG. 12 is a cross-sectional view showing the high-frequency package 1C according to the fourth embodiment. FIG. 13 is a plan view showing the high-frequency package 1C according to the fourth embodiment. This embodiment differs from the first embodiment in that a portion of the semiconductor chip 3 overlaps with the through-hole 4c. Note that in the fourth embodiment, parts that overlap with those in the first embodiment are given the same reference numerals and will not be described again. In FIG. 13, in order to clearly show the scope of the semiconductor chip 3 and the reinforcing material 5, the semiconductor chip 3 is hatched with diagonal lines and the reinforcing material 5 is hatched with dots.

[0045] As shown in FIG. 13 , the semiconductor chip 3 has a plurality of corners 3 a and a plurality of sides 3 b connecting adjacent corners 3 a. When viewed in the first direction, the second wiring substrate 4 has a plurality of through holes 4 c formed therein, each overlapping with one of the plurality of corners 3 a. In this embodiment, the number of corners 3 a and the number of through holes 4 c are four. One through hole 4 c is provided for each corner 3 a. When viewed in the first direction, each corner 3 a and the ends of the two sides 3 b adjacent to each corner 3 a are positioned to overlap one of the plurality of through holes 4 c. In other words, when viewed in the first direction, which is the plate thickness direction, a portion of the semiconductor chip 3 overlaps with the through hole 4 c. When viewed in the first direction, a portion of the reinforcing member 5 also overlaps with the through hole 4 c.

[0046] When viewed in the first direction, the through hole 4c may be located at a position overlapping with a portion other than the corner 3a and the end of the side 3b of the semiconductor chip 3. For example, when viewed in the first direction, the through hole 4c may be located at a position overlapping with only the center of the side 3b of the semiconductor chip 3.

[0047] In this embodiment, when viewed along the first direction, which is the board thickness direction, a portion of the semiconductor chip 3 is positioned so as to overlap with the through hole 4c. This configuration can achieve the following four effects: (1) The effect of being able to reduce the processing time in the step of providing the through hole 4c in the second wiring board 4. (2) The effect of being able to reduce the opening area of ​​the through hole 4c, so that distortion of the second wiring board 4 can be reduced. (3) The effect of being able to provide a wiring pattern in an area of ​​the second wiring board 4 where there is no through hole 4c. (4) The effect of being able to reduce the amount of reinforcing material 5 used.

[0048] The configurations shown in the above embodiments are merely examples, and may be combined with other known technologies, or different embodiments may be combined with each other. It is also possible to omit or modify parts of the configurations as long as they do not deviate from the gist of the invention.

[0049] 1, 1A, 1B, 1C, 1D High frequency package, 2 First wiring board, 2a First surface, 2b First back surface, 3 Semiconductor chip, 3a Corner portion, 3b Side, 4 Second wiring board, 4a Second surface, 4b Second back surface, 4c Through hole, 5 Reinforcement material, 5a First reinforcing material, 5b Second reinforcing material, 6, 6a First solder bump, 7, 7a, 7b Second solder bump, 8 Nozzle, 9 Counterbore, 10 Waveguide plate, 11 Screw.

Claims

1. A first wiring board; a semiconductor chip disposed on the first wiring board and electrically connected to the first wiring board via first solder bumps; a second wiring board disposed on the first wiring board and electrically connected to the first wiring board via second solder bumps disposed around the semiconductor chip on the first wiring board; a reinforcing material that is filled between the first solder bumps and the second solder bumps and that is filled from the first wiring substrate to the second wiring substrate and the semiconductor chip; Equipped with a through hole penetrating the second wiring board in a thickness direction of the second wiring board is formed; A high frequency package, characterized in that, when viewed along the plate thickness direction, at least a portion of the semiconductor chip and at least a portion of the reinforcing material are positioned to overlap the through hole.

2. 2. The high frequency package according to claim 1, wherein the semiconductor chip is entirely located so as to overlap the through hole when viewed in the thickness direction.

3. 2. The high frequency package according to claim 1, wherein the reinforcing material fills the entire through hole.

4. The reinforcing material is a first reinforcing material filled between the first solder bump and the second solder bump; A second reinforcing material that is laminated on the first reinforcing material and filled in the through hole; Including, 4. The high-frequency package according to claim 1, wherein a difference in linear expansion coefficient between the second reinforcing material and the second wiring board is smaller than a difference in linear expansion coefficient between the first reinforcing material and the second wiring board.

5. 5. The high frequency package according to claim 4, wherein the second reinforcing material is a conductive adhesive.

6. 1. A method for manufacturing a high frequency package comprising: a first wiring board; a semiconductor chip disposed on the first wiring board and electrically connected to the first wiring board via first solder bumps; a second wiring board disposed on the first wiring board and electrically connected to the first wiring board via second solder bumps disposed around the semiconductor chip on the first wiring board; and a reinforcing material filled between the first solder bumps and the second solder bumps and filled from above the first wiring board to the second wiring board and the semiconductor chip, wherein a through hole penetrating in a plate thickness direction of the second wiring board is formed in the second wiring board, a first reflow process of mounting the semiconductor chip on the first wiring board by the first solder bumps; a secondary reflow process of mounting the first wiring board on the second wiring board by the second solder bumps such that at least a portion of the semiconductor chip is positioned to overlap the through hole when viewed along the board thickness direction; a coating step of coating the reinforcing material between the first solder bump and the second solder bump through the through hole; a curing step of curing the applied material to form the reinforcement material; A method for manufacturing a high-frequency package comprising: