Semiconductor device, method for manufacturing same, and power conversion device

Abstract

The purpose of the present disclosure is to obtain a semiconductor device which has a cooling function for a semiconductor module and is miniaturized. In the present disclosure, a plurality of heat dissipation fins (61) include four pairs of deformed heat dissipation fins (61X), (61X) that are adjacent to each other, and a plurality of normal heat dissipation fins (61n) other than the four pairs of deformed heat dissipation fins (61X), (61X). Four cooling air passage regions (95) act as gap regions between corresponding pairs of the deformed heat radiation fins (61X) and (61X) among the four pairs of deformed heat dissipation fins (61X) and (61X). The four cooling air passage regions (95) each have a wide fin interval (S5). A plurality of cooling air passage regions (91) each have a fin interval (S1). \｛S5 > S1\｝ is satisfied between the wide fin intervals (S5) and the fin intervals (S1).

Description

Semiconductor device, manufacturing method thereof, and power conversion device

[0001] The present disclosure relates to a semiconductor device, a manufacturing method thereof, and a power conversion device, and more particularly to a heat dissipation function of a power semiconductor device.

[0002] As a conventional device having a heat dissipation function that is applied to a power semiconductor device, for example, there is a heat dissipation device that uses a modular cooling device disclosed in Japanese Patent Application Laid-Open No. 2003-222299.

[0003] The heat dissipation device includes a plurality of modular cooling devices each having a heat dissipation plate on which a heat-generating element is disposed, and a housing for detachably connecting the plurality of modular cooling devices, the housing including an outer frame, an opening formed to penetrate the interior of the outer frame, and at least one bridge provided on the outer frame to separate the opening and support the modular cooling devices inserted into the opening. The heat dissipation device further includes at least one airflow direction guide member inserted between the plurality of modular cooling devices to control the flow of air into the modular cooling devices.

[0004] Patent No. 6448732

[0005] In conventional power semiconductor devices incorporating multiple power semiconductor modules, a heat sink is generally used to dissipate heat generated by the semiconductor elements in one power semiconductor module. Therefore, when cooling air is blown in to achieve the cooling function, the heated air flows into the heat sinks of other power semiconductor modules, raising the temperatures of the semiconductor elements in those modules. This characteristic is described in detail below.

[0006] The temperature of the air passing through the heat dissipation fins directly below the heat sink on the upwind side rises as it dissipates heat generated by the power semiconductor module directly above. This heated air then passes through the heat dissipation fins directly below the heat sink on the downwind side. As a result, the temperature of the downwind air passing through the heat dissipation fins directly below the downwind heat sink is higher than the temperature of the upwind air passing through the heat dissipation fins directly below the heat sink on the upwind side. This reduces the effect of suppressing the temperature rise of the power semiconductor module directly above the downwind heat sink.

[0007] Considering the thermal interference between the upwind and downwind power semiconductor modules in such a power semiconductor device, there has been a problem in that the power semiconductor modules and heat sinks have to be large in size because it is necessary to increase the size of the power semiconductor modules themselves or the heat sinks in order to suppress the temperature rise of the power semiconductor modules due to the above-mentioned thermal interference.

[0008] The present disclosure has been made to solve the above problems, and has an object to provide a semiconductor device that has a cooling function for a semiconductor module and is miniaturized.

[0009] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0010] A semiconductor device according to the present disclosure is a semiconductor device including a first-type heat sink, a second-type heat sink, a first-type semiconductor module mounted on the first-type heat sink, and a second-type semiconductor module mounted on the second-type heat sink, wherein the first-type heat sink has a plurality of first-type heat dissipation fins, each of which has a first-type formation depth extending in a formation depth direction on a side opposite to a mounting surface of the first-type semiconductor module and a first-type formation width extending in the fin formation direction, the plurality of first-type heat dissipation fins being discretely arranged along a fin arrangement direction intersecting with the fin formation direction, and gap regions between the plurality of first-type heat dissipation fins being first-type cooling air passage regions, the second-type heat sink has a plurality of second-type heat dissipation fins, each of which has a second-type formation depth extending in the formation depth direction and a second-type formation width extending in the fin formation direction, the second-type cooling air passage area includes a plurality of second-type narrow regions and at least one first-type wide region, each of the plurality of first-type narrow regions having a first-type narrow spacing, and the at least one first-type wide region having a first-type wide spacing; the second-type cooling air passage area includes a plurality of second-type wide regions, each of the plurality of second-type wide regions having a second-type wide spacing; and in the first-type cooling air passage area, the first-type wide spacing is set wider than the first-type narrow spacing.

[0011] The first-class heat sink is located on the windward side and the second-class heat sink is located on the leeward side of the cooling air supplied by the cooling air supply structure. In the first-class cooling air passing area, the first-class wide interval is set wider than the first-class narrow interval.

[0012] Therefore, the semiconductor device of the present disclosure can minimize the temperature rise of the cooling air passing through the first type wide region and allow the cooling air to flow into the multiple second type heat dissipation fins.

[0013] Therefore, in the semiconductor device of the present disclosure, the cooling air sent by the cooling air supply structure can suppress temperature rises of the multiple type-2 heat dissipation fins in addition to the multiple type-1 heat dissipation fins, so that the type-1 heat sink can suppress temperature rises during operation of the type-1 semiconductor module, and the type-2 heat sink can suppress temperature rises during operation of the type-2 semiconductor module.

[0014] In other words, the semiconductor device of the present disclosure does not require the first and second type semiconductor modules and the first and second type heat sinks to be enlarged in order to suppress temperature increases during operation of the first and second type semiconductor modules.

[0015] As a result, the semiconductor device of the present disclosure has a cooling function for the first and second type semiconductor modules, and can also be made smaller in size.

[0016] FIG. 1 is an explanatory diagram schematically showing a planar configuration of a semiconductor device according to a first embodiment of the present disclosure; FIG. 2 is an explanatory diagram schematically showing a planar structure of a heat sink mounting frame shown in FIG. 1; FIG. 3 is an explanatory diagram schematically showing a planar structure of a semiconductor device according to a modified example of the first embodiment; FIG. 4 is a cross-sectional view (part 1) schematically showing a cross-sectional structure of a power semiconductor module; FIG. 5 is a cross-sectional view (part 2) schematically showing a cross-sectional structure of a power semiconductor module; FIG. 6 is a cross-sectional view (part 3) schematically showing a cross-sectional structure of a power semiconductor module; FIG. 1 is an explanatory diagram (part 1) schematically showing a cross-sectional structure of a semiconductor device according to the first embodiment; FIG. 2 is an explanatory diagram (part 2) schematically showing a cross-sectional structure of a heat sink; FIG. 3 is an explanatory diagram (part 3) schematically showing a cross-sectional structure of a heat sink; and FIG. 1 is an explanatory diagram (part 1) showing an effect of the semiconductor device according to the first embodiment. 19 is an explanatory diagram (part 2) showing the effect of the semiconductor device of embodiment 1. FIG. 20 is an explanatory diagram (part 3) showing the effect of the semiconductor device of embodiment 1. FIG. 21 is an explanatory diagram (part 2) showing the effect of the semiconductor device of embodiment 1. FIG. 22 is an explanatory diagram (part 3) showing the effect of the semiconductor device of embodiment 1. FIG. 23 is an explanatory diagram (part 1) showing the planar configuration of the semiconductor device of embodiment 2. FIG. 24 is an explanatory diagram (part 1) showing the planar structure of each of the first and second type heat sinks in the semiconductor device of embodiment 2. FIG. 25 is an explanatory diagram (part 2) showing the planar structure of the semiconductor device of embodiment 2. FIG. 26 is an explanatory diagram (part 1) showing the effect of the semiconductor device of embodiment 4. FIG. 27 is an explanatory diagram (part 1) showing the effect of the semiconductor device of embodiment 4. Fig. 10 is an explanatory diagram schematically showing a planar configuration of a semiconductor device which is a basic configuration of embodiment 5. Fig. 11 is an explanatory diagram schematically showing a cross-sectional structure of a semiconductor device of embodiment 5. Fig. 12 is an explanatory diagram schematically showing a cross-sectional structure of a heat sink-integrated power semiconductor module.31 is an explanatory diagram (part 1) showing the effect of the semiconductor device of embodiment 5. FIG. 32 is an explanatory diagram (part 2) showing the effect of the semiconductor device of embodiment 5. FIG. 33 is an explanatory diagram (part 2) showing the effect of the semiconductor device of embodiment 5. FIG. 34 is an explanatory diagram (part 1) showing the planar configuration of a semiconductor device that is a modification of embodiment 5. FIG. 35 is an explanatory diagram (part 2) showing the cross-sectional structure of FIG. 31. FIG. 35 is an explanatory diagram (part 1) showing the basic method for manufacturing a semiconductor device of embodiment 5. FIG. 36 is an explanatory diagram (part 2) showing the basic method for manufacturing a semiconductor device of embodiment 5. FIG. 37 is an explanatory diagram (part 1) showing a first improved method for manufacturing a semiconductor device of embodiment 5. FIG. 38 is an explanatory diagram (part 2) showing a first improved method for manufacturing a semiconductor device of embodiment 5. FIG. 39 is an explanatory diagram (part 1) showing a problem with the first improved method. FIG. 39 is an explanatory diagram (part 2) showing a problem with the first improved method. FIG. 39 is an explanatory diagram (part 1) showing a second improved method for manufacturing a semiconductor device of embodiment 5. FIG. 39 is an explanatory diagram (part 2) showing a second improved method for manufacturing a semiconductor device of embodiment 5. FIG. 39 is an explanatory diagram (part 1) showing a third improved method for manufacturing a semiconductor device of embodiment 5. FIG. 10 is an explanatory diagram (part 2) showing a third improved method for manufacturing a semiconductor device according to a fifth embodiment. FIG. 11 is an explanatory diagram (part 1) showing a fourth improved method for manufacturing a semiconductor device according to a fifth embodiment. FIG. 12 is an explanatory diagram (part 2) showing a fourth improved method for manufacturing a semiconductor device according to a sixth embodiment. FIG. 13 is a block diagram showing a configuration of a power conversion system to which a power conversion device according to a sixth embodiment is applied. FIG. 14 is an explanatory diagram (part 1) showing a cross-sectional structure of the comparative semiconductor device. FIG. 15 is an explanatory diagram (part 2) showing a cross-sectional structure of the comparative semiconductor device. FIG. 16 is an explanatory diagram (part 1) showing the characteristics of the comparative semiconductor device. FIG. 17 is an explanatory diagram (part 2) showing the characteristics of the comparative semiconductor device.

[0017] 1 is an explanatory diagram schematically illustrating a planar configuration of a semiconductor device 101 according to a first embodiment of the present disclosure. The semiconductor device 101 according to the first embodiment is a power semiconductor device having a plurality of power semiconductor modules. An XYZ Cartesian coordinate system is depicted in FIG. 1 .

[0018] In this specification, in FIG. 1 and all drawings shown thereafter, an XYZ Cartesian coordinate system is used, and the upper surface on the +Z direction side is described as the first main surface, and the lower surface on the −Z direction side is described as the second main surface.

[0019] As shown in FIG. 1, a semiconductor device 101 according to the first embodiment has a first type heat sink 5 and a second type heat sink 6, and the first and second type heat sinks 5 and 6 are attached to a heat sink attachment frame 4, which is an attachment plate.

[0020] 2 is an explanatory diagram showing a schematic planar structure of the heat sink mounting frame 4. An XYZ Cartesian coordinate system is shown in FIG. 2. As shown in the figure, the heat sink mounting frame 4 has openings K5 and K6, and the first type heat sink 5 is attached by fitting it into opening K5, and the second type heat sink 6 is attached by fitting it into opening K6. The heat sink mounting frame 4 is fixed above the housing 3.

[0021] As shown in FIG. 1, the semiconductor device 101 of the first embodiment has six power semiconductor modules M11 to M16 mounted on the first main surface of the first-type heat sink 5, and three power semiconductor modules M41 to M43 mounted on the first main surface of the second-type heat sink 6.

[0022] As described above, the semiconductor device 101 of the first embodiment has a plurality of power semiconductor modules, namely, power semiconductor modules M11 to M16 and power semiconductor modules M41 to M43. The power semiconductor modules M11 to M16 are classified as first-type semiconductor modules, and the power semiconductor modules M41 to M43 are classified as second-type semiconductor modules. Therefore, the first main surface of the first-type heat sink 5 serves as the mounting surface for the first-type semiconductor modules, and the first main surface of the second-type heat sink 6 serves as the mounting surface for the second-type semiconductor modules.

[0023] 1, a cooling fan 2 is attached to the mounting side surface of the housing 3. In order to realize a cooling air supply structure, the semiconductor device 101 of the first embodiment uses a cooling fan 2 that blows cooling air with a flow velocity vector 1 in the airflow direction along the +Y direction. Note that with regard to the side surface of the housing 3, the mounting side surface is the side surface on the -Y direction side opposite to the +Y direction side on which the second-type heat sink 6 is arranged with respect to the first-type heat sink 5. In this way, the semiconductor device 101 realizes a cooling air supply structure that supplies cooling air in the airflow direction along the Y direction by the cooling fan 2.

[0024] Flow velocity vector 1 indicates the direction in which cooling air flows from cooling fan 2. That is, cooling fan 2 takes in cooling air in the direction indicated by flow velocity vector 1, and supplies the cooling air to the multiple first-class heat dissipation fins and multiple second-class heat dissipation fins of first-class and second-class heat sinks 5 and 6, respectively, as will be described later.

[0025] Therefore, the first-class heat sink 5 is located on the upwind side and the second-class heat sink 6 is located on the downwind side of the cooling air supplied along flow velocity vector 1, which indicates the airflow direction. Note that flow velocity vector 1 may also be in the direction of exhausting air from the housing 3. In other words, as long as the air flow is structured to match flow velocity vector 1, a cooling air supply structure can be realized without using the cooling fan 2.

[0026] As such, the semiconductor device 101 of embodiment 1 includes, as its main components, power semiconductor modules M11 to M16, power semiconductor modules M41 to M43, first and second type heat sinks 5 and 6, a heat sink mounting frame 4, a housing 3, and a cooling fan 2.

[0027] In the semiconductor device 101 shown in FIG. 1, the heat sink mounting frame 4, which is the mounting plate, and the housing 3 are constructed as separate members, but the heat sink mounting frame 4 and the housing 3 may be constructed as a single unit by press working, or the heat sink mounting frame 4 and the housing 3 may be constructed as an integrated part by welding or the like.

[0028] 3 is an explanatory diagram schematically illustrating the planar structure of a semiconductor device 101s that is a modification of the first embodiment. An XYZ Cartesian coordinate system is depicted in FIG. 3. Hereinafter, components similar to those of the semiconductor device 101 are denoted by the same reference numerals and description thereof will be omitted, and the following description will focus on the features of the semiconductor device 101s that is the modification.

[0029] As shown in Figure 3, the modified semiconductor device 101s has one power semiconductor module M1 mounted on the first main surface of the first-type heat sink 5 and one power semiconductor module M4 mounted on the first main surface of the second-type heat sink 6.

[0030] In this way, the semiconductor device 101s of the modified example has the power semiconductor module M1 as the first-type semiconductor module and the power semiconductor module M4 as the second-type semiconductor module, and therefore the first main surface of the first-type heat sink 5 serves as the mounting surface for the first-type semiconductor module, and the first main surface of the second-type heat sink 6 serves as the mounting surface for the second-type semiconductor module.

[0031] In the basic configuration of semiconductor device 101 of embodiment 1 shown in FIG. 1, the number of heat sinks is "2" and the number of power semiconductor modules is "9", but in semiconductor device 101s, which is a modified example of embodiment 1 shown in FIG. 3, the number of heat sinks is "2" and the number of power semiconductor modules is "2".

[0032] 4 to 6 are cross-sectional views schematically showing the cross-sectional structures of the power semiconductor modules Mi, Mj, and Mk, and each of which depicts an XYZ orthogonal coordinate system.

[0033] First, the structure of the power semiconductor module Mi shown in Fig. 4 will be described. An insulating material 20 is provided on a first main surface of a metal plate 21. A plurality of metal conductors 19 are selectively provided on the first main surface of the insulating material 20. A plurality of semiconductor elements 16 are selectively provided on the first main surfaces of the plurality of metal conductors 19 via bonding material 17. Some of the semiconductor elements 16 and the semiconductor elements 16 and the metal conductors 19 are electrically connected via wiring 18.

[0034] The bonding material 17 is made of solder or the like, the plurality of metal conductors 19 are provided using, for example, a lead frame, the insulating material 20 is made of, for example, an insulating sheet, and the sealing material 22 is made of, for example, an epoxy resin. The plurality of semiconductor elements 16 may be, but are not particularly limited to, Si-based semiconductor elements, SiC-based semiconductor elements, or compound semiconductor elements such as GaN.

[0035] A sealing material 22 is provided to cover the metal plate 21, the insulating material 20, the plurality of metal conductors 19, the plurality of bonding materials 17, the plurality of semiconductor elements 16, and the plurality of wirings 18. The insulating material 20, the plurality of bonding materials 17, the plurality of semiconductor elements 16, and the plurality of wirings 18 are all sealed within the sealing material 22.

[0036] Some of the plurality of metal conductors 19 are sealed within the sealing material 22, and some of them protrude from the first main surface or the side surface of the sealing material 22 and are exposed to the outside. In addition, the second main surface of the metal plate 21 is exposed. Of the plurality of metal conductors 19, the metal conductors 19 protruding from above the sealing material 22 are electrically connected to any one of the plurality of semiconductor elements 16.

[0037] A power semiconductor module Mi having such a structure can be used as the power semiconductor modules M11 to M16 and the power semiconductor modules M41 to M43 of the semiconductor device 101, and can also be used as the power semiconductor module M1 and the power semiconductor module M4 of the modified semiconductor device 101s.

[0038] Next, the structure of the power semiconductor module Mj shown in Fig. 5 will be described. Components similar to those of the power semiconductor module Mi shown in Fig. 4 will be assigned the same reference numerals and descriptions thereof will be omitted where appropriate, and the description will focus on the characteristic features of the power semiconductor module Mj.

[0039] Some of the plurality of metal conductors 19 are sealed within the sealing material 22, and some of them protrude from the side surface or the first main surface of the sealing material 22 and are exposed to the outside. In this case, the exposed portion of the metal conductor 19B protruding from the side surface of the sealing material 22 has a curved shape including a portion parallel to the X direction and a portion parallel to the Z direction.

[0040] A power semiconductor module Mj having such a structure can be used as the power semiconductor modules M11 to M16 and power semiconductor modules M41 to M43 of the semiconductor device 101, and can also be used as the power semiconductor module M1 and power semiconductor module M4 of the semiconductor device 101s.

[0041] Next, the structure of the power semiconductor module Mk shown in Fig. 6 will be described. Components similar to those of the power semiconductor module Mi shown in Fig. 4 will be assigned the same reference numerals and descriptions thereof will be omitted where appropriate, and the description will focus on the characteristic features of the power semiconductor module Mk.

[0042] A sealing material 22 is provided to cover the metal plate 21, the insulating material 20, the plurality of metal conductors 19, the plurality of bonding materials 17, the plurality of semiconductor elements 16, and the plurality of wirings 18. The plurality of bonding materials 17, the plurality of semiconductor elements 16, and the plurality of wirings 18 are all sealed within the sealing material 22. Some of the plurality of metal conductors 19 are sealed within the sealing material 22, and some protrude from a first main surface of the sealing material 22 and are exposed to the outside as electrode terminals 24. In addition, the second main surface of the metal plate 21 is exposed.

[0043] The resin case 23 accommodates the metal plate 21, the insulating material 20, the plurality of metal conductors 19, the plurality of bonding materials 17, the plurality of semiconductor elements 16, and the sealing material 22. In this case, the resin case 23 is in contact with the side surfaces of the metal plate 21 and the insulating material 20.

[0044] A power semiconductor module Mk having such a structure can be used as the power semiconductor modules M11 to M16 and power semiconductor modules M41 to M43 of the semiconductor device 101, and can also be used as the power semiconductor module M1 and power semiconductor module M4 of the semiconductor device 101s.

[0045] In addition, power semiconductor modules other than the power semiconductor modules Mi, Mj, and Mk shown in Figures 4 to 6 can also be used as first-type semiconductor modules or second-type semiconductor modules for the semiconductor device 101 and the semiconductor device 101s.

[0046] Figures 7 and 8 are explanatory diagrams schematically showing the cross-sectional structure of the semiconductor device 101 of the first embodiment shown in Figure 1. Figure 7 shows the A-A cross section of Figure 1, and Figure 8 shows the B-B cross section of Figure 1. An XYZ orthogonal coordinate system is shown in each of Figures 7 and 8.

[0047] As shown in Figure 7, the first-class heat sink 5 has a heat sink base 51 and multiple heat dissipation fins 61. The multiple heat dissipation fins 61 are classified as multiple first-class heat dissipation fins. The power semiconductor modules M13 and M14 are mounted on a first main surface of the heat sink base 51. Specifically, the second main surfaces of the metal plates 21 of the power semiconductor modules M13 and M14 are bonded to the first main surface of the heat sink base 51 via a TIM (Thermal Interface Material) 25. The TIM 25 is made of a thermally conductive grease or the like, and ensures relatively high thermal conductivity between the first-class heat sink 5 and the power semiconductor modules M13 and M14.

[0048] The first main surface of the heat sink base 51 becomes the first main surface of the first-type heat sink 5, and the multiple heat dissipation fins 61 each extend in the -Z direction from the second main surface of the heat sink base 51. Therefore, each of the multiple heat dissipation fins 61 has a first-type formation depth that extends in the formation depth direction (-Z direction) on the side opposite to the first main surface of the heat sink base 51, which is the mounting surface for the first-type semiconductor module. In addition, each of the multiple heat dissipation fins 61 has a first-type formation width that extends in the fin formation direction along the Y direction.

[0049] The multiple heat dissipation fins 61 have a fin arrangement direction in the X direction, which intersects perpendicularly with the Y direction, which is the fin formation direction, and the multiple heat dissipation fins 61 are arranged discretely from each other along the X direction, and the gap areas between the multiple heat dissipation fins 61 become multiple cooling air passage areas 91 or four cooling air passage areas 95.

[0050] An assembly of the multiple cooling air passage regions 91 and the four cooling air passage regions 95 constitutes a first type cooling air passage region provided on the second main surface side of the first type heat sink 5. The multiple cooling air passage regions 91 are classified into multiple first type narrow regions, and the four cooling air passage regions 95 are classified into at least one first type wide region.

[0051] The plurality of heat dissipating fins 61 include four pairs of adjacent modified heat dissipating fins 61X, 61X. The four pairs of modified heat dissipating fins 61X, 61X are classified as at least one pair of modified heat dissipating fins, and all of the fins other than the four pairs of modified heat dissipating fins 61X, 61X are classified as normal heat dissipating fins 61n.

[0052] The four cooling air passage regions 95 classified as at least one type 1 wide region correspond one-to-one to the four pairs of modified heat dissipation fins 61X and 61X. Each of the four cooling air passage regions 95 is a gap region between a corresponding pair of modified heat dissipation fins 61X and 61X among the four pairs of modified heat dissipation fins 61X and 61X. Each of the four cooling air passage regions 95 has a wide fin spacing S5 along the X direction, which is the fin arrangement direction. This wide fin spacing S5 is classified as a type 1 wide spacing.

[0053] In this way, in the first type heat sink 5, which is arranged on the upwind side, which is the inflow side of the air that becomes the cooling air, the wide fin spacing S5 between the four pairs of deformed heat dissipation fins 61X and 61X is dimensioned to be larger than the fin spacing S1 at the design level, rather than due to differences in the fin gaps caused by manufacturing variations.

[0054] Of the multiple heat dissipation fins 61, the remaining heat dissipation fins 61 other than the four pairs of modified heat dissipation fins 61X and 61X are multiple normal heat dissipation fins 61n. The multiple cooling air passage regions 91 are gap regions between adjacent normal heat dissipation fins 61n and 61n, and have a fin spacing S1 along the X direction. This fin spacing S1 is classified as a first-type narrow spacing. Note that the fin spacing S1 is also set between adjacent normal heat dissipation fins 61n and modified heat dissipation fins 61X.

[0055] For the four cooling air passage areas 95 and the plurality of cooling air passage areas 91, the spacing ratio (S5 / S1) of the fin spacing S1 to the wide fin spacing S5 is set to, for example, about two to three times.

[0056] 7, the housing 3 supports the heat sink mounting frame 4 in a manner that accommodates a plurality of heat dissipation fins 61 of the first-class heat sink 5. The heat sink base 51 of the first-class heat sink 5 and the heat sink mounting frame 4 are fixed together with screws or the like.

[0057] 8, the second-class heat sink 6 has a heat sink base 52 and a plurality of heat dissipation fins 62. The plurality of heat dissipation fins 62 are classified as a plurality of second-class heat dissipation fins. Power semiconductor modules M41 to M43 are mounted on a first main surface of the heat sink base 52.

[0058] That is, the second main surface of the metal plate 21 of each of the power semiconductor modules M41 to M43 is bonded to the first main surface of the heat sink base 52 via the TIM material 25, ensuring relatively high thermal conductivity between the second type heat sink 6 and the power semiconductor modules M41 to M43.

[0059] The first main surface of the heat sink base 52 becomes the first main surface of the second-type heat sink 6, and the multiple heat dissipation fins 62 each extend in the -Z direction from the second main surface of the heat sink base 52. Therefore, each of the multiple heat dissipation fins 62 has a second-type formation depth that extends in the formation depth direction (-Z direction) on the side opposite to the first main surface of the heat sink base 52, which is the mounting surface for the second-type semiconductor module. In addition, each of the multiple heat dissipation fins 62 has a second-type formation width that extends in the fin formation direction along the Y direction.

[0060] The multiple heat dissipation fins 62 have a fin arrangement direction in the X direction, which intersects at right angles with the Y direction, which is the fin formation direction, and the multiple heat dissipation fins 62 are arranged discretely from each other along the X direction, and the gap areas between the multiple heat dissipation fins 62 become multiple cooling air passage areas 92.

[0061] An aggregate of the plurality of cooling air passage regions 92 constitutes a second type cooling air passage region provided on the second main surface side of the second type heat sink 6. The plurality of cooling air passage regions 92 are classified into a plurality of second type width regions.

[0062] Each of the cooling air passage areas 92 has a fin spacing S2 along the X direction, which is the fin arrangement direction. This fin spacing S2 is classified as a type 2 width spacing. The fin spacing S2 is set to, for example, approximately the same as the fin spacing S1 of the cooling air passage area 91 on the type 1 heat sink 5 side.

[0063] In this way, the fin spacing S2 of the multiple heat dissipation fins 62 of the second-type heat sink 6 arranged on the downwind side (air outlet side) is configured to be uniform at the design level, excluding differences in fin spacing due to manufacturing variations. However, the spacing of the heat dissipation fins 62 of the second-type heat sink 6 arranged on the downwind side does not necessarily have to be uniform and can be configured freely.

[0064] As described above, the cooling air is blown from the cooling fan 2 along the flow velocity vector 1, so that the cooling air passes through the first-class cooling air passage area below the first-class heat sink 5, and then is supplied to pass through the second-class cooling air passage area below the second-class heat sink 6.

[0065] 8, the housing 3 supports the heat sink mounting frame 4 in a manner that accommodates a plurality of heat dissipation fins 62 of the second-class heat sink 6. The heat sink base 52 of the second-class heat sink 6 and the heat sink mounting frame 4 are fixed together with screws or the like.

[0066] The CC cross-sectional structure of the modified semiconductor device 101s in FIG. 3 is similar to the cross-sectional structure shown in FIG. 7, except that the first-type semiconductor module mounted on the first main surface of the first-type heat sink 5 is replaced from the power semiconductor modules M13 and M14 to the power semiconductor module M1.

[0067] In addition, the D-D cross-sectional structure of the semiconductor device 101s in Figure 3 is similar to the cross-sectional structure shown in Figure 8, except that the second-type semiconductor module mounted on the first main surface of the second-type heat sink 6 is replaced with the power semiconductor module M4 from the power semiconductor modules M41 to M43.

[0068] 9 to 11 are explanatory diagrams showing the cross-sectional structure of the heat sinks HS1 to HS3, and an XYZ Cartesian coordinate system is shown in each of the figures.

[0069] 9, the heat sink HS1 has a heat sink base 53 and a plurality of heat dissipation fins 63 provided on the second main surface side of the heat sink base 53. The heat sink HS1 is manufactured by, for example, extrusion processing.

[0070] 9 may be used as the first-class heat sink 5 and the second-class heat sink 6. However, in the first-class heat sink 5, the fin spacing S1 and the wide fin spacing S5 must be set, and in the second-class heat sink 6, the fin spacing S2 must be set.

[0071] 10, the heat sink HS2 has a heat sink base 54 and a plurality of heat dissipation fins 64 provided on the second main surface side of the heat sink base 54. The plurality of heat dissipation fins 64 have a tapered structure along the formation depth direction, which is the -Z direction. That is, the thickness, which is the formation width in the X direction, of each of the plurality of heat dissipation fins 64 becomes thinner along the depth direction.

[0072] 10 may be used as the first-class heat sink 5 and the second-class heat sink 6. However, in the first-class heat sink 5, the fin spacing S1 and the wide fin spacing S5 must be set, and in the second-class heat sink 6, the fin spacing S2 must be set.

[0073] The heat sink HS2 can be manufactured by, for example, die casting. Aluminum, aluminum alloy, etc. are used as the constituent material of the heat sink HS1 and the heat sink HS2. However, the constituent material is not limited to aluminum, and other constituent materials such as copper may also be used.

[0074] 11 , the heat sink HS3 has a heat sink base 55 and a plurality of heat dissipation fins 65 provided on the second main surface side of the heat sink base 55. The heat sink HS3 shown in FIG. 11 may be used as the first-class heat sink 5 and the second-class heat sink 6. However, in the first-class heat sink 5, the fin spacing S1 and the wide fin spacing S5 must be set, and in the second-class heat sink 6, the fin spacing S2 must be set.

[0075] The heat sink HS3 can be manufactured by, for example, die casting. The heat sink HS3 is made of aluminum, aluminum alloy, or the like. However, the material is not limited to aluminum, and other materials such as copper may also be used.

[0076] The heat sink HS3 is a heat sink manufactured by crimping, and the heat sink base 55 and the plurality of heat dissipation fins 65 are integrated by crimping. The heat sink base 55 of the heat sink HS3 is manufactured by cutting, die-casting, forging, extrusion, or the like, and is made of aluminum or an aluminum alloy.

[0077] The heat sink HS3 has a plurality of heat dissipation fins 65 made of a plate material (rolled material) such as aluminum or an aluminum alloy, and therefore the heat dissipation fins 65 can be easily processed and have good heat dissipation properties.

[0078] In the heat sink HS3, the constituent materials of the heat sink base 55 and the plurality of heat dissipation fins 65 are not limited to the aluminum material described above, and may be a combination of different materials. For example, from the viewpoint of heat dissipation capacity, it is conceivable to make the plurality of heat dissipation fins 65 out of a copper-based plate material, which has a higher thermal conductivity than aluminum-based materials. In this case, the heat dissipation capacity can be improved compared to when the plurality of heat dissipation fins 65 are made out of an aluminum-based material.

[0079] When using a heat sink HS3 that is integrated by crimping, there are no processing constraints (aspect ratio) that arise from casting or extrusion, so the forming height of each of the multiple heat dissipation fins 65 and the distance between adjacent heat dissipation fins 65, 65, etc. can be freely designed, thereby improving the heat dissipation capacity of the heat sink HS3.

[0080] However, the heat sink structure used in the first type heat sink 5 and the second type heat sink 6 is not limited to the heat sinks HS1 to HS3 shown in Figures 9 to 11, and may be other heat sinks made by cutting, forging, etc.

[0081] (Effects) (Consideration of Comparative Technology) The following describes the effects of the semiconductor device 101 and the semiconductor device 101s according to the first embodiment. The effects described below are common to the semiconductor device 101 and the semiconductor device 101s, but for convenience of explanation, the semiconductor device 101 will be described as a representative example.

[0082] 46 to 48 are explanatory diagrams showing the structure of a comparative semiconductor device 201 for comparison with the semiconductor device 101 of the first embodiment. Figures 49 and 50 are explanatory diagrams showing the characteristics of the comparative semiconductor device 201. An XYZ orthogonal coordinate system is depicted in each of Figures 46 to 50.

[0083] FIG. 46 is an explanatory diagram showing a schematic planar structure of the comparative semiconductor device 201. FIG. 47 is an explanatory diagram showing a schematic E-E cross-sectional structure of FIG. 46. FIG. 48 is an explanatory diagram showing a schematic F-F cross-sectional structure of FIG. 46. FIG. 49 is an explanatory diagram showing the temperature distribution of air flowing between the heat dissipation fins of the heat sink of the comparative semiconductor device 201. FIG. 50 is an explanatory diagram showing the temperature of air flowing into the heat sink of the comparative semiconductor device 201 in the form of a contour diagram. In FIG. 50, the temperature distribution of the first type heat sink 7 is shown as air temperature contour TC2.

[0084] The comparative semiconductor device 201 shown in FIGS. 46 to 50 is a power semiconductor device of a general structure having a plurality of power semiconductor modules.

[0085] Hereinafter, the same components as those of the semiconductor device 101 of the first embodiment shown in FIGS. 1, 7 and 8 are denoted by the same reference numerals and description thereof will be omitted, and the description will focus on the parts unique to the comparative semiconductor device 201.

[0086] As shown in Figure 46, in the comparative semiconductor device 201, six power semiconductor modules M11 to M16 are mounted on a first type heat sink 7, and three power semiconductor modules M41 to M43 are mounted on a second type heat sink 8.

[0087] 47 , the first-class heat sink 7 has a heat sink base 56 and a plurality of heat dissipation fins 66. The plurality of heat dissipation fins 66 are classified as a plurality of first-class heat dissipation fins. Power semiconductor modules M13 and M14 are mounted on a first main surface of the heat sink base 56.

[0088] The heat dissipation fins 66 are arranged discretely along the X direction, and the gaps between the heat dissipation fins 66 form the cooling air passage areas 98. The collection of the cooling air passage areas 98 forms the first-class cooling air passage area provided on the second main surface side of the first-class heat sink 7.

[0089] The cooling air passage regions 98 are gap regions between adjacent heat dissipation fins 66 among the heat dissipation fins 66, and have a fin spacing S8 along the X direction. This fin spacing S8 is classified as a first type width spacing.

[0090] 47 , the housing 3 supports the heat sink mounting frame 4 in a manner that accommodates a plurality of heat dissipation fins 66 of the first-class heat sink 7. The heat sink base 56 of the first-class heat sink 7 and the heat sink mounting frame 4 are fixed together with screws or the like.

[0091] In this way, the fin spacing S8 between adjacent fins 66 of the first-class heat sink 7 arranged on the windward side is uniform at the design level, excluding differences in fin spacing due to manufacturing variations. The fin spacing S8 is set to be approximately the same as the fin spacing S1 in the first-class heat sink 5 of the semiconductor device 101, for example.

[0092] 48, the second-class heat sink 8 has a heat sink base 57 and a plurality of heat dissipation fins 67. The plurality of heat dissipation fins 67 are classified as a plurality of second-class heat dissipation fins. Power semiconductor modules M41 to M43 are mounted on a first main surface of the heat sink base 57.

[0093] The plurality of heat dissipation fins 67 are arranged separately from one another along the X direction, and gaps between the plurality of heat dissipation fins 67 form a plurality of cooling air passage regions 94 .

[0094] An aggregate of the plurality of cooling air passage regions 94 constitutes a second type cooling air passage region provided on the second main surface side of the second type heat sink 8. The plurality of cooling air passage regions 94 are classified into a plurality of second type width regions.

[0095] Each of the cooling air passage areas 94 has a fin spacing S4 along the X direction, which is the fin arrangement direction. This fin spacing S4 is classified as a second type of width spacing.

[0096] In this way, the fin spacing S4 between adjacent fins 67 of the second-class heat sink 8 arranged on the downwind side is uniform at the design level, excluding differences in fin spacing due to manufacturing variations. The fin spacing S4 is set to be approximately the same as the fin spacing S1 in the first-class heat sink 5 of the semiconductor device 101 and the fin spacing S8 in the first-class heat sink 7, for example.

[0097] 48 , the housing 3 supports the heat sink mounting frame 4 in a manner that accommodates a plurality of heat dissipation fins 67 of the second-class heat sink 8. The heat sink base 57 of the second-class heat sink 8 and the heat sink mounting frame 4 are fixed together with screws or the like.

[0098] When the conventional comparative semiconductor device 201 having such a configuration is operating, the semiconductor elements 16 in each of the power semiconductor modules M11 to M16 generate heat, and the semiconductor elements 16 in each of the power semiconductor modules M41 to M43 also generate heat.

[0099] As shown in Figure 49, heat generated from the multiple semiconductor elements 16 in each of the power semiconductor modules M11 and M12 is dissipated from the first type heat sink 7 directly below, causing the temperature of the cooling air flowing into each of the power semiconductor modules M13 and M14 to rise.

[0100] Similarly, heat generated from the multiple semiconductor elements 16 in each of the power semiconductor modules M13 and M14 is dissipated from the first-class heat sink 7 directly below, further increasing the temperature of the cooling air flowing into each of the power semiconductor modules M15 and M16.

[0101] Furthermore, since the heat generated by the multiple semiconductor elements 16 in each of the power semiconductor modules M15 and M16 is dissipated from the first-class heat sink 7 directly below, the temperature of the cooling air flowing into each of the power semiconductor modules M41 to M43 increases even further.

[0102] The width in the X direction of each of the air flow velocity vectors F1 to F3 shown in Fig. 49 indicates the amount of heat. As shown in Fig. 49, in the comparative semiconductor device 201, the amount of heat of the air flow velocity vector F3 before it reaches the second-type heat sink 8 is considerably large.

[0103] In this way, due to heat generated by the multiple semiconductor elements 16 of each of the power semiconductor modules M15 and M16 mounted on the first type heat sink 7 located on the windward side, which is the inflow side of the cooling air, the cooling air whose temperature has risen is located on the outlet side of the air and flows into the second type heat sink 8 mounted with the power semiconductor modules M41 to M43.

[0104] Under such circumstances, the second-type heat sink 8 cannot suppress the temperature rise of the multiple semiconductor elements 16 in each of the power semiconductor modules M41 to M43, which causes the power semiconductor modules M41 to M43 to reach a high temperature state.

[0105] 50, the comparative semiconductor device 201 has a problem in that the air temperature of the cooling air flowing into the second-class heat sink 8 becomes quite high. Note that in FIG. 50, the higher the air temperature, the darker the black color becomes.

[0106] Hereinafter, when each of the power semiconductor modules M11 to M16 and the power semiconductor modules M41 to M43 is generally referred to, it will be simply referred to as a "power semiconductor module MP."

[0107] 50, in a comparative semiconductor device 201 in which multiple power semiconductor modules MP are mounted along the +Y direction, which is the direction of flow velocity vector 1, air whose temperature has risen due to heat dissipation from one power semiconductor module MP arranged on the upwind side flows into another power semiconductor module MP arranged on the downwind side. Therefore, due to thermal interference between the power semiconductor modules MP, MP via the first-class heat sink 7 in the comparative semiconductor device 201, the temperature of the multiple semiconductor elements 16 in the downwind power semiconductor module MP may rise and exceed the allowable temperature.

[0108] Therefore, in order to prevent the temperature of the semiconductor element 16 from exceeding the allowable temperature during operation of the comparative semiconductor device 201, it was necessary to increase the size of the first-class heat sink 7.

[0109] In a typical comparative semiconductor device 201, air inflow and exhaust are predominantly from the inflow and outlet sides, with very little air inflow and exhaust from sides other than the inflow and outlet sides. In particular, in power semiconductor devices that require waterproofing and dustproofing, such as IP (International Protection) compliance, there is no air inflow or exhaust from the sides. For this reason, it is important to have a structure that allows air with a small temperature rise inside the housing 3 to flow into the heat sink of the power semiconductor module MP located on the downwind side (air outlet side).

[0110] 12 to 14 are explanatory diagrams showing the cooling effect of the semiconductor device 101 according to the first embodiment. An XYZ orthogonal coordinate system is depicted in each of Figs.

[0111] Fig. 12 is an explanatory diagram showing the temperature distribution of air flowing between the heat dissipation fins of the heat sink of the semiconductor device 101. Figs. 13 and 14 are explanatory diagrams showing the temperature of air flowing into the heat sink of the semiconductor device 101 in the form of a contour diagram, with Fig. 13 showing the temperature distribution of the first-class heat sink 5 as an air temperature contour TC1, and Fig. 14 showing the temperature distributions of the first-class heat sink 5 and the second-class heat sink 6 as an air temperature contour TC1B. Note that in Figs. 13 and 14, the higher the air temperature, the darker the black color.

[0112] As described above, the first-class heat sink 5 in the semiconductor device 101 of the first embodiment has four pairs of modified heat dissipation fins 61X and 61X. The four cooling air passage areas 95, which are gap areas between the four modified heat dissipation fins 61X and 61X, each have a wide fin spacing S5, which is set wider than the fin spacing S1. Therefore, during operation, the semiconductor device 101 can effectively suppress a temperature rise of the cooling air when it reaches the multiple heat dissipation fins 62 of the second-class heat sink 6.

[0113] As in the comparative semiconductor device 201, as shown in FIG. 12, heat generated by the multiple semiconductor elements 16 in each of the power semiconductor modules M11 and M12 is dissipated from the first-class heat sink 5 directly below, causing the temperature of the cooling air flowing into the power semiconductor modules M13 and M14 to rise.

[0114] Similarly, the temperature of the cooling air flowing into the power semiconductor modules M15 and M16 rises because heat generated from the multiple semiconductor elements 16 in each of the power semiconductor modules M13 and M14 is dissipated from the first-class heat sink 5 directly below. Furthermore, the temperature of the air flowing into the power semiconductor modules M41 to M43 rises because heat generated from the multiple semiconductor elements 16 in each of the power semiconductor modules M15 and M16 is dissipated from the first-class heat sink 5 directly below.

[0115] In this way, the heat generated by the multiple semiconductor elements 16 of each of the power semiconductor modules M11 to M16 mounted on the first type heat sink 5 on the upwind side, which is the air inlet side that serves as cooling air, causes the heated air to flow into the second type heat sink 6 on the downwind side, which is the air outlet side and which is mounted with the power semiconductor modules M41 to M43.

[0116] 12, the width in the X direction of each of the air flow velocity vectors F1 to F3 and the air flow velocity vector FX1 indicates the amount of heat. As shown in the figure, in the multiple cooling air passage areas 91, the amount of heat of the air flow velocity vector F3 before it reaches the second-class heat sink 6 is quite large.

[0117] In the semiconductor device 101 of embodiment 1, in the first type heat sink 5 arranged on the upwind side, the wide fin spacing S5 in the four cooling air passage areas 95 is set larger than the fin spacing S1 in the multiple cooling air passage areas 91.

[0118] Therefore, by setting the wide fin spacing S5 in each of the four cooling air passing regions 95 to be sufficiently wider than the fin spacing S1, it is possible to minimize the temperature rise of the cooling air along the flow velocity vector 1 in the four cooling air passing regions 95. This is because, in the cooling air passing regions 95 having the relatively wide fin spacing S5, the coefficient of heat transfer from the surface of the modified heat dissipation fins 61X to the air is small and the amount of heat dissipation from the modified heat dissipation fins 61X is small, so the amount of rise in the air temperature of the cooling air passing through the cooling air passing region 95 is minimal.

[0119] For this reason, the four cooling air passage regions 95 can be kept in a relatively low temperature region tc11, as shown in Figures 13 and 14. That is, as shown in Figure 12, in the air flow velocity vector FX in the four cooling air passage regions 95, the amount of heat is kept below a certain value, so that cooling air having a relatively low temperature air flow velocity vector FX can be supplied to the second-class heat sink 6.

[0120] Therefore, as shown in Figure 14, a relatively low temperature region tc12 can be provided even in the second type heat sink 6 on the downwind side (air outlet side), so the temperature of the multiple semiconductor elements 16 in each of the power semiconductor modules M41 to M43 can be kept below the allowable temperature without increasing the size of the first type heat sink 5 and the second type heat sink 6.

[0121] As a result, the sizes of the first and second type heat sinks 5 and 6 can be minimized, and the semiconductor device 101 of the first embodiment can be made smaller.

[0122] As described above, the first-class heat sink 5 is on the upwind side and the second-class heat sink 6 is on the downwind side with respect to the cooling air supplied from the cooling fan 2. The first-class heat sink 5 in the semiconductor device 101 of the first embodiment has four cooling air passing regions 95, each set to the wide fin spacing S5, and therefore, the temperature rise of the cooling air passing through the cooling air passing regions 95 classified as the first-class wide regions can be minimized, and relatively low-temperature cooling air can be made to flow into the plurality of heat dissipation fins 62 of the second-class heat sink 6.

[0123] Regarding the above effect, a numerical analysis was performed on the spacing ratio (S5 / S1) between the fin spacing S1 and the wide fin spacing S5, and it was confirmed that when the spacing ratio (S5 / S1) was set to 3, an effect of reducing the temperature rise of the cooling air by 3°C when it reached the multiple heat dissipation fins 62 was obtained. Therefore, from the above numerical analysis results, it is inferred that a beneficial effect of suppressing the temperature rise of the cooling air can be obtained by setting the wide fin spacing S5 to be between two and three times the fin spacing S1 {2≦(S5 / S1)≦3}.

[0124] Therefore, in the semiconductor device 101 of the first embodiment, the cooling air blown from the cooling fan 2 can suppress a temperature rise in the plurality of heat dissipation fins 62 in addition to the plurality of heat dissipation fins 61. Therefore, the first-class heat sink 5 can suppress a temperature rise during operation of the power semiconductor modules M11 to M16, and the second-class heat sink 6 can suppress a temperature rise during operation of the power semiconductor modules M41 to M43.

[0125] In other words, in the semiconductor device 101 of embodiment 1, in order to suppress the temperature rise during operation of the power semiconductor modules M11 to M16 and M41 to M43, there is no need to increase the size of the power semiconductor modules M11 to M16 and M41 to M43, as well as the first type heat sink 5 and the second type heat sink 6.

[0126] As a result, the semiconductor device 101 of the first embodiment has a cooling function for the power semiconductor module MP by the first and second heat sinks 5 and 6, and can also be made smaller in size.

[0127] Furthermore, by setting the fin spacing S2 of the cooling air passage area 92 in the second-type heat sink 6 of the semiconductor device 101 to be approximately the same as the fin spacing S1 of the cooling air passage area 91 of the first-type heat sink 5, the heat dissipation properties of the second-type heat sink 6 can be maintained good.

[0128] The semiconductor device 101 of embodiment 1 has a configuration in which four cooling air passage areas 95 are set using four pairs of deformed heat dissipation fins 61X and 61X, so that the temperature rise of the cooling air passing through the four cooling air passage areas 95 can be minimized and the cooling air can flow into the multiple heat dissipation fins 62 of the second type heat sink 6.

[0129] Therefore, the semiconductor device 101 of the first embodiment has a cooling function by the first and second heat sinks 5 and 6, and can be made smaller in size.

[0130] In the semiconductor device 101 of embodiment 1, four cooling air passage areas 95 are shown as at least one first type wide area, but the above-mentioned effect can be achieved if there is at least one cooling air passage area 95.

[0131] In addition, the semiconductor device 101 of embodiment 1 includes a heat sink mounting frame 4, which is a mounting plate, and a housing 3, and has a cooling fan 2 that blows cooling air with the flow velocity vector 1 as the blowing direction to realize a cooling air supply structure.

[0132] Therefore, the semiconductor device 101 of the first embodiment can obtain a structure in which the first-class heat sink 5, the second-class heat sink 6, the power semiconductor modules M11 to M16, and the power semiconductor modules M41 to M43 are integrated by the heat sink mounting frame 4 and the housing 3. Then, the cooling fan 2 can stably supply cooling air having a flow velocity vector 1.

[0133] In addition, when the heat generation amount of the power semiconductor modules M11 to M16 and the power semiconductor modules M41 to M43 is small, it is possible to obtain the above-mentioned effects by adopting a cooling air supply structure having the characteristic of setting the flow of the air that becomes the cooling air in a direction that coincides with the flow velocity vector 1 without providing a cooling fan 2.

[0134] (Manufacturing Method) The semiconductor device 101 of the first embodiment can be manufactured by the following steps (a) to (c).

[0135] Step (a) is a step of fixing the heat sink mounting frame 4, which serves as a mounting plate, to the housing 3.

[0136] Step (b) is a step of mounting the first type heat sink 5 and the second type heat sink 6 on the heat sink mounting frame 4 in such a manner that the plurality of heat dissipation fins 61 and the plurality of heat dissipation fins 62 are housed within the housing 3 .

[0137] Step (c) is a step of mounting the power semiconductor modules M11 to M16 on the first main surface of the first-class heat sink 5, and mounting the power semiconductor modules M41 to M43 on the first main surface of the second-class heat sink 6.

[0138] The semiconductor device 101 manufactured by the semiconductor device manufacturing method of embodiment 1 does not require the power semiconductor modules M11 to M16 and M41 to M43 and the first and second type heat sinks 5 and 6 to be enlarged in order to suppress the temperature rise during operation of the power semiconductor modules M11 to M16 and M41 to M43.

[0139] As a result, the semiconductor device 101 manufactured by the manufacturing method of the first embodiment has a cooling function for the power semiconductor modules M11 to M16 and M41 to M43, and can also be made smaller.

[0140] 15 is an explanatory diagram schematically illustrating a planar configuration of a semiconductor device 102 according to a second embodiment of the present disclosure. An XYZ Cartesian coordinate system is depicted in Fig. 15. The semiconductor device 102 according to the second embodiment is a power semiconductor device having a plurality of power semiconductor modules.

[0141] Hereinafter, the same components as those in the semiconductor device 101 of the first embodiment shown in FIG. 1 are denoted by the same reference numerals and description thereof will be omitted, and the description will focus on the features of the semiconductor device 102 of the second embodiment.

[0142] As shown in FIG. 15, the semiconductor device 102 of the second embodiment has a first-type heat sink 5B and a second-type heat sink 6B, and the first and second-type heat sinks 5B and 6B are attached to the heat sink mounting frame 4, which is an attachment plate, in the same manner as in the first embodiment.

[0143] The semiconductor device 102 of the second embodiment has six power semiconductor modules M11 to M16 mounted on the first main surface of the first-type heat sink 5B, and three power semiconductor modules M41 to M43 mounted on the second main surface of the second-type heat sink 6B.

[0144] Fig. 16 is an explanatory diagram showing a schematic planar structure of the first and second type heat sinks 5B and 6B in the semiconductor device 102 of the second embodiment. Fig. 17 is an explanatory diagram showing a schematic cross-sectional structure of the basic configuration of the semiconductor device 102. Fig. 17 shows the G-G cross-sectional structure of Fig. 16. An XYZ Cartesian coordinate system is depicted in each of Figs. 16 and 17.

[0145] 16. In FIG. 16, the planar structures of the plurality of heat dissipation fins provided on the first-type heat sink 5B and the plurality of heat dissipation fins provided on the second-type heat sink 6B are shown so as to be visually recognizable.

[0146] As shown in Figures 16 and 17, the first type heat sink 5B includes a heat sink base 5B0, a plurality of normal heat dissipation fins 5B1, and four notched heat dissipation fins 5B2, and the second type heat sink 6B includes a heat sink base 6B0 and a plurality of heat dissipation fins 6B1.

[0147] With respect to the first-class heat sink 5B, the gap regions between adjacent normal heat dissipation fins 5B1 among the plurality of normal heat dissipation fins 5B1 are the plurality of cooling air passage regions 91, and the spacing along the X direction, which is the fin arrangement direction, of the cooling air passage regions 91 is the fin spacing S1. The plurality of cooling air passage regions 91 are classified into a plurality of first-class narrow regions, and the fin spacing S1 is classified into the first-class narrow spacing.

[0148] The four notched fins 5B2 are classified into at least one notched fin. A pair of normal fins 5B1 adjacent to each of the four notched fins 5B2 in the X direction, which is the fin arrangement direction, is defined as four pairs of adjacent fins 5B1s and 5B1s. The four pairs of adjacent fins 5B1s and 5B1s are classified into at least one pair of adjacent fins.

[0149] 17, each of the four notched heat dissipation fins 5B2 has a normal region R51 having a normal depth DT1 in the −Z direction, which is the formation depth direction, and a modified region R52 having a modified depth DT2. On the other hand, each of the multiple normal heat dissipation fins 5B1 has only the constant normal depth DT1.

[0150] In this way, the notched heat dissipating fin 5B2 includes the normal depth DT1 and the modified depth DT2 as the first-type forming depth, while the normal heat dissipating fin 5B1 has only the normal depth DT1 as the first-type forming depth.

[0151] Because the deformation depth DT2 is shallower than the normal depth DT1, {DT1 > DT2} holds. Therefore, in the notched heat dissipation fin 5B2, the region from the deformation depth DT2 to the normal depth DT1 in the deformation region R52 becomes the partially cutout region 27 where nothing is formed. In other words, the partially cutout region 27 that becomes the notched region is the empty region from the deformation depth DT2 to the normal depth DT1 in the deformation region R52 of each of the four notched heat dissipation fins 5B2.

[0152] The gap regions between each of the four pairs of adjacent heat dissipation fins 5B1s and 5B1s form four cooling air passage regions 96, which are classified as at least one type 1 wide region. Each of the four cooling air passage regions 96 includes a region between the adjacent heat dissipation fins 5B1s and 5B1s via a partial cutout region 27.

[0153] The distance between each of the four pairs of adjacent heat dissipation fins 5B1s and 5B1s in the X direction is a wide fin distance S6. This wide fin distance S6 is classified as a first type wide distance.

[0154] As described above, in the semiconductor device 102 of the second embodiment, the first-class heat sink 5B has an assembly of a plurality of cooling air passage areas 91 and four cooling air passage areas 96 as the first-class cooling air passage area.

[0155] The first-class heat sink 5B in the semiconductor device 102 of the second embodiment has four notched heat dissipation fins 5B2. Four cooling air passage areas 96, including gap areas via the four pairs of adjacent heat dissipation fins 5B1s and the partial cutout areas 27 of the fins 5B1s, each have a wide fin spacing S6, which is set wider than the fin spacing S1. Therefore, during operation of the semiconductor device 102, it is possible to effectively suppress a rise in temperature of the cooling air supplied from the cooling fan 2 when it reaches the multiple heat dissipation fins 6B1.

[0156] The first-class heat sink 5B includes a plurality of normal fins 5B1 and four notched fins 5B2, and the fins are spaced apart at a uniform fin spacing S1. Therefore, in the semiconductor device 102 of the second embodiment, the fin spacing S6 in the cooling air passage area 96 is twice the fin spacing S1 plus the thickness of the notched fins 5B2, which is the width of the fins in the X direction.

[0157] Since the semiconductor device 102 of embodiment 2 has the structure shown in Figures 15 to 17, the temperature rise of the cooling air passing through the cooling air passage area 96, which includes the area through the partial cutout area 27 between each of the four pairs of adjacent heat dissipation fins 5B1s and 5B1s, can be minimized, and the cooling air can be allowed to flow into multiple heat dissipation fins 6B1.

[0158] Therefore, like the semiconductor device 101 of the first embodiment, the semiconductor device 102 of the second embodiment has the cooling function for the power semiconductor modules M11 to M16 and the power semiconductor modules M41 to M43, and can also be made smaller.

[0159] In semiconductor device 102 of the second embodiment, the empty area from deformation depth DT2 to normal depth DT1 of each of four notched heat dissipation fins 5B2 is defined as partial cutout region 27. In order to suppress a temperature rise in the cooling air passing through cooling air passage region 96, it is desirable to set the length of partial cutout region 27 in the Y direction to, for example, at least one-third of the formation width in the Y direction of normal heat dissipation fin 5B1.

[0160] Therefore, four cooling air passage areas 96 can be formed from a general structure in which the spacing between multiple heat dissipation fins, including multiple normal heat dissipation fins 5B1 and four notched heat dissipation fins 5B2, is set to a uniform fin spacing S1.

[0161] The basic configuration of the semiconductor device 102 shown in Figures 15 to 17 is such that, in order to provide a partial cutout region 27, the four cutout heat dissipation fins 5B2 are formed in a combination configuration of a deformation region R52 of a deformation depth DT2 and a normal region R51 of a normal depth DT1.

[0162] Fig. 18 is a cross-sectional view schematically showing the cross-sectional structure of a modified example of the semiconductor device 102. Fig. 18 shows the cross-sectional structure taken along line G-G in Fig. 16. An XYZ orthogonal coordinate system is depicted in Fig. 18. The following describes the modified example of the semiconductor device 102, focusing on the differences from the cross-sectional structure of the basic configuration of the semiconductor device 101 shown in Fig. 17.

[0163] As shown in FIGS. 16 and 18, a first type heat sink 5BB in this modification includes a heat sink base 5B0, a plurality of normal heat dissipating fins 5B1, and four notched heat dissipating fins 5B3.

[0164] In the modified example of the semiconductor device 102, the four notched heat dissipation fins 5B3 are classified into at least one notched heat dissipation fin. The normal heat dissipation fins 5B1 and 5B1 adjacent to each of the four notched heat dissipation fins 5B3 in the X direction, which is the fin arrangement direction, are defined as four pairs of adjacent heat dissipation fins 5B1s and 5B1s. The four pairs of adjacent heat dissipation fins 5B1s and 5B1s are classified into at least one pair of adjacent heat dissipation fins. Meanwhile, each of the multiple normal heat dissipation fins 5B1 has a normal depth DT1.

[0165] 18, each of the four notched heat dissipation fins 5B3 is formed only with a deformation region R53 having a deformation depth DT2. Therefore, the first-type forming depth of the notched heat dissipation fins 5B3 is only the deformation depth DT2.

[0166] Because deformation depth DT2 is shallower than normal depth DT1, {DT1 > DT2} holds. Therefore, in notched heat dissipation fin 5B3, the region from deformation depth DT2 to normal depth DT1 in deformation region R53 becomes notched region 28, where nothing is formed. In other words, notched region 28 is an empty region from deformation depth DT2 to normal depth DT1 in deformation region R53, which is the entire region of each of the four notched heat dissipation fins 5B3.

[0167] The gap regions between each of the four pairs of adjacent heat dissipation fins 5B1s and 5B1s form four cooling air passage regions 96 in the modified example, and are classified as at least one type 1 wide region. Each of the four cooling air passage regions 96 includes an area between the adjacent heat dissipation fins 5B1s and 5B1s via the cutout region 28. The spacing between each of the four pairs of adjacent heat dissipation fins 5B1s and 5B1s in the X direction is the wide fin spacing S6, which is classified as the type 1 wide spacing.

[0168] Since the modified example of the semiconductor device 102 of the second embodiment has the configuration shown in Figures 15, 16 and 18, the temperature rise of the cooling air passing through the cooling air passage area 96 including the area through the cutout area 28 between each of the four pairs of adjacent heat dissipation fins 5B1s and 5B1s can be minimized and the cooling air can be allowed to flow into the multiple heat dissipation fins 6B1.

[0169] Therefore, the modified example of the semiconductor device 102 of the second embodiment has the same cooling function for the power semiconductor modules M11 to M16 and the power semiconductor modules M41 to M43 as the basic configuration of the second embodiment, and can also achieve miniaturization of the device.

[0170] In the modified semiconductor device 102, the empty area from the deformation depth DT2 to the normal depth DT1 of each of the four notched heat dissipation fins 5B3 is defined as a notched area 28.

[0171] Therefore, four cooling air passage areas 96 can be formed from a general structure in which the spacing between multiple heat dissipation fins, including multiple normal heat dissipation fins 5B1 and four notched heat dissipation fins 5B3, is set to a uniform fin spacing S1.

[0172] The basic configuration of the semiconductor device 102 is such that the four notched heat dissipation fins 5B3 are formed to have only deformation regions R53 with a deformation depth DT2 in order to provide the notched regions 28.

[0173] Therefore, in the second embodiment, the cutout region 28 of the modified example can be fabricated more easily than the partial cutout region 27 of the basic configuration.

[0174] <Third Embodiment> Fig. 19 is an explanatory diagram schematically showing the planar structures of first and second type heat sinks 5C and 6C in a semiconductor device 103 according to a third embodiment. Fig. 20 is an explanatory diagram schematically showing the H-H cross-sectional structure of the semiconductor device 103 in Fig. 19. An XYZ orthogonal coordinate system is depicted in each of Figs. 19 and 20.

[0175] 19. Note that FIG. 19 shows the planar structures of the plurality of heat dissipation fins provided on the first-type heat sink 5C and the plurality of heat dissipation fins provided on the second-type heat sink 6C so that they can be visually recognized.

[0176] The semiconductor device 103 of the third embodiment is characterized by having a first-class heat sink 5C and a second-class heat sink 6C. The planar configuration of the semiconductor device 103 is the same as that of the semiconductor device 101 of the first embodiment, except that the first and second-class heat sinks 5 and 6 are replaced with first and second-class heat sinks 5C and 6C.

[0177] As shown in Figures 19 and 20, the first type heat sink 5C includes a heat sink base 5C0, a plurality of normal heat dissipation fins 5C1, and four notched heat dissipation fins 5C2, and the second type heat sink 6C includes a heat sink base 6C0 and a plurality of heat dissipation fins 6C1.

[0178] With respect to the first-class heat sink 5C, the gap between adjacent normal heat dissipation fins 5C1 among the plurality of normal heat dissipation fins 5C1 is a cooling air passage region 91, and the spacing along the X direction, which is the fin arrangement direction of the cooling air passage region 91, is a fin spacing S1. The cooling air passage region 91 is classified as a first-class narrow region, and the fin spacing S1 is classified as a first-class narrow spacing.

[0179] The four notched fins 5C2 are classified into at least one notched fin. The adjacent normal fins 5C1 and 5C1 in the X direction, which is the fin arrangement direction, for each of the four notched fins 5C2 are defined as four pairs of adjacent fins 5C1s and 5C1s. The four pairs of adjacent fins 5C1s and 5C1s are classified into at least one pair of adjacent fins.

[0180] As shown in Figure 20, each of the multiple normal heat dissipation fins 5C1 has a normal width WT1 in the Y direction, which is the fin formation direction, and each of the four notched heat dissipation fins 5C2 has a deformed width WT2 in the Y direction, where the deformed width WT2 is shorter than the normal width WT1, satisfying {WT2 < WT1}.

[0181] As described above, the notched heat dissipation fin 5C2 of the semiconductor device 102 according to the third embodiment has a first-type formation width including the normal width WT1 and the modified width WT2, and the modified width WT2 is narrower than the normal width WT1.

[0182] With respect to the notched heat dissipation fins 5C2, the empty area from the deformed width WT2 to the normal width WT1 of each of the four notched heat dissipation fins 5C2 is defined as the notched region 29. That is, in the Y direction, which is the fin formation direction, the notched region 29 is the non-fin region where the normal heat dissipation fins 5C1 are present but the notched heat dissipation fins 5C2 are not present.

[0183] The gap regions between each of the four pairs of adjacent heat dissipation fins 5C1s and 5C1s form cooling air passage regions 97, which are classified as at least one type 1 wide region. The spacing between each of the four pairs of adjacent heat dissipation fins 5C1s and 5C1s in the X direction is fin spacing S7, which is classified as a type 1 wide spacing. Each of the four cooling air passage regions 97 includes a region between the adjacent heat dissipation fins 5C1s and 5C1s via the cutout region 29.

[0184] In this way, in the first-class heat sink 5C in the semiconductor device 103 of the third embodiment, the assembly of the plurality of cooling air passage areas 91 and the four cooling air passage areas 97 constitutes the first-class cooling air passage area.

[0185] The first-class heat sink 5B in the semiconductor device 103 of the third embodiment has four notched heat dissipation fins 5C2. Four cooling air passage areas 97, including four pairs of adjacent heat dissipation fins 5C1s and the gap areas formed by the notched areas 28 of the fins 5C1s, each have a wide fin spacing S7, which is wider than the fin spacing S1. Therefore, during operation, the semiconductor device 103 can effectively suppress a temperature rise in the cooling air supplied from the cooling fan 2 to the multiple heat dissipation fins 6C1.

[0186] The first-class heat sink 5C includes a plurality of regular fins 5C1 and four notched fins 5C2, and the fins are spaced apart at a uniform fin spacing S1. Therefore, in the semiconductor device 103 of the third embodiment, the fin spacing S7 is twice the fin spacing S1 plus the thickness of the notched fins 5C2.

[0187] Since the semiconductor device 103 of embodiment 3 has the structure shown in Figures 19 and 20, the temperature rise of the cooling air passing through four cooling air passage areas 97, each of which includes an area through the cutout area 29 between each of four pairs of adjacent heat dissipation fins 5C1s and 5C1s, can be minimized, and cooling air can be allowed to flow into multiple heat dissipation fins 6C1.

[0188] Therefore, the semiconductor device 103 of the third embodiment, like the first and second embodiments, has the cooling function for the power semiconductor modules M11 to M16 and the power semiconductor modules M41 to M43, and can also be made smaller.

[0189] In order to obtain the above-mentioned cooling function, it is desirable to ensure that the area ratio of the notched region 29 to the normal heat dissipating fin 5C1 is 1 / 4 or more.

[0190] In the semiconductor device 103 of the third embodiment, the fin-free region of each of the four notched heat dissipation fins 5C2 is defined as a notched region 29.

[0191] Therefore, four cooling air passage areas 97 can be formed from a general structure in which the spacing between multiple heat dissipation fins, including multiple normal heat dissipation fins 5C1 and four notched heat dissipation fins 5C2, is set to a uniform fin spacing S1.

[0192] 21 is an explanatory diagram schematically illustrating a planar configuration of a semiconductor device 104 according to a fourth embodiment of the present disclosure. The semiconductor device 104 according to the fourth embodiment is a power semiconductor device having a plurality of power semiconductor modules. An XYZ Cartesian coordinate system is depicted in FIG.

[0193] Hereinafter, the same components as those of the semiconductor device 101 of the first embodiment shown in FIG. 1 are denoted by the same reference numerals and description thereof will be omitted, and the description will focus on the features of the semiconductor device 104 of the fourth embodiment.

[0194] As shown in FIG. 21, the semiconductor device 104 of the fourth embodiment has first-type heat sinks H51 to H56 and second-type heat sinks H61 to H64, and the first and second-type heat sinks 5 and 6 are attached to a heat sink mounting frame 4D, which is an attachment plate.

[0195] As described above, the semiconductor device 104 of the fourth embodiment has the first-class heat sinks H51 to H56 as a plurality of first-class heat sinks, and has the second-class heat sinks H61 to H64 as a plurality of second-class heat sinks.

[0196] The heat sink mounting frame 4D has six openings and four openings (not shown), and first-class heat sinks H51 to H56 are attached by fitting into the six openings, respectively, and second-class heat sinks H61 to H64 are attached by fitting into the four openings, respectively. The heat sink mounting frame 4D is fixed to the top of the housing 3.

[0197] The power semiconductor modules M51 to M56, which are the plurality of first-type semiconductor modules, correspond one-to-one to the first-type heat sinks H51 to H56, which are the plurality of first-type heat sinks. Therefore, the power semiconductor module M5i is mounted on the first main surface of the first-type heat sink H5i (i = 1 to 6).

[0198] The power semiconductor modules M61 to M64, which are the plurality of second-type semiconductor modules, correspond one-to-one to the second-type heat sinks H61 to H64, which are the plurality of second-type heat sinks. Therefore, the power semiconductor module M6j is mounted on the first main surface of the second-type heat sink H6j (j = 1 to 4).

[0199] In the fourth embodiment, the first main surface of each of the first-type heat sinks H51 to H56 serves as a mounting surface for a first-type semiconductor module, and the first main surface of each of the second-type heat sinks H61 to H64 serves as a mounting surface for a second-type semiconductor module.

[0200] In the semiconductor device 104 of the fourth embodiment, with respect to the flow velocity vector 1, the first type heat sinks H51 to H56 are located on the upwind side, and the second type heat sinks H61 to H64 are located on the downwind side.

[0201] Thus, the semiconductor device 104 of the fourth embodiment includes, as its main components, power semiconductor modules M51 to M56, power semiconductor modules M61 to M64, first-class heat sinks H51 to H56, second-class heat sinks H61 to H64, a heat sink mounting frame 4D, a housing 3, and a cooling fan 2.

[0202] The power semiconductor modules M51 to M56 and the power semiconductor modules M61 to M64 each have the cross-sectional structure shown in, for example, Figures 4 to 6. The heat sink mounting frame 4D, which is the mounting plate, and the housing 3 may be configured as separate members or as an integrated component.

[0203] Figures 22 and 23 are explanatory diagrams schematically showing the cross-sectional structure of the semiconductor device 104 of the fourth embodiment shown in Figure 21. Figure 22 shows the I-I cross section of Figure 21, and Figure 23 shows the J-J cross section of Figure 21. An XYZ orthogonal coordinate system is depicted in each of Figures 22 and 23.

[0204] 22, the first type heat sink H53 has a heat sink base 530 and a plurality of heat dissipation fins 531, and the first type heat sink H54 has a heat sink base 540 and a plurality of heat dissipation fins 541. The plurality of heat dissipation fins 531 and the plurality of heat dissipation fins 541 are classified as a plurality of first type heat dissipation fins.

[0205] The power semiconductor module M53 is mounted on the first main surface of the first-class heat sink H53, and the power semiconductor module M54 is mounted on the first main surface of the first-class heat sink H54.

[0206] The first-class heat sink H53 has the same structure as each of the first-class heat sinks H51, H52, H54 to H56, and the power semiconductor module M53 has the same structure as each of the power semiconductor modules M51, M52, M54 to M56. In the following, the first-class heat sink H53 and the power semiconductor module M53 will be described as representative examples.

[0207] Between the first-type heat sinks H53 and H54, the heat sink base 530 corresponds to the heat sink base 540, and the plurality of heat dissipation fins 531 (531n, 531X) corresponds to the plurality of heat dissipation fins 541 (541n, 541X).

[0208] The second main surface of the metal plate 21 of the power semiconductor module M53 is bonded to the first main surface of the first-class heat sink H53 via the TIM material 25. The TIM material 25 ensures relatively high thermal conductivity between the first-class heat sink H53 and the power semiconductor module M53.

[0209] The first main surface of the heat sink base 530 becomes the first main surface of the first-type heat sink H53, and the multiple heat dissipation fins 531 each extend in the -Z direction from the second main surface of the first-type heat sink H53. Therefore, the multiple heat dissipation fins 531 each have a first-type formation depth that extends in the formation depth direction (-Z direction) on the opposite side from the first main surface of the first-type heat sink H53, which is the mounting surface for the first-type semiconductor module. In addition, the multiple heat dissipation fins 531 each have a first-type formation width that extends in the fin formation direction along the Y direction.

[0210] The multiple heat dissipation fins 531 have a fin arrangement direction in the X direction, which intersects at right angles with the Y direction, which is the fin formation direction, and the multiple heat dissipation fins 531 are arranged discretely from each other along the X direction, and the gap areas between the multiple heat dissipation fins 531 become multiple cooling air passage areas 111 or two cooling air passage areas 115.

[0211] The assembly of the multiple cooling air passage regions 111 and the two cooling air passage regions 115 constitutes a first cooling air passage region provided on the second main surface side of the first heat sink H53. The multiple cooling air passage regions 111 are classified into multiple first narrow regions, and the two cooling air passage regions 115 are classified into at least one first wide region.

[0212] The plurality of heat dissipating fins 531 each include two pairs of adjacent modified heat dissipating fins 531X and 531X. The two pairs of modified heat dissipating fins 531X and 531X are classified as at least one pair of modified heat dissipating fins, and all of the heat dissipating fins 531 other than the two pairs of modified heat dissipating fins 531X and 531X are classified as a plurality of normal heat dissipating fins 531n.

[0213] The two cooling air passage regions 115 are classified as at least one type 1 wide region and correspond one-to-one to the two pairs of modified heat dissipation fins 531X and 531X. Each of the two cooling air passage regions 115 is a gap region between a corresponding pair of the two pairs of modified heat dissipation fins 531X and 531X. Each of the two cooling air passage regions 115 has a wide fin spacing S15 along the X direction, which is the fin arrangement direction. This wide fin spacing S15 is classified as a type 1 wide spacing.

[0214] In this way, in the first type heat sink H53, which is arranged on the upwind side, which is the inflow side of the air that becomes the cooling air, the wide fin spacing S15 between the two pairs of deformed heat dissipation fins 531X and 531X is dimensioned to be larger than the fin spacing S11 at the design level, rather than due to differences in the fin gaps caused by manufacturing variations.

[0215] The cooling air passage regions 111 are gap regions between adjacent normal heat dissipation fins 531n among the normal heat dissipation fins 531n, and have a fin spacing S11 along the X direction. This fin spacing S11 is classified as a first type narrow spacing.

[0216] With respect to the two cooling air passage areas 115 and the plurality of cooling air passage areas 111, the spacing ratio (S15 / S11) of the fin spacing S11 to the wide fin spacing S15 is set to, for example, about two to three times.

[0217] 22 , the housing 3 supports the heat sink mounting frame 4D in a manner that accommodates the plurality of heat dissipation fins 531 of the first-class heat sink H53 and the plurality of heat dissipation fins 541 of the first-class heat sink H54. The heat sink base 530 of the first-class heat sink H53 and the heat sink mounting frame 4D are fixed together with screws or the like.

[0218] To be precise, the J-J cross-sectional structure in Figure 21 includes second-type heat sinks H61 to H64 and power semiconductor modules M61 to M64, but for the sake of convenience, Figure 23 selectively shows second-type heat sinks H61 to H63 and power semiconductor modules M61 to M63.

[0219] 23, the second-type heat sink H61 has a heat sink base 610 and a plurality of heat dissipation fins 611, the second-type heat sink H62 has a heat sink base 620 and a plurality of heat dissipation fins 621, and the second-type heat sink H63 has a heat sink base 630 and a plurality of heat dissipation fins 631. The plurality of heat dissipation fins 631, the plurality of heat dissipation fins 621, and the plurality of heat dissipation fins 631 are classified as a plurality of second-type heat dissipation fins.

[0220] A power semiconductor module M61 is mounted on the first main surface of the second type heat sink H61, a power semiconductor module M62 is mounted on the first main surface of the second type heat sink H62, and a power semiconductor module M63 is mounted on the first main surface of the second type heat sink H63.

[0221] The second-class heat sink H61 has the same structure as each of the second-class heat sinks H62 to H64, and the power semiconductor module M61 has the same structure as each of the power semiconductor modules M62 to M64. In the following, the second-class heat sink H61 and the power semiconductor module M61 will be described as representative examples.

[0222] Among the second type heat sinks H61 to H63 shown in FIG. 23, the heat sink base 610, the heat sink base 620, and the heat sink base 630 correspond to one another, and the plurality of heat dissipation fins 611, the plurality of heat dissipation fins 621, and the plurality of heat dissipation fins 631 correspond to one another.

[0223] The power semiconductor module M61 is mounted on the first main surface of the heat sink base 610. That is, the second main surface of the metal plate 21 of the power semiconductor module M61 is bonded to the first main surface of the heat sink base 610 via the TIM material 25, and the TIM material 25 ensures relatively high thermal conductivity between the second-type heat sink H61 and the power semiconductor module M61.

[0224] The first main surface of the heat sink base 610 becomes the first main surface of the second-type heat sink H61, and the multiple heat dissipation fins 611 each extend in the -Z direction from the second main surface of the heat sink base 610. Therefore, the multiple heat dissipation fins 611 each have a second-type formation depth that extends in the formation depth direction (-Z direction) on the side opposite to the first main surface of the heat sink base 610, which is the mounting surface for the second-type semiconductor module. In addition, the multiple heat dissipation fins 611 each have a second-type formation width that extends in the fin formation direction along the Y direction.

[0225] The multiple heat dissipation fins 611 have a fin arrangement direction that is the X direction, which is the fin formation direction, and the multiple heat dissipation fins 611 are arranged discretely from each other along the X direction, and the gap areas between the multiple heat dissipation fins 611 become multiple cooling air passage areas 121.

[0226] An aggregate of the plurality of cooling air passage regions 121 constitutes a second cooling air passage region provided on the second main surface side of the second-type heat sink H61. The plurality of cooling air passage regions 121 are classified into a plurality of second-type width regions.

[0227] Each of the cooling air passage areas 121 has a fin spacing S21 along the X direction, which is the fin arrangement direction. This fin spacing S21 is classified as a type 2 width spacing. The fin spacing S21 is set to, for example, approximately the same as the fin spacing S11 of the cooling air passage area 111 on the type 1 heat sink H53 side.

[0228] In this way, the fin spacing S21 of the multiple heat dissipation fins 611 of the second-type heat sink H61 arranged on the downwind side is configured to be uniform at the design level, excluding differences in fin spacing due to manufacturing variations. However, the spacing between the heat dissipation fins 611 and 611 of the second-type heat sink H61 arranged on the downwind side does not necessarily have to be uniform and can be configured freely.

[0229] 23, the housing 3 supports the heat sink mounting frame 4D in a manner that accommodates the plurality of heat dissipation fins 611, the plurality of heat dissipation fins 621, and the plurality of heat dissipation fins 631 of the second-class heat sinks H61 to H63. The heat sink bases 610 of the second-class heat sinks H61 to H63 and the heat sink mounting frame 4D are fixed with screws or the like.

[0230] 24 and 25 are explanatory diagrams showing the cooling effect of the semiconductor device 104 according to the fourth embodiment. An XYZ orthogonal coordinate system is shown in each of FIGS.

[0231] Fig. 24 is an explanatory diagram showing the temperature distribution of air flowing between the heat dissipation fins of the heat sink of the semiconductor device 104. Fig. 25 is an explanatory diagram showing the temperature of air flowing into the first-class heat sinks H51 to H56 of the semiconductor device 104 in the form of a contour diagram, and Fig. 25 shows the temperature distribution of the first-class heat sinks H51 to H56 as air temperature contour TC4.

[0232] The first-class heat sink H53 in the semiconductor device 104 of the fourth embodiment has two pairs of modified heat dissipation fins 531X and 531X. Two cooling air passage regions 115, which are gap regions between the two pairs of modified heat dissipation fins 531X and 531X, each have a wide fin spacing S15 that is set wider than the fin spacing S11 of the cooling air passage region 111. Therefore, during operation of the semiconductor device 104, the temperature rise of the cooling air when it reaches the multiple heat dissipation fins 61 of the second-class heat sink H61 can be effectively suppressed.

[0233] As shown in FIG. 24, heat generated by the multiple semiconductor elements 16 in each of the power semiconductor modules M51 and M52 is dissipated from the first-class heat sinks H51 and H52, respectively, causing the temperature of the air flowing into the power semiconductor modules M53 and M54 to rise.

[0234] Similarly, heat generated from the multiple semiconductor elements 16 in each of the power semiconductor modules M53 and M54 is dissipated from the first-class heat sinks H53 and H54, respectively, causing the temperature of the air flowing into the power semiconductor modules M55 and M56 to rise. Furthermore, heat generated from the multiple semiconductor elements 16 in each of the power semiconductor modules M55 and M56 is dissipated from the first-class heat sinks H55 and H56, respectively, causing the temperature of the air flowing into the power semiconductor modules M61 to M64 to rise.

[0235] In this way, due to heat generated by the multiple semiconductor elements 16 of each of the power semiconductor modules M51 to M56 mounted on the first type heat sinks H51 to H56 on the windward side, cooling air that has increased in temperature flows into the second type heat sinks H61 to H64 on the downwind side that are mounted with the power semiconductor modules M61 to M64.

[0236] The width in the X direction of each of the air flow velocity vectors F11 to F13 and the air flow velocity vector FX1 shown in Fig. 24 indicates the amount of heat. As shown in the figure, in the multiple cooling air passage areas 91, the amount of heat of the air flow velocity vector F13 before it reaches the second-class heat sinks H61 to H64 is quite large.

[0237] In the semiconductor device 104 of the fourth embodiment, in each of the first type heat sinks H51 to H56 arranged on the windward side, the wide fin spacing S15, which is the spacing between two pairs of modified heat dissipation fins 531X and 531X among the multiple heat dissipation fins 531, is set to be larger than the fin spacing S11 between adjacent normal heat dissipation fins 531n and 531n.

[0238] In this way, by setting the wide fin spacing S15 in each of the two cooling air passing areas 115 to be sufficiently wider than the fin spacing S11, it is possible to minimize the temperature rise along the flow velocity vector 1 in the two cooling air passing areas 115. This is because, in the cooling air passing area 115 having the relatively wide fin spacing S15, the coefficient of heat transfer from the surface of the modified heat dissipation fin 631X to the air is small and the amount of heat dissipation from the modified heat dissipation fin 631X is small, so the amount of rise in the air temperature of the cooling air passing through the cooling air passing area 115 is minimal.

[0239] Therefore, the two cooling air passage areas 115 can be kept within a relatively low temperature area tc41 as shown in Fig. 25. Note that in Fig. 15, the higher the air temperature, the darker the black color.

[0240] That is, as shown in Figure 24, in the X direction, the air flow velocity vector FX4 of the four cooling air passage areas 115 keeps the heat quantity below a certain value, so that cooling air having a relatively low temperature air flow velocity vector FX4 can be supplied to the second type heat sinks H61 to H64.

[0241] Therefore, a relatively low temperature region can be provided even in the second type heat sinks H61 to H64 on the downwind side, so the temperature of the multiple semiconductor elements 16 in each of the power semiconductor modules M61 to M64 can be kept below the allowable temperature without increasing the size of each of the first type heat sinks H51 to H56 and the second type heat sinks H61 to H64.

[0242] As a result, the size of the first type heat sinks H51 to H56 and the second type heat sinks H61 to H64 can be minimized to achieve miniaturization, and therefore the semiconductor device 104 of the fourth embodiment can be miniaturized.

[0243] As described above, the first-class heat sinks H51 to H56 are on the windward side and the second-class heat sinks H61 to H64 are on the leeward side with respect to the cooling air supplied from the cooling fan 2. Each of the first-class heat sinks H51 to H56 in the semiconductor device 104 of the fourth embodiment has two cooling air passage areas 115 set at a wide fin spacing S15. Therefore, the temperature rise of the cooling air passing through the cooling air passage areas 115 classified as the first-class wide areas can be minimized, and the cooling air can flow into the multiple heat dissipation fins 611 of the second-class heat sinks H61 to H64.

[0244] Regarding the above effect, similar to the spacing ratio (S5 / S1) described in embodiment 1, it is estimated that if the wide fin spacing S15 is set to be between two and three times the fin spacing S11 {2≦(S15 / S11)≦3}, a beneficial effect of suppressing temperature rise of the cooling air can be obtained.

[0245] Therefore, in the semiconductor device 104 of the fourth embodiment, the cooling air blown from the cooling fan 2 can suppress the temperature rise of the plurality of heat dissipation fins 611 etc. in addition to the plurality of heat dissipation fins 531 etc. Therefore, the first-class heat sinks H51 to H56 can suppress the temperature rise of the power semiconductor modules M51 to M56 during operation, and the second-class heat sinks H61 to H64 can suppress the temperature rise of the power semiconductor modules M61 to M64 during operation.

[0246] In other words, in the semiconductor device 104 of the fourth embodiment, in order to suppress the temperature rise during operation of the power semiconductor modules M51 to M56 and M61 to M64, there is no need to enlarge the power semiconductor modules M51 to M56 and M61 to M64, as well as the first type heat sinks H51 to H56 and the second type heat sinks H61 to H64.

[0247] As a result, the semiconductor device 104 of embodiment 4, like embodiments 1 to 3, has a cooling function for the power semiconductor module MP using first-type heat sinks H51 to H56 and second-type heat sinks H61 to H64, and can also be made smaller.

[0248] Furthermore, the semiconductor device 104 of the fourth embodiment has a structure in which first-type heat sinks H51 to H56 and power semiconductor modules M51 to M56 correspond one-to-one, and second-type heat sinks H61 to H64 and power semiconductor modules M61 to M64 correspond one-to-one, thereby enabling the device to be made smaller.

[0249] In the fourth embodiment, the structure of the plurality of heat dissipation fins 531, etc., is similar to the structure of the plurality of heat dissipation fins 61 of the first embodiment shown in Fig. 7, but is not limited to this structure. For example, the structure of the plurality of heat dissipation fins 531, etc., may be a structure including a plurality of normal heat dissipation fins 5B1 and four notched heat dissipation fins 5B2 (5B3) of the second embodiment shown in Figs. 16 to 18, or a structure including a plurality of normal heat dissipation fins 5C1 and four notched heat dissipation fins 5C2 shown in Figs. 19 and 20.

[0250] In addition, in the fourth embodiment, the first type heat sinks H51 to H56 are described as being on the windward side, and the second type heat sinks H61 to H64 are described as being on the leeward side, but the present invention is not limited to this classification.

[0251] It is expected that a similar effect can be obtained by adopting a structure having at least one pair of modified heat dissipation fins 531X, 531X, etc. for at least one of the first-type heat sinks H51 to H56 and the second-type heat sinks H61 to H64, which is on the upwind side of the second-type heat sink H61 to H64, which is the most downwind side, with respect to the flow velocity vector 1 indicating the direction of air inflow and outflow.

[0252] 26 is an explanatory diagram schematically illustrating a planar configuration of a semiconductor device 105 that is a basic configuration of a fifth embodiment of the present disclosure. The semiconductor device 105 of the fifth embodiment is a power semiconductor device having a plurality of power semiconductor modules. An XYZ Cartesian coordinate system is depicted in FIG.

[0253] Hereinafter, components similar to those of the semiconductor device 101 of the first embodiment shown in FIG. 1 are denoted by the same reference numerals and description thereof will be omitted, and the description will focus on the characteristics of the semiconductor device 105 of the fifth embodiment.

[0254] 26, a semiconductor device 105 having a basic configuration according to the fifth embodiment has heatsink-integrated power semiconductor modules HM51 to HM56 and heatsink-integrated power semiconductor modules HM61 to HM64. The heatsink-integrated power semiconductor modules HM51 to HM56 and HM61 to HM64 are attached to a heatsink mounting frame 4D, which is an attachment plate.

[0255] The heat sink integrated power semiconductor module HM5i (i = 1 to 6) has a structure in which a power semiconductor module portion MM5i and a heat sink portion HK5i are integrated together. The heat sink integrated power semiconductor module HM5j (j = 1 to 4) has a structure in which a power semiconductor module portion MM5j and a heat sink portion HK6j are integrated together.

[0256] Therefore, there is a one-to-one correspondence between the power semiconductor module portions MM51 to MM56, which are the plurality of first-type semiconductor modules, and the heat sink portions HK51 to HK56, which are the plurality of first-type heat sinks. That is, the power semiconductor module portion MM5i is mounted on the first main surface of the heat sink portion HK5i (i = 1 to 6).

[0257] Similarly, there is a one-to-one correspondence between the power semiconductor modules M61-M64, which are the plurality of type-2 semiconductor modules, and the heat sink portions HK61-HK64, which are the plurality of type-2 heat sinks. Therefore, the power semiconductor module portion MM6j is mounted on the first main surface of the heat sink portion HK6j (j = 1 to 4).

[0258] As described above, the semiconductor device 105 of the fifth embodiment has heat sink portions HK51 to HK56 as a plurality of first-class heat sinks, and has heat sink portions HK61 to HK64 as a plurality of second-class heat sinks.

[0259] The heat sink mounting frame 4D has six openings and four openings (not shown), and the heat sink integrated power semiconductor modules HM51 to HM56 are attached by fitting into the six openings, respectively, and the heat sink integrated power semiconductor modules HM61 to HM64 are attached by fitting into the four openings, respectively. The heat sink mounting frame 4D is fixed to the top of the housing 3.

[0260] Therefore, the first main surfaces of the heat sink portions HK51 to HK56 serve as mounting surfaces for the first type semiconductor modules, and the first main surfaces of the heat sink portions HK61 to HK64 serve as mounting surfaces for the second type semiconductor modules.

[0261] In the semiconductor device 105 of the fifth embodiment, the heat sink integrated power semiconductor modules HM51 to HM56 are located on the upwind side of the flow velocity vector 1, and the heat sink integrated power semiconductor modules HM61 to HM64 are located on the downwind side.

[0262] As described above, the semiconductor device 105 of the fifth embodiment includes heat sink integrated power semiconductor modules HM51 to HM56, heat sink integrated power semiconductor modules HM61 to HM64, a heat sink mounting frame 4D, a housing 3, and a cooling fan 2 as main components.

[0263] The power semiconductor module portions MM51 to MM56 and the power semiconductor module portions MM61 to MM64 each have the cross-sectional structure shown in, for example, Figures 4 to 6. The heat sink mounting frame 4D, which is the mounting plate, and the housing 3 may be configured as separate members or as an integrated component.

[0264] Fig. 27 is an explanatory diagram schematically showing the cross-sectional structure of the semiconductor device 105 of the fifth embodiment shown in Fig. 26. Fig. 27 shows the K-K cross section of Fig. 26. For convenience of explanation, the L-L cross-sectional structure of Fig. 26 is omitted. An XYZ orthogonal coordinate system is shown in Fig. 27.

[0265] 27, each of the heat sink portions HK53 and HK54 has a heat sink base 70 and a plurality of heat dissipation fins 71. The plurality of heat dissipation fins 71 are classified as a plurality of first-class heat dissipation fins.

[0266] The power semiconductor module portion MM53 is mounted on the first main surface of the heat sink portion HK53, and the power semiconductor module portion MM54 is mounted on the first main surface of the heat sink portion HK54.

[0267] 28 is an explanatory diagram showing a cross-sectional structure of the heat sink integrated power semiconductor module HM. The heat sink integrated power semiconductor modules HM51 to HM56 and HM61 to HM64 each have a structure similar to the heat sink integrated power semiconductor module HM shown in FIG.

[0268] 28 corresponds to each of the power semiconductor module parts MM51 to MM56 and MM61 to MM64, and the heat sink part HK corresponds to each of the heat sink parts HK51 to HK56 and HK61 to HK64, except that the structure of the plurality of heat dissipation fins 71 of each of the heat sink parts HK51 to HK56 is the structure shown in FIG.

[0269] The structure of the heat sink integrated power semiconductor module HM will be described below with reference to FIG.

[0270] The heat sink portion HK includes a heat sink base 70 having a first main surface and a second main surface, and a plurality of heat dissipation fins 71 provided on the second main surface side of the heat sink base 70. The first main surface of the heat sink base 70 is textured. That is, an uneven region is provided on the first main surface of an upwardly protruding region, which is a part of the first main surface of the heat sink base 70.

[0271] The heat sink part HK shown in Fig. 28 has a structure employing a crimped heat sink, in which a heat sink base 70 and a plurality of heat dissipation fins 71 are integrated by crimping. The heat sink base 70 of the heat sink part HK shown in Fig. 28 is produced by cutting, die-casting, forging, extrusion, or the like, and is made of aluminum, aluminum alloy, or the like.

[0272] Furthermore, the heat dissipation fins 71 of the heat sink portion HK shown in FIG. 28 are made of a plate material (rolled material) such as aluminum or an aluminum alloy, and therefore can achieve both workability and heat dissipation properties.

[0273] However, the constituent materials of the fin base 48, heat sink base 70, and multiple heat dissipation fins 71 described below are not limited to aluminum materials, and each may be a combination of different materials. For example, from the perspective of heat dissipation capacity, by making the multiple heat dissipation fins 71 out of copper-based plate material, which has a higher thermal conductivity than aluminum-based materials, the heat dissipation capacity can be further improved compared to when using aluminum-based materials.

[0274] When a crimped heat sink is used in which the heat sink portion HK shown in Figure 28 is formed by crimping a heat sink base 70 and multiple heat dissipation fins 71 together, there are no processing restrictions (aspect ratio) associated with die-casting or extrusion, so the multiple heat dissipation fins 71 can be designed freely, thereby improving the heat dissipation capacity of the heat sink portion HK.

[0275] However, the heat sink portion HK is not limited to the crimped heat sink shown in Fig. 28, and may be made by extrusion, casting (die casting), cutting, or forging, as in the first and second type heat sinks 5 and 6 of embodiment 1. Note that the configuration is not limited to the above, and the same effect can be obtained by employing a heat sink-integrated power module in which the power semiconductor module and the heat sink are connected with a joining material such as solder or an adhesive, rather than integrating the power semiconductor module and the crimped heat sink.

[0276] The heatsink-integrated power semiconductor module HM further includes a fin base 48, which is provided between the heatsink portion HK and the power semiconductor module portion MM and serves as an intermediate assembly having a first main surface and a second main surface. The second main surface of the fin base 48, which is an intermediate structure, is textured. That is, an uneven region is provided on the second main surface of the fin base 48.

[0277] The fin base 48 is manufactured by cutting, die-casting, forging, extrusion, or the like, and is made of aluminum or an aluminum alloy.

[0278] When the fin base 48 is made of aluminum, its thermal conductivity is 222 W / (m·K), whereas the thermal conductivity of the TIM material 25 is approximately 5 to 10 W / (m·K) for typical constituent materials. Therefore, the fin base 48 has significantly better thermal conductivity than the TIM material 25.

[0279] A power semiconductor module portion MM is coupled to the first main surface of the fin base 48, and a heat sink portion HK is coupled to the second main surface of the fin base 48, thereby forming a heat sink integrated power semiconductor module HM.

[0280] Next, the structure of the power semiconductor module portion MM will be described. An insulating material 40 is provided on a first main surface of the fin base 48. A plurality of metal conductors 39 are provided on the first main surface of the insulating material 40. A plurality of semiconductor elements 36 are selectively provided on the first main surfaces of the plurality of metal conductors 39 via bonding material 37. Some of the semiconductor elements 36 and the semiconductor elements 36 and the metal conductors 39 are electrically connected via wiring 38.

[0281] The bonding material 37 is made of solder or the like, the plurality of metal conductors 39 are provided using, for example, a lead frame, the insulating material 40 is made of, for example, an insulating sheet, and the sealing material 42 is made of, for example, an epoxy-based resin.

[0282] The plurality of semiconductor elements 36 may be Si-based semiconductor elements, SiC-based semiconductor elements, compound semiconductor elements such as GaN, etc., and are not particularly limited.

[0283] A sealing material 42 is provided to cover the fin base 48, the insulating material 40, the plurality of metal conductors 39, the plurality of bonding materials 37, the plurality of semiconductor elements 36, and the plurality of wirings 38. The insulating material 40, the plurality of bonding materials 37, the plurality of semiconductor elements 36, and the plurality of wirings 38 are all sealed within the sealing material 42. Some of the plurality of metal conductors 39 are sealed within the sealing material 42, and some protrude to the outside from a first main surface or a side surface of the sealing material 42. Of the plurality of metal conductors 39, the exposed portions of the metal conductors 39 protruding from the side surface of the sealing material 42 serve as main terminals 391, and the exposed portions of the metal conductors 39 protruding from the first main surface of the sealing material 42 serve as control terminals 392.

[0284] In this way, the heat sink integrated type power semiconductor modules HM51 to HM56 and HM61 to HM64 each have substantially the same structure as the heat sink integrated type power semiconductor module HM shown in FIG.

[0285] Here, in the semiconductor device 105 of embodiment 5, the heat sink integrated power semiconductor modules HM51 to HM56 are classified into a plurality of first type heat sink integrated power semiconductor modules, and the power semiconductor module portions MM51 to MM56 are classified into a plurality of first type semiconductor modules.

[0286] Furthermore, the fin bases 48 provided in each of the heatsink-integrated power semiconductor modules HM61 to HM64 are classified as type 1 intermediate combined bodies. Hereinafter, the fin bases 48 classified as type 1 intermediate combined bodies may be referred to as "fin bases 48i (I = 1 to 6)."

[0287] Meanwhile, in semiconductor device 105 of embodiment 5, heatsink-integrated power semiconductor modules HM61-HM64 are classified into a plurality of second-type heatsink-integrated power semiconductor modules, and power semiconductor module portions MM61-MM64 are classified into a plurality of second-type semiconductor modules. Furthermore, fin bases 48 provided on each of heatsink-integrated power semiconductor modules HM61-HM64 are classified into second-type intermediate combined bodies. Hereinafter, fin bases 48 classified into second-type intermediate combined bodies may be referred to as "fin bases 48j (j = 1 to 4)."

[0288] The heat sink portions HK53 and HK54, which are the plurality of first-class heat sinks, will be described below with reference to Fig. 27. Since the heat sink portions HK51 to HK56 have the same structure, the heat sink portion HK53 will be described below as a representative.

[0289] The first main surface of the heatsink base 70 becomes the first main surface of the heatsink portion HK53, and the multiple heat dissipation fins 71 each extend in the −Z direction from the second main surface of the heatsink base 70. Therefore, the multiple heat dissipation fins 71 each have a first-type formation depth that extends in the formation depth direction (−Z direction) on the side opposite to the first main surface of the heatsink base 70, which is the mounting surface for the first-type semiconductor module. In addition, the multiple heat dissipation fins 71 each have a first-type formation width that extends in the fin formation direction along the Y direction.

[0290] The multiple heat dissipation fins 71 have the fin arrangement direction in the X direction, which is the fin formation direction, and the multiple heat dissipation fins 71 are arranged discretely from each other along the X direction, and the gap areas between the multiple heat dissipation fins 71 become multiple cooling air passage areas 111 or two cooling air passage areas 115.

[0291] The assembly of the multiple cooling air passage regions 111 and the two cooling air passage regions 115 constitutes a first cooling air passage region provided on the second main surface side of the first heat sink H53. The multiple cooling air passage regions 111 are classified into multiple first narrow regions, and the two cooling air passage regions 115 are classified into at least one first wide region.

[0292] Each of the plurality of heat dissipating fins 71 includes two adjacent pairs of modified heat dissipating fins 71X, 71X. The two pairs of modified heat dissipating fins 71X, 71X are classified as at least one pair of modified heat dissipating fins, and all of the fins other than the two pairs of modified heat dissipating fins 71X, 71X are classified as normal heat dissipating fins 71n.

[0293] The two cooling air passage regions 115 are classified as at least one type 1 wide region and correspond one-to-one to the two pairs of modified heat dissipation fins 71X and 71X. Therefore, the two cooling air passage regions 115 are the gap regions between the corresponding pairs of modified heat dissipation fins 71X and 71X, respectively, and each have a wide fin spacing S15 along the X direction, which is the fin arrangement direction. This wide fin spacing S15 is classified as a type 1 wide spacing.

[0294] In this way, in the first type heat sink H53 arranged on the windward side, the wide fin spacing S15 between the two deformed heat dissipation fins 71X and 71X is dimensioned to be larger than the fin spacing S11 of the cooling air passage area 111 at the design level, not due to differences in fin spacing caused by manufacturing variations.

[0295] The cooling air passage areas 111 are gap areas between adjacent normal heat dissipation fins 71n among the normal heat dissipation fins 71n, and have a fin spacing S11 along the X direction. This fin spacing S11 is classified as a first type narrow spacing.

[0296] With respect to the two cooling air passage areas 115 and the plurality of cooling air passage areas 111, the spacing ratio (S15 / S11) of the fin spacing S11 to the wide fin spacing S15 is set to, for example, about two to three times.

[0297] As shown in FIG. 27, the housing 3 supports the heat sink mounting frame 4D in a manner that accommodates the plurality of heat dissipation fins 71 of each of the first-class heat sinks H53 and H54.

[0298] Although not shown in the figure, the multiple heat dissipation fins 71 that each heat sink portion HK61 to HK64 has are arranged in the X direction as the fin arrangement direction, and the multiple heat dissipation fins 71 are arranged discretely from each other along the X direction, with the gap areas between the multiple heat dissipation fins 71 becoming multiple cooling air passage areas.

[0299] The multiple cooling air passing regions are regions equivalent to the cooling air passing region 92 of the first embodiment shown in Figure 8. Therefore, the collection of the multiple cooling air passing regions is a second type cooling air passing region provided on the second main surface side of each of the heat sink portions HK61 to HK64. The multiple cooling air passing regions are classified into multiple second type width regions.

[0300] The plurality of cooling air passage areas each have a fin spacing S2 along the X direction, which is the fin arrangement direction, similar to the plurality of cooling air passage areas 92 in embodiment 1. This fin spacing S2 is the second type width spacing.

[0301] In this way, the fin spacing S2 in the heat sink portions HK61 to HK64 arranged on the downwind side is configured with uniform fin spacing at the design level, similar to the fin spacing S2 in the second type heat sink 6 of embodiment 1, except for differences in fin spacing due to manufacturing variations.

[0302] (Cooling Effect of Embodiment 5) Figures 29 and 30 are explanatory diagrams showing the cooling effect of the semiconductor device 105 of embodiment 5. An XYZ orthogonal coordinate system is depicted in each of Figures 29 and 30.

[0303] Fig. 29 is an explanatory diagram showing the temperature distribution of air flowing between the heat dissipation fins of the heat sink of the semiconductor device 105. Fig. 30 is an explanatory diagram showing the temperature of air flowing into the heat sink of the semiconductor device 105 in the form of a contour diagram, and Fig. 30 shows the temperature distribution of the heat sink portions HK51 to HK56 in the heat sink-integrated power semiconductor modules HM51 to HM56 as an air temperature contour TC5.

[0304] The heat sink portion HK53 in the semiconductor device 105 of the fifth embodiment has two pairs of modified heat dissipation fins 71X and 71X. Two cooling air passage areas 115, which are gap areas between the two pairs of modified heat dissipation fins 71X and 71X, each have a wide fin spacing S15 that is set wider than the fin spacing S11. Therefore, during operation of the semiconductor device 105, the temperature rise of the cooling air when it reaches the multiple heat dissipation fins 71 of the first-class heat sink H53 can be effectively suppressed.

[0305] As shown in Figure 29, heat generated by the multiple semiconductor elements 36 in each of the power semiconductor module parts MM51 and MM52 is dissipated from the heat sink parts HK51 and HK52, respectively, causing the temperature of the cooling air flowing into the power semiconductor module parts MM53 and MM54 to rise.

[0306] Similarly, heat generated from the multiple semiconductor elements 36 in each of the power semiconductor module portions MM53 and MM54 is dissipated from the heat sink portions HK53 and HK54, respectively, thereby increasing the temperature of the cooling air flowing into the power semiconductor module portions MM55 and MM56. Furthermore, heat generated from the multiple semiconductor elements 36 in each of the power semiconductor module portions MM55 and MM56 is dissipated from the heat sink portions HK55 and HK56, respectively, thereby increasing the temperature of the cooling air flowing into the power semiconductor module portions MM61 to MM64.

[0307] In this way, due to heat generated from the multiple semiconductor elements 36 of each of the power semiconductor module parts MM61 to MM64 corresponding to the heatsink-integrated power semiconductor modules HM51 to HM56 on the windward side, heated air flows into the heatsink-integrated power semiconductor modules HM61 to HM64 on the downwind side which have the power semiconductor module parts MM61 to MM64.

[0308] The width in the X direction of each of the air flow velocity vectors F11 to F13 and the air flow velocity vector FX5 shown in Figure 29 indicates the amount of heat. As shown in the figure, in the multiple cooling air passage areas 111, the amount of heat of the air flow velocity vector F13 before it reaches the heat sink portions HK61 to HK64 is quite large.

[0309] In the semiconductor device 105 of the fifth embodiment, in each of the heat sink portions HK51 to HK56 arranged on the windward side, the wide fin spacing S15, which is the spacing between two pairs of modified heat dissipation fins 71X and 71X among the multiple heat dissipation fins 71, is set to be larger than the fin spacing S11 between the normal heat dissipation fins 71n and 71n.

[0310] In this way, by setting the wide fin spacing S15 of each of the two cooling air passage areas 115 to be sufficiently wider than the fin spacing S11, the temperature rise along the flow velocity vector 1 in the two cooling air passage areas 115 can be kept to a minimum.

[0311] Therefore, the two cooling air passage areas 115 can be kept in a relatively low temperature area tc51 as shown in Fig. 30. In Fig. 30, the higher the air temperature, the darker the black color.

[0312] That is, as shown in FIG. 29, in the air flow velocity vector FX5 of the two cooling air passage areas 115 in the X direction, the amount of heat is kept below a certain value, so that cooling air having a relatively low temperature air flow velocity vector FX5 can be supplied to the heat sink portions HK61 to HK64 of the heat sink-integrated power semiconductor modules HM61 to HM64.

[0313] Therefore, a relatively low temperature region can be provided even in the heatsink portions HK61 to HK64 on the downwind side, so the temperature of the multiple semiconductor elements 36 in each of the power semiconductor module portions MM61 to MM64 can be kept below the allowable temperature without increasing the size of the heatsink-integrated power semiconductor modules HM51 to HM56 and the heatsink-integrated power semiconductor modules HM61 to HM64.

[0314] As a result, the size of the heat sink integrated power semiconductor modules HM51 to HM56 and the heat sink integrated power semiconductor modules HM61 to HM64 can be reduced to the minimum necessary, and the semiconductor device 105 of the fifth embodiment can be made smaller.

[0315] As described above, the heatsink-integrated power semiconductor modules HM51-HM56 are on the windward side and the heatsink-integrated power semiconductor modules HM61-HM64 are on the leeward side with respect to the cooling air supplied from the cooling fan 2. Each of the heatsink portions HK51-HK56 in the semiconductor device 105 of the fifth embodiment has two cooling air passage areas 115 set at wide fin spacing S15. Therefore, the temperature rise of the cooling air passing through the cooling air passage areas 115 classified as the first wide areas can be minimized, and the cooling air can flow into the multiple heat dissipation fins 71 of each of the heatsink portions HK61-HK64.

[0316] Therefore, in semiconductor device 105 of the fifth embodiment, the temperature rise of the plurality of heat dissipation fins 71 of each of heat sink portions HK61 to HK64, in addition to the plurality of heat dissipation fins 71 of each of heat sink portions HK51 to HK56, can be suppressed by the cooling air blown from cooling fan 2. Therefore, the heat sink portions HK51 to HK56 can suppress the temperature rise of power semiconductor module portions MM51 to MM56 during operation, and the heat sink portions HK61 to HK64 can suppress the temperature rise of power semiconductor module portions MM61 to MM64 during operation.

[0317] In other words, in the semiconductor device 105 of embodiment 5, there is no need to increase the size of the heatsink-integrated power semiconductor modules HM51 to HM56 and the heatsink-integrated power semiconductor modules HM61 to HM64 in order to suppress temperature rise during operation of the power semiconductor module portions MM51 to MM56 and MM61 to MM64.

[0318] As a result, the semiconductor device 105 of embodiment 5, like embodiments 1 to 4, has a cooling function for the power semiconductor module portion MM by the heat sink portions HK51 to HK56 and HK61 to HK64, and can also be made smaller.

[0319] The semiconductor device 105 of embodiment 5 includes heat sink portions HK51 to HK56 which are multiple first-type heat sinks as first-type heat sinks, and multiple fin bases 48i used in the heat sink-integrated power semiconductor modules HM51 to HM56 as first-type intermediate combined bodies.

[0320] Furthermore, the first type semiconductor module includes a plurality of first type semiconductor modules, that is, power semiconductor module portions MM51 to MM56, and there is a one-to-one correspondence between the heat sink portions HK51 to HK56, the plurality of fin bases 48i, and the plurality of power semiconductor module portions MM416.

[0321] Furthermore, the first type heat sink integrated power semiconductor modules include heat sink integrated power semiconductor modules HM51 to HM56, which are classified into a plurality of first type heat sink integrated power semiconductor modules.

[0322] The heat sink integrated power semiconductor modules HM51 to HM56 each include a power semiconductor module part MM51 to MM56, a plurality of first type intermediate coupling bodies (fin bases 48i), and a corresponding power semiconductor module part MMi (i = 1 to 6), a corresponding fin base 48i, and a corresponding heat sink part HKi among the heat sink parts HK51 to HK56.

[0323] The second type heat sink includes a plurality of second type heat sink heat sink portions HK61 to HK64, and the second type intermediate combined bodies include a plurality of second type intermediate combined bodies (fin bases 48j) used in the heat sink integrated power semiconductor modules HM61 to HM64.

[0324] Furthermore, the second-type semiconductor module includes a plurality of second-type semiconductor modules, that is, power semiconductor module portions MM61 to MM64, and there is a one-to-one correspondence between the heat sink portions HK61 to HK64, the plurality of second-type intermediate combination bodies (fin bases 48j), and the power semiconductor module portions MM61 to MM64.

[0325] The second type heat sink integrated power semiconductor modules include heat sink integrated power semiconductor modules HM61 to HM64, which are classified into a plurality of second type heat sink integrated power semiconductor modules.

[0326] The heat sink integrated power semiconductor modules HM61 to HM64 each include a power semiconductor module part MM61 to MM64, a plurality of second type intermediate coupling bodies (fin bases 48j), and a corresponding power semiconductor module part MM6j (j = any one of 1 to 4), a corresponding fin base 48j, and a corresponding heat sink part HKj among the heat sink parts HK61 to HK64.

[0327] The semiconductor device 105 of the fifth embodiment has heatsink-integrated power semiconductor modules HM51 to HM56, each of which includes a power semiconductor module portion MM5i, a fin base 48i, and a heatsink portion HK5i, and therefore can improve the heat dissipation performance of each of the heatsink-integrated power semiconductor modules HM51 to HM56.

[0328] Furthermore, the semiconductor device 105 of the fifth embodiment has heatsink-integrated power semiconductor modules HM61 to HM64, each of which includes a power semiconductor module portion MM6j, a fin base 48j, and a heatsink portion HK6j, and therefore the heat dissipation properties of each of the heatsink-integrated power semiconductor modules HM61 to HM64 can be improved.

[0329] Additionally, in semiconductor device 105 of the fifth embodiment, the uneven area provided on the second main surface of fin base 48 and the uneven area provided on the first main surface of heat sink base 70 are integrated by fitting them together by press working. As a result, a greaseless power module can be configured using fin base 48 without using thermally conductive grease between power semiconductor module portion MM and heat sink portion HK, and therefore high heat dissipation performance can be achieved.

[0330] 31 is an explanatory diagram schematically illustrating a planar configuration of a semiconductor device 105B according to a modification of the fifth embodiment of the present disclosure. The semiconductor device 105B according to the fifth embodiment is a power semiconductor device having a plurality of power semiconductor modules.

[0331] Hereinafter, components similar to those of the semiconductor device 105 having the basic configuration of the fifth embodiment shown in FIG. 26 will be assigned the same reference numerals and explanations thereof will be omitted, and the description will focus on the characteristic features of the semiconductor device 105B of the modified example.

[0332] As shown in Fig. 31, a semiconductor device 105B of the modified example has heatsink-integrated power semiconductor modules HM51 to HM56 and a heatsink-integrated power semiconductor module HM60. The heatsink-integrated power semiconductor modules HM51 to HM56 and HM60 are attached to a heatsink mounting frame 4E, which is a mounting plate. An XYZ Cartesian coordinate system is shown in Fig. 31.

[0333] The cross section of the semiconductor device 105B of the modified example taken along the line K2-K2 in FIG. 31 has the same structure as the cross section of the semiconductor device 105 of the basic structure shown in FIG.

[0334] Fig. 32 is an explanatory diagram schematically showing the cross-sectional structure of the semiconductor device 105B according to the fifth embodiment shown in Fig. 31. Fig. 32 shows the L2-L2 cross section of Fig. 31. An XYZ orthogonal coordinate system is shown in Fig. 32.

[0335] Regarding the L2-L2 cross-sectional structure in FIG. 31, to be precise, power semiconductor module portions MM61 to MM64 exist, but in FIG. 32, of the power semiconductor module portions MM61 to MM64, power semiconductor module portions MM62 and MM63 are selectively shown.

[0336] Hereinafter, the heat sink portion HK7 that serves as a single second-type heat sink will be described with reference to FIG.

[0337] The single heat sink portion HK7 includes a heat sink base 70B having a first main surface and a second main surface, and a plurality of heat dissipation fins 71B provided on the second main surface side of the heat sink base 70B, and the first main surface of the heat sink base 70B is textured at four locations. That is, a textured area is formed on the first main surface of each of the four upwardly protruding areas of the heat sink base 70B.

[0338] 32 shows the concave and convex areas of the two upwardly protruding areas for the power semiconductor module portions MM63 and MM64. The plurality of heat dissipation fins 71B are classified into a plurality of second-type heat dissipation fins.

[0339] The power semiconductor module portions MM61 to MM64 are mounted on the first main surface of the heat sink portion HK7, and only the power semiconductor module portions MM62 and MM63 are shown in FIG.

[0340] The heatsink-integrated power semiconductor module HM60 is provided between the heatsink portion HK7 and the power semiconductor module portions MM61 to MM64, and includes four fin bases 48 that serve as intermediate structures having first and second main surfaces. The second main surfaces of the four fin bases 48, which are the four intermediate structures, are textured. That is, a textured region is formed on the second main surface of each of the four fin bases 48. Note that FIG. 32 shows two fin bases 48 for the power semiconductor module portions MM63 and MM64.

[0341] The power semiconductor module parts MM61 to MM64 are joined to the first main surfaces of the four fin bases 48, and the heat sink part HK7 is joined to the second main surfaces of the four fin bases 48, thereby forming a heat sink integrated power semiconductor module HM60.

[0342] In the semiconductor device 105B of the modified example, the heatsink-integrated power semiconductor module HM60 is classified as a second-type heatsink-integrated power semiconductor module, and the four fin bases 48 provided on the heatsink-integrated power semiconductor module HM60 are classified as four second-type intermediate combined bodies.

[0343] The first main surface of the heatsink base 70B is the first main surface of the heatsink portion HK7, and the multiple heat dissipation fins 71B each extend in the -Z direction from the second main surface of the heatsink base 70B. Therefore, each of the multiple heat dissipation fins 71B has a second-type formation depth that extends in the formation depth direction (-Z direction) on the side opposite to the first main surface of the heatsink base 70B, which is the mounting surface for the second-type semiconductor module. In addition, each of the multiple heat dissipation fins 71B has a second-type formation width that extends in the fin formation direction along the Y direction.

[0344] The multiple heat dissipation fins 71B have the fin arrangement direction in the X direction, which is the fin formation direction, and the multiple heat dissipation fins 71B are arranged discretely from each other along the X direction, and the gap areas between the multiple heat dissipation fins 71B become multiple cooling air passage areas 112.

[0345] An aggregate of the plurality of cooling air passage regions 112 constitutes a second type cooling air passage region provided on the second main surface side of the heat sink portion HK7. The plurality of cooling air passage regions 112 are classified into a plurality of second type width regions.

[0346] The cooling air passage areas 112 each have a fin spacing S12 along the X direction, which is the fin arrangement direction. The fin spacing S12 is classified as a second type of width spacing.

[0347] In this way, the fin spacing S12 in the heat sink portion HK7 arranged on the downwind side is configured to have a uniform fin spacing at the design level, excluding differences in fin spacing due to manufacturing variations.

[0348] The semiconductor device 105B, which is a modified example of the fifth embodiment, as described above, has the same cooling function for the power semiconductor module part MM by the heat sink parts HK51 to HK56 and the heat sink part HK7 as the semiconductor device 105 having the basic configuration, and can also be made smaller.

[0349] In the modified example, a structure is shown in which a single heatsink-integrated power semiconductor module HM60 is provided as a second-class heatsink-integrated power semiconductor module collectively having the power semiconductor module portions MM61 to MM64. As a second modified example different from the modified example, a first-class heatsink-integrated power semiconductor module collectively having the power semiconductor module portions MM51 to MM56 may be employed.

[0350] Although the fifth embodiment shows the same structure as the plurality of heat dissipation fins 61 of the first embodiment shown in Fig. 7 as the structure of the plurality of heat dissipation fins 71, the structure is not limited to this. For example, the structure of the plurality of heat dissipation fins 71 may be the structure including the plurality of normal heat dissipation fins 5B1 and four notched heat dissipation fins 5B2 (5B3) of the second embodiment shown in Figs. 16 to 18, or the structure including the plurality of normal heat dissipation fins 5C1 and four notched heat dissipation fins 5C2 shown in Figs. 19 and 20.

[0351] In the fifth embodiment, the heat sink integrated power semiconductor modules HM51 to HM56 are on the windward side, and the heat sink integrated power semiconductor modules HM61 to HM64 (HM60) are on the leeward side, but the present invention is not limited to this classification.

[0352] It is expected that a similar effect can be obtained by adopting a structure having at least one pair of deformed heat dissipation fins 71X, 71X for at least one of the heatsink-integrated power semiconductor modules HM51 to HM56 and HM61 to HM64 (HM60) that is upwind of the heatsink-integrated power semiconductor module HM61 to HM64 (HM60) that is furthest downwind with respect to the flow velocity vector 1 indicating the direction of air inflow and outflow.

[0353] (Manufacturing Method) Figures 33 and 34 are explanatory diagrams showing a basic manufacturing method, which is the basic manufacturing method for semiconductor device 105 or semiconductor device 105B according to embodiment 5, respectively. An XYZ orthogonal coordinate system is depicted in each of Figures 33 and 34. These figures show the basic manufacturing method for the heatsink-integrated power semiconductor module HM shown in Figure 28. Note that, since the basic manufacturing method is the same for semiconductor device 105 and semiconductor device 105B, the following description will be given as the basic manufacturing method for the heatsink-integrated power semiconductor module HM shown in Figure 38.

[0354] In the semiconductor device 105, the second main surface of the fin base 48, which is a first-type or second-type intermediate combined body, is textured. That is, the fin base 48 has a textured area on the second main surface. The heat sink portion HK, which is a first-type or second-type heat sink, includes a heat sink base 70 having a first main surface and a second main surface, and a plurality of heat dissipation fins 71 provided on the second main surface side of the heat sink base 70.

[0355] A portion of the first main surface of the heat sink base 70 is textured. That is, the fin base 48 has a textured area on the second main surface in the central upward protruding area. The power semiconductor module portion MM is classified as a first-type semiconductor module or a second-type semiconductor module, and the multiple heat dissipation fins 71 are classified as multiple first-type heat dissipation fins or multiple second-type heat dissipation fins.

[0356] The basic manufacturing method of the semiconductor device 105 includes the following steps (a) and (b).

[0357] Step (a) is a step of fixing a power semiconductor module part MM onto a first main surface of a fin base 48 having a first main surface and a second main surface, to obtain a fin-based power semiconductor module part MMF, as shown in Figure 33. The fin-based power semiconductor module part MMF becomes a module part intermediate structure.

[0358] Step (a) is described in detail below. A plurality of semiconductor elements 36 are die-bonded to metal conductors 39 using a bonding material 37 such as solder, and the semiconductor elements 36 and the metal conductors 39, as well as the metal conductors 39, are connected by wire bonding using wiring 38 such as aluminum. Note that some of the plurality of metal conductors 39 become main terminals 391 and control terminals 392.

[0359] Thereafter, the fin base-equipped power semiconductor module portion MMF can be obtained by providing a fin base 48 to which an insulating material 40 such as an insulating sheet is temporarily attached and a metal conductor 39 to which the die bonding and wire bonding described above have been completed, covered with a sealing material 42 such as epoxy resin. The multiple semiconductor elements 36 may be any semiconductor elements, such as Si-based semiconductor elements, SiC-based semiconductor elements, or compound semiconductor elements such as GaN.

[0360] Step (b) is a step in which the heat sink portion HK is supported by a press load receiving device 31 from the second main surface side of the heat sink base 70, and a press load PL2 is applied to the fin-based power semiconductor module portion MMF from the first main surface side of the heat sink base 70, as shown in FIG.

[0361] 33 and 34 , the press load receiver 31 has a support base 310 and a plurality of partial support portions 311. The plurality of partial support portions 311 are each erected from the support base 310 toward the second main surface side of the heat sink base 70.

[0362] The plurality of partial support parts 311 correspond one-to-one to the plurality of cooling air passage regions 111, and by inserting the plurality of partial support parts 311 into the corresponding cooling air passage regions 111, the heat sink base 70 of the heat sink part HK can be supported from the second main surface side when step (b) is performed. Note that if the heat sink part HK is a second-class heat sink, the cooling air passage region 111 is replaced with a cooling air passage region 112.

[0363] By performing the above-mentioned step (b), the uneven area on the second main surface of the fin base 48 and the uneven area on the first main surface of the heat sink base 70 are fitted together and bonded, thereby obtaining the heat sink-integrated power semiconductor module HM shown in Figure 28.

[0364] As described above, the press load PL2 is applied with multiple partial support parts 311 inserted into multiple cooling air passage areas 111 formed between multiple heat dissipation fins 71, so deformation of the heat sink base 70 when the press load PL2 is applied can be suppressed, and the press load PL2 can be applied to the uneven areas of the fin base 48 and the uneven areas of the heat sink base 70.

[0365] Therefore, the uneven areas of the fin base 48 and the heat sink base 70 can be integrated with sufficient surface pressure remaining as residual stress, resulting in a sufficiently small contact thermal resistance.

[0366] By carrying out the basic manufacturing method of the semiconductor device 105 having the above-mentioned steps (a) and (b), it is possible to obtain the semiconductor device 105 or the semiconductor device 105B of the fifth embodiment, which has a heatsink-integrated power semiconductor module HM having a structure in which the heatsink portion HK and the power semiconductor module portion MM are integrated.

[0367] The basic manufacturing method involves performing the above-mentioned step (b) to integrate the fin base 48 and the heat sink base 70 by press processing, so there is a risk of damage to the multiple semiconductor elements 36 during press processing, cracks or changes in the characteristics of each of the multiple semiconductor elements 36, cracks in the sealing material 42, a decrease in pressure resistance, and peeling between components within the sealing material 42.

[0368] Considering this risk, it is desirable to keep the press load PL2 as low as possible when integrating the fin base 48 and the heat sink base 70. The fin base 48 is produced by cutting, die-casting, forging, extrusion, or the like, and is made of aluminum or an aluminum alloy.

[0369] (First Improved Manufacturing Method) In the basic manufacturing method described above, when mounting the heat sink portion HK on the press load receiver 31, it is necessary to insert the plurality of partial support portions 311 into the plurality of cooling air passage regions 111 of the plurality of heat dissipation fins 71 of the heat sink portion HK, which raises concerns about reduced productivity. This concern will be explained below.

[0370] To improve the heat dissipation performance of the heat sink portion HK, a required number of heat dissipation fins 71 are provided, and therefore the fin spacing S11 of the cooling air passage area 111 is relatively narrow. When performing step (b), the partial support parts 311 must be inserted into the cooling air passage areas 111 all at once, which reduces workability and productivity. On the other hand, if the thickness, which is the width of each of the partial support parts 311 formed in the X direction, is reduced to facilitate insertion into the cooling air passage areas 111, the partial support parts 311 are more likely to buckle.

[0371] Conversely, if the fin spacing S11 of the cooling air passage area 111 is set wide, workability and productivity during execution of step (b) will improve, but the heat dissipation performance of the heat sink portion HK will deteriorate due to the reduced number of multiple heat dissipation fins 71. For this reason, a trade-off occurs in which it is desirable to make the fin spacing S11 of the multiple cooling air passage areas 111 formed by the multiple heat dissipation fins 71 as narrow as possible and to make the thickness of the multiple partial support portions 311 as thick as possible.

[0372] Due to the trade-off relationship described above, the basic manufacturing method has the above-mentioned concern of reduced productivity. The first improved manufacturing method described below aims to resolve this concern.

[0373] 35 and 36 are explanatory diagrams showing a first improved manufacturing method of the semiconductor device 105. Figures 37 and 38 are explanatory diagrams showing problems with the first improved manufacturing method. An XYZ orthogonal coordinate system is shown in each of Figures 35 to 38.

[0374] 35 and 36, in the first improved manufacturing method, a press load receiver 32 is used in place of the press load receiver 31. The press load receiver 32 has a support base 320 and a peripheral support portion 321.

[0375] The peripheral support portion 321 corresponds to the peripheral region of the heat sink base 70, and stands from the support base 320 toward the peripheral region of the heat sink base 70. No heat dissipation fins 71 are formed in the peripheral region of the heat sink base 70. The peripheral region may be, for example, the two end regions of the heat sink base 70 in the X direction.

[0376] That is, the press load receiver 32 supports the heat sink base 70 in a peripheral region where the heat dissipation fins 71 are not mounted, and receives the press load PL2. Therefore, the press load receiver 32 makes it easy to mount the heat sink portion HK on the peripheral support portion 321, and has a jig configuration that is highly productive.

[0377] However, since the press load receiver 32 is configured to receive the press load PL2 only in the peripheral region of the heat sink base 70, the heat sink base 70 is prone to elastic and plastic deformation during and after the press process. Specifically, as shown in Figure 37, when the press load PL2 is received, the heat sink base 70 deforms into a deformed heat sink base shape 170.

[0378] If the heat sink base 70 undergoes elastic deformation during press processing and plastic deformation after press processing, sufficient surface pressure will not be applied between the uneven areas of the fin base 48 and the uneven areas of the heat sink base 70, resulting in increased contact thermal resistance and making it impossible to obtain the desired thermal resistance.

[0379] 38, the heatsink mounting frame 4D is usually fixed with screws at the four corners of each of the heatsink-integrated power semiconductor modules HM51 to HM56 and HM61 to HM64, i.e., through holes 49 provided in the four corners of the heatsink base 70. If the heatsink base 70 is plastically deformed after press working, the positions of the through holes 49 provided in the heatsink base 70 and the screw holes in the heatsink mounting frame 4D will become misaligned, which may result in the modules being unable to be fixed to the heatsink mounting frame 4D, or may be able to be fixed but with reduced workability and productivity.

[0380] As described above, the first improved method still has some problems to solve. The second to fourth improved methods described below aim to solve these problems.

[0381] (Second Improved Manufacturing Method) Figures 39 and 40 are explanatory diagrams showing a second improved manufacturing method for semiconductor device 105. An XYZ Cartesian coordinate system is shown in each of Figures 39 and 40. As shown in these figures, the third improved manufacturing method uses a press load receiver 33 that is compatible with the structure of the heat sink portion HK5.

[0382] The heat sink portion HK5 corresponds to the heat sink portions HK51 to HK56 of the heat sink-integrated power semiconductor modules HM51 to HM56, respectively. That is, the heat sink portion HK5 is a general term for the heat sink portions HK51 to HK56.

[0383] The heat sink portion HK5 has a plurality of heat dissipation fins 71, each of which includes two pairs of adjacent modified heat dissipation fins 71X and 71X. Of the plurality of heat dissipation fins 71, the heat dissipation fins 71 other than the two pairs of modified heat dissipation fins 71X and 71X are normal heat dissipation fins 71n.

[0384] The gap between the two pairs of modified heat dissipation fins 71X and 71X forms two cooling air passage regions 115, and the two cooling air passage regions 115 form at least one type 1 wide region, which is classified as a type 1 wide region. The spacing between the cooling air passage regions 115 in the X direction, which is the fin formation direction, is the wide fin spacing S15.

[0385] On the other hand, the gap regions between adjacent normal heat dissipation fins 71n and 71n form a plurality of cooling air passage regions 111, which are classified as type 1 narrow regions. The spacing between the cooling air passage regions 111 in the X direction is the fin spacing S11. The wide fin spacing S15 is wider than the fin spacing S11.

[0386] As shown in FIGS. 39 and 40, the press load receiver 33 has a support base 330 , a peripheral support portion 331 , and two intermediate support portions 332 .

[0387] The peripheral support portion 331 corresponds to the peripheral region of the heat sink base 70 and stands from the support base 330 toward the peripheral region of the heat sink base 70. No heat dissipation fins 71 are formed in the peripheral region of the heat sink base 70. The peripheral region may be, for example, both end regions of the heat sink base 70 in the X direction.

[0388] The two intermediate support parts 332 correspond one-to-one to the two cooling air passage areas 115 and are erected from the support base 310 toward the second main surface side of the heat sink base 70. When step (b) shown in the basic manufacturing method is performed, the two intermediate support parts 332 are inserted into the two corresponding cooling air passage areas 115.

[0389] That is, when step (b) is performed, the press load receiving device 33 supports the peripheral areas on the second main surface of the heat sink base 70, which are the areas at both ends where the heat dissipation fins 71 are not mounted, with the peripheral support parts 331, and supports the areas corresponding to the two cooling air passage areas 115 with the two intermediate support parts 332.

[0390] When step (b) is performed, the second main surface of the heat sink base 70 is supported by a limited number of peripheral support portions 331 and two intermediate support portions 332. Therefore, when step (b) is performed, productivity can be improved compared to the basic manufacturing method shown in Figures 33 and 34.

[0391] Furthermore, since the second main surface of the heat sink base 70 is supported by the peripheral support portion 331 and the two intermediate support portions 332, elastic deformation and plastic deformation of the heat sink base 70 can be suppressed during the press processing when step (b) is performed and after the press processing of step (b).

[0392] As a result, the contact thermal resistance between the uneven area provided on the second main surface of the fin base 48 and the uneven area provided on the first main surface of the heat sink base 70 is reduced, and the thermal resistance of the entire completed heat sink-integrated power semiconductor module HM is reduced, thereby improving the quality of the semiconductor device 105.

[0393] 34 and 35, it is possible to apply the press load PL1 in a support manner similar to that of the second improved manufacturing method. However, if the plurality of heat dissipation fins 71 are composed of only normal heat dissipation fins, that is, if there is no cooling air passage area 115 at all, the thickness of the support portion corresponding to the intermediate support portion 332 (hereinafter abbreviated as "member corresponding to the intermediate support portion") will be thin, and there is a possibility that the member corresponding to the intermediate support portion will buckle when subjected to the press load PL1 (PL2).

[0394] On the other hand, in the second improved manufacturing method shown in Figures 39 and 40, two intermediate support parts 332 are inserted into two cooling air passage areas 115 having a relatively wide fin spacing S15, so the thickness of each of the two intermediate support parts 332 that receive the press load PL1 can be set wide, and the heat sink base 70 can be stably supported by a limited number of intermediate support parts 332.

[0395] The two intermediate support parts 332, which are at least one intermediate support part in the press load receiving tool 33 used in the second improved manufacturing method, support the second main surface of the heat sink base 70 via the corresponding one of the two cooling air passage areas 115.

[0396] Therefore, when step (b) is performed, the heat sink portion HK5 can be stably supported from the second main surface side of the heat sink base 70 by multiple support parts consisting of the two intermediate support parts 342 and the peripheral support part 341.

[0397] As a result, the quality of the semiconductor device 105 manufactured by the second improved manufacturing method can be improved.

[0398] 39 and 40, when there are two peripheral support portions 331 corresponding to the end regions of the heat sink base 70, the press load PL1 is supported on four surfaces together with the two intermediate support portions 332. In this case, simultaneous contact on all four surfaces may not be possible due to machining tolerances on the jig side, tolerances of the heat sink, and process variations. The third improved manufacturing method described below improves on this point.

[0399] 41 and 42 are explanatory diagrams showing a third improved manufacturing method of the semiconductor device 105. An XYZ Cartesian coordinate system is shown in each of Figs. 41 and 42. As shown in these figures, a press load receiver 34 adapted to the structure of the heat sink portion HK5 is used.

[0400] As shown in FIGS. 41 and 42, the press load receiver 34 has a support base 340 , a peripheral support portion 341 , and two intermediate support portions 342 .

[0401] The peripheral support portion 341 corresponds to the peripheral region of the heat sink base 70, and stands from the support base 340 toward the peripheral region of the heat sink base 70. No heat dissipation fins 71 are formed in the peripheral region of the heat sink base 70.

[0402] The two intermediate support parts 342 correspond to the two cooling air passage areas 115 and are erected from the support base 310 toward the second main surface side of the heat sink base 70. When step (b) shown in the basic manufacturing method is performed, the two intermediate support parts 342 are inserted into the two corresponding cooling air passage areas 115.

[0403] Each of the two intermediate support parts 342 has a support part main body 342A and an elastic member 342B, and the support part main body 342A contacts the second main surface of the heat sink base 70, while the elastic member 342B is interposed between the support base 340 and the support part main body 342A and has elastic force.

[0404] When step (b) is performed, the press load receiver 34 having such a structure supports the peripheral area on the second main surface of the heat sink base 70 where the heat dissipation fins 71 are not mounted with the peripheral support portion 341, and supports the area corresponding to the two cooling air passage areas 115 with the two intermediate support portions 342.

[0405] Therefore, like the second improved manufacturing method, the third improved manufacturing method is an aspect in which two intermediate support parts 342 are inserted into two cooling air passage areas 115 having a relatively wide fin spacing S15. Therefore, by increasing the thickness of the two intermediate support parts 342 that receive the press load PL1, the heat sink base 70 can be stably supported by a limited number of intermediate support parts 342.

[0406] Additionally, in the third improved manufacturing method, when the second main surface of the heatsink base 70 is supported by the two intermediate support parts 342, an elastic member 342B having elasticity is provided between the support part main body 342A and the support base 340. Therefore, the contact surface between the upper end of the support part main body 342A and the second main surface of the heatsink base 70 at the two intermediate support parts 342 is stabilized, thereby making it possible to effectively suppress elastic deformation and plastic deformation of the heatsink base 70.

[0407] In this way, the two intermediate support portions 342 of the press load receiver 34 used in the third improved manufacturing method each have an elastic member 342B interposed between the support base 340 and the support portion main body 342A and having elastic force, so that variation between the two intermediate support portions 342 can be suppressed regarding the contact state between the support portion main body 342A and the second main surface of the heat sink base 70 when step (b) is performed.

[0408] Therefore, the quality of the semiconductor device 105 manufactured by the third improved manufacturing method can be improved.

[0409] 43 and 44 are explanatory diagrams showing a fourth improved manufacturing method of the semiconductor device 105. An XYZ Cartesian coordinate system is shown in each of Figs. 43 and 44. As shown in these figures, a press load receiver 35 adapted to the structure of the heat sink portion HK5B is used.

[0410] The heat sink portion HK5B corresponds to the heat sink portions HK51 to HK56 of the heat sink-integrated power semiconductor modules HM51 to HM56, respectively, and has a modified structure of a plurality of heat dissipation fins. In other words, the heat sink portion HK5B is a general term for the modified structures of the heat sink portions HK51 to HK56.

[0411] The heat sink portion HK5B has a plurality of heat dissipation fins 73, including a pair of adjacent modified heat dissipation fins 73X and 73X. Of the plurality of heat dissipation fins 73, the heat dissipation fins 73 other than the pair of modified heat dissipation fins 73X and 73X are normal heat dissipation fins 73n.

[0412] The pair of modified heat dissipation fins 73X and 73X are provided in the central region of the second main surface of the heat sink base 70. The gap region between the pair of modified heat dissipation fins 73X and 73X forms one cooling air passage region 117, and one cooling air passage region 117 is classified as at least one type 1 wide region. The spacing in the X direction between the cooling air passage regions 117 is the wide fin spacing S17.

[0413] On the other hand, the gap regions between adjacent normal heat dissipation fins 73n and 73n form multiple cooling air passage regions 111, which are classified as multiple type 1 narrow regions. The spacing between the cooling air passage regions 111 in the X direction is the fin spacing S11. The wide fin spacing S17 is wider than the fin spacing S11.

[0414] As shown in FIGS. 43 and 44, the press load receiver 35 has a support base 350 , peripheral support portions 351 and one intermediate support portion 352 .

[0415] The peripheral support portion 351 corresponds to the peripheral region of the heat sink base 70, and stands from the support base 350 toward the peripheral region of the heat sink base 70. No heat dissipation fins 73 are formed in the peripheral region of the heat sink base 70.

[0416] The intermediate support part 352 corresponds to the cooling air passage area 117 and stands upright from the support base 310 toward the second main surface side of the heat sink base 70. When step (b) shown in the basic manufacturing method is performed, the central intermediate support part 352 is inserted into the cooling air passage area 117.

[0417] The intermediate support portion 352 has a support portion main body 352A and an elastic member 352B, the support portion main body 352A contacts the second main surface of the heat sink base 70, and the elastic member 352B is interposed between the support base 350 and the support portion main body 352A and has elastic force.

[0418] When step (b) is performed, the press load receiving device 35 having such a structure supports the peripheral area on the second main surface of the heat sink base 70 where the heat dissipation fins 73 are not mounted with the peripheral support portion 351, and supports the area corresponding to the central cooling air passage area 117 with the intermediate support portion 352.

[0419] Therefore, like the second and third improved manufacturing methods, the fourth improved manufacturing method is an aspect in which the intermediate support parts 352 are inserted into the cooling air passage area 117 having a relatively wide fin spacing S17. Therefore, by increasing the thickness of the intermediate support parts 352 that receive the press load PL1, the heat sink base 70 can be stably supported by a limited number of intermediate support parts 352.

[0420] Additionally, in the fourth improved manufacturing method, when the intermediate support portion 352 supports the second main surface of the heatsink base 70, an elastic member 352B having elasticity is provided between the support portion main body 352A and the support base 350. Therefore, similar to the third improved manufacturing method, the fourth improved manufacturing method can effectively suppress elastic deformation and plastic deformation of the heatsink base 70 by stabilizing the contact surface between the upper end of the support portion main body 352A and the second main surface of the heatsink base 70 in the intermediate support portion 352.

[0421] In this way, the intermediate support portion 352 of the press load receiver 35 used in the fourth improved manufacturing method has an elastic member 352B interposed between the support base 350 and the support portion main body 352A and having elastic force, so that the quality of the semiconductor device 105 manufactured by the fourth improved manufacturing method can be improved, just like the semiconductor device 105 manufactured by the third improved manufacturing method.

[0422] Furthermore, as shown in FIGS. 43 and 44, the heat sink part HK5B to be manufactured is provided with a cooling air passage area 117 having a relatively wide fin spacing S17 corresponding to the central area of ​​the heat sink base 70.

[0423] Therefore, by using a press load receiving device 35 having a relatively thick rod-shaped support body 342A corresponding to the central region of the heat sink base 70, the effect of suppressing elastic deformation and plastic deformation of the heat sink base 70 can be improved.

[0424] Sixth Embodiment In the sixth embodiment, the semiconductor devices 101 to 105 according to the first to fifth embodiments described above are applied to a power conversion device. Although the present disclosure is not limited to a specific power conversion device, the sixth embodiment will be described below as a case where the present disclosure is applied to a three-phase inverter. In the following, the semiconductor device 101 according to the first embodiment will be described as a concept including the semiconductor device 101s, which is a modified example, and the semiconductor device 105 according to the fifth embodiment will be described as a device including the semiconductor device 105B, which is a modified example.

[0425] FIG. 45 is a block diagram illustrating a configuration of a power conversion system to which a power conversion device according to the sixth embodiment of the present disclosure is applied.

[0426] The power conversion system shown in Figure 45 is composed of a power supply 1000, a power conversion device 2000, and a load 3000. The power supply 1000 is a DC power supply and supplies DC power to the power conversion device 2000. The power supply 1000 can be composed of various components, such as a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit connected to an AC system or an AC / DC converter. The power supply 1000 may also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0427] The power conversion device 2000 is a three-phase inverter connected between the power supply 1000 and the load 3000, and converts DC power supplied from the power supply 1000 into AC power and supplies the AC power to the load 3000. As shown in Fig. 45 , the power conversion device 2000 includes a main conversion circuit 2001 that converts DC power into AC power and outputs it, and a control circuit 2003 that outputs a control signal to the main conversion circuit 2001 to control the main conversion circuit 2001.

[0428] The load 3000 is a three-phase electric motor driven by AC power supplied from the power conversion device 2000. The load 3000 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0429] The power conversion device 2000 will be described in detail below. The main conversion circuit 2001 includes switching elements and freewheel diodes (not shown), and converts DC power supplied from the power supply 1000 into AC power by switching the switching elements, and supplies the AC power to the load 3000. There are various specific circuit configurations for the main conversion circuit 2001, but the main conversion circuit 2001 according to this embodiment is a two-level, three-phase full-bridge circuit that can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. At least one of the switching elements and freewheel diodes of the main conversion circuit 2001 is configured by a type 1 semiconductor module or a type 2 semiconductor module used in the semiconductor devices 101 to 105 of the first to fifth embodiments described above.

[0430] The first type semiconductor modules include the power semiconductor modules M11 to M16 and the power semiconductor module M1 used in the first to third embodiments, the power semiconductor modules M51 to M56 used in the fourth embodiment, and the power semiconductor module portions MM51 to MM56 also used in the fifth embodiment.

[0431] The second type semiconductor modules include the power semiconductor modules M41 to M43 and the power semiconductor module M4 used in the first to third embodiments, the power semiconductor modules M61 to M64 used in the fourth embodiment, and the power semiconductor module portions MM61 to MM64 used in the fifth embodiment.

[0432] For example, when the first type semiconductor module is configured as the power semiconductor module Mi shown in FIG. 4, any one of the plurality of semiconductor elements 16 functions as the above-mentioned switching element or free wheel diode.

[0433] The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm forms one phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 2001, are connected to the load 3000.

[0434] Furthermore, the main conversion circuit 2001 includes a drive circuit (not shown) that drives each switching element, but the drive circuit may be built into the semiconductor module 2002, or the drive circuit may be provided separately from the semiconductor module 2002. The semiconductor module 2002 may be configured using the first-type semiconductor module or the second-type semiconductor module used in the semiconductor devices 101 to 105 of the first to fifth embodiments described above.

[0435] The drive circuit generates drive signals for driving the switching elements of the main conversion circuit 2001 and supplies them to the control electrodes of the switching elements of the main conversion circuit 2001. Specifically, in accordance with control signals from a control circuit 2003 (described later), the drive circuit outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0436] The control circuit 2003 controls the switching elements of the main conversion circuit 2001 so that the desired power is supplied to the load 3000. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 2001 should be in the on state based on the power to be supplied to the load 3000. For example, the main conversion circuit 2001 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 2003 then outputs a control command (control signal) to a drive circuit included in the main conversion circuit 2001 so that an on signal is output to a switching element that should be in the on state at each time point, and an off signal is output to a switching element that should be in the off state at each time point. In accordance with this control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0437] In the power conversion device 2000 of the sixth embodiment, the first-type semiconductor modules and the second-type semiconductor modules used in the semiconductor devices 101 to 105 of the first to fifth embodiments are applied as the switching elements and freewheel diodes of the main conversion circuit 2001, and therefore the power conversion device 2000 has a cooling function for the first-type semiconductor modules and the second-type semiconductor modules, and can achieve miniaturization of the device.

[0438] In the sixth embodiment, an example in which the present disclosure is applied to a two-level three-phase inverter has been described, but the present disclosure is not limited to this and can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be used. In addition, when power is supplied to a single-phase load, the present disclosure may also be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the present disclosure may also be applied to a DC / DC converter or an AC / DC converter.

[0439] Furthermore, the power conversion device to which the present disclosure is applied is not limited to cases in which the above-mentioned load is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, etc.

[0440] It should be noted that, within the scope of the present disclosure, it is possible to freely combine the embodiments, and to modify or omit the embodiments as appropriate.

[0441] Although the present disclosure has been described in detail, the above description is illustrative in all respects and does not limit the present disclosure to the above. It is understood that countless variations not illustrated can be envisioned without departing from the scope of the present disclosure.

[0442] Various aspects of the present disclosure are summarized below as appendices.

[0443] (Supplementary Note 1) A semiconductor device comprising: a first-type heat sink; a second-type heat sink; a first-type semiconductor module mounted on the first-type heat sink; and a second-type semiconductor module mounted on the second-type heat sink, wherein the first-type heat sink has a plurality of first-type heat dissipation fins, each of the plurality of first-type heat dissipation fins having a first-type formation depth extending in a formation depth direction on a side opposite to a mounting surface of the first-type semiconductor module and a first-type formation width extending in the fin formation direction, the plurality of first-type heat dissipation fins being arranged discretely from one another along a fin arrangement direction intersecting with the fin formation direction, and gap regions between the plurality of first-type heat dissipation fins being first-type cooling air passage regions, the second-type heat sink has a plurality of second-type heat dissipation fins, each of which has a second-type formation depth extending in the formation depth direction and a second-type formation width extending in the fin formation direction, the plurality of second-type heat dissipation fins being arranged discretely from one another along the fin arrangement direction, and gap regions between the plurality of second-type heat dissipation fins being second-type cooling air passing regions; the semiconductor device has a cooling air supply structure that supplies cooling air to the first and second-type heat sinks in an air flow direction along the fin formation direction, the cooling air being supplied so as to pass through the first-type cooling air passing region and then the second-type cooling air passing region; the first-type cooling air passing region includes a plurality of first-type narrow regions and at least one first-type wide region, the plurality of first-type narrow regions each having a first-type narrow spacing and the at least one first-type wide region each having a first-type wide spacing; the second-class cooling air passage area includes a plurality of second-class width areas, each of the plurality of second-class width areas having a second-class width interval, and the first-class wide interval is set wider than the first-class narrow interval so that a temperature rise of the cooling air when it reaches the plurality of second-class heat dissipation fins during operation of the semiconductor device is suppressed.

[0444] (Supplementary Note 2) A semiconductor device as described in Supplementary Note 1, wherein the plurality of first-type heat dissipation fins include a plurality of normal heat dissipation fins and at least one pair of adjacent deformed heat dissipation fins, the at least one first-type wide region corresponds one-to-one with the at least pair of deformed heat dissipation fins, each of the at least one first-type wide region being a gap region between a corresponding pair of deformed heat dissipation fins of the at least pair of deformed heat dissipation fins, the first-type wide spacing being a spacing along the fin arrangement direction for each of the at least pair of deformed heat dissipation fins, the first-type narrow region being a gap region between adjacent normal heat dissipation fins of the plurality of normal heat dissipation fins, and the first-type narrow spacing being a spacing along the fin arrangement direction between adjacent normal heat dissipation fins of the plurality of normal heat dissipation fins.

[0445] (Supplementary Note 3) A semiconductor device according to Supplementary Note 1, wherein the plurality of first-type heat dissipation fins include a plurality of normal heat dissipation fins and at least one notched heat dissipation fin, and the at least one notched heat dissipation fin has a notched region; among the plurality of first-type heat dissipation fins, a pair of heat dissipation fins adjacent to each of the at least one notched heat dissipation fin in the fin arrangement direction are defined as at least a pair of adjacent heat dissipation fins; the first-type wide region includes a region between each of the at least pair of adjacent heat dissipation fins via the notched region, and the first-type wide spacing is a spacing along the fin arrangement direction between each of the at least one adjacent heat dissipation fin; the first-type narrow region is a gap region between adjacent normal heat dissipation fins among the plurality of normal heat dissipation fins, and the first-type narrow spacing is a spacing along the fin arrangement direction between adjacent normal heat dissipation fins among the plurality of normal heat dissipation fins.

[0446] (Appendix 4) A semiconductor device according to Appendix 3, wherein each of the plurality of normal heat dissipation fins has a normal depth in the formation depth direction, each of the at least one notched heat dissipation fin has a deformation region in the formation depth direction that has a deformation depth shallower than the normal depth, the first type formation depth includes the normal depth and the deformation depth, and the notch region includes an empty region in the deformation region of each of the at least one notched heat dissipation fin from the deformation depth to the normal depth.

[0447] (Supplementary Note 5) The semiconductor device according to Supplementary Note 4, wherein each of the at least one notched heat dissipation fins further includes a normal region having the normal depth in the formation depth direction.

[0448] (Supplementary Note 6) The semiconductor device according to Supplementary Note 4, wherein each of the at least one notched heat dissipation fins has only the deformation region.

[0449] (Supplementary Note 7) A semiconductor device according to Supplementary Note 3, wherein the plurality of normal heat dissipation fins each have a normal width in the fin formation direction, the at least one notched heat dissipation fin each has a deformed width in the fin formation direction, the first type formation width includes the normal width and the deformed width, and the deformed width is narrower than the normal width, and the notched region includes a non-fin formation region in which the plurality of normal heat dissipation fins are present in the fin formation direction and the at least one notched heat dissipation fin is not present.

[0450] (Appendix 8) A semiconductor device according to any one of Appendices 1 to 7, wherein the first-type heat sink includes a plurality of first-type heat sinks, the first-type semiconductor module includes a plurality of first-type semiconductor modules, the plurality of first-type heat sinks and the plurality of first-type semiconductor modules are in a one-to-one correspondence, and each of the plurality of first-type semiconductor modules is mounted on a corresponding one of the plurality of first-type heat sinks, the second-type heat sink includes a plurality of second-type heat sinks, and the second-type semiconductor module includes a plurality of second-type semiconductor modules, the plurality of second-type heat sinks and the plurality of second-type semiconductor modules are in a one-to-one correspondence, and each of the plurality of second-type semiconductor modules is mounted on a corresponding one of the plurality of second-type heat sinks.

[0451] (Supplementary Note 9) A semiconductor device according to any one of Supplementary Notes 1 to 8, further comprising: a mounting plate on which the first-class heat sink and the second-class heat sink are mounted; and a housing supporting the mounting plate in a manner that accommodates the plurality of first-class heat dissipation fins and the plurality of second-class heat dissipation fins, and the cooling air supply structure includes a cooling fan that blows the cooling air in the air blowing direction.

[0452] (Appendix 10) A semiconductor device according to any one of appendices 1 to 7, further comprising a first-type intermediate assembly provided between the first-type heat sink and the first-type semiconductor module, the first-type intermediate assembly having a first main surface and a second main surface, wherein the first-type semiconductor module is attached to the first main surface side of the first-type intermediate assembly and the first-type heat sink is attached to the second main surface side of the first-type intermediate assembly, thereby forming a first-type heat sink-integrated power semiconductor module.

[0453] (Appendix 11) The semiconductor device according to appendix 10, further comprising a second-type intermediate coupling body provided between the second-type heat sink and the second-type semiconductor module, the second-type intermediate coupling body having a first main surface and a second main surface, wherein the second-type semiconductor module is coupled to the first main surface side of the second-type intermediate coupling body and the second-type heat sink is coupled to the second main surface side of the second-type intermediate coupling body, thereby forming a second-type heat sink-integrated power semiconductor module.

[0454] (Supplementary Note 12) A semiconductor device according to Supplementary Note 11, wherein the first-type heat sink includes a plurality of first-type heat sinks, the first-type intermediate combination body includes a plurality of first-type intermediate combination bodies, the first-type semiconductor module includes a plurality of first-type semiconductor modules, and the plurality of first-type heat sinks, the plurality of first-type intermediate combination bodies, and the plurality of first-type semiconductor modules correspond one-to-one, the first-type heat sink-integrated power semiconductor module includes a plurality of first-type heat sink-integrated power semiconductor modules, and each of the plurality of first-type heat sink-integrated power semiconductor modules includes a corresponding first-type semiconductor module, a corresponding first-type intermediate combination body, and a corresponding first-type heat sink among the plurality of first-type semiconductor modules, the plurality of first-type intermediate combination bodies, and the plurality of first-type heat sinks, the second-type heat sink includes a plurality of second-type heat sinks, and the second-type intermediate combination body includes a plurality of second-type intermediate combination bodies, a semiconductor device, wherein the second-type semiconductor module includes a plurality of second-type semiconductor modules, and the plurality of second-type heat sinks, the plurality of second-type intermediate combinations, and the plurality of second-type semiconductor modules correspond one-to-one; the second-type heat sink-integrated power semiconductor module includes a plurality of second-type heat sink-integrated power semiconductor modules, and each of the plurality of second-type heat sink-integrated power semiconductor modules includes a corresponding second-type semiconductor module, a corresponding second-type intermediate combination, and a corresponding second-type heat sink among the plurality of second-type semiconductor modules, the plurality of second-type intermediate combinations, and the plurality of second-type heat sinks.

[0455] (Appendix 13) A method for manufacturing a semiconductor device, wherein the semiconductor device includes the semiconductor device described in Appendix 9, comprising: (a) a step of fixing the mounting plate to the housing; (b) a step of mounting the first-type heat sink and the second-type heat sink on the mounting plate in a manner such that the plurality of first-type heat dissipation fins and the plurality of second-type heat dissipation fins are accommodated within the housing; and (c) a step of mounting the first-type semiconductor module on the first-type heat sink and the second-type semiconductor module on the second-type heat sink.

[0456] (Supplementary Note 14) A method for manufacturing a semiconductor device, wherein the semiconductor device includes the semiconductor device according to any one of Supplementary Note 10 to Supplementary Note 12, wherein the second main surface of the first-type intermediate combined body is textured, and the first-type heat sink includes a heat sink base having a first main surface and a second main surface, and the plurality of first-type heat dissipation fins provided on the second main surface side of the heat sink base, the first main surface of the heat sink base being textured, and the method for manufacturing a semiconductor device includes the steps of: (a) fixing the first-type semiconductor module on the first main surface of the first-type intermediate combined body to obtain a module portion intermediate structure; and (b) supporting the first-type heat sink from the second main surface side of the heat sink base with a press load receiver, and applying a press load to the module portion intermediate structure from the first main surface side of the heat sink base, and by performing step (b), the second main surface of the first-type intermediate combined body and the first main surface of the heat sink base are fitted together and bonded to obtain the first-type heat sink-integrated power semiconductor module.

[0457] (Supplementary Note 15) A method for manufacturing a semiconductor device according to Supplementary Note 14, wherein the plurality of first-type heat dissipating fins include a plurality of normal heat dissipating fins and at least one pair of adjacent modified heat dissipating fins, the at least one first-type wide region corresponds one-to-one with the at least pair of modified heat dissipating fins, the at least one first-type wide region is a gap region between a corresponding pair of modified heat dissipating fins of the at least pair of modified heat dissipating fins, and the first-type wide spacing is a spacing along the fin arrangement direction for each of the at least pair of modified heat dissipating fins, the first-type narrow region is a gap region between adjacent normal heat dissipating fins of the plurality of normal heat dissipating fins, and the first-type narrow spacing is a spacing along the fin arrangement direction between adjacent normal heat dissipating fins of the plurality of normal heat dissipating fins, the press load receiver includes a support base and a plurality of support parts erected from the support base toward the second main surface of the heat sink base, the plurality of support parts including at least one intermediate support part, the at least one intermediate support part corresponding one-to-one with the at least one first-type wide region, When performing step (b), the at least one intermediate support portion supports the second main surface of the heat sink base via a corresponding one of the at least one first-type wide region.

[0458] (Appendix 16) A method for manufacturing a semiconductor device according to Appendix 15, wherein each of the at least one intermediate support portion includes a support body that contacts the second main surface of the heat sink base, and an elastic member that is interposed between the support base and the support body and has elastic force.

[0459] (Supplementary Note 17) A power conversion device comprising: a main conversion circuit having the semiconductor device according to any one of Supplementary Note 1 to Supplementary Note 12, which converts input power and outputs the converted power; and a control circuit which outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

[0460] 2 Cooling fan, 3 Housing, 4, 4D, 4E Heat sink mounting frame, 5, 5B, H51 to H56 Type 1 heat sink, 6, 6B, H61 to H64 Type 2 heat sink, 5B0, 5C0, 6B0, 51 to 55, 70, 530, 540, 610, 620, 630 Heat sink base, 5B1, 5C1, 61n, 71n, 73n, 531n, 541n Normal heat dissipation fin, 5B2, 5B3, 5C2 Notched heat dissipation fin, 6B1, 6C1, 61 to 65, 71, 73, 531, 541, 611, 621, 631 Heat dissipation fin, 31 to 35 Press load receiver, 61X, 71X, 73X, 531X, 541X Deformed heat dissipation fin, 101, 101s, 102 to 105, 105B semiconductor device, 1000 power supply, 2000 power conversion device, 2001 main conversion circuit, 2002 semiconductor module, 2003 control circuit, 3000 load, HK, HK5, HK5B, HK7, HK51 to HK56, HK61 to HK64 heat sink portion, HM, HM51 to HM56, HM60 to HM64 heat sink integrated power semiconductor module, M1, M4, M11 to M16, M41 to M43, M51 to M56, MM51 to MM56, M61 to M64, MM61 to MM64, Mi, Mj, Mk power semiconductor module, MM, MM51 to MM56, MM61 to MM64 Power semiconductor module part.

Claims

1. A first type heat sink; A second type heat sink; a first type semiconductor module mounted on the first type heat sink; a second type semiconductor module mounted on the second type heat sink, the first-type heat sink has a plurality of first-type heat dissipation fins, each of the plurality of first-type heat dissipation fins having a first-type formation depth extending in a formation depth direction on a side opposite to a mounting surface of the first-type semiconductor module and a first-type formation width extending in the fin formation direction, the plurality of first-type heat dissipation fins being arranged discretely from one another along a fin arrangement direction intersecting with the fin formation direction, and gap regions between the plurality of first-type heat dissipation fins being first-type cooling air passing regions; the second-type heat sink has a plurality of second-type heat dissipation fins, each of the plurality of second-type heat dissipation fins having a second-type formation depth extending in the formation depth direction and a second-type formation width extending in the fin formation direction, the plurality of second-type heat dissipation fins are arranged discretely from one another along the fin arrangement direction, and gap regions between the plurality of second-type heat dissipation fins are second-type cooling air passage regions; The semiconductor device includes: a cooling air supply structure for supplying cooling air to the first and second heat sinks in a blowing direction along the fin formation direction, the cooling air being supplied to pass through the first type cooling air passing area and then the second type cooling air passing area; the first type cooling air passage region includes a plurality of first type narrow regions and at least one first type wide region, the plurality of first type narrow regions each having a first type narrow interval, and the at least one first type wide region each having a first type wide interval, the second type cooling air passage region includes a plurality of second type width regions, each of the plurality of second type width regions having a second type width interval; In the first type cooling air passage area, the first type wide interval is set wider than the first type narrow interval. Semiconductor device.

2. 2. The semiconductor device according to claim 1, The first type of heat dissipating fins include a plurality of normal heat dissipating fins and at least a pair of modified heat dissipating fins adjacent to each other, The at least one first type wide region corresponds to the at least one pair of modified heat dissipating fins one-to-one, the at least one first type wide region is a gap region between a corresponding pair of modified heat dissipating fins of the at least one pair of modified heat dissipating fins, and the first type wide interval is an interval along the fin arrangement direction of each of the at least one pair of modified heat dissipating fins, The first type narrow region is a gap region between adjacent normal heat dissipation fins among the plurality of normal heat dissipation fins, and the first type narrow interval is an interval along the fin arrangement direction between adjacent normal heat dissipation fins among the plurality of normal heat dissipation fins. Semiconductor device.

3. 2. The semiconductor device according to claim 1, The plurality of first type heat dissipating fins include a plurality of normal heat dissipating fins and at least one notched heat dissipating fin, and the at least one notched heat dissipating fin has a notched region; Among the plurality of first type heat dissipation fins, a pair of heat dissipation fins adjacent to each of the at least one notched heat dissipation fins in the fin arrangement direction are defined as at least a pair of adjacent heat dissipation fins, the first type wide region includes a region between each of the at least one pair of adjacent heat dissipation fins via the notch region, and the first type wide interval is an interval between each of the at least one adjacent heat dissipation fins along the fin arrangement direction, The first type narrow region is a gap region between adjacent normal heat dissipation fins among the plurality of normal heat dissipation fins, and the first type narrow interval is an interval along the fin arrangement direction between adjacent normal heat dissipation fins among the plurality of normal heat dissipation fins. Semiconductor device.

4. 4. The semiconductor device according to claim 3, Each of the plurality of normal heat dissipation fins has a normal depth in the formation depth direction, Each of the at least one notched heat dissipation fins has a deformation region having a deformation depth shallower than the normal depth in the formation depth direction, the first type forming depth includes the normal depth and the deformation depth, The cutout region includes an empty region from the deformation depth to the normal depth in the deformation region of each of the at least one cutout heat dissipation fins. Semiconductor device.

5. 5. The semiconductor device according to claim 4, Each of the at least one notched heat dissipation fins further includes a normal region having the normal depth in the formation depth direction. Semiconductor device.

6. 5. The semiconductor device according to claim 4, Each of the at least one notched heat dissipating fins has only the deformation region; Semiconductor device.

7. 4. The semiconductor device according to claim 3, Each of the plurality of normal heat dissipation fins has a normal width in the fin formation direction, Each of the at least one notched heat dissipation fins has a deformation width in the fin formation direction, the first type forming width includes the normal width and the modified width, the modified width being narrower than the normal width, The cutout region includes a fin non-forming region in which the plurality of normal heat dissipating fins are present in the fin forming direction and the at least one cutout heat dissipating fin is not present. Semiconductor device.

8. 8. The semiconductor device according to claim 1, the first type heat sink includes a plurality of first type heat sinks; the first type semiconductor module includes a plurality of first type semiconductor modules, the plurality of first type heat sinks and the plurality of first type semiconductor modules correspond one-to-one to each other, and the plurality of first type semiconductor modules are mounted on corresponding one of the plurality of first type heat sinks; the second type heat sink includes a plurality of second type heat sinks; the second type semiconductor module includes a plurality of second type semiconductor modules, the plurality of second type heat sinks and the plurality of second type semiconductor modules are in one-to-one correspondence, and the plurality of second type semiconductor modules are mounted on corresponding ones of the plurality of second type heat sinks; Semiconductor device.

9. 8. The semiconductor device according to claim 1, a mounting plate on which the first type heat sink and the second type heat sink are mounted; a housing that supports the mounting plate in a manner to accommodate the plurality of first-type heat dissipation fins and the plurality of second-type heat dissipation fins; The cooling air supply structure includes a cooling fan that blows the cooling air in the blowing direction. Semiconductor device.

10. 8. The semiconductor device according to claim 1, a first type intermediate coupling body provided between the first type heat sink and the first type semiconductor module and having a first main surface and a second main surface; a first-type heat sink-integrated power semiconductor module is configured by coupling the first-type semiconductor module to a first main surface side of the first-type intermediate assembly and coupling the first-type heat sink to a second main surface side of the first-type intermediate assembly, Semiconductor device.

11. 11. The semiconductor device according to claim 10, a second type intermediate coupling body provided between the second type heat sink and the second type semiconductor module and having a first main surface and a second main surface; a second-type heat sink-integrated power semiconductor module is configured by coupling the second-type semiconductor module to a first main surface side of the second-type intermediate assembly and coupling the second-type heat sink to a second main surface side of the second-type intermediate assembly, Semiconductor device.

12. 12. The semiconductor device according to claim 11, the first type heat sink includes a plurality of first type heat sinks; the first type intermediate conjugate comprises a plurality of first type intermediate conjugates; the first type semiconductor module includes a plurality of first type semiconductor modules, the plurality of first type heat sinks, the plurality of first type intermediate combination bodies, and the plurality of first type semiconductor modules are in one-to-one correspondence; the first type heat sink integrated power semiconductor module includes a plurality of first type heat sink integrated power semiconductor modules, Each of the plurality of first-type heat sink integrated power semiconductor modules includes a corresponding first-type semiconductor module, a corresponding first-type intermediate combination body, and a corresponding first-type heat sink among the plurality of first-type semiconductor modules, the plurality of first-type intermediate combination bodies, and the plurality of first-type heat sinks; the second type heat sink includes a plurality of second type heat sinks; the second type intermediate conjugate comprises a plurality of second type intermediate conjugates; the second type semiconductor module includes a plurality of second type semiconductor modules, the plurality of second type heat sinks, the plurality of second type intermediate combination bodies, and the plurality of second type semiconductor modules are in one-to-one correspondence; the second type heat sink integrated power semiconductor module includes a plurality of second type heat sink integrated power semiconductor modules, Each of the plurality of second-type heat sink integrated power semiconductor modules includes a corresponding second-type semiconductor module, a corresponding second-type intermediate combination body, and a corresponding second-type heat sink among the plurality of second-type semiconductor modules, the plurality of second-type intermediate combination bodies, and the plurality of second-type heat sinks; Semiconductor device.

13. 8. The semiconductor device according to claim 1, The first type wide interval is set to be two or more times and three or less times the first type narrow interval. Semiconductor device.

14. A semiconductor device according to any one of claims 1 to 7, the plurality of first-type narrow regions are arranged only in a region facing the first-type semiconductor module mounted on the first-type heat sink, the at least one first type wide region is disposed on both ends of the plurality of first type narrow regions; Semiconductor device.

15. A semiconductor device according to any one of claims 1 to 7, The cooling air is supplied so as to pass through the at least one first type wide region and then pass through the plurality of second type wide regions. Semiconductor device.

16. A method for manufacturing a semiconductor device, comprising: The semiconductor device includes the semiconductor device according to claim 9, (a) fastening the mounting plate to the housing; (b) mounting the first type heat sink and the second type heat sink on the mounting plate in a manner such that the plurality of first type heat dissipation fins and the plurality of second type heat dissipation fins are housed within the housing; (c) mounting the first type semiconductor module on the first type heat sink and mounting the second type semiconductor module on the second type heat sink. A method for manufacturing a semiconductor device.

17. A method for manufacturing a semiconductor device, comprising: The semiconductor device includes the semiconductor device according to claim 10, The second main surface of the first type intermediate bond is textured, the first type heat sink includes a heat sink base having a first main surface and a second main surface, and the plurality of first type heat dissipation fins provided on the second main surface side of the heat sink base, the first main surface of the heat sink base being textured, (a) fixing the first type semiconductor module onto a first main surface of the first type intermediate assembly to obtain a module portion intermediate structure; (b) supporting the first type heat sink from a second main surface side of the heat sink base with a press load receiver and applying a press load to the module portion intermediate structure from a first main surface side of the heat sink base, By carrying out the step (b), the second main surface of the first type intermediate assembly and the first main surface of the heat sink base are fitted together and joined to obtain the first type heat sink integrated power semiconductor module. A method for manufacturing a semiconductor device.

18. 18. A method for manufacturing a semiconductor device according to claim 17, comprising the steps of: The first type of heat dissipating fins include a plurality of normal heat dissipating fins and at least a pair of modified heat dissipating fins adjacent to each other, The at least one first type wide region corresponds to the at least one pair of modified heat dissipating fins one-to-one, the at least one first type wide region is a gap region between a corresponding pair of modified heat dissipating fins of the at least one pair of modified heat dissipating fins, and the first type wide interval is an interval along the fin arrangement direction of each of the at least one pair of modified heat dissipating fins, the first type narrow region is a gap region between adjacent normal heat dissipation fins among the plurality of normal heat dissipation fins, and the first type narrow interval is an interval along the fin arrangement direction between adjacent normal heat dissipation fins among the plurality of normal heat dissipation fins, The press load receiver is A support base; a plurality of support portions extending from the support base toward a second main surface side of the heat sink base, The plurality of support portions include at least one intermediate support portion, and the at least one intermediate support portion corresponds one-to-one to the at least one first type wide region; During the execution of step (b), the at least one intermediate support portion supports the second main surface of the heat sink base via a corresponding one of the at least one first type wide region. A method for manufacturing a semiconductor device.

19. 20. The method of manufacturing a semiconductor device according to claim 18, further comprising the steps of: Each of the at least one intermediate support portions comprises: a support body in contact with the second main surface of the heat sink base; An elastic member having an elastic force is interposed between the support base and the support body, A method for manufacturing a semiconductor device.

20. A main conversion circuit having the semiconductor device according to any one of claims 1 to 7, which converts input power and outputs the converted power; a control circuit for outputting a control signal for controlling the main conversion circuit to the main conversion circuit, Power conversion equipment.