Semiconductor device

Abstract

Provided is a semiconductor device with which it is possible to improve the reliability of insulation around a bonding wire. This semiconductor device comprises: a semiconductor chip (3) having a first main electrode (31) on the upper surface side and a second main electrode (33) on the lower surface side; a bonding wire (4b) connected to the first main electrode (31); an insulating layer (9b) covering the outer periphery of the bonding wire (4b); and a sealing member (7) for sealing the semiconductor chip (3), the bonding wire (4b) and the insulating layer (4b). The ratio of the Young's modulus of the insulating layer (9b) to the Young's modulus of the sealing member (7) is 10 or more.

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device (semiconductor module).

[0002] Patent Document 1 discloses coating the connection portion of a bonding wire on a chip with a resin. Patent Document 2 discloses that an aluminum wire bonded to a semiconductor element is coated with a primer layer, and the aluminum wire coated with the primer layer is covered with a first sealing layer. Patent Document 3 discloses a circuit board having a semiconductor element mounted via a bonding wire and the semiconductor element and bonding wire coated with a resin coating material, and the surface of the resin coating material is covered with a silicone gel.

[0003] Patent Document 4 discloses a power semiconductor device in which a semiconductor element and aluminum wires are sealed with epoxy resin and then sealed with a silicone gel-based resin to cover the epoxy resin. Patent Document 5 discloses that bonding wires connected to a semiconductor element are coated with resin. Patent Document 6 discloses that bonding wires connected between a substrate and a case and their connection portions are coated with a resin that is harder than the gel.

[0004] Patent Document 7 discloses a semiconductor device including wiring connected to a semiconductor element, a resin sealing member that seals the semiconductor element, and a semiconducting film that covers at least a portion of the wiring and is disposed between at least a portion of the wiring and the resin sealing member. Patent Document 8 discloses a semiconductor device including a bonding wire bonded to a semiconductor element, a resin layer that covers a bonding portion of the bonding wire on the surface of the semiconductor element, and a gel filler that seals the semiconductor element, the bonding wire, and the resin layer.

[0005] Patent Document 9 discloses a bonding wire for semiconductor elements, which includes a bonding wire and a copper ion diffusion suppression layer covering the surface of the bonding wire. Patent Document 10 discloses coating a bonding wire with a foamed polymer. Patent Document 11 discloses a coated wire in which a core wire is coated with a coating resin. Patent Document 12 discloses a semiconductor device in which a metal terminal and a lead of a semiconductor chip are connected by the coated wire, and the coated wire and the connection portion of the coated wire are covered with resin.

[0006] Patent Document 13 discloses a coated wire in which a core wire is coated with a coating resin. Patent Documents 14 and 15 each disclose connecting a metal terminal and a lead of a semiconductor chip using a coated wire in which the surface of a metal wire is coated with an insulating coating film. Patent Document 16 discloses a semiconductor device having a bonding wire that connects a substrate and a semiconductor element, a first sealing layer that seals a space below the apex of the bonding wire, and a second sealing layer provided on top of the first sealing layer via the bonding wire.

[0007] JP 2007-012831 A JP 2021-150466 A JP 2000-228482 A JP 2012-15222 A JP 2019-9171 A JP 2022-7343 A JP 2017-224778 A JP 2017-147327 A JP 2012-231034 A JP 2002-170842 A JP 9-260414 A JP 8-316264 A JP 2-304943 A JP 2-266541 A JP 63-318132 A International Publication No. 2019 / 31513

[0008] When voids occur around bonding wires connected to a semiconductor chip or the like due to air bubbles inside the sealing member or peeling of the sealing member, the electric field strength increases in the voids, reducing insulation reliability.

[0009] In view of the above-mentioned problems, an object of the present disclosure is to provide a semiconductor device that can improve the insulation reliability around bonding wires.

[0010] One aspect of the present disclosure is a semiconductor device comprising: a semiconductor chip having a first main electrode on its upper surface side and a second main electrode on its lower surface side; a bonding wire connected to the first main electrode; an insulating layer covering the outer periphery of the bonding wire; and a sealing member that seals the semiconductor chip, the bonding wire, and the insulating layer, wherein the ratio of the Young's modulus of the insulating layer to the Young's modulus of the sealing member is 10 or greater.

[0011] According to the present disclosure, it is possible to provide a semiconductor device that can improve the insulation reliability around the bonding wires.

[0012] 1 is a cross-sectional view of an example of a semiconductor device according to an embodiment; 2 is a perspective view of another example of a semiconductor device according to an embodiment; 3 is a schematic view of a bonding wire, an insulating layer, and a sealing member according to an embodiment; 4 is a graph showing the relationship between the coating thickness and the electric field strength of a bonding wire according to an embodiment; and 5 is a graph showing the relationship between the wire diameter and the electric field strength of a bonding wire according to an embodiment.

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, identical or similar parts are designated by identical or similar reference numerals, and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc. may differ from the actual ones. Furthermore, parts with different dimensional relationships and ratios may be included between the drawings. Furthermore, the embodiments shown below are examples of devices and methods for embodying the technical idea of ​​the present disclosure, and the technical idea of ​​the present disclosure does not specify the materials, shapes, structures, arrangements, etc. of component parts to those described below.

[0014] Furthermore, the definitions of directions such as up / down and left / right in the following explanation are merely for the convenience of explanation and do not limit the technical idea of ​​the present disclosure. For example, if an object is rotated 90 degrees and observed, up / down is converted to left / right and read as such, and if it is rotated 180 degrees and observed, up / down is obviously read as reversed.

[0015] In the following description, the "first main electrode" of a semiconductor chip refers to an electrode through which a main current flows in or out of the semiconductor chip. If the semiconductor chip is a field-effect transistor (FET) or a static induction transistor (SIT), the "first main electrode" refers to either the source electrode or the drain electrode, if the semiconductor chip is an insulated gate bipolar transistor (IGBT), the "first main electrode" refers to either the emitter electrode or the collector electrode, and if the semiconductor chip is a static induction (SI) thyristor or a gate turn-off (GTO) thyristor, the "first main electrode" refers to either the anode electrode or the cathode electrode. Furthermore, the "second main electrode" of a semiconductor chip means either a source electrode or a drain electrode that does not become the first main electrode if the semiconductor chip is an FET or SIT; it means either an emitter electrode or a collector electrode that does not become the first main electrode if the semiconductor chip is an IGBT; and it means either an anode electrode or a cathode electrode that does not become the first main electrode if the semiconductor chip is an SI thyristor or GTO thyristor. That is, if the "first main electrode" of a semiconductor chip is a source electrode, the "second main electrode" means a drain electrode. If the "first main electrode" of a semiconductor chip is an emitter electrode, the "second main electrode" means a collector electrode. If the "first main electrode" of a semiconductor chip is an anode electrode, the "second main electrode" means a cathode electrode.

[0016] (Embodiment) <Configuration of Semiconductor Device> As shown in FIG. 1 , a semiconductor device (semiconductor module) according to an embodiment includes an insulating circuit board 1 and a power semiconductor chip (semiconductor chip) 3 provided on one main surface (top surface) of the insulating circuit board 1 via a bonding layer 2. A case 5 is disposed to surround the outer periphery of the insulating circuit board 1, the bonding layer 2, and the semiconductor chip 3. Terminals (external connection terminals) 6a and 6b are attached to the case 5. The insulating circuit board 1, the semiconductor chip 3, and the external connection terminals 6a and 6b are electrically connected to one another via bonding wires 4a to 4c. A sealing member (sealing resin) 7 is provided inside the case 5 to seal the insulating circuit board 1, the bonding layer 2, the semiconductor chip 3, the bonding wires 4a to 4c, the insulating layers 9a to 9c, etc.

[0017] The insulating circuit board 1 is configured, for example, as a direct copper bond (DCB) board or an activated metal brazing (AMB) board. The insulating circuit board 1 includes an insulating plate 10, conductive layers 11a and 11b provided on one main surface (upper surface) of the insulating plate 10, and a conductive layer 12 provided on the other main surface (lower surface) of the insulating plate 10. The insulating plate 10 is made of, for example, aluminum oxide (Al ２ O ３ ), aluminum nitride (AlN), silicon nitride (Si ３ N ４ The conductive layers 11a, 11b, and 12 are made of, for example, a conductor foil made of copper (Cu) or aluminum (Al).

[0018] The bonding layer 2 is made of, for example, solder or a sintered material, etc. Examples of solder that can be used include lead-free solders such as tin-antimony (Sn—Sb)-based, tin-copper (Sn—Cu)-based, tin-copper-silver (Sn—Cu-Ag)-based, tin-silver (Sn—Ag)-based, tin-silver-copper (Sn—Ag-Cu)-based, tin-silver-bismuth-copper (Sn—Ag-Bi-Cu)-based, tin-indium-silver-bismuth (Sn—In-Ag-Bi)-based, tin-zinc (Sn—Zn)-based, tin-zinc-bismuth (Sn—Zn-Bi)-based, tin-bismuth (Sn—Bi)-based, and tin-indium (Sn—In)-based solders, and lead solders such as tin-lead (Sn—Pb)-based solders. The sintered material is formed by sintering, for example, a sheet-like sintered sheet or a paste-like conductive paste containing fine metal particles of gold (Au), silver (Ag), copper (Cu), etc., with a particle size of several nanometers to several micrometers, and an organic component (binder), by applying pressure while heating.

[0019] The semiconductor chip 3 is configured by, for example, an insulated gate bipolar transistor (IGBT), a field effect transistor (FET), a static induction (SI) thyristor, a gate turn-off (GTO) thyristor, a free wheel diode (FWD), or the like. Here, the case where the semiconductor chip 3 is a MOSFET is illustrated. The semiconductor chip 3 may be configured on, for example, a silicon (Si) substrate, or may be configured on a silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga２ O ３ ), or may be configured on a semiconductor substrate using a wide band gap semiconductor such as diamond.

[0020] The maximum rated voltage of the semiconductor chip 3 is, for example, about 1.7 kV or more. The maximum rated voltage of the semiconductor chip 3 may be about 1.7 kV or less, or about 3.3 kV or more. The higher the maximum rated voltage of the semiconductor chip 3, the greater the insulation distance required between each member.

[0021] The semiconductor chip 3 has a first main electrode (source electrode) 31 and a gate electrode 32 on one main surface (upper surface) side, and a second main electrode (drain electrode) 33 on the other main surface (lower surface) side. The second main electrode 33 is bonded to the conductive layer 11a via the bonding layer 2. While one semiconductor chip 3 is shown as an example in Figure 1, the number of semiconductor chips can be set appropriately depending on the current capacity of the semiconductor module, and two or more semiconductor chips may be included.

[0022] The case 5 is made of a thermoplastic resin such as polyphenylene sulfide (PPS) or polybutylene terephthalate (PBT).

[0023] The external connection terminals 6a, 6b are made of a metal material such as copper (Cu) or aluminum (Al). The external connection terminals 6a, 6b can be connected to an external circuit. The shape, arrangement, and number of the external connection terminals 6a, 6b are not particularly limited. The external connection terminals 6a, 6b may be bonded to the conductive layers 11a, 11b via a bonding layer such as solder or a sintered material, without using the bonding wires 4a, 4c.

[0024] One end of the bonding wire 4a is connected to the conductive layer 11a, and the other end of the bonding wire 4a is connected to the external connection terminal 6a. The second main electrode 33 of the semiconductor chip 3 is electrically connected to the external connection terminal 6a via the conductive layer 11a and the bonding wire 4a.

[0025] One end of the bonding wire 4b is connected to the first main electrode 31 of the semiconductor chip 3, and the other end of the bonding wire 4b is connected to the conductive layer 11b. One end of the bonding wire 4c is connected to the conductive layer 11b, and the other end of the bonding wire 4c is connected to the external connection terminal 6b. The first main electrode 31 of the semiconductor chip 3 is electrically connected to the external connection terminal 6b via the bonding wire 4b, the conductive layer 11b, and the bonding wire 4c.

[0026] Although not shown in FIG. 1, the gate electrode 32 of the semiconductor chip 3 is electrically connected to another external connection terminal (not shown) that can be connected to an external circuit via a bonding wire (not shown) or the like.

[0027] 1, the potential of the bonding wire 4a is the same as that of the external connection terminal 6a electrically connected to the second main electrode 33 of the semiconductor chip 3, but is a different potential from that of the external connection terminal 6b electrically connected to the first main electrode 31 of the semiconductor chip 3. The potentials of the bonding wires 4b and 4c are the same as that of the external connection terminal 6b, but are a different potential from that of the external connection terminal 6a.

[0028] For example, the bonding wire 4a may be located at a distance of about 5 mm or less via the sealing member 7 to the external connection terminal 6b having a potential different from that of the bonding wire 4a. The bonding wires 4b and 4c may be located at a distance of about 5 mm or less via the sealing member 7 to the external connection terminal 6a having a potential different from that of the bonding wires 4b and 4c.

[0029] The bonding wires 4a to 4c are made of a metal material such as copper (Cu), aluminum (Al), or gold (Au). The diameter of the bonding wires 4a to 4c is, for example, approximately 125 μm or more and 500 μm or less. The diameter of the bonding wires 4a to 4c may be approximately 400 μm or less, or may be approximately 300 μm or less. The smaller the diameter of the bonding wires 4a to 4c, the smaller the pads to which the bonding wires 4a to 4c are connected, allowing for a smaller element size. On the other hand, the smaller the diameter of the bonding wires 4a to 4c, the higher the electric field strength around the bonding wires 4a to 4c, and therefore the greater the required insulation distance between the bonding wires 4a to 4c and each component.

[0030] The sealing member 7 is made of a resin material such as gel silicone (silicone gel) or fluorine-based gel. The Young's modulus of the sealing member 7 is, for example, about 1 kPa or more and 100 kPa or less. The relative dielectric constant of the sealing member 7 is, for example, about 3 or more and 5 or less.

[0031] The sealing member 7 functions to mechanically protect the internal circuitry from foreign matter and the like. For example, if a conductive foreign matter adheres between exposed circuits, the circuitry will short-circuit and fail. Even foreign matter with low conductivity can cause a short-circuit failure due to tracking. Covering the internal circuitry with the sealing member 7 can prevent such failures.

[0032] The sealing member 7 also functions to insulate between electrodes (between circuits). The sealing member 7 covers and fills the circuit surface including the element surface, bonding wire surface, and terminal surface, and between electrodes (between circuits), thereby ensuring insulation reliability. Insulation between electrodes using the sealing member 7 can significantly shorten the insulation distance compared to insulation using air, allowing for miniaturization of the module through high-density packaging.

[0033] The silicone gel and other gels that make up the sealing member 7 are soft and highly conformable, making them difficult to peel off, but they are highly hygroscopic (moisture permeable), making them prone to forming air bubbles inside. Making the sealing member 7 harder can prevent air bubbles from forming, but it also reduces its conformability to the bonding wires 4a-4c, making it more susceptible to peeling. Furthermore, there are countless tiny gaps in the joints between the sealing member 7 and other components, making it technically difficult to completely eliminate gaps during construction. Furthermore, filling the gaps with resin increases the stress during thermal cycles, increasing the risk of damage during heat cycles and power cycles. It is also difficult to completely fill the gaps in large modules.

[0034] Because the silicone gel or other gel that constitutes the sealing member 7 has a higher dielectric constant than air, if a gap occurs between the electrodes due to air bubbles inside the sealing member 7 or peeling of the sealing member 7, the electric field strength increases in the gap, reducing insulation reliability. For example, if a gap occurs, the discharge inception voltage decreases to about one-third. In particular, because the electric field is likely to concentrate on the surfaces of the bonding wires 4a to 4c, the discharge inception voltage decreases to about one-sixth of that in other regions. Furthermore, the thinner the bonding wires 4a to 4c, the lower the insulation performance becomes.

[0035] If the maximum rated voltage of the semiconductor chip 3 is about 1.7 kV or less, even if a gap is formed between the electrodes, the insulation distance required for the bonding wires 4 a to 4 c is relatively small, so there are few design (miniaturization) constraints. However, if the maximum rated voltage of the semiconductor chip 3 is a high withstand voltage of 3.3 kV or more, the insulation distance required for the bonding wires 4 a to 4 c with a diameter of about 300 μm becomes larger than the insulation distance required for the bonding wires 4 a to 4 c with a diameter of about 125 μm when the maximum rated voltage is about 1.7 kV or less, which becomes an obstacle to miniaturization.

[0036] For example, if the distance between the different potentials of the bonding wires 4a to 4c is short, such as 5 mm or less, the electric field strength increases, and if air bubbles form around the bonding wires 4a to 4c, the insulation performance deteriorates significantly, increasing the risk of discharge and short-circuit failure. While the risk of short-circuit failure due to air bubble formation can be reduced by increasing the distance between the different potentials of the bonding wires 4a to 4c, it is becoming increasingly difficult to ensure sufficient insulation distance due to the increasing use of high voltages, miniaturization, and high-density packaging. While using thicker bonding wires is effective in reducing the electric field, this increases the chip area and cost, and it is also necessary to avoid damage to the pads to which the bonding wires are connected.

[0037] Therefore, in the semiconductor device according to the embodiment, the outer peripheries of the bonding wires 4a to 4c are coated with insulating layers (coating layers) 9a to 9c. The insulating layers 9a to 9c contain at least one type of resin selected from, for example, polyamide resin, polyimide resin, polyamideimide resin, polyester resin, epoxy resin, phenolic resin, fluororesin, acrylic resin, silicone resin, polyolefin resin, and polyetherimide resin. The insulating layers 9a to 9c may contain two or more types of resin selected from the above resins.

[0038] As a method for forming the insulating layers 9a-9c around the bonding wires 4a-4c, the insulating layers 9a-9c may be formed by spray coating, immersion (dip) coating, dispense coating, or the like after bonding the bonding wires 4a-4c to the first main electrodes 31, conductive layers 11a and 11b, external connection terminals 6a and 6b, etc. of the semiconductor chip 3. Alternatively, the bonding wires 4a-4c, such as enameled wires, that are previously coated with the insulating layers 9a-9c may be prepared, and the bonding wires 4a-4c may be bonded to the first main electrodes 31, conductive layers 11a and 11b, external connection terminals 6a and 6b, etc. of the semiconductor chip 3, respectively.

[0039] 1 illustrates a case in which all of the bonding wires 4a to 4c are covered with insulating layers 9a to 9c, but only some of the bonding wires 4a to 4c may be covered with insulating layers. For example, when the bonding wire 4b is close to a different potential portion such as an external connection terminal 6a that has a different potential from that of the bonding wire 4b, only the bonding wire 4b close to the different potential portion may be covered with insulating layer 9b. By selectively covering only some of the bonding wires 4a to 4c with insulating layers, material costs and process costs can be reduced.

[0040] The insulating layers 9a to 9c are harder than the sealing member 7, and the Young's modulus of the insulating layers 9a to 9c is higher than that of the sealing member 7. The Young's modulus of the insulating layers 9a to 9c is, for example, about 100 kPa or more and 10 GPa or less, and more preferably about 100 kPa or more and 1 GPa or less. When the Young's modulus of the insulating layers 9a to 9c is 100 kPa or more, the generation of bubbles inside the insulating layers 9a to 9c can be effectively suppressed. When the Young's modulus of the insulating layers 9a to 9c is 1 GPa or less, the followability of the insulating layers 9a to 9c to the bonding wires 4a to 4c can be effectively ensured.

[0041] The ratio of the Young's modulus of the insulating layers 9a to 9c to the Young's modulus of the sealing member 7 is, for example, about 10 or more. By making the ratio of the Young's modulus of the insulating layers 9a to 9c to the Young's modulus of the sealing member 7 10 or more, it is possible to effectively suppress the generation of bubbles inside the insulating layers 9a to 9c.

[0042] The dielectric constants of the insulating layers 9a to 9c may be higher or lower than the relative dielectric constant of the sealing member 7. The lower the relative dielectric constant of the insulating layers 9a to 9c, the more the electric field strength can be alleviated even when air bubbles are generated inside the sealing member 7, creating an air layer with a dielectric constant of 1. The relative dielectric constant of the insulating layers 9a to 9c is, for example, approximately 7 or less, and more preferably approximately 3 or less. By setting the relative dielectric constant of the insulating layers 9a to 9c to 7 or less, the electric field strength can be alleviated even when air bubbles are generated inside the sealing member 7. By setting the relative dielectric constant of the insulating layers 9a to 9c to 3 or less, the electric field strength can be further reduced even when air bubbles are generated inside the sealing member 7. Lowering the relative dielectric constant of the insulating layers 9a to 9c is a technical concept opposite to that of stepped insulation, in which insulating layers with higher dielectric constants are stacked closer to the core material, thereby averaging the electric field strength applied to each layer.

[0043] The smaller the ratio of the dielectric constant of the insulating layers 9a to 9c to the dielectric constant of the sealing member 7, the more the electric field strength on the surface side (sealing member 7 side) of the insulating layers 9a to 9c can be alleviated. The ratio of the dielectric constant of the insulating layers 9a to 9c to the dielectric constant of the sealing member 7 is, for example, about 3 or less. By making the ratio of the dielectric constant of the insulating layers 9a to 9c to the dielectric constant of the sealing member 7 3 or less, the electric field strength on the surface side of the insulating layers 9a to 9c can be effectively alleviated. The ratio of the dielectric constant of the insulating layers 9a to 9c to the dielectric constant of the sealing member 7 may be about 2 or less, about 1 or less, or about 0.5 or less.

[0044] The thickness of the insulating layers 9a-9c can be adjusted by adjusting the viscosity of the insulating layers 9a-9c before curing, the pull-up speed in the case of dip coating, or the number of applications in the case of spray coating or dip coating. The thickness of the insulating layers 9a-9c may be substantially constant, or may be variable and have thick and thin portions. The thicker the insulating layers 9a-9c, the more the electric field strength on the surface side (the sealing member 7 side) of the insulating layers 9a-9c can be reduced. The thickness of the insulating layers 9a-9c is, for example, approximately 25 μm or more and 500 μm or less. By making the thickness of the insulating layers 9a-9c 25 μm or more, the electric field strength on the surface side of the insulating layers 9a-9c can be effectively reduced.

[0045] A heat dissipation base 8 is provided on the other main surface (lower surface) of the insulating circuit board 1 via a bonding layer 14. The bonding layer 14 is made of, for example, a sintered material or solder. The bonding layer 14 may be made of the same material as the bonding layer 2, or may be made of a different material. The heat dissipation base 8 is made of, for example, a metal such as copper (Cu).

[0046] Heat dissipation fins 13 are provided on the lower surface of the heat dissipation base 8 via a bonding layer 15. It is also possible to provide the heat dissipation fins 13 on the lower surface of the insulating circuit board 1 via a bonding layer 15 without providing the heat dissipation base 8. It is also possible to not provide the heat dissipation fins 13 and have the lower surfaces of the heat dissipation fins 13 exposed.

[0047] The heat dissipation fin 13 is made of a metal such as copper (Cu). The bonding layer 15 is made of a sintered material, solder, or thermal interface material (TIM). Examples of TIM that can be used include thermally conductive materials (thermal compounds) such as thermally conductive grease, elastomer sheets, room temperature vulcanization (RTV) rubber, gel, phase change materials, and silver solder. The bonding layer 15 may be made of the same material as the bonding layers 2 and 14, or may be made of a different material.

[0048] 2 is a perspective view of another example of a semiconductor device according to an embodiment. A plurality of semiconductor chips 3a-3d are provided on the upper surface of conductive layer 11a via bonding layers 2a-2d. An external connection terminal 6a is provided on the upper surface of conductive layer 11a via bonding layer 2e. An external connection terminal 6b is provided on the upper surface of conductive layer 11b via bonding layer 2f. A case 5 is provided to surround conductive layers 11a and 11b, bonding layers 2a-2f, and semiconductor chips 3a-3d. In FIG. 2, the sealing member 7 that fills the inside of case 5 and seals conductive layers 11a and 11b, bonding layers 2a-2f, and semiconductor chips 3a-3d is not shown.

[0049] The bonding wires 4a, each covered with the insulating layer 9a, electrically connect the first main electrode on the upper surface of the semiconductor chip 3a, the first main electrode on the upper surface of the semiconductor chip 3c, and the conductive layer 11b. The bonding wires 4b, covered with the insulating layer 9b, electrically connect the first main electrode on the upper surface of the semiconductor chip 3b, the first main electrode on the upper surface of the semiconductor chip 3d, and the conductive layer 11b.

[0050] 2, the bonding wires 4a, 4b have the same potential as the external connection terminal 6b electrically connected to the first main electrode on the upper surface of the semiconductor chips 3a to 3d, and have a different potential from the external connection terminal 6a electrically connected to the second main electrode on the lower surface of the semiconductor chips 3a to 3d. The bonding wires 4a, 4b may be located approximately 5 mm or less away from the external connection terminal 6a, which has a different potential from the bonding wires 4a, 4b, via the sealing member 7. For example, only one of the bonding wires 4a closest to the external connection terminal 6a may be located approximately 5 mm or less away from the external connection terminal 6a and covered with an insulating layer 9a, while the other bonding wires 4a, 4b may be located more than 5 mm away from the external connection terminal 6a and not covered with an insulating layer.

[0051] 3 shows the bonding wire 4a, insulating layer 9a, and sealing member 7 in a longitudinal cross section of the bonding wire 4a, and the sealing member 7 is modeled as a cylinder coaxial with the bonding wire 4a. The outer peripheral surface of the sealing member 7 corresponds to the surface of the terminal at a different potential. The electric field concentration around the bonding wire 4a is maximized.

[0052] In FIG. 3, ε1 is the relative dielectric constant of the insulating layer 9a, ε2 is the relative dielectric constant of the sealing member 7, a is the radius of the bonding wire 4a, b is the distance between the center of the bonding wire 4a and the terminal surface, and c is the outer radius of the insulating layer 9a.

[0053] Here, if the radius of the uncoated bonding wire is a' and the distance between the center of the uncoated bonding wire and the terminal surface is b', the electric field strength E(r) of the uncoated bonding wire can be expressed by the following equation (1):

[0054]

[0055] On the other hand, as shown in Figure 3, in a bonding wire 4a covered with an insulating layer 9a, the electric field strength E1(r) inside the insulating layer 9a and the electric field strength E2(r) outside the insulating layer 9a can be expressed by the following equations (2) and (3), respectively.

[0056]

[0057]

[0058] In the semiconductor device according to the embodiment, the coating thickness (c-a) of the insulating layer 9a is set so that E2(a, b, c, r=c)≦E(a', b', r=a'). This is particularly effective in regions where the distances (b-a) and (b'-a') between different potentials are approximately 5 mm or less.

[0059] 4 shows the relationship between the thickness of the insulating layer and the electric field strength on the surface side (the sealing member side) of the insulating layer when a voltage of 3.3 kV is applied between a bonding wire and a terminal at a different potential, with the distance between the bonding wire and the terminal being 5 mm, as an example of a semiconductor device according to the embodiment. The bonding wire diameters are 300 μm and 400 μm, and the ratios of the dielectric constant ε1 of the insulating layer to the dielectric constant ε2 of the sealing member (ε1 / ε2) are 0.5, 1, and 2.

[0060] 5 shows the relationship between the diameter of an uncoated bonding wire and the electric field strength on the surface side of the bonding wire when the distance between the bonding wire and the terminal of a different potential is 5 mm and 3.3 kV is applied between the bonding wire and the terminal as a comparative example of the semiconductor device according to the embodiment. For convenience, dashed auxiliary lines are added in FIGS. 4 and 5 to indicate the electric field strength positions corresponding to the diameters of the uncoated bonding wire of 400 μm and 500 μm in FIG. 5.

[0061] 4, for bonding wires coated with an insulating layer, whether the diameter is 300 μm or 400 μm, the thicker the insulating layer, the more the electric field strength can be alleviated. Also, for bonding wires coated with an insulating layer, whether the diameter is 300 μm or 400 μm, the smaller the ratio of the relative dielectric constant ε1 of the insulating layer to the relative dielectric constant ε2 of the sealing member (ε1 / ε2) is, the more the electric field strength can be alleviated.

[0062] As shown in Figures 4 and 5, in the case of a bonding wire coated with an insulating layer, where the ratio (ε1 / ε2) of the relative dielectric constant ε1 of the insulating layer to the relative dielectric constant ε2 of the sealing member is 0.5 and the diameter is 300 μm, if the thickness of the insulating layer is 25 μm or more, the electric field strength can be reduced to the same extent as in the case of an uncoated bonding wire with a diameter of 400 μm.

[0063] Furthermore, as shown in Figures 4 and 5, in the case of a bonding wire coated with an insulating layer, where the ratio (ε1 / ε2) of the relative dielectric constant ε1 of the insulating layer to the relative dielectric constant ε2 of the sealing member is 0.5 and the diameter is 300 μm, if the thickness of the insulating layer is 50 μm or more, the electric field strength can be reduced to the same extent as in the case of an uncoated bonding wire with a diameter of 500 μm.

[0064] Furthermore, as shown in Figures 4 and 5, in the case of a bonding wire coated with an insulating layer, where the ratio (ε1 / ε2) of the relative dielectric constant ε1 of the insulating layer to the relative dielectric constant ε2 of the sealing member is 0.5 and the diameter is 400 μm, if the thickness of the insulating layer is 25 μm or more, the electric field strength can be reduced to the same extent as in the case of an uncoated bonding wire with a diameter of 500 μm.

[0065] 1 and 2, the outer peripheries of the bonding wires 4a to 4c, where electric fields are likely to concentrate, are covered with insulating layers 9a to 9c, which are harder than the sealing member 7, such as silicone gel. This makes it possible to suppress the generation of air bubbles inside the insulating layers 9a to 9c, thereby suppressing the generation of air bubbles between the bonding wires 4a to 4c and the sealing member 7. Therefore, even if peeling of the sealing member 7 and the generation of air bubbles cannot be completely suppressed, the insulating layers 9a to 9c are present between the sealing member 7 and the bonding wires 4a to 4c, thereby improving insulation reliability.

[0066] For example, with uncoated bonding wires, bubbles generated in the sealing material near the bonding wire or at the interface between the sealing material and other materials cling to the bonding wire, forming voids around the bonding wire similar to those caused by peeling. In contrast, with the semiconductor device according to the embodiment, the outer peripheries of the bonding wires 4a to 4c are coated with insulating layers 9a to 9c, so bubbles generated at the interface between the sealing material and other materials do not reach the bonding wires. This also makes it possible to suppress the generation of bubbles near the bonding wires and the formation of voids.

[0067] Therefore, according to the semiconductor device of the embodiment, even if the maximum rated voltage of the semiconductor chip 3 is a high withstand voltage of about 3.3 kV or more, the same electric field relaxation effect as with thicker wires can be obtained without changing the wire diameter, making it possible to design a more compact semiconductor chip 3 with a maximum rated voltage of about 1.7 kV. For example, even if the maximum rated voltage of the semiconductor chip 3 is about 3.3 kV, relatively thin bonding wires 4a to 4c with a diameter of about 300 μm can be used, allowing the size of the gate pad used only for signal input on the element surface to be reduced. In particular, since the element size can be reduced for SiC elements, which are more expensive than Si elements, costs can be reduced.

[0068] Furthermore, according to the semiconductor device of the embodiment, the insulating layers 9a to 9c are provided only on the outer periphery of the bonding wires 4a to 4c, so even if the insulating layers 9a to 9c are harder than the sealing member 7, the insulating layers 9a to 9c can maintain their ability to conform to the bonding wires 4a to 4c, and peeling between the bonding wires 4a to 4c and the insulating layers 9a to 9c can be suppressed.

[0069] As described above, the present disclosure has been described by way of embodiments, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present disclosure. Various alternative embodiments, examples, and operating techniques will become apparent to those skilled in the art from this disclosure.

[0070] For example, the case where the bonding wires 4a to 4c included in the semiconductor device according to the embodiment are connected to the first main electrode 31, the conductive layers 11a and 11b, and the external connection terminals 6a and 6b of the semiconductor chip 3 has been exemplified, but the connection destinations of the bonding wires 4a to 4c are not limited to this and can be selected as appropriate. Furthermore, the number of bonding wires 4a to 4c included in the semiconductor device according to the embodiment is not limited to this and can be selected as appropriate.

[0071] Furthermore, the configurations disclosed in the embodiments can be appropriately combined within a range that does not cause contradictions. As such, the present disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of the present disclosure is defined only by the invention-specifying matters according to the scope of the claims that are appropriate from the above description.

[0072] REFERENCE SIGNS LIST 1...insulating circuit board 2, 2a to 2f...bonding layer 3, 3a to 3d...semiconductor chip 4a to 4c...bonding wire 5...case 6a, 6b...external connection terminal 7...sealing member 8...heat dissipation base 9a to 9c...insulating layer 10...insulating plate 11a, 11b, 12...conductive layer 13...heat dissipation fin 14, 15...bonding layer 31...first main electrode 32...gate electrode 33...second main electrode

Claims

1. A semiconductor chip having a first main electrode on the upper side and a second main electrode on the lower side, bonding wires connected to the first main electrode, an insulating layer covering the outer periphery of the bonding wires, a sealing member for sealing the semiconductor chip, the bonding wires, and the insulating layer, characterized in that a ratio of a Young's modulus of the insulating layer to a Young's modulus of the sealing member is 10 or more, and a ratio of a dielectric constant of the insulating layer to a dielectric constant of the sealing member is 3 or less. A semiconductor device.

2. The semiconductor device according to claim 1, wherein the Young's modulus of the insulating layer is 100 kPa or more and 10 GPa or less.

3. The semiconductor device according to claim 1 or 2, wherein the relative dielectric constant of the insulating layer is 7 or less.

4. The semiconductor device according to claim 1 or 2, wherein a diameter of the bonding wire is 300 μm or more.

5. The semiconductor device according to claim 1 or 2, wherein a thickness of the insulating layer is 25 μm or more.

6. The semiconductor device according to claim 1 or 2, wherein the thickness of the insulating layer is 500 μm or less.

7. The semiconductor device according to claim 1 or 2, wherein a maximum rated voltage of the semiconductor chip is 1.7 kV or more.

8. The semiconductor device according to claim 1 or 2, wherein the bonding wire is provided at a distance of 5 mm or less from a terminal having a potential different from that of the bonding wire through the sealing member.

9. The semiconductor device according to claim 8, wherein the second main electrode is electrically connected to the terminal.

10. The semiconductor device according to claim 1 or 2, wherein the insulating layer contains at least one resin selected from the group consisting of polyamide resin, polyimide resin, polyamideimide resin, polyester resin, epoxy resin, phenol resin, fluororesin, acrylic resin, silicone resin, polyolefin resin, and polyetherimide resin.

11. The semiconductor device according to claim 1 or 2, wherein the sealing member contains silicone gel or fluorine-based gel.

12. (Deleted)