Power Conversion Device

Abstract

The power conversion device includes a power converter (6) and a control device (5). The control device (5) includes: a first circulating current command generator (417) that generates a first circulating current command value for controlling the balance of the voltages of the energy storage elements (32) among the arms (13pu to 13nw); a second circulating current command generator (419) that generates a second circulating current command value having a frequency component that is an even multiple of the fundamental frequency of the AC system (2); and a circulating current control unit (421) that generates a circulating voltage command value so that the circulating current circulating in the power converter (6) follows the circulating current command value based on the first circulating current command value and the second circulating current command value. The second circulating current command generator (419) calculates a first control margin based on one or more representative values ​​of the voltages of the energy storage elements (32) and one or more representative command values ​​corresponding to the one or more representative values, and controls the amplitude of the second circulating current command value based on at least one first control margin.

Description

Technical Field

[0001] The present disclosure relates to a power conversion device.

Background Art

[0002] In recent years, a modular multilevel converter (MMC) is known as a high-voltage and large-capacity power conversion device applied to a high-voltage system such as a power grid. The MMC is composed of arms in which a plurality of unit converters called cells are cascade-connected. Each cell includes a plurality of semiconductor switches and capacitors, and outputs the voltage across the capacitor or zero voltage by turning on and off the semiconductor switches.

[0003] Capacitors are one of the factors that increase the size of the unit converter, and miniaturization is required. As a means of miniaturizing the capacitor, reducing the capacitance can be mentioned. However, when the capacitance is reduced, the voltage ripple applied to the capacitor increases. When the voltage ripple of the capacitor increases, a failure may occur due to exceeding the rated voltage of the capacitor, or there is a possibility that the desired voltage cannot be output. In order to suppress this voltage ripple, a method of flowing a circulating current including a frequency that is an even multiple of the frequency of the AC system in the power converter is known.

[0004] For example, the power conversion device according to Japanese Patent No. 7038936 (Patent Document 1) has a first control mode for controlling the circulating current so that an AC component having a frequency that is an even multiple of the frequency of the fundamental wave of the AC, excluding multiples of 3, is included in the circulating current flowing between the leg circuits of each phase in the power converter, and determines the validity or invalidity of the first control mode based on the voltage value of the energy storage element.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

[0006] The power converter described in Patent Document 1 executes a first control mode that controls the circulating current when the voltage value of the energy storage element exceeds a set threshold range. However, the amplitude of the circulating current is constant within the operating range in which it is necessary to flow. Therefore, the flow of more circulating current than necessary may lead to an increase in power loss in the power converter.

[0007] One objective of this disclosure is to provide a power converter that can reduce voltage pulsation in the capacitor of a unit converter while minimizing the increase in power loss. [Means for solving the problem]

[0008] According to one embodiment, a power converter connected to an AC system is provided. The power converter comprises a power converter including a plurality of arms for each phase of the AC system, and a control device for controlling the power converter. Each of the plurality of arms has a plurality of converter cells cascaded together. Each of the plurality of converter cells has a plurality of switching elements and energy storage elements connected to the plurality of switching elements. The control device includes a first circulating current command generation unit that generates a first circulating current command value for controlling the balance of the voltages of the energy storage elements between each arm, a second circulating current command generation unit that generates a second circulating current command value having frequency components that are even multiples of the fundamental frequency of the AC system, and a circulating current control unit that generates a circulating voltage command value such that the circulating current circulating within the power converter follows a circulating current command value based on the first and second circulating current command values. The second circulating current command generation unit calculates a first control margin based on one or more representative values ​​of the voltage of each energy storage element and one or more representative command values ​​corresponding to each of the one or more representative values, and controls the amplitude of the second circulating current command value based on at least one first control margin. [Effects of the Invention]

[0009] According to the power conversion device described herein, it is possible to reduce voltage pulsation in the capacitor of the unit converter while minimizing the increase in power loss. [Brief explanation of the drawing]

[0010] [Figure 1] This is a diagram showing an example of the configuration of a power conversion device. [Figure 2] This is a circuit diagram showing an example of a converter cell. [Figure 3] This is a block diagram showing an example of the hardware configuration of a control device. [Figure 4] This diagram shows the internal configuration of a control device according to Embodiment 1. [Figure 5] This figure shows a part of the functional configuration of the basic control unit according to Embodiment 1. [Figure 6] This figure shows the other parts of the functional configuration of the basic control unit according to Embodiment 1. [Figure 7] This figure shows an example of the functional configuration of the second circulating current command generation unit according to Embodiment 1. [Figure 8] This figure shows a specific configuration example of the amplitude control unit according to Embodiment 1. [Figure 9] This is a diagram illustrating an example of the function of the filter section. [Figure 10] This is a diagram illustrating another example of the filter's functionality. [Figure 11] This figure shows a partial functional configuration of the basic control unit according to Embodiment 2. [Figure 12] This figure shows the functional configuration of the zero-sequence voltage command generation unit according to Embodiment 2. [Figure 13] This figure shows the functional configuration of the phase control unit according to Embodiment 2. [Figure 14] This figure shows the upper and lower control margins monitored in each section. [Figure 15] These are waveform diagrams of the zero-sequence voltage command value in each section before phase adjustment. [Figure 16]This is an example of various waveform diagrams in each section after the phase adjustment of the zero-phase voltage command value. [Figure 17] This is another example of various waveform diagrams in each section after the phase adjustment of the zero-phase voltage command value. [Figure 18] FIG. is a diagram showing an example of the functional configuration of the second circulating current command generation unit according to Embodiment 2. [Figure 19] FIG. is a diagram showing a specific configuration example of the amplitude control unit according to Embodiment 2. [Figure 20] FIG. is a diagram showing the functional configuration of the phase control unit according to a modification of Embodiment 2. [Embodiments for Carrying Out the Invention]

[0011] Hereinafter, this embodiment will be described with reference to the drawings. In the following description, the same parts are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed descriptions thereof will not be repeated.

[0012] [Configuration Underlying Each Embodiment] [Overall Configuration] FIG. 1 is a diagram showing a configuration example of the power conversion device 100. Referring to FIG. 1, the power conversion device 100 is connected between the AC system 2 and the DC circuit 4. The DC circuit 4 includes a power storage element connected to the DC terminal of the power converter 6. The power storage element is, for example, a power storage device including an electric double layer capacitor or a storage battery such as a lithium ion battery. Alternatively, the DC circuit 4 includes the DC terminals of other power converters connected to the DC terminal of the power converter 6. In this case, a BTB (Back To Back) system for connecting AC power systems with different rated frequencies and the like is configured by connecting two power converters.

[0013] The power converter 100 includes a self-commutated power converter 6 and a control device 5 for controlling the power converter 6. Typically, the power converter 6 is composed of a modular multilevel converter including a plurality of converter cells 1 (corresponding to "cells" in Figure 1) connected in series with each other. A "converter cell" is also called a "submodule" or "unit converter".

[0014] The power converter 6 is connected to the DC circuit 4 and performs power conversion between the DC circuit 4 and the AC system 2. Specifically, the power converter 6 converts the DC power output from the DC circuit 4 into AC power and outputs this AC power to the AC system 2 via the transformer 3. The power converter 6 also converts the AC power from the AC system 2 into DC power and outputs this DC power to the DC circuit 4.

[0015] In the example shown in Figure 1, the power converter 6 includes multiple arms for each phase of the AC system 2. Specifically, the power converter 6 includes multiple leg circuits 8u, 8v, 8w (hereinafter referred to collectively as "leg circuit 8" when referring to them collectively or specifically) connected in parallel between the positive DC terminal (i.e., the high-potential DC terminal) Np and the negative DC terminal (i.e., the low-potential DC terminal) Nn.

[0016] The leg circuits 8 are provided for each of the multiple phases that make up the alternating current. The leg circuits 8 are connected between the AC system 2 and the DC circuit 4 and perform power conversion between the two circuits. Figure 1 shows the case where the AC system 2 is a three-phase AC, and three leg circuits 8u, 8v, and 8w are provided corresponding to the U phase, V phase, and W phase, respectively.

[0017] The AC terminals Nu, Nv, and Nw provided on the leg circuits 8u, 8v, and 8w, respectively, are connected to the AC system 2 via the transformer 3. The AC system 2 is a three-phase AC power system, for example, an AC power supply. In Figure 1, for the sake of illustration, the connection between the AC terminals Nv and Nw and the transformer 3 is not shown. The DC terminals provided in common to each leg circuit 8 (i.e., the positive DC terminal Np and the negative DC terminal Nn) are connected to the DC circuit 4.

[0018] Instead of using the transformer 3 in Figure 1, the leg circuits 8u, 8v, and 8w may be configured to be connected to the AC system 2 via an interconnection reactor. Furthermore, instead of the AC terminals Nu, Nv, and Nw, primary windings may be provided for each of the leg circuits 8u, 8v, and 8w, and the leg circuits 8u, 8v, and 8w may be AC-connected to the transformer 3 or the interconnection reactor via secondary windings that are magnetically coupled to these primary windings. In this case, the primary windings may be the reactors 7a and 7b described below. That is, the leg circuit 8 is electrically (i.e., DC- or AC-) connected to the AC system 2 via connection points provided for each of the leg circuits 8u, 8v, and 8w, such as the AC terminals Nu, Nv, and Nw or the primary windings described above.

[0019] The leg circuit 8u includes a positive arm 13pu from the positive DC terminal Np to the AC terminal Nu, and a negative arm 13nu from the negative DC terminal Nn to the AC terminal Nu. The connection point between the positive arm 13pu and the negative arm 13nu is connected to the transformer 3 as the AC terminal Nu. The positive DC terminal Np and the negative DC terminal Nn are connected to the DC circuit 4. The leg circuit 8v includes a positive arm 13pv and a negative arm 13nv, and the leg circuit 8w includes a positive arm 13pw and a negative arm 13nw.

[0020] In the following, the positive arms 13pu, 13pv, and 13pw will be referred to collectively as "positive arm 13p" or to any specific arm. The negative arms 13nu, 13nv, and 13nw will be referred to collectively as "negative arm 13n" or to any specific arm. The positive arms 13pu, 13pv, and 13pw, and the negative arms 13nu, 13nv, and 13nw will be referred to collectively as "arm 13" or to any specific arm.

[0021] Since the leg circuits 8V and 8W have the same configuration as leg circuit 8U, the following description will use leg circuit 8U as a representative example. In leg circuit 8U, the positive arm 13pu includes a plurality of converter cells 1_1 to 1_M connected in cascade with each other, and a reactor 7a. The plurality of converter cells 1 and reactor 7a are connected in series with each other. The negative arm 13nu includes a plurality of converter cells 1_1 to 1_M connected in cascade with each other, and a reactor 7b. The plurality of converter cells 1 and reactor 7b are connected in series with each other.

[0022] In this embodiment, for example, let M be the number of converter cells included in each arm 13, where M ≥ 2. Also, converter cells 1_1 to 1_M may be collectively referred to as converter cell 1. The values ​​and variables after the underscore in converter cells 1_1 to 1_M indicate the index of converter cell 1. An arbitrary converter cell 1 may also be referred to as "converter cell 1_i" using index i. However, index i is not related to the physical arrangement of converter cell 1.

[0023] The reactor 7a may be inserted at any position on the positive arm 13pu, and the reactor 7b may be inserted at any position on the negative arm 13nu. There may be multiple reactors 7a and 7b. The inductance values ​​of each reactor may be different from each other. Furthermore, only the reactor 7a on the positive arm 13pu, or only the reactor 7b on the negative arm 13nu may be provided.

[0024] The power converter 100 further includes an AC voltage detector 10, an AC current detector 15, DC voltage detectors 11a and 11b, and arm current detectors 9a and 9b provided in each leg circuit 8. These detectors measure the electrical quantities (i.e., current and voltage) used to control the power converter 100. The signals detected by these detectors are input to the control device 5.

[0025] The AC voltage detector 10 detects the AC voltage Vacu of the U phase, the AC voltage Vacp of the V phase, and the AC voltage Vacw of the W phase (hereinafter collectively referred to as "AC voltage Vac") of the AC system 2. The AC current detector 15 detects the measured AC current Isysu of the U phase, the measured AC current Isysv of the V phase, and the measured AC current Isysw of the W phase of the AC system 2. The DC voltage detector 11a detects the DC voltage Vdcp of the positive DC terminal Np connected to the DC circuit 4. The DC voltage detector 11b detects the DC voltage Vdcn of the negative DC terminal Nn connected to the DC circuit 4.

[0026] The arm current detectors 9a and 9b provided in the leg circuit 8u for the U phase detect the positive arm current Ipu flowing through the positive arm 13pu and the negative arm current Inu flowing through the negative arm 13nu, respectively. The arm current detectors 9a and 9b provided in the leg circuit 8v for the V phase detect the positive arm current Ipv and the negative arm current Inv, respectively. The arm current detectors 9a and 9b provided in the leg circuit 8w for the W phase detect the positive arm current Ipw and the negative arm current Inw, respectively.

[0027] In the following explanation, the positive arm currents Ipu, Ipv, and Ipw will be collectively referred to as the positive arm current Iarmp. The negative arm currents Inu, Inv, and Inw will be collectively referred to as the negative arm current Iarmn. The positive arm current Iarmp and the negative arm current Iarmn will be collectively referred to as the arm current Iarm.

[0028] As shown in Figure 1, the AC terminal Nu, which is the connection point between the positive arm 13pu and the negative arm 13nu of the leg circuit 8u, is connected to the transformer 3. Therefore, the AC current Iacu flowing from the AC terminal Nu towards the transformer 3 is the current value obtained by subtracting the negative arm current Inu from the positive arm current Ipu. The same applies to the AC currents Iacv and Iacw. Thus, the following equations (1) to (3) hold true.

[0029] Iacu = Ipu - Inu …(1) Iacv = Ipv - Inv …(2) Iacw = Ipw - Inw …(3) If the average value of the positive arm current Ipu and the negative arm current Inu is taken as the common current flowing through the positive arm 13pu and the negative arm 13nu, then this current is the leg current Icomu (=(Ipu+Inu) / 2) flowing through the DC terminal of the leg circuit 8u. This current is similar for the leg currents Icomv and Icomw of the leg circuits 8v and 8w.

[0030] The positive DC terminals of the leg circuits 8u, 8v, and 8w for each phase are connected in common as the positive DC terminal Np, and the negative DC terminals are connected in common as the negative DC terminal Nn. From this configuration, the sum of the leg currents Icomu, Icomv, and Icomw for each phase becomes the DC current Idc that flows in from the positive terminal of DC circuit 4 and returns to DC circuit 4 via the negative terminal. Therefore, the DC current Idc is expressed as shown in equation (4).

[0031] Idc=(Ipu+Ipv+Ipw+Inu+Inv+Inw) / 2…(4) If the DC current component included in the leg current is distributed equally among the phases, the current capacity of the cell can be made equal. Considering this, the difference between the leg current and 1 / 3 of the DC current value can be calculated as the current value of the circulating current that flows between the legs of each phase, although it does not flow in the DC circuit 4. Therefore, the circulating currents Izu, Izv, and Izw of the U, V, and W phases are expressed as shown in equations (5), (6), and (7) below, respectively.

[0032] Izu = (Ipu + Inu) / 2 - Idc / 3 …(5) Izv = (Ipv + Inv) / 2 - Idc / 3 …(6) Izw = (Ipw + Inw) / 2 - Idc / 3 …(7) <Example of converter cell configuration> Figure 2 is a circuit diagram showing an example of a converter cell 1. The converter cell 1 shown in Figure 2(a) has a circuit configuration called a half-bridge configuration. This converter cell 1 includes a series unit formed by connecting two switching elements 31p and 31n in series, a capacitor 32 as an energy storage element, a voltage detector 33, and a bypass switch 34. The series unit and the capacitor 32 are connected in parallel. The voltage detector 33 detects the capacitor voltage Vc, which is the voltage across the capacitor 32.

[0033] The converter cell 1 shown in Figure 2(b) has a circuit configuration called a full-bridge configuration. This converter cell 1 includes a first series unit formed by connecting two switching elements 31p1 and 31n1 in series, a second series unit formed by connecting two switching elements 31p2 and 31n2 in series, a capacitor 32, a voltage detector 33, and a bypass switch 34. The first series unit, the second series unit, and the capacitor 32 are connected in parallel. The voltage detector 33 detects the capacitor voltage Vc. The capacitor voltage Vc is input to the control device 5.

[0034] The two switching elements 31p and 31n in Figure 2(a) and the four switching elements 31p1, 31n1, 31p2, and 31n2 in Figure 2(b) are configured by connecting a freewheeling diode in antiparallel to a self-extinguishing semiconductor switching element such as an IGBT (Insulated Gate Bipolar Transistor), MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), or GCT (Gate Commutated Turn-off) thyristor. In Figures 2(a) and 2(b), a film capacitor or the like is mainly used for the capacitor 32.

[0035] In the following, the voltage of capacitor 32_i contained in the i-th converter cell 1_i in the positive arm 13pu of the U phase will be denoted as Vcpu_i. The voltage of capacitor 32_i contained in the i-th converter cell 1_i in the negative arm 13nu of the U phase will be denoted as Vcnu_i. The same applies to the V phase and W phase. Capacitor voltages are collectively referred to as Vc, and any capacitor voltage is also referred to as Vc_i.

[0036] In the following explanation, switching elements 31p, 31n, 31p1, 31n1, 31p2, and 31n2 will also be collectively referred to as switching element 31. Furthermore, the on / off state of the semiconductor switching elements within switching element 31 will simply be described as "on / off state of switching element 31".

[0037] Referring to Figure 2(a), both terminals of the switching element 31n are designated as input / output terminals G1 and G2. The switching operation of the switching elements 31p and 31n outputs the voltage across the capacitor 32 and a zero voltage. For example, when switching element 31p is on and switching element 31n is off, the voltage across the capacitor 32 is output. When switching element 31p is off and switching element 31n is on, a zero voltage is output.

[0038] The bypass switch 34 is connected between input / output terminals G1 and G2. In Figure 2(a), the bypass switch 34 is connected in parallel with the switching element 31n. Turning on the bypass switch 34 short-circuits the converter cell 1. For example, the bypass switch 34 is used to short-circuit the converter cell 1 when any element of the converter cell 1 fails. This allows the power converter 6 to continue operating by using other converter cells 1 even if any converter cell 1 fails.

[0039] Next, referring to Figure 2(b), the midpoints of switching elements 31p1 and 31n1, and the midpoints of switching elements 31p2 and 31n2, are designated as input / output terminals G1 and G2 of the converter cell 1, respectively. The converter cell 1 shown in Figure 2(b) outputs a positive voltage or zero voltage by turning on switching element 31n2, turning off switching element 31p2, and alternately turning on switching elements 31p1 and 31n1. Furthermore, the converter cell 1 shown in Figure 2(b) can output a zero voltage or a negative voltage by turning off switching element 31n2, turning on switching element 31p2, and alternately turning on switching elements 31p1 and 31n1.

[0040] The bypass switch 34 is connected between input / output terminals G1 and G2. The bypass switch 34 is connected in parallel with the series configuration of switching elements 31n1 and 31n2. Turning on the bypass switch 34 short-circuits the converter cell 1.

[0041] In this embodiment, the converter cell 1 may be configured as a half-bridge cell as shown in Figure 2(a), or as a full-bridge configuration as shown in Figure 2(b). Furthermore, converter cells with configurations other than those shown above, such as a circuit configuration called a clamped double cell, may be used, and the switching elements and energy storage elements are not limited to those described above.

[0042] <Example of hardware configuration for control device> Figure 3 is a block diagram showing an example of the hardware configuration of the control device 5. In the case of Figure 3, the control device 5 is configured based on a computer. Referring to Figure 3, the control device 5 includes one or more input converters 70, one or more sample-and-hold (S / H) circuits 71, a multiplexer (MUX) 72, and an A / D converter 73. Furthermore, the control device 5 includes one or more CPUs (Central Processing Units) 74, RAM (Random Access Memory) 75, and ROM (Read Only Memory) 76. Furthermore, the control device 5 includes one or more input / output interfaces 77, an auxiliary storage device 78, and a bus 79 that interconnects the above components.

[0043] The input converter 70 is equipped with an auxiliary transformer for each input channel. Each auxiliary transformer converts the detection signals from each electrical quantity detector in Figure 1 into signals with a voltage level suitable for subsequent signal processing.

[0044] A sample-and-hold circuit 71 is provided for each input converter 70. The sample-and-hold circuit 71 samples and holds the signal representing the quantity of electricity received from the corresponding input converter 70 at a specified sampling frequency.

[0045] The multiplexer 72 sequentially selects signals held by multiple sample-and-hold circuits 71. The A / D converter 73 converts the signals selected by the multiplexer 72 into digital values. Note that by providing multiple A / D converters 73, A / D conversion may be performed in parallel for detection signals from multiple input channels.

[0046] The CPU 74 controls the entire control unit 5 and performs arithmetic processing according to the program. The RAM 75, which is volatile memory, and the ROM 76, which is non-volatile memory, are used as the main memory of the CPU 74. The ROM 76 stores the program and setting values ​​for signal processing. The auxiliary storage device 78 is a non-volatile memory with a larger capacity than the ROM 76, and stores the program and data of detected electrical quantities.

[0047] The input / output interface 77 is an interface circuit used for communication between the CPU 74 and external devices.

[0048] Furthermore, at least a portion of the control device 5 may be configured using circuits such as FPGA (Field Programmable Gate Array) and ASIC (Application Specific Integrated Circuit). Alternatively, at least a portion of the control device 5 may be configured using analog circuits.

[0049] The following describes each embodiment in detail. Embodiment 1. <Functional Configuration of Control Device> Figure 4 is a diagram showing the internal configuration of the control device 5 according to Embodiment 1. Referring to Figure 4, the control device 5 includes a basic control unit 502 and an arm control unit 503. The basic control unit 502 includes a U-phase basic control unit 502u, a V-phase basic control unit 502v, and a W-phase basic control unit 502w. The arm control unit 503 includes a U-phase positive arm control unit 503pu and a negative arm control unit 503nu, a V-phase positive arm control unit 503pv and a negative arm control unit 503nv, and a W-phase positive arm control unit 503pw and a negative arm control unit 503nw.

[0050] The configuration of the basic control unit 502 and the arm control unit 503 is realized, for example, by a processing circuit. The processing circuit may be dedicated hardware, or it may be a CPU 74 that executes a program stored in the internal memory of the control device 5. If the processing circuit is dedicated hardware, it may be composed of, for example, an FPGA, an ASIC, or a combination thereof.

[0051] The basic control unit 502 uses the electrical quantities measured by each of the above detectors to generate two arm voltage command values ​​Varmp* and Varmn* for the positive arm 13p and negative arm 13n of each phase, as well as a capacitor voltage command value Vcp* for the positive arm 13p of each phase and a capacitor voltage command value Vcn* for the negative arm 13n of each phase. In the following description, when it is not specified which arm of each phase is being referred to, the arm voltage command value Varm* and the capacitor voltage command value Vc* will be used as descriptive terms. Furthermore, the basic control unit 502 generates a modulation signal Karm* for each arm voltage command value Varm*, which causes each of the multiple converter cells 1 in each arm 13 to output a voltage.

[0052] The arm control unit 503 generates a gate control signal GP to control the on and off states of the switching elements 31p and 31n provided in each converter cell 1 constituting the arm, based on each modulation signal Karm* and capacitor voltage command value Vc*, and outputs the gate control signal GP to each converter cell 1.

[0053] Figure 5 shows a part of the functional configuration of the basic control unit 502 according to Embodiment 1. Referring to Figure 5, the basic control unit 502 includes an electrical quantity calculation unit 401, an average value calculation unit 402, a maximum value detection unit 403, a minimum value detection unit 404, a normalization unit 405, and a capacitor voltage command generation unit 406.

[0054] The electrical quantity calculation unit 401 accepts DC voltages Vdcp and Vdcn, positive arm currents Ipu, Ipv, and Ipw, and negative arm currents Inu, Inv, and Inw as inputs. The electrical quantity calculation unit 401 calculates the difference between DC voltage Vdcp and DC voltage Vdcn (i.e., Vdcp - Vdcn) as DC voltage Vdc. The electrical quantity calculation unit 401 calculates AC currents Iacu, Iacv, and Iacw using equations (1) to (3) described above. The electrical quantity calculation unit 401 calculates DC current Idc using equation (4) described above. The electrical quantity calculation unit 401 calculates circulating currents Izu, Izv, and Izw using equations (5) to (7) described above.

[0055] The average value calculation unit 402 calculates the average value of the capacitor voltage Vc of each arm based on the capacitor voltage Vc of all converter cells 1 (for example, "6 × M" converter cells 1) included in the power converter 6.

[0056] Specifically, the average value calculation unit 402 calculates the total voltage value VcpuS (for example, "Vcpu_1 + ... + Vcpu_M") of the capacitor voltages Vc of each converter cell 1 included in the positive arm 13pu for the U phase, and calculates the average capacitor voltage Vcpua (for example, VcpuS / M) in the positive arm 13pu. The average value calculation unit 402 also calculates the total voltage value VcnuS (for example, "Vcnu_1 + ... + Vcnu_M") of the capacitor voltages Vc of each converter cell 1 included in the negative arm 13nu, and calculates the average capacitor voltage Vcnua (for example, VcnuS / M) in the negative arm 13nu.

[0057] Similarly, the average value calculation unit 402 calculates the average capacitor voltage Vcpva at the positive arm 13pv and the average capacitor voltage Vcnva at the negative arm 13nv for the V phase. For the W phase, the average value calculation unit 402 calculates the average capacitor voltage Vcpwa at the positive arm 13pw and the average capacitor voltage Vcnwa at the negative arm 13nw.

[0058] The average value calculation unit 402 may calculate the average value of each capacitor voltage from the active power or reactive power output from the power converter 6, rather than from the actual capacitor voltage Vc detected.

[0059] The maximum value detection unit 403 detects the maximum value among the capacitor voltages Vc of all converter cells 1 included in the power converter 6 as the maximum capacitor voltage Vcmax. The minimum value detection unit 404 detects the minimum value among the capacitor voltages Vc of all converter cells 1 included in the power converter 6 as the minimum capacitor voltage Vcmin.

[0060] Note that "all converter cells 1 included in the power converter 6" shall not include any faulty converter cells 1. For example, a "faulty converter cell 1" is a converter cell 1 in which the bypass switch 34 is turned on.

[0061] The normalization unit 405 outputs values ​​that have been normalized using the corresponding reference value (e.g., rated value) for each input calculated value and each detected value. Specifically, the normalization unit 405 outputs the normalized AC voltages Vacu_pu, Vacu_pu, and Vacu_pu (hereinafter also collectively referred to as "AC voltage Vac_pu") obtained by dividing the AC voltages Vacu, Vacu, and Vacuw by the rated value.

[0062] The normalization unit 405 outputs the value obtained by dividing the DC voltage Vdc by the rated value as the normalized DC voltage Vdc_pu. The normalization unit 405 outputs the values ​​obtained by dividing the AC currents Iacu, Iacv, Iacw by the rated value as the normalized AC currents Iacu_pu, Iacv_pu, Iacw_pu (hereinafter also collectively referred to as "AC current Iac_pu"). The normalization unit 405 outputs the values ​​obtained by dividing the circulating currents Izu, Izv, Izw by the rated value as the normalized circulating currents Izu_pu, Izv_pu, Izw_pu (hereinafter also collectively referred to as "circulating current Iz_pu").

[0063] The normalization unit 405 outputs the normalized capacitor voltage average values ​​Vcpua, Vcpva, Vcpwa, Vcnua, Vcnva, and Vcnwa, respectively, by dividing them by their rated values, as Vcpua_pu, Vcpva_pu, Vcpwa_pu, Vcnua_pu, Vcnva_pu, and Vcnwa_pu (hereinafter also collectively referred to as "capacitor voltage average value Vca_pu"). The normalization unit 405 outputs the normalized capacitor voltage maximum value Vcmax_pu by dividing the capacitor voltage maximum value Vcmax by its rated value. The normalization unit 405 outputs the normalized capacitor voltage minimum value Vcmin_pu by dividing the capacitor voltage minimum value Vcmin by its rated value.

[0064] The capacitor voltage command generation unit 406 calculates the capacitor voltage command value Vcp* for the capacitor 32 of each converter cell 1 included in the positive arm 13p of each phase. The capacitor voltage command generation unit 406 also calculates the capacitor voltage command value Vcn* for the capacitor 32 of each converter cell 1 included in the negative arm 13n of each phase. For example, the capacitor voltage command value Vcp* for each phase is the average voltage value of the capacitor 32 of each converter cell 1 within the positive arm 13p of each phase. The capacitor voltage command value Vcn* for each phase is the average voltage value of the capacitor 32 of each converter cell 1 within the negative arm 13n of each phase.

[0065] Figure 6 shows other parts of the functional configuration of the basic control unit 502 according to Embodiment 1. Referring to Figure 6, the basic control unit 502 further includes a total capacitor voltage control unit 411, a DC control unit 413, an AC current control unit 415, a first circulating current command generation unit 417, a second circulating current command generation unit 419, a circulating current control unit 421, a zero-sequence voltage command generation unit 423, a voltage command generation unit 425, and a modulation command generation unit 427.

[0066] The total capacitor voltage control unit 411 calculates the average value of the six capacitor voltage average values ​​Vca_pu (i.e., Vcpua_pu ~ Vcnwa_pu) and generates an AC current correction command value ΔIac* so that the average value follows the total capacitor voltage command value Vcall* (for example, so that the deviation between the average value and the total capacitor voltage command value Vcall* is 0). The total capacitor voltage command value Vcall* is a command value given for the average voltage of all capacitors included in the power converter 6. The total capacitor voltage control unit 411 may also generate a correction command value to correct the DC current command value Idc* instead of the AC current correction command value ΔIac*, or it may generate both the AC current correction command value and the AC current correction command value ΔIac*.

[0067] The DC control unit 413 performs DC current control to make the DC current Idc_pu follow the DC current command value Idc*. Typically, the DC control unit 413 generates a DC control command value Varmdc* such that the DC current Idc_pu follows the DC current command value Idc* (for example, so that the deviation between the DC current Idc_pu and the DC current command value Idc* is 0).

[0068] Alternatively, the DC control unit 413 may be configured to perform DC voltage control based on making the DC voltage Vdc follow the DC voltage command value Vdc*, and to perform DC current control when the DC current exceeds a predetermined upper limit. Typically, it generates a DC control command value Varmdc* to make the deviation between the DC voltage command value Vdc* and the DC voltage Vdc zero, and performs the above DC current control when the DC current exceeds the upper limit. The DC current command value Idc* and the DC voltage command value Vdc* are set in advance, for example, by the system operator. Note that the DC voltage command value Vdc* may be calculated based on the DC voltage Vdc_pu.

[0069] The AC current control unit 415 calculates a command value (for example, Iac* + ΔIac*) by correcting the AC current command value Iac* for each phase with the AC current correction command value ΔIac* for each phase. The AC current control unit 415 generates the AC control command value Varmac* for each phase by performing feedback control to make the deviation between the command value and the AC current Iac_pu zero, and by performing feedforward control of the AC voltage Vac_pu. Note that a configuration in which feedforward control of the AC voltage Vac_pu for each phase is not performed is also possible.

[0070] The first circulating current command generation unit 417 generates a first circulating current command value Iz1* to control the balance of the capacitor voltages 32 between each arm 13. Specifically, the first circulating current command generation unit 417 generates the first circulating current command value Iz1* so that the average value of each capacitor voltage Vcpua_pu ~ Vcnwa_pu is balanced. For example, the first circulating current command generation unit 417 performs phase-to-phase balance voltage control and positive / negative arm-to-arm balance voltage control.

[0071] The first circulating current command generation unit 417 performs feedback control for the U phase to make the average capacitor voltage of each capacitor 32 included in the leg circuit 8u (for example, the average value of Vcpua_pu and Vcnua_pu) follow the inter-phase balance voltage command value. Similar control is performed for the V phase and W phase. This control corresponds to inter-phase balance voltage control that matches the average voltage of all capacitors included in the phase (for example, the U phase) to the command value.

[0072] Furthermore, the first circulating current command generation unit 417 controls the balance of the capacitor voltages of the capacitors 32 between the positive and negative arms by performing feedback control for the U phase to make the average capacitor voltage Vcnua_pu of the negative arm 13n follow the average capacitor voltage Vcpua_pu of the positive arm 13p. The first circulating current command generation unit 417 may also perform feedback control to make the average capacitor voltage Vcpua_pu follow the average capacitor voltage Vcnua_pu. Similar control is performed for the V and W phases. This control corresponds to positive-negative arm balance voltage control that matches the average voltage of all capacitors included in one arm (e.g., the negative arm) of a phase (e.g., the U phase) to a command value (e.g., the average capacitor voltage of the positive arm).

[0073] The first circulating current command generation unit 417 generates the first circulating current command value Iz1* by adding the feedback calculation result from the inter-phase balance voltage control and the feedback calculation result from the positive-negative balance voltage control.

[0074] The second circulating current command generation unit 419 generates a second circulating current command value Iz2* having frequency components that are even multiples of the fundamental frequency of the AC system 2, based on the DC current Idc_pu, the AC current Iac_pu, the average value Vca_pu of each capacitor voltage, the maximum value Vcmax_pu of the capacitor voltage, the minimum value Vcmin_pu of the capacitor voltage, the DC control command value Varmdc*, the AC control command value Varmac*, and the arm voltage command value Varm*. The detailed configuration of the second circulating current command generation unit 419 will be described later.

[0075] The circulating current control unit 421 generates a circulating voltage command value Vz* such that the circulating current Iz_pu circulating within the power converter 6 follows the circulating current command value Iz*, which is based on a first circulating current command value Iz1* and a second circulating current command value Iz2* (for example, so that the deviation between the circulating current command value Iz* and the circulating current Iz_pu becomes 0). Typically, the circulating current command value Iz* is the sum of the first circulating current command value Iz1* and the second circulating current command value Iz2*.

[0076] The zero-sequence voltage command generation unit 423 aligns the zero-crossings of the AC control command values ​​Varmac* for each phase, and then generates a zero-sequence voltage command value V0* having a frequency three times that of the AC control command value Varmac*.

[0077] The voltage command generation unit 425 generates arm voltage command values ​​Varm*, which are command values ​​for the output voltage of each arm, based on the DC control command value Varmdc*, the AC control command value Varmac*, the zero-sequence voltage command value V0*, and the circulating voltage command value Vz*. For example, the arm voltage command value Varmpu* for the positive arm 13pu of the U phase is expressed as "Varmdc*-Varmac*+Vz*-V0". The arm voltage command value Varmnu* for the negative arm 13nu of the U phase is expressed as "Varmdc*+Varmac*+Vz*+V0". The same applies to the arm voltage command values ​​Varmpv* for the positive arm 13pv of the V phase, Varmnv* for the negative arm 13nv, Varmpw* for the positive arm 13pw of the W phase, and Varmnw* for the negative arm 13nw.

[0078] The modulation command generation unit 427 generates modulation signals Karm* (e.g., Karmpu*, Karmnu*, Karmpv*, Karmnv*, Karmpw*, Karmnw*) for each arm voltage command value Varm*, which cause each of the multiple converter cells 1 in each arm 13 to output a voltage. The modulation signal Karm* is calculated, for example, by dividing the arm voltage command value Varm* of a certain arm 13 by the sum of the voltages of the capacitors 32 corresponding to that arm 13 and the number of converter cells 1. This reduces the influence of pulsation in the capacitor voltage of each arm 13. The voltage actually output from each arm 13 is close to the value obtained by multiplying the output voltage command value of each arm 13 by a reference value (e.g., rated value) and returning it to the voltage dimension.

[0079] <Second circulating current command generation section> The calculation method for the second circulating current command value Iz2* by the second circulating current command generation unit 419 and the specific functional configuration of the second circulating current command generation unit 419 will be explained.

[0080] (Calculation method for the second circulating current command value) The second circulating current command generation unit 419 calculates a second circulating current command value Iz2* to reduce the voltage pulsation of the capacitor 32. In the MMC, if the frequency of the AC voltage is taken as the fundamental frequency, the voltage pulsation of the capacitor 32 includes frequency components of 1x and 2x the fundamental frequency. These frequency components are common within the arm 13 and are based on the power flowing into the arm 13.

[0081] Therefore, the voltage pulsation of the capacitor 32 can be reduced by reducing the pulsation of frequency components that are one or two times the fundamental frequency of the power flowing into the arm 13. In this embodiment, for example, a second circulating current command value Iz2* is calculated to reduce the one-times fundamental frequency component of the power flowing into the arm 13.

[0082] Typically, we consider the voltage pulsation that occurs in the average capacitor voltage Vcpua of the positive arm 13pu of the U phase. The output voltage Vpu of the positive arm 13pu is expressed by equation (8) below, and the positive arm current Ipu is expressed by equation (9) below. Note that in the following formulas, for the sake of simplicity of notation, I pu It shall be indicated in the form of a subscript, such as "I in a mathematical formula". pu " is the same as "Ipu in the text and drawings".

[0083]

number

[0084] Varmdc represents the DC component of the output voltage Vpu of the positive arm 13pu, and Varmacp represents the amplitude of the fundamental frequency component of the output voltage Vpu of the positive arm 13pu. Iarmdc represents the DC component of the positive arm current Ipu of the positive arm 13pu, and Iarmacp represents the amplitude of the fundamental frequency component of the positive arm current Ipu of the positive arm 13pu. ω is the angular frequency of AC system 2, t is time, Larm is the inductance value of reactor 7a, and Iz2amp represents the amplitude of the second circulating current command value Iz2*. θ represents the phase difference between the phase of the AC voltage of AC system 2 (hereinafter also referred to as the "reference phase") and the phase of the fundamental frequency component of the output voltage Vpu. α represents the phase difference between the reference phase and the phase of the second circulating current command value Iz2*. φ represents the phase difference between the reference phase and the phase of the fundamental frequency component of the positive arm current Ipu.

[0085] Decompose each AC component in equations (8) and (9) into a sine component and a cosine component. Specifically, let the amplitudes of the sine and cosine components of the fundamental frequency component of the output voltage Vpu be VarmacS and VarmacC, respectively. Let the amplitudes of the sine and cosine components of the second circulating current command value Iz2* be Iz2S and Iz2C, respectively. Let the amplitudes of the sine and cosine components of the fundamental frequency component of the positive arm current Ipu be IarmacS and IarmacC, respectively. In this case, equations (10) to (15) below hold.

[0086]

number

[0087] By using equations (10) to (15) to rearrange equations (8) and (9), the output voltage Vpu is expressed by the following equation (16), and the positive arm current Ipu is expressed by the following equation (17).

[0088]

number

[0089] Let Ppu1f be the power flowing into the positive arm 13pu in the fundamental frequency component of AC system 2, with Ppu1fS being the sine component and Ppu1fC being the cosine component of this power. In this case, equations (18) to (20) below hold.

[0090]

number

[0091] Here, the variables AS, AC, kS, and kC are defined as shown in equations (21) to (24) below.

[0092]

number

[0093] Applying equations (21) to (24) to equations (18) to (20), the power Ppu1f can be expressed as shown in equation (25).

[0094]

number

[0095] Using a positive number K, the variables kS and kC can be expressed as shown in equations (26) and (27), respectively.

[0096]

number

[0097] Equations (25) to (27) show that increasing the positive number K can reduce the pulsation of the power Ppu1f. Also, a vector having magnitude B and angle θB is defined as shown in equations (28) and (29) below.

[0098]

number

[0099] Applying equations (28) and (29) to equations (23) and (24), we obtain the determinant shown in equation (30) below.

[0100]

number

[0101] Furthermore, if we set the right-hand side of equation (26) to KcosθA and the right-hand side of equation (27) to KsinθA, and set "Iz2amp = K / B", then from equation (30), Iz2S and Iz2C can be expressed by the following equation (31).

[0102]

number

[0103] Furthermore, sinθA, cosθA, sinθB, and cosθB are expressed by the following equations (32), (33), (34), and (35), respectively.

[0104]

number

[0105] Since K and B are values ​​representing magnitude (i.e., positive values), Iz2amp is positive on the right-hand side of equation (31), and the remainder on the right-hand side is a unit vector. Therefore, by deriving the unit vector components from equations (31) to (35) and adding an arbitrary positive value of Iz2amp, the frequency component of the voltage pulsation of capacitor 32 that is one times the fundamental frequency can be reduced. Note that the matrix part of the unit vector on the right-hand side of equation (31) represents a rotation matrix. Also, from equation (31), equations (12), and equation (13), we have "α = θA - θB". Therefore, the second circulating current command value Iz2* is expressed by the following equation (36).

[0106]

number

[0107] (Functional configuration of the second circulating current command generation unit) The specific functional configuration of the second circulating current command generation unit 419 for calculating the second circulating current command value Iz2* described above will now be explained.

[0108] Figure 7 shows an example of the functional configuration of the second circulating current command generation unit according to Embodiment 1. The second circulating current command generation unit 419 includes an amplitude control unit 452, a phase adjustment unit 454, and a generation unit 456.

[0109] The amplitude control unit 452 accepts inputs of six arm voltage command values ​​Varm*, six capacitor voltage average values ​​Vca_pu, a capacitor voltage maximum value Vcmax_pu, and a capacitor voltage minimum value Vcmin_pu. Based on each of the input values, the amplitude control unit 452 generates the amplitude Iz2amp of the second circulating current command value Iz2*. Details of the amplitude control unit 452 will be described later.

[0110] The phase adjustment unit 454 adjusts the phase θ2 of the second circulating current command value Iz2* so that the fundamental frequency component of the voltage across the capacitor 32 becomes smaller. Specifically, the phase adjustment unit 454 accepts inputs of the AC control command value Varmac*, which is the AC component of the arm voltage command value, the DC control command value Varmdc*, which is its DC component, the AC current Iac_pu, and the DC current Idc_pu.

[0111] The phase adjustment unit 454 calculates the phase θ2 (=θA-θB) of the second circulating current command value Iz2* using the received parameters, the inductance value Larm of the reactor, the angular frequency ω of the AC voltage of AC system 2, and equations (32) to (35). Note that the AC current Iac_pu and DC current Idc_pu may be preset command values, and the angular frequency ω may be an angular frequency obtained from a PLL (Phase Locked Loop) or the like, or a rated value.

[0112] The generation unit 456 generates the second circulating current command value Iz2* for each phase based on the amplitude Iz2amp output from the amplitude control unit 452, the phase θ2 output from the phase adjustment unit 454, and equation (36).

[0113] Figure 8 shows a specific configuration example of the amplitude control unit 452 according to Embodiment 1. Referring to Figure 8, the amplitude control unit 452 includes an arithmetic unit 471, a minimum value detection unit 472, subtractors 473, 474, 475, a minimum value detection unit 476, a filter unit 477, a polarity inversion unit 478, and an amplitude adjustment unit 480. The amplitude adjustment unit 480 includes an integrator 482 and a limiter 484.

[0114] The arithmetic unit 471 calculates the deviation for each arm 13 between the average value of the voltages of each capacitor 32 included in that arm (i.e., the average capacitor voltage) and the value obtained by dividing the arm voltage command value by the number M (i.e., the number of converter cells 1 included in arm 13). The value obtained by dividing the arm voltage command value by the number M corresponds to the command value of the output voltage of each of the multiple converter cells 1 included in arm 13.

[0115] Specifically, the arithmetic unit 471 calculates the deviation σpu (=Vcpua_pu-Varmpu* / M) between the average capacitor voltage Vcpua_pu and 1 / M times the arm voltage command value Varmpu* (i.e., Varmpu* / M) for the positive arm 13pu. Similarly, the arithmetic unit 471 calculates the deviation σpv between the average capacitor voltage Vcpva_pu and 1 / M times the arm voltage command value Varmpv*, the deviation σpw between the average capacitor voltage Vcpwa_pu and 1 / M times the arm voltage command value Varmpw*, the deviation σnu between the average capacitor voltage Vcnua_pu and 1 / M times the arm voltage command value Varmnu*, the deviation σnv between the average capacitor voltage Vcnva_pu and 1 / M times the arm voltage command value Varmnv*, and the deviation σnw between the average capacitor voltage Vcnwa_pu and 1 / M times the arm voltage command value Varmnw*.

[0116] The deviations σpu, σpv, σpw, σnu, σnv, and σnw are collectively referred to as the deviation σs. In this case, the deviation σs indicates the upper control margin, which shows how much margin there is in the average value of the output voltages of the multiple capacitors 32 included in the arm 13 with respect to the value obtained by dividing the arm voltage command value of the arm 13 by the number M (i.e., the output voltage command value of each converter cell 1).

[0117] For example, consider the case where the deviation σpu is negative for the positive arm 13pu of the U phase (i.e., 1 / M times the arm voltage command value Varmpu* is greater than the average capacitor voltage Vcpua_pu). In this case, the upper limit of the output voltage of each converter cell 1 included in the positive arm 13pu corresponds to the "average capacitor voltage Vcpua_pu," which means an overmodulation state in which the desired voltage cannot be output. If the overmodulation state occurs steadily, there is a possibility of extra harmonics flowing in and out. Therefore, each deviation σs must be kept at a value of 0 or greater on a steady basis. That is, the minimum value of each deviation σs must be kept at 0 or greater.

[0118] The minimum value detection unit 472 detects the minimum value σmin1 (i.e., the minimum value among each deviation σs) among the deviations σpu, σpv, σpw, σnu, σnv, and σnw.

[0119] The subtractor 473 calculates the deviation σvH (=VcHlim-Vcmax_pu) between the upper limit voltage value VcHlim of capacitor 32 and the maximum capacitor voltage value Vcmax_pu. The deviation σvH indicates the maximum control margin of the capacitor voltage. The subtractor 474 calculates the deviation σvL (=Vcmin_pu-VcLlim) between the lower limit voltage value VcLlim of capacitor 32 and the minimum capacitor voltage value Vcmin_pu. The deviation σvL indicates the minimum control margin of the capacitor voltage.

[0120] The upper limit voltage value VcHlim is determined, for example, from the voltage that can be applied to the capacitor, the rated voltage of the semiconductor element, and the rated voltages and isolation voltages of other components. The lower limit voltage value VcLlim is determined from the lower limit of the capacitor voltage at which the power converter 6 can operate steadily.

[0121] The subtractor 475 calculates the deviation σcL (=σmin1-σLlim) between the minimum value σmin1 and the lower limit of the control margin σLlim. The deviation σcL is the minimum value of the upper control margin. The lower limit of the control margin σLlim is set to 0 or a very small positive value.

[0122] As the pulsation of the capacitor voltage decreases, the deviations σcL, σvH, and σvL increase. When the phase θ2 (=θA-θB) of the second circulating current command value Iz2* satisfies equations (32) to (36), the deviations σcL, σvH, and σvL can be increased by increasing the amplitude Iz2amp. If the deviations σcL, σvH, and σvL are negative values, the amplitude Iz2amp is increased, and if they are positive values, the amplitude Iz2amp is decreased, thereby making the control margin greater than or equal to zero with the smallest possible second circulating current command value Iz2*.

[0123] The minimum value detection unit 476 detects the minimum value σmin2 (i.e., the value with the smallest control margin) among the deviations σcL, σvH, and σvL. The minimum value σmin2 is input to the filter unit 477. The minimum value σmin2 is the smallest control margin when all of the deviations σcL, σvH, and σvL are considered.

[0124] The filter unit 477 receives the minimum value σmin2 as an input value, filters this input value, and outputs an output value. Since this input value is the minimum value of the control margin of the output voltage of each arm 13, it has momentary pulsations.

[0125] It is necessary to calculate the second circulating current command value Iz2* based on the minimum value within a certain time period (for example, one cycle of the voltage of AC system 2). Therefore, the filter unit 477 has a function to detect this minimum value.

[0126] In certain situations, the filter unit 477 has the detection function, and if the input value input to the filter unit 477 in the current control cycle (hereinafter also referred to as "the current input value") is less than the output value output from the filter unit 477 in the previous control cycle (hereinafter also referred to as "the previous output value"), it outputs the same value as the current input value as the current output value (i.e., the output value output from the filter unit 477 in the current control cycle).

[0127] Furthermore, if the current input value is greater than or equal to the previous output value, the filter unit 477 outputs a value that is less than or equal to the current input value and greater than or equal to the previous output value as the current output value. In this case, for example, the filter unit 477 gradually increases the output value.

[0128] Figure 9 is a diagram illustrating an example of the function of the filter unit. Referring to Figure 9, the filter unit 477 performs a comparison of the current input value and the previous output value for each control cycle. In the example in Figure 9, the filter unit 477 determines that the current input value is greater than or equal to the previous output value during the period from time t0 to time t1, and outputs a value that is less than or equal to the current input value and greater than or equal to the previous output value as the current output value. Therefore, the filter unit 477 gradually increases the output value.

[0129] On the other hand, the filter unit 477 determines that the current input value is less than the previous output value during the period from time t1 to time t2. Therefore, the filter unit 477 outputs the same value as the current input value as the current output value. Subsequently, the filter unit 477 determines that the current input value is less than the previous output value during the period from time t2 onward, and gradually increases the output value.

[0130] In other scenarios, if the input value does not fall below the output value at the nth update timing within a specified period from the nth update timing (where n is an integer greater than or equal to 1), the filter unit 477 sets the timing after the specified period from the nth update timing as the (n+1)th update timing. In this case, the filter unit 477 outputs the minimum input value within the specified period from the nth update timing as the output value at the (n+1)th update timing.

[0131] On the other hand, if the input value falls below the output value at the nth update timing within a specified period from the nth update timing, the filter unit 477 sets the first timing at which the input value fell below the output value at the nth update timing as the (n+1)th update timing, and outputs the same value as the current input value as the current output value until the current input value becomes equal to or greater than the previous output value.

[0132] Figure 10 is a diagram illustrating another example of the filter unit's function. Referring to Figure 10, the filter unit 477 basically updates the output value at predetermined update intervals. For example, suppose the nth update timing is set at time tn, and the output value at that update timing is Xa. The filter unit 477 determines whether the input value will be less than the output value Xa within a specified period (i.e., the update cycle) from the nth update timing.

[0133] In the example shown in Figure 10, since the input value is not less than the output value Xa within the specified period from the nth update timing, the filter unit 477 sets the time t(n+1), which is after the specified period has elapsed from the nth update timing, as the (n+1)th update timing. The filter unit 477 also outputs Xb, which is the minimum input value within the specified period from the nth update timing, as the output value at the (n+1)th update timing.

[0134] Similarly, the filter unit 477 sets time t(n+2) as the (n+2)th update timing and outputs Xc, which is the minimum input value within a specified period from the (n+1)th update timing, as the output value at the (n+2)th update timing.

[0135] On the other hand, at time t(n+3), the input value is less than the output value Xc within the specified period from the (n+2)th update timing. In this case, the filter unit 477 sets time t(n+3) as the (n+3)th update timing. Furthermore, from time t(n+3) onward, the filter unit 477 outputs the same value as the current input value as the current output value until the current input value becomes equal to or greater than the previous output value (for example, from time t(n+3) in Figure 10 until time Ta has elapsed).

[0136] After time Ta has elapsed from time t(n+3), the input value is greater than or equal to the output value Xd, so the filter unit 477 continues to output the output value Xd. Next, the filter unit 477 sets time t(n+4), which is the time after a specified period has elapsed from the time Ta has elapsed from time t(n+3), as the (n+4)th update timing. The filter unit 477 also outputs Xd, which is the minimum input value within the specified period from the t(n+4)th update timing, as the output value at the (n+4)th update timing.

[0137] The configuration of the filter section 477 described above allows for the formation of a filter that is highly sensitive to input values ​​decreasing. Therefore, when any of the deviations σcL, σvH, and σvL decrease, the amplitude Iz2amp of the second circulating current command value Iz2* can be quickly increased, thereby increasing the control margin. Furthermore, by gradually increasing the output value in the direction of increasing input values, pulsation detection on a control cycle basis is suppressed, preventing pulsation in the amplitude Iz2amp.

[0138] Referring again to Figure 8, the polarity inversion unit 478 outputs a value with the polarity of the output value of the filter unit 477 reversed (i.e., the output value multiplied by "-1"). Note that the polarity inversion unit 478 may be provided before the filter unit 477 or after the integrator 482. In the latter case, it is necessary to ensure consistency in terms of positive / negative and greater / lesser values. For example, if the polarity inversion unit 478 is provided before the filter unit 477, the filter unit 477 will be configured to be more sensitive when the current input value is greater than the previous output value.

[0139] The amplitude adjustment unit 480 adjusts the amplitude Iz2amp of the second circulating current command value Iz2* based on the output value of the filter unit 477. Specifically, the integrator 482 of the amplitude adjustment unit 480 receives an input from the polarity inversion unit 478 of the output value of the filter unit 477 with the polarity inverted, and outputs a value obtained by integrating that value over time.

[0140] The limiter 484 outputs the amplitude Iz2amp of the second circulating current command value Iz2*, which is a value obtained by limiting the output value of the integrator 482 using specified limit values ​​(e.g., upper limit value and lower limit value). Specifically, it outputs the amplitude Iz2amp as a value obtained by limiting the output value of the integrator 482 to be greater than or equal to the lower limit value and less than or equal to the upper limit value. For example, the lower limit value is set to 0, and the upper limit value is set to Iz2max. That is, the amplitude Iz2amp is limited to 0 or more and less than or equal to Iz2max.

[0141] Furthermore, if the lower limit of the amplitude Iz2amp is not restricted to 0, when the deviations σcL, σvH, and σvL are large, a circulating current flows according to the second circulating current command value Iz2*, which has a negative amplitude Iz2amp, so that the minimum value of any of these deviations becomes 0. This increases the voltage pulsation of capacitor 32. In this case, power loss increases, and the voltage pulsation of capacitor 32 becomes unnecessarily large. Therefore, it is necessary to prevent the amplitude Iz2amp from becoming negative using the limiter 484.

[0142] In the example shown in Figure 8, a configuration was described in which the amplitude Iz2amp is calculated based on the deviations σcL, σvH, and the minimum value σmin2 among the deviations σvL, but the configuration is not limited to this. The second circulating current command generation unit 419 (specifically, the amplitude control unit 452) may be configured to calculate the amplitude Iz2amp using one or two of the deviations σcL, σvH, and σvL.

[0143] Specifically, the amplitude control unit 452 may calculate a control margin based on one or more representative values ​​of the voltage of each capacitor 32 and one or more representative command values ​​corresponding to each of these representative values, and control the amplitude Iz2amp based on at least one of these control margins.

[0144] In one example, the representative value is the minimum value σmin1 among the deviations σpu~σnw. The representative command value corresponding to this representative value is the lower control margin value σLlim. In this case, the amplitude control unit 452 calculates the deviation σcL as the control margin by subtracting the lower control margin value σLlim from the minimum value σmin1, and controls the amplitude Iz2amp based on this control margin. This control margin is input as the input value to the filter unit 477. In this case, it is not necessary to set the upper voltage limit value VcHlim and the lower voltage limit value VcLlim, and the maximum capacitor voltage value Vcmax_pu and the minimum capacitor voltage value Vcmin_pu do not need to be input to the amplitude control unit 452.

[0145] In another example, the representative value is the maximum capacitor voltage Vcmax_pu. The representative command value corresponding to this representative value is the upper limit voltage value VcHlim of the capacitor 32. In this case, the amplitude control unit 452 calculates the deviation σvH obtained by subtracting the maximum capacitor voltage Vcmax_pu from the upper limit voltage value VcHlim as a control margin, and controls the amplitude Iz2amp based on this control margin.

[0146] In yet another example, the representative value is the minimum capacitor voltage Vcmin_pu. The representative command value corresponding to this representative value is the lower limit voltage value VcLlim of the capacitor 32. In this case, the amplitude control unit 452 calculates the deviation σvL obtained by subtracting the lower limit voltage value VcLlim from the minimum capacitor voltage Vcmin_pu as a control margin, and controls the amplitude Iz2amp based on this control margin.

[0147] The amplitude control unit 452 may also be configured to select two of the deviations σpu to σnw and calculate the amplitude Iz2amp using the minimum value of those two deviations.

[0148] <Advantages> According to Embodiment 1, during steady-state operation of the power converter 6, it is possible to reduce voltage pulsation in the capacitor 32 of the converter cell 1 while suppressing the increase in power loss as much as possible.

[0149] Embodiment 2. Embodiment 1 describes a configuration in which the control margin is adjusted by controlling the amplitude Iz2amp of the second circulating current command value Iz2*. On the other hand, the control margin can also be adjusted by adjusting the phase of the zero-sequence voltage command value V0*. However, if amplitude control of amplitude Iz2amp and phase adjustment control of the zero-sequence voltage command value V0* are performed simultaneously, the control margin may not be properly adjusted. Therefore, Embodiment 2 describes a configuration in which, if necessary, one of the amplitude control and phase adjustment control is stopped.

[0150] <Functional Configuration of Control Device> The internal configuration of the control device 5 according to Embodiment 2 is the same as in Figure 4. The basic control unit 502A according to Embodiment 2 has the same functional configuration as shown in Figure 11, in addition to the electrical quantity calculation unit 401, average value calculation unit 402, maximum value detection unit 403, minimum value detection unit 404, normalization unit 405, and capacitor voltage command generation unit 406 shown in Figure 5. For convenience, the basic control unit 502A is denoted with the letter "A" to distinguish it from the basic control unit 502 according to Embodiment 1.

[0151] Figure 11 shows a partial functional configuration of the basic control unit 502A according to Embodiment 2. The configuration of the basic control unit 502A shown in Figure 11 corresponds to replacing the second circulating current command generation unit 419 and the zero-sequence voltage command generation unit 423 shown in Figure 6 with the second circulating current command generation unit 419A and the zero-sequence voltage command generation unit 423A, respectively.

[0152] The second circulating current command generation unit 419A generates a second circulating current command value Iz2* based on the DC current Idc_pu, the AC current Iac_pu, the average value Vca_pu of each capacitor voltage, the maximum value Vcmax_pu of the capacitor voltage, the minimum value Vcmin_pu of the capacitor voltage, the DC control command value Varmdc*, the AC control command value Varmac*, the arm voltage command value Varm*, and the adjustment phase θv0 of the zero-sequence voltage. The detailed configuration of the second circulating current command generation unit 419A will be described later.

[0153] The zero-sequence voltage command generation unit 423A generates a zero-sequence voltage command value V0* and also generates an adjustment phase θv0 for adjusting the phase of the zero-sequence voltage command value V0*.

[0154] (Zero-sequence voltage command generation unit) Figure 12 shows the functional configuration of the zero-sequence voltage command generation unit according to Embodiment 2. Referring to Figure 12, the zero-sequence voltage command generation unit 423A includes a reference phase generation unit 611, a phase control unit 613, and a zero-sequence voltage generation unit 615.

[0155] The reference phase generation unit 611 generates a reference phase θv based on the AC control command value Varmac* for each phase. For example, the reference phase θv is generated when the AC control command value VarmacU* for the U phase becomes the amplitude VacU of the AC voltage of the U phase. In this case, the AC control command value VarmacU* is expressed as shown in equation (37).

[0156]

number

[0157] The phase control unit 613 controls the phase of the zero-sequence voltage command value V0* of the power converter 2. The phase control unit 613 generates an adjusted phase θv0 based on the reference phase θv, the average value Vca_pu of each capacitor voltage, and the arm voltage command value Varm*. The specific configuration of the phase control unit 613 will be described later.

[0158] The zero-sequence voltage generation unit 615 generates a zero-sequence voltage command value V0* based on the AC control command value Varmac* for each phase, the reference phase θv, and the adjustment phase θv0. Specifically, the zero-sequence voltage generation unit 615 generates the zero-sequence voltage command value V0* using the following equation (38). Note that β is a constant, for example, 1 / 6.

[0159]

number

[0160] This section describes the phase adjustment control method for the zero-sequence voltage command value V0*. Figure 13 shows the functional configuration of the phase control unit according to Embodiment 2. Referring to Figure 13, the phase control unit 613 calculates a control margin for each of the plurality of arms based on the voltage of each capacitor 32 included in the arm and the arm voltage command value of the arm, and calculates an adjustment phase θv0 for adjusting the phase of the zero-sequence voltage command value V0* based on each control margin. Specifically, the phase control unit 613 includes an arithmetic unit 621, an adder 623, a phase state detection unit 625, minimum value detection units 627, 629, 631, a subtractor 633, a proportional unit 635, an adder 637, and a holding unit 639.

[0161] The arithmetic unit 621 calculates the deviation for each arm 13 between the average value of the voltages of each capacitor 32 included in that arm (i.e., the average capacitor voltage) and the value obtained by dividing the arm voltage command value by the number M. Specifically, the arithmetic unit 621 outputs the upper control margin σpuU, which is the deviation (=Vcpua_pu-Varmpu* / M) between the average capacitor voltage Vcpua_pu and 1 / M times the arm voltage command value Varmpu*. The deviation σpuU corresponds to the deviation σpu explained in Figure 8. Similarly, the arithmetic unit 621 outputs the deviations σpv, σpw, σnu, σnv, and σnw explained in Figure 8 as upper control margins σpvU, σpwU, σnuU, σnvU, and σnwU, respectively. Hereafter, the upper control margin will also be simply referred to as the "upper margin".

[0162] The arithmetic unit 621 outputs Varmpu* / M, Varmpv* / M, Varmpw* / M, Varmnu* / M, Varmnv* / M, and Varmnw* / M as lower control margins σpuL, σpvL, σpwL, σnuL, σnvL, and σnwL, respectively. Hereafter, the lower control margin will also be simply referred to as the "lower margin".

[0163] The adder 623 calculates the phase θa by adding the reference phase θv and the adjustment phase θv0. The phase state detection unit 625 divides one period of the AC system 2 into six sections and outputs a section Ph (for example, Ph=0 to 5) corresponding to the phase θa. Specifically, if 0°<θa≦60°, Ph=0; if 60°<θa≦120°, Ph=1; if 120°<θa≦180°, Ph=2; if 180°<θa≦240°, Ph=3; if 240°<θa≦300°, Ph=4; and if 300°<θa≦360°, Ph=5.

[0164] The minimum value detection unit 627 monitors the upper and lower margins set in each interval Ph (Ph=0~5) and calculates the first upper margin minimum value σU1min, the second upper margin minimum value σU2min, the first lower margin minimum value σL1min, and the second lower margin minimum value σL2min.

[0165] Figure 14 shows the upper and lower control margins monitored in each interval. Referring to Figure 14, Table 700 shows the upper and lower margins that can be minimized in each interval Ph. For example, at Ph=0, the upper margin σpwU, lower margin σnwL, upper margin σnuU, and lower margin σpuL can be the first upper margin minimum σU1min, the first lower margin minimum σL1min, the second upper margin minimum σU2min, and the second lower margin minimum σL2min, respectively.

[0166] The minimum value detection unit 627 calculates the first upper margin minimum value σU1min, the first lower margin minimum value σL1min, the second upper margin minimum value σU2min, and the second lower margin minimum value σL2min for each interval Ph, at the timing immediately before switching from the current interval Ph (for example, Ph=0) to the next interval Ph (for example, Ph=1). For example, when Ph=0, the minimum value detection unit 627 calculates the minimum value of the upper margin σpwU as the first upper margin minimum value σU1min, the minimum value of the lower margin σnwL as the first lower margin minimum value σL1min, the minimum value of the upper margin σnuU as the second upper margin minimum value σU2min, and the minimum value of the lower margin σpuL as the second lower margin minimum value σL2min.

[0167] Referring again to Figure 13, the minimum value detection unit 629 detects the smaller of the first upper margin minimum value σU1min and the first lower margin minimum value σL1min. The minimum value detection unit 631 detects the smaller of the second upper margin minimum value σU2min and the second lower margin minimum value σL2min. The subtractor 633 outputs the difference Δσ obtained by subtracting the value detected by the minimum value detection unit 629 from the value detected by the minimum value detection unit 631.

[0168] The proportionalizer 635 outputs the product of the difference Δσ and the gain Kdeg, "Δσ × Kdeg", as the change in the adjustment phase θv0, Δθv0. The adder 637 outputs the sum of the change in Δθv0 and the output value of the holding unit 639 as the adjustment phase θv0. The holding unit 639 holds the adjustment phase θv0 output from the adder 637 in the previous interval Ph. Therefore, the adjustment phase θv0 output from the adder 637 in the current interval Ph corresponds to the sum of the adjustment phase θv0 in the previous interval Ph and the change in Δθv0 calculated in the current interval Ph.

[0169] The zero-sequence voltage generation unit 615 shown in Figure 12 generates a zero-sequence voltage command value V0* based on the AC control command value Varmac* for each phase, the reference phase θv, and the adjustment phase θv0 calculated as described above. The specific changes in the control margin due to the zero-sequence voltage command value V0* generated in this way will be explained below.

[0170] Figure 15 shows various waveforms for each section before phase adjustment of the zero-sequence voltage command value. Figure 15 shows the average capacitor voltage Vcnua_pu, 1 / M times the arm voltage command value Varmnu* (hereinafter also simply referred to as the voltage command value VnuM*), upper margin σnuU, lower margin σnuL, and zero-sequence voltage command value V0*. Here, as an example, the negative arm 13nu will be explained. This is also the case in Figures 16 and 17 below.

[0171] Focusing on the negative arm 13nu and referring to Table 700 in Figure 14, the upper margin σnuU can be the first minimum upper margin σU1min when Ph=5, and the second minimum upper margin σU2min when Ph=0. This is consistent with Figure 15, where the minimum upper margin σnuU in the Ph=5 interval is shown as the first minimum upper margin σU1min, and the minimum upper margin σnuU in the Ph=0 interval is shown as the second minimum upper margin σU2min.

[0172] Similarly, referring to Table 700 in Figure 14, the lower margin σnuL can be the first lower margin minimum σL1min when Ph=2, and the second lower margin minimum σL2min when Ph=3. This is consistent with Figure 15, where the minimum value of the lower margin σnuL in the interval Ph=2 is shown as the first lower margin minimum σL1min, and the minimum value of the lower margin σnuL in the interval Ph=3 is shown as the second upper margin minimum σL2min.

[0173] As shown in Figure 15, it can be seen that the first upper margin minimum value σU1min is particularly small before phase adjustment of the zero-sequence voltage command value V0*.

[0174] Figure 16 shows examples of various waveform diagrams for each section after phase adjustment of the zero-sequence voltage command value. Referring to Figure 16, it can be seen that when the phase of the zero-sequence voltage command value V0* is adjusted based on the adjustment phase θv0, the first upper margin minimum value σU1min is larger compared to the zero-sequence voltage command value V0* before phase adjustment shown in Figure 15. Specifically, the first upper margin minimum value σU1min is the same as the second lower margin minimum value σL2min.

[0175] Figure 17 shows other examples of various waveform diagrams for each section after phase adjustment of the zero-sequence voltage command value. Referring to Figure 17, it can be seen that the first upper margin minimum value σU1min has increased compared to the zero-sequence voltage command value V0* shown in Figure 15 before phase adjustment. Specifically, the first upper margin minimum value σU1min is the same as the second upper margin minimum value σU2min.

[0176] In this way, by adjusting the phase of the zero-sequence voltage command value V0*, the control margin of the voltage command value with respect to the output voltage range can be increased for the power converter 100 as a whole.

[0177] (Second circulating current command generation section) Next, the specific configuration of the second circulating current command generation unit 419A according to Embodiment 2 will be described.

[0178] Figure 18 shows an example of the functional configuration of the second circulating current command generation unit according to Embodiment 2. Referring to Figure 18, the second circulating current command generation unit 419A includes an amplitude control unit 452A, a phase adjustment unit 454, and a generation unit 456. The configuration of the phase adjustment unit 454 and the generation unit 456 is the same as the configuration described in Figure 7. The amplitude control unit 452A differs from the amplitude control unit 452 according to Embodiment 1 in that it generates the amplitude Iz2amp of the second circulating current command value Iz2* using the adjustment phase θv0.

[0179] Figure 19 shows a specific example of the configuration of the amplitude control unit according to Embodiment 2. Referring to Figure 19, the amplitude control unit 452A has a configuration that adds a differentiator 491, an absolute value calculation unit 492, a comparator 493, and a multiplier 494 to the amplitude control unit 452 of Figure 8.

[0180] The differentiator 491 calculates the time derivative of the adjustment phase θv0. The absolute value calculation unit 492 calculates the absolute value γ1 of the time derivative of the adjustment phase θv0. The absolute value γ1 indicates the magnitude of the time change of the adjustment phase θv0. The comparator 493 outputs a value of "1" if the absolute value γ1 is less than or equal to the threshold Th1 (i.e., γ1 ≤ Th1). The comparator 493 outputs a value of "0" if the absolute value γ1 is greater than the threshold Th1 (i.e., γ1 > Th1).

[0181] The multiplier 494 calculates the product of the output value of the polarity inversion unit 478 and the output value of the comparator 493. Specifically, if γ1 ≤ Th1, the multiplier 494 outputs the output value of the polarity inversion unit 478 to the integrator 482, and if γ1 > Th1, it outputs the value "0" to the integrator 482.

[0182] As a result, when the time variation of the adjustment phase θv0 is small (for example, γ1 ≤ Th1), the amplitude Iz2amp is controlled based on the control margin in the same manner as in Embodiment 1. On the other hand, when the time variation of the adjustment phase θv0 is large (for example, γ1 > Th1), the input value to the integrator 482 becomes "0". In this case, the integrator 482 outputs the amplitude Iz2amp calculated in the previous control period to the limiter 484. In this way, the amplitude Iz2amp is not updated and is fixed to the previous value.

[0183] As described above, if the magnitude of the time change of the adjustment phase θv0 of the zero-sequence voltage command value V0* is greater than the threshold Th1, the amplitude control unit 452 stops updating the amplitude Iz2amp using the control margin. This is because when the time change of the adjustment phase θv0 is large, the upper margin changes significantly, and if the amplitude Iz2amp is controlled simultaneously, the control becomes unstable. On the other hand, if the time change of the adjustment phase θv0 of the zero-sequence voltage command value V0* is small, it is not necessary to stop updating the amplitude Iz2amp.

[0184] By a similar line of reasoning, a configuration may be used in which the update of the adjustment phase θv0 of the zero-sequence voltage command value V0* is stopped when the change in amplitude Iz2amp is large.

[0185] Figure 20 shows the functional configuration of the phase control unit according to a modified example of Embodiment 2. Referring to Figure 20, the phase control unit 613A has a configuration that adds a differentiator 641, an absolute value calculation unit 642, a comparator 643, and a multiplier 644 to the phase control unit 613 of Figure 13.

[0186] The differentiator 641 calculates the time derivative of the amplitude Iz2amp. The absolute value calculation unit 642 calculates the absolute value γ2 of the time derivative of the amplitude Iz2amp. The absolute value γ2 indicates the magnitude of the time change of the amplitude Iz2amp. The comparator 643 outputs a value of "1" if the absolute value γ2 is less than or equal to the threshold Th2 (i.e., γ2 ≤ Th2). The comparator 643 outputs a value of "0" if the absolute value γ2 is greater than the threshold Th2 (i.e., γ2 > Th2).

[0187] The multiplier 644 calculates the product of the output value of the proportionalizer 635 and the output value of the comparator 643. Specifically, if γ2 ≤ Th2, the multiplier 644 outputs the output value of the proportionalizer 635 to the adder 637, and if γ2 > Th2, it outputs the value "0" to the adder 637.

[0188] As a result, when the time variation of the amplitude Iz2amp is small (for example, γ2 ≤ Th2), the adjustment phase θv0 is updated according to the method described in Figure 13. On the other hand, when the time variation of the amplitude Iz2amp is large (for example, γ2 > Th2), the input value to the adder 637 becomes "0". In this case, the adder 637 outputs the output value of the holding unit 639 (i.e., the adjustment phase θv0 calculated in the previous interval Ph) as the adjustment phase θv0 for the current interval Ph. As a result, the adjustment phase θv0 is not updated and is fixed to the previous value.

[0189] As described above, if the time variation of the amplitude Iz2amp is greater than the threshold Th2, the phase control unit 613 calculates the previous adjustment phase θv0 as the current adjustment phase θv0. In other words, the update control of the adjustment phase θv0 of the zero-sequence voltage command value V0* is stopped. On the other hand, if the time variation of the amplitude Iz2amp is small, it is not necessary to stop the update control of the adjustment phase θv0 of the zero-sequence voltage command value V0*.

[0190] <Advantages> According to Embodiment 2, by simultaneously performing amplitude control of the second circulating current command value and phase control of the zero-sequence voltage command value, it is possible to prevent the control from becoming unstable.

[0191] Other embodiments. The configurations illustrated above as embodiments are examples of the configurations of this disclosure, and can be combined with other known technologies, or modified, such as by omitting parts, without departing from the gist of this disclosure. Furthermore, in the embodiments described above, processes and configurations described in other embodiments may be appropriately adopted and implemented.

[0192] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims rather than by the foregoing description, and all modifications within the meaning and scope of the claims are intended to be included. [Explanation of symbols]

[0193] 1 Converter cell, 2 AC system, 3 Transformer, 4 DC circuit, 5 Control device, 6 Power converter, 7a, 7b Reactor, 8u, 8v, 8w Reg circuit, 9a, 9b Arm current detector, 10 AC voltage detector, 11a, 11b DC voltage detector, 13nu, 13nv, 13nw Negative arm, 13pu, 13pv, 13pw Positive arm, 15 AC current detector, 31n, 31p Switching element, 32 Capacitor, 33 Voltage detector, 34 Bypass switch, 70 Input converter, 71 Sample-and-hold circuit, 72 Multiplexer, 73 A / D converter, 74 CPU, 75 RAM, 76 ROM, 77 Input / Output interface, 78 Auxiliary storage device, 79 Bus, 100 Power converter, 401 Electrical quantity calculation unit, 402 Average value calculation unit, 403 Maximum value detection unit, 404, 472, 476, 627, 629, 631 Minimum value detection unit, 405 Normalization unit, 406 Capacitor voltage command generation unit, 411 Total capacitor voltage control unit, 413 DC control unit, 415 AC current control unit, 417 First circulating current command generation unit, 419, 419A Second circulating current command generation unit, 421 Circulating current control unit, 423, 423A Zero-sequence voltage command generation unit, 425 Voltage command generation unit, 427 Modulation command generation unit, 452, 452A Amplitude control unit, 454 Phase adjustment unit, 456 Generation unit, 477 Filter unit, 478 Polarity inversion unit, 480 Amplitude adjustment unit, 482 Integrator, 484 Limiter, 502 Basic control unit, 503 Arm control unit, 611 Reference phase generation unit, 613, 613A Phase control unit, 615 zero-sequence voltage generation unit, 625 phase state detection unit, 635 proportional unit, 639 holding unit.

Claims

1. A power conversion device connected to an AC system, a power converter including a plurality of arms for each phase of the AC system; A control device for controlling the power converter, each of the plurality of arms includes a plurality of transducer cells cascaded with one another; Each of the plurality of converter cells includes a plurality of switching elements and an energy storage element connected to the plurality of switching elements; The control device includes: a first circulating current command generating unit that generates a first circulating current command value for controlling a balance of voltages of the energy storage elements between the arms; a second circulating current command generating unit that generates a second circulating current command value having a frequency component that is an even multiple of a fundamental wave frequency of the AC system; a circulating current control unit that generates a circulating voltage command value such that a circulating current circulating in the power converter follows a circulating current command value that is based on the first circulating current command value and the second circulating current command value, The second circulating current command generating unit is Calculating a first control margin based on one or more representative values ​​of the voltages of the energy storage elements and one or more representative command values ​​respectively corresponding to the one or more representative values; a power conversion device that controls an amplitude of the second circulating current command value based on at least one of the first control margins;

2. the second circulating current command generating unit calculates, for each of the plurality of arms, a deviation between an average value of voltages of the energy storage elements included in the arm and a value obtained by dividing a voltage command value of the arm by the number of the converter cells included in the arm; the one or more representative values ​​include a minimum value of each of the deviations; the one or more representative command values ​​include a lower limit value for the deviation, The power conversion device according to claim 1 , wherein the second circulating current command generating unit calculates, as the first control margin, a first value obtained by subtracting the lower limit value from a minimum value of the deviations.

3. the one or more representative values ​​include a maximum voltage value among voltages of the energy storage elements included in the power converter; the one or more representative command values ​​include an upper limit voltage value of the energy storage element, The power conversion device according to claim 1 , wherein the second circulating current command generating unit calculates, as the first control margin, a second value obtained by subtracting the maximum voltage value from an upper limit voltage value of the energy storage element.

4. the one or more representative values ​​include a minimum voltage value among voltages of the energy storage elements included in the power converter; the one or more representative command values ​​include a lower limit voltage value of the energy storage element, The power conversion device according to claim 1 , wherein the second circulating current command generating unit calculates, as the first control margin, a third value obtained by subtracting a lower limit voltage value of the energy storage element from the minimum voltage value.

5. the second circulating current command generating unit calculates, for each of the plurality of arms, a deviation between an average value of voltages of the energy storage elements included in the arm and a value obtained by dividing a voltage command value of the arm by the number of the converter cells included in the arm; the one or more representative values ​​include a minimum value of each of the deviations, a maximum voltage value of each of the energy storage elements included in the power converter, and a minimum voltage value of each of the energy storage elements included in the power converter; the one or more representative command values ​​include a lower limit value for the deviation, an upper limit voltage value of the energy storage element, and a lower limit voltage value of the energy storage element, 2. The power conversion device according to claim 1, wherein the second circulating current command generating unit calculates, as the first control margin, a minimum value among a first value obtained by subtracting the lower limit value from a minimum value of the deviations, a second value obtained by subtracting the maximum voltage value from an upper limit voltage value of the energy storage element, and a third value obtained by subtracting a lower limit voltage value of the energy storage element from the minimum voltage value.

6. The second circulating current command generating unit is a filter unit that receives the first control margin as an input value, processes the input value, and outputs an output value; an amplitude adjustment unit that adjusts an amplitude of the second circulating current command value based on the output value, The filter unit includes: If the current input value is less than the previous output value, the current input value is output as the current output value; When the current input value is equal to or greater than the previous output value, a value that is equal to or less than the current input value and equal to or greater than the previous output value is output as the current output value. The power conversion device according to any one of claims 1 to 5.

7. The second circulating current command generating unit is a filter unit that receives the first control margin as an input value, processes the input value, and outputs an output value; an amplitude adjustment unit that adjusts an amplitude of the second circulating current command value based on the output value, The filter unit includes: if the input value does not become less than the output value at the nth update timing within a specified period from the nth update timing (n is an integer equal to or greater than 1), set the timing after the specified period from the nth update timing as the (n+1)th update timing, and output the minimum value of the input value within the specified period from the nth update timing as the output value at the (n+1)th update timing; 6. The power conversion device according to claim 1, wherein if the input value becomes less than the output value at the nth update timing within the specified period from the nth update timing, a first timing at which the input value becomes less than the output value at the nth update timing is set as the (n+1)th update timing, and from the first timing onwards, a value identical to the current input value is output as the current output value until the current input value becomes equal to or greater than the previous output value.

8. The amplitude adjustment unit is an integrator that time-integrates a value obtained by inverting the polarity of the output value; a limiter that limits an output value of the integrator using a specified limit value and outputs the limit value as an amplitude of the second circulating current command value, The power conversion device according to claim 6 , wherein a lower limit value of the specified limit value is zero.

9. The power conversion device according to any one of claims 1 to 5, wherein the second circulating current command generating unit adjusts a phase of the second circulating current command value so that a frequency component of the fundamental frequency of the voltage of the energy storage element becomes small.

10. The control device further includes a phase control unit that controls a phase of a zero-phase sequence voltage command value of the power converter, The phase control unit includes: calculating, for each of the plurality of arms, a second control margin based on a voltage of each of the energy storage elements included in the arm and a voltage command value of the arm; Calculating an adjustment phase for adjusting a phase of the zero-phase voltage command value based on each of the second control margins; The power conversion device according to any one of claims 1 to 5, wherein when a magnitude of a time change of the adjustment phase is greater than a first threshold, the second circulating current command generation unit stops control of an amplitude of the second circulating current command value.

11. The control device further includes a phase control unit that controls a phase of a zero-phase sequence voltage command value of the power converter, The phase control unit includes: calculating, for each of the plurality of arms, a second control margin based on a voltage of each of the energy storage elements included in the arm and a voltage command value of the arm; Calculating an adjustment phase for adjusting a phase of the zero-phase voltage command value based on each of the second control margins; 6. The power conversion device according to claim 1, wherein when a magnitude of a time change in the amplitude of the second circulating current command value is greater than a second threshold, the previous adjustment phase is calculated as the current adjustment phase.

Images