Semiconductor Device

Abstract

The semiconductor device (1) includes a plurality of semiconductor modules (2). Each of the plurality of semiconductor modules (2) includes a base plate (13) having a first surface exposed to the outside of the semiconductor module (2) and a second surface opposite to the first surface, an insulating substrate on which a circuit pattern is provided, a semiconductor chip bonded to the circuit pattern, a sealing portion for sealing the insulating substrate and the semiconductor chip, and a first main electrode and a second main electrode extending from inside the sealing portion in a direction opposite to the direction from the sealing portion toward the base plate (13). The planar shape of the semiconductor module (2) has four corners and is a shape having rotational symmetry. The first main electrode extends from inside the sealing portion at each of the first and second corners of the four corners. The second main electrode extends from inside the sealing portion at each of the third and fourth corners of the four corners.

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device including a semiconductor element for power control. [Background technology]

[0002] Conventionally, designers of electrical equipment such as industrial equipment or consumer equipment often select a power module from among several power modules provided by manufacturers of semiconductor devices for power control to design the electrical equipment. A power module is a semiconductor device in which multiple semiconductor chips are mounted in one package. When selecting a power module from among the power modules provided by a manufacturer, the selected power module determines the circuit layout or the shape of the cooler, so that the external shape of the electrical equipment is somewhat limited. On the other hand, there is also a demand for increasing the freedom of shape of the electrical equipment. However, from the viewpoint of the manufacturing cost of the power module or the reliability of the power module, it is difficult to redesign the power module for each electrical equipment.

[0003] Patent Document 1 discloses a semiconductor device in which a plurality of semiconductor chips are arranged in semiconductor modules having mutually independent configurations, and functions equivalent to those of a power module can be realized by connecting the semiconductor modules together. Each semiconductor module of the semiconductor device disclosed in Patent Document 1 has a similar configuration to each other. Each of the collector main electrode and the emitter main electrode of the semiconductor module is arranged so as to reach the upper surface of the semiconductor module, and can be connected to an external circuit and to the semiconductor module adjacent to the semiconductor module. For example, the adjacent semiconductor modules are arranged so that the collector main electrode of one semiconductor module and the emitter main electrode of the other semiconductor module face each other, and each of the collector main electrode and the emitter main electrode is fixed to a conductive plate with a bolt. As a result, the collector main electrode and the emitter main electrode are connected to each other, and the two semiconductor modules are fixed to each other. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2014 / 030254 Summary of the Invention [Problem to be solved by the invention]

[0005] In each semiconductor module of the semiconductor device disclosed in Patent Document 1, two collector main electrodes are adjacent to each other, and two emitter electrodes are adjacent to each other. For example, when adjacent semiconductor modules are arranged such that the collector main electrode of one semiconductor module faces the emitter main electrode of the other semiconductor module, the main electrode of the one semiconductor module at a position that can be connected to an external circuit is limited to the emitter electrode, and the main electrode of the other semiconductor module at a position that can be connected to an external circuit is limited to the collector electrode. That is, in the semiconductor device disclosed in Patent Document 1, when the manner of connection between the semiconductor modules is determined, the arrangement of each semiconductor module is inevitably determined, and there is a problem that the degree of freedom in the arrangement of each semiconductor module is small. In the case of the semiconductor device disclosed in Patent Document 1, it is difficult to change the arrangement of each semiconductor module to suit the convenience of connection with an external circuit, so that measures such as wiring to connect the main electrodes of each semiconductor module to an external circuit may be required.

[0006] The present disclosure has been made in view of the above, and has an object to provide a semiconductor device that allows each of a plurality of semiconductor modules to be arranged with a high degree of freedom. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems and achieve the object, the semiconductor device according to the present disclosure includes a plurality of semiconductor modules. Each of the plurality of semiconductor modules includes a base plate having a first surface exposed to the outside of the semiconductor module and a second surface opposite to the first surface, an insulating substrate arranged on the second surface side and having a circuit pattern, a semiconductor chip bonded to the circuit pattern, a sealing portion arranged on the second surface side and sealing the insulating substrate and the semiconductor chip, and a first main electrode and a second main electrode drawn out from inside the sealing portion in a direction opposite to the direction from the sealing portion to the base plate. The planar shape of the semiconductor module when viewed from the normal direction of the second surface has four corners and has rotational symmetry. The first main electrode is drawn out from inside the sealing portion at each of the first corner and the second corner, which are two of the four corners that face each other across the center of the planar shape. The second main electrode is drawn out from inside the sealing portion at each of the third and fourth corners, which are the other two of the four corners other than the first and second corners. Effect of the Invention

[0008] The semiconductor device according to the present disclosure has an advantage that each of the multiple semiconductor modules can be arranged with a high degree of freedom. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is an exploded perspective view showing a configuration example of a semiconductor device according to a first embodiment; [Diagram 2] FIG. 1 is a perspective view of a semiconductor module included in a semiconductor device according to a first embodiment; [Diagram 3] FIG. 1 is a top view of a semiconductor module included in a semiconductor device according to a first embodiment; [Figure 4] FIG. 1 is a side view of a semiconductor module included in a semiconductor device according to a first embodiment; [Diagram 5] FIG. 1 is a bottom view of a semiconductor module included in a semiconductor device according to a first embodiment; [Figure 6]FIG. 1 is a vertical cross-sectional view of a semiconductor module included in a semiconductor device according to a first embodiment; [Figure 7] FIG. 1 is a cross-sectional view of a semiconductor module included in a semiconductor device according to a first embodiment; [Figure 8] FIG. 1 is an internal connection diagram of a semiconductor module included in a semiconductor device according to a first embodiment. [Figure 9] FIG. 1 is a perspective view showing a state in which a semiconductor device according to a first embodiment is mounted on a substrate; [Figure 10] FIG. 1 is a plan view of a substrate on which a semiconductor device according to a first embodiment is mounted; [Figure 11] FIG. 1 is a diagram showing a first example of a combination pattern of semiconductor modules according to the first embodiment; [Figure 12] FIG. 13 is a diagram showing a second example of a combination pattern of semiconductor modules according to the first embodiment; [Figure 13] FIG. 1 is a perspective view showing a semiconductor device according to a first modification of the first embodiment; [Figure 14] FIG. 1 is a top view showing a semiconductor device according to a first modification of the first embodiment; [Figure 15] FIG. 11 is a perspective view showing a semiconductor device according to a second modification of the first embodiment; [Figure 16] FIG. 11 is a top view showing a semiconductor device according to a second modification of the first embodiment; [Figure 17] FIG. 13 is a perspective view showing a semiconductor device according to a third modification of the first embodiment; [Figure 18] FIG. 13 is a perspective view showing a semiconductor device according to a fourth modification of the first embodiment; [Figure 19] FIG. 13 is a perspective view showing a semiconductor device according to a fifth modification of the first embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Semiconductor devices according to embodiments will be described in detail below with reference to the drawings.

[0011] Embodiment 1 FIG. 1 is an exploded perspective view showing a configuration example of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 according to the first embodiment includes a plurality of semiconductor modules 2. The semiconductor device 1 is an integrated module in which the plurality of semiconductor modules 2 are integrated. Each of the plurality of semiconductor modules 2 has a similar configuration to one another. The semiconductor device 1 illustrated in FIG. 1 includes two semiconductor modules 2.

[0012] FIG. 1 shows a semiconductor device 1, a substrate 3 on which the semiconductor device 1 is mounted, and a cooler 4 for cooling the semiconductor device 1. The substrate 3 is a circuit board on which a circuit is mounted. For example, a control circuit for controlling the semiconductor device 1 is mounted on the substrate 3. In the example shown in FIG. 1, the cooler 4 is fixed to the semiconductor device 1 by two screws 5. The cooler 4 may have any configuration. A heat sink may be used as the cooler 4 for cooling the semiconductor device 1. In the following description, the side on which the substrate 3 is disposed relative to the semiconductor device 1 is referred to as "upper", and the side on which the cooler 4 is disposed relative to the semiconductor device 1 is referred to as "lower". The expressions "upper" and "lower" are used for convenience and do not mean upper and lower when the semiconductor device 1 is actually disposed.

[0013] FIG. 2 is a perspective view of the semiconductor module 2 included in the semiconductor device 1 according to the first embodiment. FIG. 3 is a top view of the semiconductor module 2 included in the semiconductor device 1 according to the first embodiment. FIG. 4 is a side view of the semiconductor module 2 included in the semiconductor device 1 according to the first embodiment. FIG. 5 is a bottom view of the semiconductor module 2 included in the semiconductor device 1 according to the first embodiment. FIG. 6 is a vertical cross-sectional view of the semiconductor module 2 included in the semiconductor device 1 according to the first embodiment. FIG. 7 is a horizontal cross-sectional view of the semiconductor module 2 included in the semiconductor device 1 according to the first embodiment. FIG. 8 is an internal wiring diagram of the semiconductor module 2 included in the semiconductor device 1 according to the first embodiment.

[0014] As shown in Figures 6 and 7, the semiconductor module 2 includes a plurality of main electrodes 10, an IGBT (Insulated Gate Bipolar Transistor) 11, an FWD (Free Wheeling Diode) 12, a base plate 13, an insulating substrate 14, a plurality of wires 16, a case 17, a lid 18, and a sealing material 19.

[0015] The base plate 13 is a metal plate. The base plate 13 transfers heat generated in each of the IGBT 11 and the FWD 12 to the cooler 4. The material of the base plate 13 is a metal material with high thermal conductivity, such as copper or aluminum. The base plate 13 has a lower surface which is a first surface, and an upper surface which is a second surface opposite to the first surface. The lower surface of the base plate 13 is a surface exposed to the outside of the semiconductor module 2, and is a surface facing the side where the cooler 4 is arranged. By directly or indirectly contacting the lower surface with the cooler 4, the base plate 13 can transfer the above-mentioned generated heat to the cooler 4.

[0016] The insulating substrate 14 is disposed on the upper surface side of the base plate 13. The insulating material constituting the insulating substrate 14 is, for example, ceramic or resin. On the upper surface of the insulating substrate 14, a circuit pattern 15 made of copper foil is provided.

[0017] Each of the IGBT 11 and the FWD 12 is a semiconductor chip joined to a circuit pattern 15. Each of the IGBT 11 and the FWD 12 is joined to the circuit pattern 15 by, for example, soldering. The IGBT 11 and the FWD 12 are connected in parallel to each other.

[0018] The multiple wires 16 provided in the semiconductor module 2 include wires 16 connecting electrodes of the IGBT 11 and the FWD 12, wires 16 connecting electrodes of the IGBT 11 and the circuit pattern 15, and wires 16 connecting electrodes of the FWD 12 and the circuit pattern 15.

[0019] Case 17 is provided on the upper surface of base plate 13. Case 17 forms the outer shell of semiconductor module 2. Case 17 has four side surfaces along the outer edge of base plate 13. Each of the four side surfaces includes a normal direction to the upper surface of base plate 13. In the following description, the normal direction to the upper surface of base plate 13 will be simply referred to as the normal direction. FIG. 4 shows one of the four side surfaces of case 17.

[0020] Case 17 surrounds insulating substrate 14, and IGBT 11, FWD 12, circuit pattern 15, and multiple wires 16 on insulating substrate 14. The lower end of case 17 is closed by base plate 13. The upper end of case 17 is closed by lid 18. A space formed by base plate 13, case 17, and lid 18 is filled with sealing material 19. Case 17, lid 18, and sealing material 19 are provided on the upper surface side of base plate 13 and form a sealing portion that seals insulating substrate 14 and the semiconductor chip.

[0021] A groove 21 is formed on each of the four side surfaces of the case 17. The groove 21 is recessed from the outside of the sealing portion toward the inside of the sealing portion, and extends along a direction perpendicular to the normal direction. The depth direction of the groove 21 is the direction from the outside of the sealing portion toward the inside of the sealing portion. The extension direction of the groove 21 is a direction perpendicular to the normal direction and perpendicular to the depth direction of the groove 21. In the following description, the extension direction of the groove 21 is also referred to as the longitudinal direction of the groove 21.

[0022] The cross section shown in Fig. 6 is a cross section including the normal direction, and is a cross section perpendicular to the longitudinal direction of groove 21 formed on each of two mutually opposing side surfaces among the four side surfaces. The shape of groove 21 in the cross section shown in Fig. 6 is a trapezoidal shape in which the width of groove 21, which is the length in the normal direction perpendicular to the longitudinal direction, increases from the outside of the sealing portion toward the inside of the sealing portion.

[0023] One of two adjacent semiconductor modules 2 shown in FIG. 1 is a first semiconductor module, and the other is a second semiconductor module. The first semiconductor module and the second semiconductor module are arranged with one side of the first semiconductor module and one side of the second semiconductor module facing each other. As shown in FIG. 1, a pin 6 is inserted into a gap formed by combining a groove 21 on the side of the first semiconductor module and a groove 21 on the side of the second semiconductor module. The pin 6 is inserted along the longitudinal direction of these grooves 21. The first semiconductor module and the second semiconductor module are connected to each other by the pin 6 inserted into the gap formed by combining the groove 21 of the first semiconductor module and the groove 21 of the second semiconductor module.

[0024] When the pin 6 is inserted, a part of the pin 6 is inserted into the groove 21 of the first semiconductor module, and another part of the pin 6 is inserted into the groove 21 of the second semiconductor module. The cross section of the part of the pin 6 inserted into the groove 21 of the first semiconductor module and the cross section of the part of the pin 6 inserted into the groove 21 of the second semiconductor module each have a trapezoidal shape that can be fitted into the groove 21. When the pin 6 is inserted into the groove 21, even if the pin 6 is pulled in a direction perpendicular to the longitudinal direction of the groove 21, the pin 6 does not come out of the groove 21. Even if a force in a direction that separates the first semiconductor module and the second semiconductor module from each other is applied to at least one of the first semiconductor module and the second semiconductor module, the pin 6 does not come out of the groove 21, and therefore the first semiconductor module and the second semiconductor module are not separated from each other. In this way, the first semiconductor module and the second semiconductor module are connected to each other by the pin 6. The first and second semiconductor modules are integrated together using pins 6 .

[0025] In the above description, the pin 6 is inserted into the groove 21 on the side surface of the first semiconductor module and the groove 21 on the side surface of the second semiconductor module facing the side surface of the first semiconductor module. Alternatively, the pin 6 may be inserted into the groove 21 on the side surface of the first semiconductor module and the groove 21 on the side surface of the second semiconductor module adjacent to the side surface of the first semiconductor module. In this case, the pin 6 is disposed so as to straddle the first semiconductor module and the second semiconductor module in the direction in which the pin 6 is inserted. In this case, the first semiconductor module and the second semiconductor module are integrated by using the pin 6. The number of pins 6 used to connect the first semiconductor module and the second semiconductor module is not limited to one, and may be multiple. The pin 6 may be inserted into the groove 21 of the first semiconductor module and the groove 21 of the second semiconductor module, and may be inserted into any position. The shape of the groove 21 is not limited to a trapezoidal shape. Groove 21 may be formed in any way so that when a force is applied to at least one of the first and second semiconductor modules in a direction that pulls the first and second semiconductor modules apart, inserted pin 6 does not come out of groove 21. For example, groove 21 may be in an L-shape or an S-shape, and pin 6 may have a shape that corresponds to groove 21 so that it can be inserted into groove 21.

[0026] 5, four semicircular cutouts 22 are formed on the outer edge of the base plate 13. The planar shape of the base plate 13 is a square with the four cutouts 22. Each cutout 22 is formed at the center of each side of the square.

[0027] 1 is passed through the notch 22 and screwed into a hole in the cooler 4. By screwing the screw 5, the base plate 13 is fastened to the cooler 4. By fastening the base plate 13 to the cooler 4, the semiconductor module 2 is fixed to the cooler 4.

[0028] A recess 23 is formed on each of the four side surfaces of the case 17. The recess 23 is formed on the notch 22. The recess 23 is recessed from the outside of the sealing portion toward the inside of the sealing portion and is formed along the normal direction. The cross section shown in FIG. 7 is a cross section perpendicular to the normal direction and passing through the groove 21 formed on each of the four side surfaces of the case 17. The shape of the recess 23 in the cross section shown in FIG. 7 is a semicircle that is slightly larger than the notch 22. The depth of the recess 23, which is the length recessed from the outside of the sealing portion toward the inside of the sealing portion, is set to a depth that allows the head of the screw 5 to pass when the screw 5 is attached.

[0029] 1, screws 5 are attached to two locations, namely, a notch 22 at one end in the direction in which the first semiconductor module and the second semiconductor module are arranged and a notch 22 at the other end. The first semiconductor module and the second semiconductor module, which are integrated with each other by pins 6, are fixed to the cooler 4 by the two screws 5, whereby the cooler 4 is fixed to the semiconductor device 1.

[0030] The position where the screw 5 is attached is not limited to the example shown in Fig. 1. The number of attached screws 5 is not limited to two and is arbitrary. It is sufficient that the screw 5 is attached to at least one of the positions where the screw 5 can be attached. Note that a hole into which the screw 5 is screwed is formed at the position of the cooler 4 where the screw 5 is attached.

[0031] 1, there are six notches 22 on the outer edge of the planar shape of the semiconductor device 1 when viewed from above. A screw 5 can be attached at the position of each of the six notches 22. Furthermore, there is one hole formed by combining the notch 22 of the first semiconductor module and the notch 22 of the second semiconductor module at the center of the semiconductor device 1 when viewed from above. A screw 5 can also be attached at the position of this hole. The screw 5 is attached at least in one of these positions.

[0032] 1, when the pin 6 is inserted so as to pass through the center of the semiconductor device 1, and when the screw 5 is attached to the hole in the center of the semiconductor device 1, the pin 6 is inserted after the screw 5 is attached. Alternatively, the pin 6 is inserted into the groove 21 of the first semiconductor module and the groove 21 of the second semiconductor module, excluding the recess 23 through which the screw 5 is passed. This prevents the pin 6 from interfering with the attachment of the screw 5.

[0033] According to the above description, the multiple semiconductor modules 2 of the semiconductor device 1 are integrated by the pins 6 and fixed to the cooler 4 by the screws 5. In this way, the cooler 4 is fixed to the semiconductor device 1. By using the screws 5 and the pins 6 as parts for fixing the cooler 4, the cooler 4 can be fixed to the semiconductor device 1 with a small number of parts. This makes it possible to miniaturize the configuration including the semiconductor device 1 and the cooler 4. In addition, it is possible to simplify the assembly work for the configuration including the semiconductor device 1 and the cooler 4. By forming the four notches 22 in the base plate 13, the positions of the screws 5 can be appropriately selected to fix the cooler 4.

[0034] Fig. 3 shows the shape of the top surface of the semiconductor module 2. Fig. 5 shows the shape of the bottom surface of the semiconductor module 2. The outer edge shape of the top surface of the semiconductor module 2 and the outer edge shape of the bottom surface of the semiconductor module 2 are the same. The planar shapes of the outer edge shape of the top surface of the semiconductor module 2 and the outer edge shape of the bottom surface of the semiconductor module 2 are the planar shapes of the semiconductor module 2 when viewed from the normal direction.

[0035] When the planar shape of the semiconductor module 2 is rotated 90 degrees around the center of the planar shape of the semiconductor module 2, the planar shape of the semiconductor module 2 after the rotation overlaps with the planar shape of the semiconductor module 2 before the rotation. That is, the planar shape of the semiconductor module 2 has four-fold symmetry. In this way, the planar shape of the semiconductor module 2 has rotational symmetry. The posture of the outer hull of the semiconductor module 2 does not appear to change before and after the semiconductor module 2 is rotated 90 degrees around an axis in the normal direction that passes through the center of the planar shape of the semiconductor module 2 as the rotation axis.

[0036] The planar shape of the semiconductor module 2 is the same as that of the base plate 13, and is a square with four notches 22. Since each notch 22 is formed at the center of each side of the square, the planar shape of the semiconductor module 2 has four-fold symmetry. Also, the planar shape of the semiconductor module 2 has four corners, just like a square.

[0037] Here, of the four corners, the lower left corner of the semiconductor module 2 is defined as the first corner. The corner on the same diagonal line as the first corner in the planar shape of the semiconductor module 2 is defined as the second corner. The second corner is defined as the upper right corner of the semiconductor module 2. That is, the first corner and the second corner are two of the four corners that face each other across the center of the planar shape of the semiconductor module 2. In addition, the two corners other than the first corner and the second corner are defined as the third corner and the fourth corner. The third corner is defined as the upper left corner of the semiconductor module 2. The fourth corner is defined as the lower right corner of the semiconductor module 2. In the description of FIG. 3, the upper left, lower left, upper right, and lower right represent positions relative to the center of the planar shape of the semiconductor module 2, and represent positions in FIG. 3.

[0038] 8, the multiple main electrodes 10 of the semiconductor module 2 include two gate electrodes 10a, six collector electrodes 10b, and six emitter electrodes 10c. The term "main electrodes 10" refers to the two gate electrodes 10a, the six collector electrodes 10b, and the six emitter electrodes 10c without distinction. Each of the six collector electrodes 10b is also referred to as a first main electrode. Each of the six emitter electrodes 10c is also referred to as a second main electrode.

[0039] One end of each of the main electrodes 10 is soldered to the circuit pattern 15. Each of the main electrodes 10 is electrically insulated from the base plate 13 by the insulating substrate 14. The other end of each of the main electrodes 10 is exposed to the outside of the sealing portion. Each of the main electrodes 10 is drawn from the inside of the sealing portion to the outside of the sealing portion through the lid 18. Each of the main electrodes 10 is drawn from the inside of the sealing portion in a direction opposite to the direction from the sealing portion to the base plate 13, i.e., upward. Each of the main electrodes 10 extends from the surface of the sealing portion opposite the base plate 13, i.e., in the normal direction from the upper surface of the lid 18.

[0040] As shown in Fig. 3, three collector electrodes 10b serving as first main electrodes are drawn out from the first corner. Three collector electrodes 10b serving as first main electrodes are drawn out from the second corner. Three emitter electrodes 10c serving as second main electrodes are drawn out from the third corner. Three emitter electrodes 10c serving as second main electrodes are drawn out from the fourth corner. In addition, two gate electrodes 10a are drawn out from positions adjacent to the three emitter electrodes 10c at the fourth corner.

[0041] Fig. 9 is a perspective view showing a state in which the semiconductor device 1 according to the first embodiment is mounted on a substrate 3. Fig. 10 is a plan view of the substrate 3 on which the semiconductor device 1 according to the first embodiment is mounted.

[0042] As shown in FIG. 10, a plurality of holes 25 are formed in the substrate 3. A main electrode 10 is passed through each of the plurality of holes 25. A plurality of electrodes 24 are also provided in the substrate 3. Each of the plurality of electrodes 24 is formed at a position where the main electrode 10 is passed through. The plurality of electrodes 24 provided in the substrate 3 include an electrode 24a to which only the main electrode 10 of one of the two semiconductor modules 2 is connected, and an electrode 24b to which the main electrodes 10 of both of the two semiconductor modules 2 are connected. The electrode 24b is an electrode that electrically connects the main electrode 10 of one of the two semiconductor modules 2 to the main electrode 10 of the other semiconductor module 2. The term "electrode 24" refers to the electrode 24a and the electrode 24b without distinguishing between them.

[0043] The substrate 3 is placed on the semiconductor device 1. The main electrodes 10 passed through the holes 25 are connected to the electrodes 24 by soldering. In this way, the semiconductor device 1 is mounted on the substrate 3, as shown in Fig. 9. The two semiconductor modules 2 are electrically connected to each other via a circuit mounted on the substrate 3.

[0044] Each of the multiple main electrodes 10 extends in the normal direction from the upper surface of the lid 18, so that when the substrate 3 is placed on the semiconductor device 1, the main electrodes 10 can be passed through each hole 25. Since each main electrode 10 is directly joined to the substrate 3 by soldering, no additional elements, such as wiring or a terminal block, are required to mount the semiconductor device 1 on the substrate 3. It is sufficient that the electrodes 24 and holes 25 are formed on the substrate 3, and no elements different from those required when a conventional power module is mounted need to be added to the substrate 3. Therefore, the semiconductor device 1 can be easily mounted on the substrate 3.

[0045] By providing the insulating substrate 14 in the semiconductor module 2, each of the main electrodes 10 and the circuit pattern 15 are electrically insulated from the base plate 13. Since each of the main electrodes 10 extends upward from the upper surface of the lid 18, electrical insulation between each of the main electrodes 10 and the cooler 4 can be easily ensured. This makes it possible to simplify the insulation design of the semiconductor device 1.

[0046] The semiconductor modules 2 are arranged so that the main electrodes 10 of one semiconductor module 2 and the main electrodes 10 of the other semiconductor module 2 are adjacent to each other, so that the two semiconductor modules 2 can be electrically connected in various arrangements by a short wiring pattern. That is, the two semiconductor modules 2 can be electrically connected by a wiring pattern with small inductance. Since the two semiconductor modules 2 can be electrically connected by a short wiring pattern, it is also easy to implement a snubber circuit or a protection circuit for noise countermeasures. The fact that the two semiconductor modules 2 can be electrically connected by a short wiring pattern is also advantageous in terms of ease of design and less malfunction. It can be said that the semiconductor device 1 is advantageous in terms of the arrangement of each of the semiconductor modules 2 with a high degree of freedom, simplification of insulation design, simplicity of wiring pattern, miniaturization of the circuit, and small inductance, compared to the case where a conventionally known discrete semiconductor is used.

[0047] Next, combination patterns of the semiconductor modules 2 will be described. Two examples of combination patterns will be described here. Fig. 11 is a diagram showing a first example of a combination pattern of the semiconductor modules 2 in the first embodiment. Fig. 12 is a diagram showing a second example of a combination pattern of the semiconductor modules 2 in the first embodiment. Figs. 11 and 12 show the top surface of a semiconductor device 1 consisting of two semiconductor modules 2.

[0048] Of the two semiconductor modules 2, the left semiconductor module 2 in each of Figures 11 and 12 is a first semiconductor module, and the right semiconductor module 2 is a second semiconductor module. In addition, in Figures 11 and 12, electrode 24b is shown for reference to show main electrode 10 of the first semiconductor module and main electrode 10 of the second semiconductor module that are electrically connected to each other by electrode 24b of substrate 3.

[0049] The first example shown in FIG. 11 is an example in which the positions of the collector electrode 10b and the emitter electrode 10c in the first semiconductor module are the same as those of the collector electrode 10b and the emitter electrode 10c in the second semiconductor module. In FIG. 11, the collector electrode 10b is disposed at the lower left and upper right parts of the first semiconductor module, and the emitter electrode 10c is disposed at the upper left and lower right parts of the first semiconductor module. The arrangement of the collector electrode 10b and the emitter electrode 10c in the second semiconductor module is the same as that of the first semiconductor module. In the first example, the first semiconductor module and the second semiconductor module are arranged so that the collector electrode 10b and the emitter electrode 10c, which are different main electrodes 10, are adjacent to each other.

[0050] In the first example shown in Fig. 11, the collector electrode 10b in the upper right portion of the first semiconductor module and the emitter electrode 10c in the upper left portion of the second semiconductor module are connected to each other by the electrode 24b. In the first example, the first semiconductor module and the second semiconductor module are connected in series. In the explanation of Fig. 11, the upper left, lower left, upper right, and lower right represent positions relative to the center of the planar shape of the semiconductor module 2, and represent positions in Fig. 11.

[0051] In the second example shown in FIG. 12, the second semiconductor module is rotated 90 degrees clockwise from the state shown in FIG. 11. The positions of the collector electrode 10b and the emitter electrode 10c in the first semiconductor module in FIG. 12 are the same as those in the first semiconductor module shown in FIG. 11. In FIG. 12, the collector electrode 10b is disposed at the upper left and lower right of the second semiconductor module, and the emitter electrode 10c is disposed at the lower left and upper right of the second semiconductor module. In the second example, the first semiconductor module and the second semiconductor module are disposed so that the main electrodes 10 of the same type are adjacent to each other. That is, the collector electrodes 10b of the same type of main electrodes 10 are adjacent to each other, and the emitter electrodes 10c of the same type of main electrodes 10 are adjacent to each other.

[0052] In a second example shown in Fig. 12, an emitter electrode 10c at the lower right of the first semiconductor module and an emitter electrode 10c at the lower left of the second semiconductor module are connected to each other by an electrode 24b. In the second example, the first semiconductor module and the second semiconductor module are connected in parallel. In the description of Fig. 12, the upper left, lower left, upper right, and lower right represent positions relative to the center of the planar shape of the semiconductor module 2, and represent positions in Fig. 12. The combination patterns of the semiconductor modules 2 are not limited to those exemplified in Figs. 11 and 12.

[0053] Since the planar shape of the semiconductor module 2 has rotational symmetry, the posture of the outer periphery of the second semiconductor module does not appear to change before and after the second semiconductor module is rotated. Also, since the collector electrode 10b is disposed at two corners on one diagonal line and the emitter electrode 10c is disposed at two corners on the other diagonal line, the positions of the collector electrode 10b and the emitter electrode 10c in the second semiconductor module are different between Figures 11 and 12.

[0054] 11 and 12, the semiconductor device 1 can change the arrangement of the first main electrodes and the second main electrodes in each semiconductor module 2 without changing the posture of the outer hull of each semiconductor module 2. This allows the arrangement of the semiconductor modules 2 connected to each other with a high degree of freedom. In addition, the main electrodes 10 electrically connected to each other in the semiconductor modules 2 can be selected with a high degree of freedom.

[0055] In the semiconductor device 1, by appropriately arranging the electrodes 24b, it is possible to select with a high degree of freedom the manner of electrical connection between the semiconductor modules 2 that are coupled to each other. For example, the electrical connection between the semiconductor modules 2 can be arbitrarily selected to be a series connection or a parallel connection. The semiconductor device 1 may include a mixture of semiconductor modules 2 connected in series to each other and semiconductor modules 2 connected in parallel to each other.

[0056] In the above description, each main electrode 10 is electrically connected to the substrate 3 by soldering, but a method other than soldering may be used to connect each main electrode 10 to the substrate 3. For example, each main electrode 10 may be electrically connected to the substrate 3 by press-fitting each main electrode 10 into the substrate 3.

[0057] In the above description, the sealing portion of the semiconductor module 2 includes the case 17, the lid 18, and the sealing material 19. The configuration of the sealing portion is not limited to the configuration described above. The sealing portion may be made of, for example, a molded resin. The configuration provided on the upper surface of the base plate 13 is sealed by being covered with the molded resin. The molded resin may be a transfer mold formed by transfer molding.

[0058] The semiconductor chip included in the semiconductor module 2 may be a semiconductor chip other than the IGBT 11 or the FWD 12. The semiconductor chip included in the semiconductor module 2 may be, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a diode, a silicon carbide (SiC) device, or a gallium nitride (GaN) device. For example, when the semiconductor chip included in the semiconductor module 2 is a MOSFET, the first main electrode and the second main electrode in the above description may be a source electrode and a drain electrode. When the semiconductor chip included in the semiconductor module 2 is a diode, the first main electrode and the second main electrode in the above description may be an anode electrode and a cathode electrode. The semiconductor module 2 may be an IPM (Intelligent Power Module) in which a gate drive circuit is added to a configuration sealed in a sealing portion.

[0059] In the above description, the semiconductor device 1 includes two semiconductor modules 2. The number of semiconductor modules 2 constituting the semiconductor device 1 may be any number. The arrangement of each of the multiple semiconductor modules 2 may also be any number. The arrangement of the multiple semiconductor modules 2 may be determined in accordance with the configuration of an electrical device in which the semiconductor device 1 is provided. For example, the arrangement of the multiple semiconductor modules 2 may be determined in accordance with the circuit system of a power conversion device in which the semiconductor device 1 is provided.

[0060] Next, modified examples of the semiconductor device 1 will be described. Fig. 13 is a perspective view showing a semiconductor device 1A according to a first modified example of the first embodiment. Fig. 14 is a top view showing the semiconductor device 1A according to the first modified example of the first embodiment. Figs. 13 and 14 show the semiconductor device 1A and a heat sink 4A which is a cooler. The heat sink 4A is fixed to the semiconductor device 1A.

[0061] The semiconductor device 1A includes six semiconductor modules 2 arranged in a line according to the shape of the heat sink 4A. In FIG. 14, an example of connection by wiring on the front side of the substrate 3 is shown by a dashed line, and an example of connection by wiring on the back side of the substrate 3 is shown by a broken line. The six semiconductor modules 2 include semiconductor modules 2 that are adjacent to each other and connected to each other by the substrate 3. Also, as shown in FIG. 14, among the six semiconductor modules 2, semiconductor modules 2 that are not adjacent to each other may be connected to each other by the substrate 3. For example, a configuration in which multiple semiconductor modules 2 are arranged in a line like the semiconductor device 1A can be applied to an electric device having a slim shape. In this way, the semiconductor device 1A in which multiple semiconductor modules 2 are arranged to fit the shape desired for the electric device can be realized.

[0062] Fig. 15 is a perspective view showing a semiconductor device 1B according to a second modified example of the first embodiment. Fig. 16 is a top view showing the semiconductor device 1B according to the second modified example of the first embodiment. Figs. 15 and 16 show the semiconductor device 1B and a heat sink 4B which is a cooler. The heat sink 4B is fixed to the semiconductor device 1B.

[0063] The semiconductor device 1B includes three sets of two semiconductor modules 2 similar to those shown in Fig. 1. That is, the semiconductor device 1B includes six semiconductor modules 2. The six semiconductor modules 2 are arranged in a staggered arrangement. In Fig. 16, an example of connection by wiring on the substrate 3 is represented by dashed lines.

[0064] Fig. 17 is a perspective view showing a semiconductor device 1C according to a third modified example of the first embodiment. Fig. 17 shows the semiconductor device 1C and a heat sink 4C which is a cooler. The heat sink 4C is fixed to the semiconductor device 1C. The semiconductor device 1C includes three sets of two semiconductor modules 2 similar to those shown in Fig. 1. That is, the semiconductor device 1C includes six semiconductor modules 2. The six semiconductor modules 2 are arranged in a matrix.

[0065] The semiconductor modules 2 of the semiconductor device 1 may be arranged in a staggered arrangement as shown in Figures 15 and 16, or may be arranged in a matrix as shown in Figure 17. The semiconductor modules 2 of the semiconductor device 1 may include a mixture of the semiconductor modules 2 arranged in a staggered arrangement and the semiconductor modules 2 arranged in a matrix.

[0066] FIG. 18 is a perspective view showing a semiconductor device 1D according to a fourth modified example of the first embodiment. FIG. 18 shows the semiconductor device 1D and a heat sink 4D, which is a cooler. The heat sink 4D is fixed to the semiconductor device 1D. The semiconductor device 1D includes six semiconductor modules 2. The heat sink 4D has an L-shaped planar shape. The six semiconductor modules 2 are arranged in an L-shape so as to match the planar shape of the heat sink 4D. For example, the arrangement of the multiple semiconductor modules 2 may be determined as in the semiconductor device 1D according to the shape of an electrical device intended by a designer. In this way, it is possible to realize the semiconductor device 1D in which the multiple semiconductor modules 2 are arranged so as to match the shape desired for the electrical device.

[0067] Fig. 19 is a perspective view showing a semiconductor device 1E according to a fifth modified example of the first embodiment. Fig. 19 shows the semiconductor device 1E and a heat sink 4E which is a cooler. The heat sink 4E is fixed to the semiconductor device 1E. The semiconductor device 1E includes six semiconductor modules 2. The six semiconductor modules 2 are arranged to match the planar shape of the heat sink 4E. The arrangement of the six semiconductor modules 2 in Fig. 19 is a further modification of the arrangement shown in Fig. 17 or the arrangement shown in Fig. 18.

[0068] For example, the arrangement of the multiple semiconductor modules 2 may be determined as in the semiconductor device 1E according to the shape of the electrical device intended by the designer. In this way, it is possible to realize the semiconductor device 1E in which the multiple semiconductor modules 2 are arranged so as to match the desired shape of the electrical device.

[0069] As in each of the modifications of the first embodiment, the semiconductor device 1A-1E can be realized with a configuration that meets the designer's intentions by arranging a plurality of semiconductor modules 2. This makes it possible to apply the semiconductor device 1A-1E to power conversion devices of various circuit types, such as a three-phase inverter, a single-phase inverter, a chopper, and a three-level inverter. By combining a plurality of semiconductor modules 2, the semiconductor device 1A-1E can also realize functions equivalent to those of a power module in which a plurality of semiconductor chips are mounted in one package.

[0070] In the semiconductor device 1, 1A-1E described in the first embodiment, when a failure occurs in one of the multiple semiconductor modules 2, only the failed semiconductor module 2 can be replaced. Therefore, according to the first embodiment, it is possible to reduce the repair cost of the semiconductor device 1, 1A-1E.

[0071] According to the first embodiment, each of the semiconductor modules 2 included in the semiconductor device 1, 1A-1E has a planar shape having four corners and rotational symmetry. The first main electrode is drawn out at each of the first and second corners that face each other among the four corners. The second main electrode is drawn out at each of the third and fourth corners, which are the two corners other than the first and second corners among the four corners. The semiconductor module 2 having such a configuration can change the arrangement of the first and second main electrodes in the semiconductor module 2 by rotating the semiconductor module 2 without changing the posture of the outer hull of the semiconductor module 2. In addition, the main electrodes 10 electrically connected between the semiconductor modules 2 can be selected with a high degree of freedom. As a result, it is possible to achieve an effect that each of the semiconductor modules 2 can be arranged with a high degree of freedom.

[0072] The configurations shown in the above embodiments are examples of the contents of the present disclosure. The configurations of the embodiments can be combined with other known technologies. Part of the configurations of the embodiments can be omitted or modified without departing from the gist of the present disclosure. [Explanation of symbols]

[0073] 1, 1A, 1B, 1C, 1D, 1E semiconductor device, 2 semiconductor module, 3 substrate, 4 cooler, 4A, 4B, 4C, 4D, 4E heat sink, 5 screw, 6 pin, 10 main electrode, 10a gate electrode, 10b collector electrode, 10c emitter electrode, 11 IGBT, 12 FWD, 13 base plate, 14 insulating substrate, 15 circuit pattern, 16 wire, 17 case, 18 lid, 19 sealing material, 21 groove, 22 cutout, 23 recess, 24, 24a, 24b electrodes, 25 hole.

Claims

1. A semiconductor device comprising a plurality of semiconductor modules, each of the plurality of semiconductor modules comprising: a base plate having a first surface exposed to the outside of the semiconductor module and a second surface opposite to the first surface; an insulating substrate disposed on the second surface side and provided with a circuit pattern; a semiconductor chip bonded to the circuit pattern; a sealing portion provided on the second surface side for sealing the insulating substrate and the semiconductor chip; a first main electrode and a second main electrode drawn out from inside the sealing portion in a direction opposite to the direction from the sealing portion toward the base plate; when the semiconductor module is viewed from the normal direction of the second surface, the planar shape of the semiconductor module has four corners and has rotational symmetry, the first main electrode is drawn out from inside the sealing portion at each of a first corner and a second corner that are two of the four corners and face each other across the center of the planar shape, the second main electrode is drawn out from inside the sealing portion at each of a third corner and a fourth corner that are two of the four corners other than the first corner and the second corner. A semiconductor device characterized by the above.

2. The sealing portion has four side surfaces including the normal direction of the second surface, each of the four side surfaces is formed with a groove that is recessed toward the inside of the sealing portion and extends along a direction perpendicular to the normal direction of the second surface, a first semiconductor module and a second semiconductor module, which are two adjacent semiconductor modules, are connected to each other by pins inserted into the groove of the first semiconductor module and the groove of the second semiconductor module. The semiconductor device according to claim 1, characterized by the above.

3. The semiconductor device according to claim 1 or 2, characterized in that a notch through which a screw for fixing the base plate to a cooler is passed is formed at the outer edge of the base plate.

4. The semiconductor device according to claim 1 or 2, characterized in that each of the first main electrode and the second main electrode is electrically insulated from the base plate by the insulating substrate.

5. The semiconductor device according to claim 1 or 2, characterized in that each of the first main electrode and the second main electrode extends from the surface of the sealing portion opposite to the base plate side in the normal direction of the second surface.

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