Multilayer ceramic capacitor

Abstract

The present invention provides a multilayer ceramic capacitor with which it is possible to increase capacity without increasing the size. A multilayer ceramic capacitor 1 includes: a first region EA1, a second region EA2, a third region EB1, and a fourth region EB2 on an end face side; a first central region EA0 which is disposed between the first region EA1 and the second region EA2 so as to be biased to the outside in a lamination direction T of a laminate 10, and has higher coverage; a second central region EB0 which is disposed between the third region EB1 and the fourth region EB2 so as to be biased to the outside in the lamination direction T of the laminate 10, and has higher coverage; a first inclined portion FA1 linking the first region EA1 and the first central region EA0; a second inclined portion FA2 linking the second region EA2 and the first central region EA0; a third inclined portion FB1 linking the third region EB1 and the second central region EB0; and a fourth inclined portion FB2 linking the fourth region EB2 and the second central region EB0.

Description

Multilayer ceramic capacitors

[0001] The present invention relates to a multilayer ceramic capacitor.

[0002] Multilayer ceramic capacitors have been known as multilayer ceramic electronic components. Generally, a multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes connected to the internal electrode layers and provided on both end surfaces of the laminate (see Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2003-243249

[0004] Multilayer ceramic capacitors are required to be smaller and have higher capacitance, but it has been difficult to achieve both of these characteristics.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor that can increase the capacitance without increasing the size of the multilayer ceramic capacitor.

[0006] The multilayer ceramic capacitor of the present invention comprises a laminate including a plurality of laminated dielectric layers, and including first and second main surfaces opposing each other in the lamination direction, first and second side surfaces opposing each other in a width direction perpendicular to the lamination direction, and first and second end surfaces opposing each other in a length direction perpendicular to the lamination direction and the width direction; first internal electrode layers arranged on the dielectric layers and exposed at the first end surfaces; second internal electrode layers arranged on the dielectric layers and exposed at the second end surfaces; and first internal electrode layers arranged on the first end surfaces and connected to the first internal electrode layers. a multilayer ceramic capacitor having an external electrode and a second external electrode disposed on the second end face and connected to the second internal electrode layer, wherein the first internal electrode layer has a first opposing portion facing the second internal electrode layer and a first lead portion drawn from the first opposing portion to the first end face side, the second internal electrode layer has a second opposing portion facing the first internal electrode layer and a second lead portion drawn from the second opposing portion to the second end face side, and the first opposing portion is a first lead portion that is a region on the first end face side a first region which is a region on the second end face side, a second region which is a region on the second end face side, and a first central region which is a region located between the first region and the second region, which is arranged biased toward the outside of the stack in the stacking direction with respect to the first region and the second region, and which has a higher coverage than the coverage of the first region and the second region; and the second opposing portion has a third region which is a region on the second end face side, a fourth region which is a region on the first end face side, and a region located between the third region and the fourth region, and a second central region that is positioned biased toward the outside of the laminate in the stacking direction relative to the first region and has higher coverage than the coverage of the third region and the fourth region, the first internal electrode layer further has a first inclined portion connecting the first region and the first central region and a second inclined portion connecting the second region and the first central region, and the second internal electrode layer further has a third inclined portion connecting the third region and the second central region and a fourth inclined portion connecting the fourth region and the second central region.

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor that can increase the capacitance without increasing the size of the multilayer ceramic capacitor.

[0008] 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment. FIG. 1 is a cross-sectional view taken along II-II in FIG. 1 , illustrating a schematic configuration of a laminate. FIG. 1 is a cross-sectional view taken along II-II in FIG. 1 , illustrating details of internal electrode layers of the laminate. FIG. 2A is a cross-sectional view taken along III-III in FIG. 2A. FIG. 2A is a cross-sectional view taken along IVA-IVA in FIG. 2A , illustrating a cross-sectional view along a first internal electrode layer. FIG. 2B is a cross-sectional view taken along IVB-IVB in FIG. 2A , illustrating a cross-sectional view along a second internal electrode layer. FIG. 5 is an enlarged photograph of a portion including a first central region and a second central region of the internal electrode layer in the photograph of FIG. 5. FIG. 5 is an enlarged photograph of a portion including a second region and a third region of the internal electrode layer in the photograph of FIG. 5. FIG. 6 is a diagram illustrating measurement points when measuring the thicknesses of the internal electrode layers and the dielectric layers. FIG. 7 is a diagram illustrating an example of an enlarged image of an exposed cross section of an internal layer portion by SEM. FIG. 8 is a schematic view illustrating a cross section of a dielectric sheet on which a conductive paste P1 is printed. FIG. 9 is a schematic view illustrating a cross section of a dielectric sheet on which a conductive paste P2 is printed on the dielectric sheet of FIG. 10. FIG. 2 is a schematic diagram showing a portion of a laminate sheet in which a portion that will become a first main surface side outer layer portion and a portion that will become a second main surface side outer layer portion are formed above and below a portion that will become an inner layer portion.

[0009] A multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to an embodiment of the present disclosure will be described with reference to the drawings. FIG. 1 is an external perspective view of the multilayer ceramic capacitor 1 according to the embodiment. FIG. 2A is a cross-sectional view taken along II-II in FIG. 1, illustrating a schematic configuration of a laminate. FIG. 2B is a cross-sectional view taken along II-II in FIG. 1, illustrating details of the internal electrode layers of the laminate. FIG. 3 is a cross-sectional view taken along III-III in FIG. 2A. FIG. 4A is a cross-sectional view taken along IVA-IVA in FIG. 2A, illustrating a cross-sectional view along a first internal electrode layer. FIG. 4B is a cross-sectional view taken along IVB-IVB in FIG. 2A, illustrating a cross-sectional view along a second internal electrode layer.

[0010] The drawings may be drawn in a simplified schematic form to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match those described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted. For example, the number of internal electrode layers shown in Figures 2A, 2B, and 3 is 12 for the sake of convenience, but this does not indicate the actual number of internal electrode layers 30. Terms used in the present invention that specify shapes and geometric conditions, as well as their degrees of similarity, such as "parallel," "orthogonal," and "identical," as well as values ​​of length and angle, are not limited to their strict meanings but are interpreted to include a range within which similar functions can be expected.

[0011] 1, the multilayer ceramic capacitor 1 according to the embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 10 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at both ends of the laminate 10 while being spaced apart from each other.

[0012] In Fig. 1, arrow T indicates the stacking direction of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T also corresponds to the thickness direction and height direction of the multilayer ceramic capacitor 1 and the laminate 10. In Fig. 1, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T. In Fig. 1, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T and the length direction L. A pair of external electrodes 40 are respectively disposed at one end and the other end of the length direction L of the laminate 10.

[0013] An XYZ Cartesian coordinate system is shown in Figures 1 to 4B and Figures 5 and 8 described below. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross sections shown in Figures 2A, 2B, and 8 are also referred to as LT cross sections. The cross section shown in Figure 3 is also referred to as WT cross section. The cross sections shown in Figures 4A and 4B are also referred to as LW cross sections.

[0014] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in the stacking direction T, a first end surface LS1 and a second end surface LS2 that face each other in a length direction L that is perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 that face each other in a width direction W that is perpendicular to the stacking direction T and the length direction L.

[0015] As shown in FIG. 1 , the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, unevenness may be formed on part or all of the surfaces constituting the laminate 10.

[0016] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, the L dimension is preferably 0.2 mm or more and 6 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, the T dimension is preferably 0.05 mm or more and 5 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, the W dimension is preferably 0.1 mm or more and 5 mm or less.

[0017] As shown in Figures 2A, 2B, and 3, the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0018] The internal layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers alternately stacked in the stacking direction T. The internal layer portion 11 includes, in the stacking direction T, the internal electrode layer 30 located closest to the first main surface TS1 to the internal electrode layer 30 located closest to the second main surface TS2. In the internal layer portion 11, the multiple internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The internal layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor. The thickness of the internal layer portion 11 in the stacking direction T varies along the length direction L according to the shapes of the internal electrode layer 30 located closest to the first main surface TS1 and the internal electrode layer 30 located closest to the second main surface TS2.

[0019] The dielectric layers 20 are made of a dielectric material, such as BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ The dielectric material may be a dielectric ceramic containing components such as BaTiO as the main component. The dielectric material may also be a material containing these main components to which subcomponents such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds are added. The dielectric material may be a material containing BaTiO as the main component. ３ It is particularly preferred that the material contains:

[0020] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 10 μm or less. The number of laminated dielectric layers 20 is preferably 15 or more and 1200 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers 20 in the inner layer portion 11 and the number of the dielectric layers 20 in each of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0021] The multiple internal electrode layers 30 include multiple first internal electrode layers 31 as multiple first internal conductor layers and multiple second internal electrode layers 32 as multiple second internal conductor layers. The first internal electrode layers 31 and the second internal electrode layers 32 are alternately arranged in the stacking direction T with the dielectric layer 20 sandwiched therebetween. The first internal electrode layers 31 are extended to the first end face LS1. The second internal electrode layers 32 are extended to the second end face LS2. Note that, hereinafter, when it is not necessary to distinguish between the first internal electrode layers 31 and the second internal electrode layers 32, the first internal electrode layers 31 and the second internal electrode layers 32 may be collectively referred to as the internal electrode layers 30.

[0022] 2A and 4A , the first internal electrode layer 31 has a first opposing portion EA and a first lead portion D1. The first opposing portion EA is a region facing the second internal electrode layer 32 with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The first lead portion D1 is a portion that extends from the first opposing portion EA to the first end face LS1 and is exposed at the first end face LS1.

[0023] 2A and 4B , the second internal electrode layer 32 has a second opposing portion EB and a second lead portion D2. The second opposing portion EB is a region facing the first internal electrode layer 31 with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The second lead portion D2 is a portion that is led from the second opposing portion EB to the second end face LS2 and is exposed at the second end face LS2.

[0024] In this embodiment, the first opposing portion EA and the second opposing portion EB face each other with the dielectric layer 20 interposed therebetween, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0025] The shapes of the first opposing portion EA and the second opposing portion EB are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or may be oblique. The shapes of the first lead-out portion D1 and the second lead-out portion D2 are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or may be oblique.

[0026] The width direction W of the first opposing portion EA and the width direction W of the first lead portion D1 may be the same, or one of them may be smaller. The width direction W of the second opposing portion EB and the width direction W of the second lead portion D2 may be the same, or one of them may be smaller.

[0027] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0028] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 15 or more and 1000 or less.

[0029] 2A, 2B, and 3, the first main surface side outer layer portion 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface side outer layer portion 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 may both be the same as the dielectric layers 20 used in the internal layer portion 11.

[0030] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where a first counter portion EA of the first internal electrode layer 31 and a second counter portion EB of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the inner layer portion 11. Figures 4A and 4B show the range of the counter electrode portion 11E in the width direction W and the length direction L. The counter electrode portion 11E is also called the effective portion of the capacitor.

[0031] The laminate 10 has a side surface outer layer portion. The side surface outer layer portion includes a first side surface outer layer portion WG1 and a second side surface outer layer portion WG2. The first side surface outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side surface WS1. The second side surface outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side surface WS2. Figures 3, 4A, and 4B show the ranges in the width direction W of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2. The side surface outer layer portion is also referred to as a W gap or a side gap.

[0032] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion includes a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion located between the counter electrode portion 11E and the first end face LS1 and including the dielectric layer 20 and the first lead portion D1. That is, the first end surface side outer layer portion LG1 is an aggregate of the portions of the plurality of dielectric layers 20 on the first end face LS1 side and the plurality of first lead portions D1. The second end surface side outer layer portion LG2 is a portion located between the counter electrode portion 11E and the second end face LS2 and including the dielectric layer 20 and the second lead portion D2. That is, the second end surface side outer layer portion LG2 is an aggregate of the portions of the plurality of dielectric layers 20 on the second end face LS2 side and the plurality of second lead portions D2. 2A, 2B, 4A, and 4B show the range of the first end-side outer layer portion LG1 and the second end-side outer layer portion LG2 in the length direction L. The end-side outer layer portions are also called L gaps or end gaps.

[0033] As shown in Figures 1, 2A, and 2B, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0034] The first external electrode 40A and the second external electrode 40B have the same basic configuration. The first external electrode 40A and the second external electrode 40B have shapes that are approximately plane-symmetric with respect to a WT cross section at the center in the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40.

[0035] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is in contact with the first lead portions D1 of each of the first internal electrode layers 31 exposed at the first end face LS1. This electrically connects the first external electrode 40A to the first internal electrode layers 31. The first external electrode 40A may also be disposed on a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0036] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is in contact with the second lead portions D2 of each of the second internal electrode layers 32 exposed at the second end face LS2. This electrically connects the second external electrode 40B to the second internal electrode layers 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0037] As described above, in the laminate 10, capacitance is formed by the first opposing portion EA of the first internal electrode layer 31 and the second opposing portion EB of the second internal electrode layer 32 facing each other via the dielectric layer 20. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0038] 2A, 2B, 4A, and 4B, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0039] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first lead portions D1 of each of the first internal electrode layers 31 exposed at the first end face LS1. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0040] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is in contact with the second lead portions D2 of each of the second internal electrode layers 32 exposed at the second end face LS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2.

[0041] The first underlying electrode layer 50A and the second underlying electrode layer 50B include at least one selected from a baked layer, a thin film layer, and the like.

[0042] The first base electrode layer 50A and the second base electrode layer 50B of this embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component may be the same type of ceramic material as that of the dielectric layer 20, or a different type of ceramic material. The ceramic component may be, for example, BaTiO ３, CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ It includes at least one selected from the following:

[0043] The baked layer is formed by, for example, applying and baking a conductive paste containing glass and metal to the laminate 10. The baked layer can be formed by simultaneously firing a pre-fired laminated chip, which is the material for the laminate 10 having multiple internal electrodes and dielectric layers, with a conductive paste applied to the laminated chip. Alternatively, the baked layer can be formed by first firing the laminated chip to obtain the laminate 10, and then applying and baking a conductive paste to the laminate 10. In the above configuration, the baked layer is preferably formed by baking a material containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the ceramic material added. The baked layer may be multiple layers.

[0044] The thickness of the first base electrode layer 50A located on the first end surface LS1 in the longitudinal direction L is preferably, for example, approximately 3 μm or more and 200 μm or less at the center of the first base electrode layer 50A in the stacking direction T and width direction W.

[0045] The thickness corresponding to the length direction L of the second base electrode layer 50B located on the second end surface LS2 is preferably, for example, approximately 3 μm or more and 200 μm or less at the center of the second base electrode layer 50B in the stacking direction T and width direction W.

[0046] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the first base electrode layer 50A provided in this portion, corresponding to the stacking direction T, is, for example, approximately 3 μm or more and 25 μm or less at the center of the length direction L and width direction W of the first base electrode layer 50A provided in this portion.

[0047] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness corresponding to the width direction W of the first base electrode layer 50A provided in this portion be, for example, approximately 3 μm or more and 25 μm or less at the center of the length direction L and stacking direction T of the first base electrode layer 50A provided in this portion.

[0048] When the second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, it is preferable that the thickness of the second base electrode layer 50B provided on this portion, corresponding to the stacking direction T, is, for example, approximately 3 μm or more and 25 μm or less at the center of the length direction L and width direction W of the second base electrode layer 50B provided on this portion.

[0049] When the second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness corresponding to the width direction W of the second base electrode layer 50B provided in this portion be, for example, approximately 3 μm or more and 25 μm or less at the center of the length direction L and stacking direction T of the second base electrode layer 50B provided in this portion.

[0050] In this embodiment, the first and second underlying electrode layers 50A and 50B may be thin film layers, which are layers on which metal particles are deposited.

[0051] When the first and second underlying electrode layers 50A and 50B are formed as thin film layers, they are preferably formed by a thin film formation method such as sputtering or vapor deposition. Here, a sputtered electrode formed by sputtering will be described.

[0052] In this embodiment, the first base electrode layer 50A is composed of a first thin film layer formed by a sputtered electrode. The second base electrode layer 50B is composed of a second thin film layer formed by a sputtered electrode. When forming the base electrode layer using a sputtered electrode, it is preferable to form the sputtered electrode directly on a portion of at least one of the first main surface TS1 and the second main surface TS2 of the laminate 10. In this embodiment, the first thin film layer formed by the sputtered electrode is disposed on a portion of the first main surface TS1 on the first side surface WS1 side. The second thin film layer formed by the sputtered electrode is disposed on a portion of the first main surface TS1 on the second side surface WS2 side.

[0053] The thin film layer formed by the sputtered electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This increases the adhesive strength of the external electrode 40 to the laminate 10. The thin film layer may be a single layer or may be formed of multiple layers. For example, it may be formed of a two-layer structure consisting of a layer of Ni—Cr alloy and a layer of Ni—Cu alloy.

[0054] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A.

[0055] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B.

[0056] The first plating layer 60A and the second plating layer 60B may contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of multiple layers. The first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0057] In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0058] In this embodiment, the second plating layer 60B has a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0059] The Ni plating layer prevents the first and second base electrode layers 50A and 50B from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 2 μm or more and 10 μm or less.

[0060] The external electrode 40 of this embodiment may have, for example, a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be disposed so as to cover the baked layer. When the conductive resin layer is disposed so as to cover the baked layer, the conductive resin layer is disposed between the baked layer and the plating layer (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the baked layer or may cover only a portion of the baked layer.

[0061] The conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even when the multilayer ceramic capacitor 1 is subjected to a physical shock or a shock due to a thermal cycle, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0062] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. The conductive particles preferably contain Ag. The conductive particles are, for example, Ag metal powder. Ag has the lowest resistivity among metals and is therefore suitable as an electrode material. Furthermore, Ag is a noble metal, so it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as conductive particles.

[0063] The conductive particles may also be metal powder whose surface is coated with Ag. When using metal powder whose surface is coated with Ag, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy powder thereof. In order to maintain the properties of Ag while making the base metal inexpensive, it is preferable to use Ag-coated metal powder.

[0064] Furthermore, the conductive particles may be Cu or Ni that has been subjected to an anti-oxidation treatment. Furthermore, the conductive particles may be metal powder in which the surface of metal powder is coated with Sn, Ni, or Cu. When using metal powder in which the surface of Sn, Ni, or Cu is coated, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0065] The shape of the conductive particles is not particularly limited. The conductive particles may be spherical, flat, or other shapes, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0066] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the electrical conductivity of the conductive resin layer. Specifically, the contact between the conductive particles forms an electrical path within the conductive resin layer.

[0067] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins, such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, the resin of the conductive resin layer preferably includes a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds, such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0068] The conductive resin layer may be formed of a plurality of layers. The thickness of the thickest part of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0069] Note that a configuration may be adopted in which a first plating layer 60A and a second plating layer 60B, which will be described later, are disposed directly on the laminate 10 without providing the first base electrode layer 50A and the second base electrode layer 50B. That is, the multilayer ceramic capacitor 1 may be configured to include plating layers that are directly and electrically connected to the first internal electrode layer 31 and the second internal electrode layer 32. In such a case, a catalyst may be disposed on the surface of the laminate 10 as a pretreatment, and then the plating layers may be formed.

[0070] Even in this case, the plating layer preferably comprises multiple layers. The lower plating layer and the upper plating layer each preferably contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing these metals. The lower plating layer is more preferably formed using Ni, which has solder barrier properties. The upper plating layer is more preferably formed using Sn or Au, which have good solder wettability. For example, when the first internal electrode layer 31 and the second internal electrode layer 32 are formed using Ni, the lower plating layer is preferably formed using Cu, which has good bonding properties with Ni. The upper plating layer may be formed as needed, and the external electrode 40 may be composed of only the lower plating layer. Furthermore, the upper plating layer may be the outermost layer, or another plating layer may be formed on the surface of the upper plating layer.

[0071] The thickness of each plating layer disposed without a base electrode layer is preferably 2 μm or more and 10 μm or less. The plating layer preferably does not contain glass. The metal content per unit volume of the plating layer is preferably 99% by volume or more.

[0072] Note that, when the plating layer is formed directly on the laminate 10, the thickness of the base electrode layer can be reduced. Therefore, the dimension of the multilayer ceramic capacitor 1 in the height direction T can be reduced by the amount of the reduced thickness of the base electrode layer, thereby making it possible to reduce the height of the multilayer ceramic capacitor 1. Alternatively, the thickness of the dielectric layer 20 sandwiched between the first internal electrode layer 31 and the second internal electrode layer 32 can be increased by the amount of the reduced thickness of the base electrode layer, thereby improving the thickness of the element body. In this way, by forming the plating layer directly on the laminate 10, the design freedom of the multilayer ceramic capacitor can be improved.

[0073] The above is the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the lengthwise dimension of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, the L dimension is preferably 0.2 mm or more and 6 mm or less. If the lengthwise dimension of the multilayer ceramic capacitor 1 is defined as T, the T dimension is preferably 0.05 mm or more and 5 mm or less. If the widthwise dimension of the multilayer ceramic capacitor 1 is defined as W, the W dimension is preferably 0.1 mm or more and 5 mm or less.

[0074] Here, through repeated studies, experiments, and simulations, the inventors of the present application have found that it is desirable to appropriately set the dimensions and coverage of each component included in a multilayer ceramic capacitor in order to increase capacitance without increasing the size of the multilayer ceramic capacitor. The internal electrode layers 30 contain, in addition to the metal material, voids where no metal material is present. The percentage of the internal electrode layers 30 occupied by the metal material will be described as coverage. Coverage is also referred to as the coverage rate of the internal electrode layers 30 relative to the dielectric layers 20. The voids where no metal material is present may contain ceramic components such as dielectrics or glass components such as silica. Alternatively, they may be voids. Hereinafter, this embodiment will be described in detail with reference to FIGS. 1 to 7 .

[0075] As shown in Figures 2A to 3, the inner layer portion 11 has a first main surface side inner layer portion 112, a second main surface side inner layer portion 113, and a central inner layer portion 111 arranged between the first main surface side inner layer portion and the second main surface side inner layer portion.

[0076] The first main surface side inner layer portion 112 is a portion on the first main surface TS1 side of the inner layer portion 11. The first main surface side inner layer portion 112 is, for example, a portion on the first main surface TS1 side of the inner layer portion 11, and is a portion including at least the fifth internal electrode layer 30 from the internal electrode layer 30 closest to the first main surface TS1. The first main surface side inner layer portion 112 is, for example, 25% of the inner layer portion 11 on the first main surface TS1 side in the stacking direction.

[0077] The second main surface side inner layer portion 113 is a portion on the second main surface TS2 side of the inner layer portion 11. The second main surface side inner layer portion 113 is, for example, a portion on the second main surface TS2 side of the inner layer portion 11, and is a portion including at least the fifth internal electrode layer 30 from the internal electrode layer 30 closest to the second main surface TS2. The second main surface side inner layer portion 113 is, for example, 25% of the inner layer portion 11 on the second main surface TS2 side in the stacking direction.

[0078] The central inner layer portion 111 is a portion of the inner layer portion 11 that is located on the central side in the stacking direction T of the laminate 10. The central inner layer portion 111 is, for example, a portion that includes at least the internal electrode layer 30 arranged in the central region of the laminate in the stacking direction T. The thicknesses of the central inner layer portion 111, the first main surface side internal layer portion 112, and the second main surface side internal layer portion 113 in the stacking direction T each vary along the length direction L in accordance with the shape of the internal electrode layer 30.

[0079] As shown in FIGS. 3 to 4B, the opposing electrode portion 11E of the inner layer portion 11 has a first side surface opposing electrode portion 112E, a second side surface opposing electrode portion 113E, and a central opposing electrode portion 111E.

[0080] The first side surface side opposing electrode portion 112E is a portion of the opposing electrode portion 11E on the first side surface WS1 side. For example, the first side surface side opposing electrode portion 112E is 25% of the opposing electrode portion 11E on the first side surface WS1 side in the width direction W. The first side surface side opposing electrode portion 112E has an area that overlaps with the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and parts of the central inner layer portion 111.

[0081] The second side surface side opposing electrode portion 113E is a portion of the opposing electrode portion 11E on the second side surface WS2 side. For example, the second side surface side opposing electrode portion 113E is 25% of the opposing electrode portion 11E on the second side surface WS2 side in the width direction W. The second side surface side opposing electrode portion 113E has an area that overlaps with the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and parts of the central inner layer portion 111.

[0082] The central opposing electrode portion 111E is disposed between the first side surface side opposing electrode portion 112E and the second side surface side opposing electrode portion 113E. The central opposing electrode portion 111E is a portion of the opposing electrode portion 11E that includes a central region in the width direction W. The central opposing electrode portion 111E has regions that overlap with the first main surface side inner layer portion 112, the second main surface side inner layer portion 113, and parts of the central inner layer portion 111.

[0083] Next, the internal electrode layer 30 will be described in detail with reference to FIG. 2B and FIGS. 4A to 4B.

[0084] The first opposing portion EA has a first region EA1, a second region EA2, and a first central region EA0. The first region EA1 is disposed on the first end face LS1 side. The second region EA2 is disposed on the second end face LS2 side. The first central region EA0 is located between the first region EA1 and the second region EA2. The first central region EA0 has higher coverage than the first region EA1 and the second region EA2. Also, as shown in FIG. 2B , the first central region EA0 is disposed closer to the outside of the laminate 10 than the first region EA1 and the second region EA2.

[0085] Specifically, in the first main surface side inner layer portion 112, the first central region EA0 of the first internal electrode layer 31 is arranged biased toward the first main surface TS1 side of the laminate 10 relative to the first region EA1 and the second region EA2. Also, in this embodiment, in the second main surface side inner layer portion 113, the first central region EA0 of the first internal electrode layer 31 is arranged biased toward the second main surface TS2 side of the laminate 10 relative to the first region EA1 and the second region EA2. Note that, in at least either the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113, the first central region EA0 may be arranged biased toward the outside of the laminate 10 relative to the first region EA1 and the second region EA2.

[0086] The second opposing portion EB has a third region EB1, a fourth region EB2, and a second central region EB0. The third region EB1 is disposed on the second end face LS2 side. The fourth region EB2 is disposed on the first end face LS1 side. The second central region EB0 is located between the third region EB1 and the fourth region EB2. The second central region EB0 has higher coverage than the third region EB1 and the fourth region EB2. As shown in FIG. 2B , the second central region EB0 is disposed closer to the outside of the stack 10 than the third region EB1 and the fourth region EB2.

[0087] Specifically, in the first main surface side inner layer portion 112, the second central region EB0 of the second internal electrode layer 32 is arranged biased toward the first main surface TS1 side of the laminate 10 relative to the third region EB1 and the fourth region EB2. Also, in this embodiment, in the second main surface side inner layer portion 113, the second central region EB0 of the second internal electrode layer 32 is arranged biased toward the second main surface TS2 side of the laminate 10 relative to the third region EB1 and the fourth region EB2. Note that in at least either the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113, the second central region EB0 may be arranged biased toward the outside of the laminate 10 relative to the third region EB1 and the fourth region EB2.

[0088] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0089] The first central region EA0 is preferably substantially parallel to a plane perpendicular to the stacking direction T. The first central region EA0, the first region EA1, and the second region EA2 preferably have substantially parallel portions. More preferably, the first central region EA0, the first region EA1, and the second region EA2 have substantially parallel portions to a plane perpendicular to the stacking direction T.

[0090] The second central region EB0 is preferably substantially parallel to a plane perpendicular to the stacking direction T. The second central region EB0, the third region EB1, and the fourth region EB2 preferably have substantially parallel portions. More preferably, the second central region EB0, the third region EB1, and the fourth region EB2 have substantially parallel portions to a plane perpendicular to the stacking direction T.

[0091] This makes it possible to prevent the formation of portions of the multilayer ceramic capacitor 1 that are locally large in size, thereby increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0092] In the longitudinal direction L, the distance Le0 of the first central region EA0 is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B. In addition, in the longitudinal direction L, the distance Le0 of the second central region EB0 is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B. It is preferable, but not limited to, that the distances of the first central region EA0 and the second central region EB0 be approximately equal in the longitudinal direction L. It is preferable that the first central region EA0 and the second central region EB0 be disposed within the range of the distance L1 between the first external electrode 40A and the second external electrode 40B in the longitudinal direction L.

[0093] In the longitudinal direction L, the ends of the first central region EA0 and the second central region EB0 on ​​the first end face LS1 side are located closer to the second end face LS2 than the ends 40AE of the first external electrodes 40A on the stack center side, which are located on the first main surface TS1 and the second main surface TS2. In the longitudinal direction L, the ends of the first central region EA0 and the second central region EB0 on ​​the second end face LS2 side are located closer to the first end face LS1 than the ends 40BE of the second external electrodes 40B on the stack center side, which are located on the first main surface TS1 and the second main surface TS2.

[0094] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0095] In the longitudinal direction L, the ends of the first region EA1 and the fourth region EB2 on the first end face LS1 side (left ends of the EA and EB regions in FIG. 2B ) are located closer to the first end face LS1 than the end 40AE, toward the center of the laminate, of the first external electrode 40A, which is located on the first main surface TS1 and the second main surface TS2. In the longitudinal direction L, the ends of the second region EA2 and the third region EB1 on the second end face LS2 side (right ends of the EA and EB regions in FIG. 2B ) are located closer to the second end face LS2 than the end 40BE, toward the center of the laminate, of the second external electrode 40B, which is located on the first main surface TS1 and the second main surface TS2.

[0096] This makes it possible to prevent the size of the multilayer ceramic capacitor 1 from increasing, while ensuring a large area for the opposing electrode portion 11E and increasing the capacitance.

[0097] The thickness of the first central region EA0 of the first internal electrode layer 31 in the stacking direction T is greater than the thickness of the first region EA1 and the thickness of the second region EA2 in the stacking direction T.

[0098] For example, the thickness of the first central region EA0 is preferably 101.6% to 111.3% of the thickness of the first region EA1 and the thickness of the second region EA2. The thickness of the first central region EA0 may be 101.6% to 109.8% of the thickness of the first region EA1 and the thickness of the second region EA2, and more preferably 102.0% to 109.8%. For example, the thickness of the first central region EA0 is even more preferably 103.0% to 109.8% of the thickness of the first region EA1 and the thickness of the second region EA2.

[0099] The thickness of the second central region EB0 of the second internal electrode layer 32 in the stacking direction T is greater than the thickness of the third region EB1 and the thickness of the fourth region EB2.

[0100] For example, the thickness of the second central region EB0 is preferably 101.6% to 111.3% of the thickness of the third region EB1 and the thickness of the fourth region EB2. The thickness of the second central region EB0 may be 101.6% to 109.8% of the thickness of the third region EB1 and the thickness of the fourth region EB2, and more preferably 102.0% to 109.8%. For example, the thickness of the second central region EB0 is even more preferably 103.0% to 109.8% of the thickness of the third region EB1 and the thickness of the fourth region EB2.

[0101] To collectively describe the first internal electrode layer 31 and the second internal electrode layer 32, the thicknesses of the first central region EA0 and the second central region EB0 are greater than the thicknesses of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. The thicknesses of the first central region EA0 and the second central region EB0 are preferably 101.6% to 111.3% of the thicknesses of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. The thicknesses of the first central region EA0 and the second central region EB0 may be 101.6% to 109.8% of the thicknesses of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2, and more preferably 102.0% to 109.8%. For example, it is more preferable that the thickness of the first central region EA0 and the second central region EB0 is 103.0% or more and 109.8% or less of the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2.

[0102] The thickness of the first central region EA0 of the first internal electrode layer 31 in the stacking direction T is greater than the thickness of the first lead portion D1.

[0103] For example, the thickness of the first central region EA0 is preferably 101.6% to 111.3% of the thickness of the first lead portion D1. For example, the thickness of the first central region EA0 may be 101.6% to 109.8% of the thickness of the first lead portion D1, and more preferably 102.0% to 109.8%. For example, the thickness of the first central region EA0 is even more preferably 103.0% to 109.8% of the thickness of the first lead portion D1.

[0104] The thickness of the second central region EB0 of the second internal electrode layer 32 in the stacking direction T is greater than the thickness of the second lead portion D2.

[0105] For example, the thickness of the second central region EB0 is preferably 101.6% to 111.3% of the thickness of the second lead portion D2. For example, the thickness of the second central region EB0 may be 101.6% to 109.8% of the thickness of the second lead portion D2, and more preferably 102.0% to 109.8%. For example, the thickness of the second central region EB0 is even more preferably 103.0% to 109.8% of the thickness of the second lead portion D2.

[0106] The first central area EA0 has a higher coverage than the first area EA1 and the second area EA2.

[0107] The difference between the coverage of the first central area EA0 and the coverage of the first area EA1 and the coverage of the second area EA2 is preferably 2.2 percentage points or more, and the difference between the coverage of the first central area EA0 and the coverage of the first area EA1 and the coverage of the second area EA2 is preferably 2.2 percentage points or more and 11.4 percentage points or less.

[0108] The difference between the coverage of the first central area EA0 and the coverage of the first area EA1 and the coverage of the second area EA2 is preferably 3.0 to 11.4 percentage points, inclusive, which is expected to produce a greater effect. Furthermore, the difference between the coverage of the first central area EA0 and the coverage of the first area EA1 and the coverage of the second area EA2 is more preferably 4.0 to 11.4 percentage points, inclusive.

[0109] The second central region EB0 has a higher coverage than the third region EB1 and the fourth region EB2.

[0110] The difference between the coverage of the second central region EB0 and the coverage of the third and fourth regions EB1 and EB2 is preferably 2.2 percentage points or more, and the difference between the coverage of the second central region EB0 and the coverage of the third and fourth regions EB1 and EB2 is preferably 2.2 percentage points or more and 11.4 percentage points or less.

[0111] The difference between the coverage of the second central region EB0 and the coverage of the third and fourth regions EB1 and EB2 is preferably 3.0 to 11.4 percentage points, which is more preferable for achieving a higher effect. Furthermore, the difference between the coverage of the second central region EB0 and the coverage of the third and fourth regions EB1 and EB2 is more preferably 4.0 to 11.4 percentage points.

[0112] To collectively describe the first internal electrode layer 31 and the second internal electrode layer 32, the coverage of the first central region EA0 and the second central region EB0 is higher than the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. The coverage of the first central region EA0 and the second central region EB0 is preferably 2.2 percentage points or more higher than the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. Furthermore, the difference between the coverage of the first central region EA0 and the second central region EB0 and the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 is preferably 2.2 percentage points or more and 11.4 percentage points or less. The difference between the coverage of the first central region EA0 and the second central region EB0 and the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 is preferably 3.0 to 11.4 percentage points, inclusive, to achieve a greater effect. Furthermore, the difference between the coverage of the first central region EA0 and the second central region EB0 and the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 is more preferably 4.0 to 11.4 percentage points, inclusive.

[0113] This allows the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to be increased, thereby sufficiently increasing the coverage, thereby further increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0114] The first internal electrode layer 31 further has a first inclined portion FA1 connecting the first region EA1 and the first central region EA0, and a second inclined portion FA2 connecting the second region EA2 and the first central region EA0, as shown in FIG. 2B.

[0115] The second internal electrode layer 32 further has a third inclined portion FB1 connecting the third region EB1 and the second central region EB0, and a fourth inclined portion FB2 connecting the fourth region EB2 and the second central region EB0.

[0116] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0117] The distance Le3 in the longitudinal direction L of the first inclined portion FA1 and the distance Le4 in the longitudinal direction L of the second inclined portion FA2 are shorter than the distance Le0 in the longitudinal direction L of the first central region EA0. Also, the distance Le4 in the longitudinal direction L of the third inclined portion FB1 and the distance Le3 in the longitudinal direction L of the fourth inclined portion FB2 are shorter than the distance Le0 in the longitudinal direction L of the second central region EB0.

[0118] This makes it possible to ensure the areas of the first central region EA0 and the second central region EB0 with high coverage, thereby enabling the capacitance to be increased without increasing the size of the multilayer ceramic capacitor 1.

[0119] The distance Le1 in the length direction L of the first region EA1 and the distance Le2 in the length direction L of the second region EA2 may be shorter than the distance Le0 in the length direction L of the first central region EA0. The distance Le2 in the length direction L of the third region EB1 and the distance Le1 in the length direction L of the fourth region EB2 may be shorter than the distance Le0 in the length direction L of the second central region EB0.

[0120] The ratio of the area of ​​the first central region EA0 to the area of ​​the first facing portion EA is preferably 50% to 90% and may be 60% to 85%. It is more preferably 70% to 80%, for example, 75%. The ratio of the area of ​​the second central region EB0 to the area of ​​the second facing portion EB is preferably 50% to 90% and may be 60% to 85%. It is more preferably 70% to 80% and may be 75%.

[0121] This allows a large area to be secured for the opposing electrode portion 11E, while also securing an area for arranging the first external electrode 40A and the second external electrode 40B, and further allows the areas of the first central region EA0 and the second central region EB0, which have high coverage, to be appropriately secured, thereby enabling the capacitance to be increased without increasing the size of the multilayer ceramic capacitor 1.

[0122] It is preferable, but not limited to, that the distance Le3 in the length direction L between the first inclined portion FA1 and the fourth inclined portion FB2 and the distance Le4 in the length direction L between the second inclined portion FA2 and the third inclined portion FB1 be approximately equal. It is preferable that the first central region EA0 and the second central region EB0 are arranged within the range of the distance L1 between the first external electrode 40A and the second external electrode 40B, and that the first inclined portion FA1, the second inclined portion FA2, the third inclined portion FB1, and the fourth inclined portion FB2 are also arranged. The sum of the distance Le0 in the length direction L between the first central region EA0 and the second central region EB0, the distance Le3 in the length direction L between the first inclined portion FA1 and the fourth inclined portion FB2, and the distance Le4 in the length direction L between the second inclined portion FA2 and the third inclined portion FB1 (=Le0+Le3+Le4) is preferably shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B, although this is not limited to this.

[0123] The inclination angle θ of the first inclined portion FA1 with respect to the first central region EA0 is preferably 1° or greater. For example, the inclination angle θ of the first inclined portion FA1 with respect to the first central region EA0 may be 1° or greater and 12° or less. More preferably, the inclination angle θ of the first inclined portion FA1 with respect to the first central region EA0 may be 2° or greater and 10° or less.

[0124] The inclination angle θ of the second inclined portion FA2 with respect to the first central region EA0 is preferably 1° or greater. For example, the inclination angle θ of the second inclined portion FA2 with respect to the first central region EA0 may be 1° or greater and 12° or less. More preferably, the inclination angle θ of the second inclined portion FA2 with respect to the first central region EA0 may be 2° or greater and 10° or less.

[0125] The inclination angle θ of the third inclined portion FB1 with respect to the second central region EB0 is preferably 1° or greater. For example, the inclination angle θ of the third inclined portion FB1 with respect to the second central region EB0 may be 1° or greater and 12° or less. More preferably, the inclination angle θ of the third inclined portion FB1 with respect to the second central region EB0 may be 2° or greater and 10° or less.

[0126] The inclination angle θ of the fourth inclined portion FB2 with respect to the second central region EB0 is preferably 1° or greater. For example, the inclination angle θ of the fourth inclined portion FB2 with respect to the second central region EB0 may be 1° or greater and 12° or less. More preferably, the inclination angle θ of the fourth inclined portion FB2 with respect to the second central region EB0 may be 2° or greater and 10° or less.

[0127] FIG. 2B shows the inclination angle θ of the third inclined portion FB1 with respect to the second central region EB0 in the second internal electrode layer 32 as a representative of the inclination angles θ.

[0128] This allows the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to be increased, thereby improving coverage and increasing capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing. Specifically, by setting the inclination angle θ to 1° or more, preferably 2° or more, an area for increasing the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 can be secured. Furthermore, by setting the inclination angle θ to 12° or less, preferably 10° or less, it is possible to prevent the surface of the laminate 10 from excessively bulging in the stacking direction T and protruding outward beyond the surfaces of the external electrodes 40. More specifically, by setting the inclination angle θ within the above range, it becomes easy to set the relationship between the thicknesses of the first central region EA0 and the second central region and the thicknesses of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 within the range of this embodiment. Furthermore, by setting the inclination angle θ within the above-mentioned range, it becomes easy to set the relationship between the distance T0 at the center of the exposed portion of the laminate 10 described below and the maximum distance T1 in the covered portion of the laminate described below within the range of this embodiment described below.

[0129] The thickness of the first inclined portion FA1 gradually decreases toward the first end face LS1 as shown in Figures 2A and 2B, and the thickness of the second inclined portion FA2 gradually decreases toward the second end face LS2 as shown in Figures 2A and 2B.

[0130] The thickness of the third inclined portion FB1 gradually decreases toward the second end face LS2 as shown in Figures 2A and 2B, and the thickness of the fourth inclined portion FB2 gradually decreases toward the first end face LS1 as shown in Figures 2A and 2B.

[0131] If there is a portion where the thickness of the internal electrode layers 30 changes suddenly, there is a possibility that a portion where the distance between the internal electrode layers 30 sandwiching the dielectric layer 20 is locally short will be formed. In this case, an electric field will be concentrated in that portion, which may reduce the reliability of the multilayer ceramic capacitor 1. With the above configuration, it is possible to prevent the formation of a portion where the distance between the internal electrode layers 30 is locally short near the inclined portion, and therefore it is possible to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1, while also preventing a reduction in the reliability of the multilayer ceramic capacitor 1 due to electric field concentration.

[0132] Furthermore, since stress concentration at the inclined portions can be prevented, the capacitance can be increased without increasing the size of the multilayer ceramic capacitor 1, and furthermore, the occurrence of cracks in the laminate can be suppressed.

[0133] 2B , the step distance ls1 in the stacking direction T between the first region EA1 and the first central region EA0 caused by the first inclined portion FA1 is larger than the thickness Tc in the stacking direction T of the dielectric layer 20 disposed between the internal electrode layers 30. More preferably, the step distance ls1 in the stacking direction T between the first region EA1 and the first central region EA0 caused by the first inclined portion FA1 is larger than the sum Tt (=Te+Tc) of the thickness Te in the stacking direction T of the internal electrode layer 30 and the thickness Tc in the stacking direction T of the dielectric layer 20. Even more preferably, the step distance ls1 in the stacking direction T between the first region EA1 and the first central region EA0 caused by the first inclined portion FA1 is at least twice the sum Tt of the thickness Te in the stacking direction T of the internal electrode layer 30 and the thickness Tc in the stacking direction T of the dielectric layer 20. Furthermore, the step distance ls1 in the stacking direction T between the first region EA1 and the first central region EA0 caused by the first inclined portion FA1 may be three times or more the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0134] 2B , the step distance ls2 in the stacking direction T between the second region EA2 and the first central region EA0 caused by the second inclined portion FA2 is larger than the thickness Tc in the stacking direction T of the dielectric layer 20 disposed between the internal electrode layers 30. More preferably, the step distance ls2 in the stacking direction T between the second region EA2 and the first central region EA0 caused by the second inclined portion FA2 is larger than the sum Tt (=Te+Tc) of the thickness Te in the stacking direction T of the internal electrode layer 30 and the thickness Tc in the stacking direction T of the dielectric layer 20. Even more preferably, the step distance ls2 in the stacking direction T between the second region EA2 and the first central region EA0 caused by the second inclined portion FA2 is at least twice the sum Tt of the thickness Te in the stacking direction T of the internal electrode layer 30 and the thickness Tc in the stacking direction T of the dielectric layer 20. Furthermore, the step distance ls2 in the stacking direction T between the second region EA2 and the first central region EA0 created by the second inclined portion FA2 may be three times or more the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0135] 2B , a step distance ls3 in the stacking direction T between the third region EB1 and the second central region EB0 caused by the third inclined portion FB1 is larger than a thickness Tc in the stacking direction T of the dielectric layer 20 disposed between the internal electrode layers 30. More preferably, the step distance ls3 in the stacking direction T between the third region EB1 and the second central region EB0 caused by the third inclined portion FB1 is larger than a sum Tt (=Te+Tc) of a thickness Te in the stacking direction T of the internal electrode layer 30 and a thickness Tc in the stacking direction T of the dielectric layer 20. Even more preferably, the step distance ls3 in the stacking direction T between the third region EB1 and the second central region EB0 caused by the third inclined portion FB1 is at least twice the sum Tt of a thickness Te in the stacking direction T of the internal electrode layer 30 and a thickness Tc in the stacking direction T of the dielectric layer 20. Furthermore, the step distance ls3 in the stacking direction T between the third region EB1 and the second central region EB0 caused by the third inclined portion FB1 may be three times or more the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0136] 2B , the step distance ls4 in the stacking direction T between the fourth region EB2 and the second central region EB0 caused by the fourth inclined portion FB2 is larger than the thickness Tc in the stacking direction T of the dielectric layer 20 disposed between the internal electrode layers 30. More preferably, the step distance ls4 in the stacking direction T between the fourth region EB2 and the second central region EB0 caused by the fourth inclined portion FB2 is larger than the sum Tt (=Te+Tc) of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Even more preferably, the step distance ls4 in the stacking direction T between the fourth region EB2 and the second central region EB0 caused by the fourth inclined portion FB2 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Furthermore, the step distance ls4 in the stacking direction T between the fourth region EB2 and the second central region EB0 created by the fourth inclined portion FB2 may be three times or more the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0137] The thickness Te of the internal electrode layer 30 in the stacking direction T is the thickness of the internal electrode layer 30 in the first central region EA0 and the second central region EB0 in the stacking direction T. The thickness Tc of the dielectric layer 20 in the stacking direction T is the thickness of the dielectric layer 20 arranged between the first central region EA0 and the second central region EB0 in the stacking direction T.

[0138] This allows the thickness of the internal electrode layer 30 in the first central region EA0 and the second central region EB0 to be increased by taking advantage of the steps created by the inclined portions, thereby sufficiently increasing the coverage, thereby further increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0139] The step distance ls1 in the stacking direction T between the first region EA1 and the first central region EA0, which is caused by the first inclined portion FA1, may be 1.6 μm or more, or may be 1.6 μm or more and 16 μm or less. For example, it may be 2.9 μm or more and 14.8 μm or less. The step distance ls2 in the stacking direction T between the second region EA2 and the first central region EA0, which is caused by the second inclined portion FA2, may be 1.6 μm or more and may be 1.6 μm or more and 16 μm or less. For example, it may be 2.9 μm or more and 14.8 μm or less. The step distance ls3 in the stacking direction T between the third region EB1 and the second central region EB0, which is caused by the third inclined portion FB1, may be 1.6 μm or more and may be 1.6 μm or more and 16 μm or less. For example, it may be 2.9 μm or more and 14.8 μm or less. The step distance ls4 in the stacking direction T between the fourth region EB2 and the second central region EB0, which is generated by the fourth inclined portion FB2, may be 1.6 μm or more, or may be 1.6 μm or more and 16 μm or less, for example, 2.9 μm or more and 14.8 μm or less.

[0140] The first internal electrode layer 31 further has a fifth inclined portion FA3 located in the first lead portion D1, and the second internal electrode layer 32 further has a sixth inclined portion FB3 located in the second lead portion D2.

[0141] This ensures a long path for moisture to penetrate from the outside, thereby increasing the capacitance and ensuring moisture resistance without increasing the size of the multilayer ceramic capacitor 1.

[0142] Moisture from a plating solution or the like may penetrate through the interface between the laminate 10 and the external electrode layers. By providing the fifth inclined portion FA3 and the sixth inclined portion FB3, the distance of the penetration path through this interface to the end of the internal electrode layer 30 can be increased. Therefore, the capacitance can be increased and moisture resistance can be ensured without increasing the size of the multilayer ceramic capacitor 1.

[0143] Furthermore, moisture such as plating solution may penetrate from the surface of the external electrode 40 through the thickness direction of the external electrode 40. By providing the fifth inclined portion FA3 and the sixth inclined portion FB3, the end of the internal electrode layer 30 can be positioned closer to the center in the height direction of the laminate 10, where the thickness of the external electrode 40 in the length direction L usually tends to be large. Therefore, it is possible to increase the capacitance and ensure moisture resistance without increasing the size of the multilayer ceramic capacitor 1.

[0144] Furthermore, by providing the fifth inclined portion FA3 and the sixth inclined portion FB3, the distance from the end of the internal electrode layer 30 to the opposing portion of the internal electrode layer 30 can be increased. This increases the distance of the path for moisture penetration to reach the opposing portion of the internal electrode layer 30. Therefore, the capacitance can be increased and moisture resistance can be ensured without increasing the size of the multilayer ceramic capacitor 1.

[0145] The inclination angle θ of the first inclined portion FA1 and the second inclined portion FA2 is smaller than the inclination angle θ2 of the fifth inclined portion FA3. That is, the inclination angle θ of the fifth inclined portion FA3 is larger than the inclination angle θ of the first inclined portion FA1 and the second inclined portion FA2.

[0146] The inclination angle θ2 of the fifth inclined portion FA3 with respect to the first central area EA0 or the first area EA1 may be, for example, 10° or more, or 15° or more.

[0147] The inclination angle θ of the third inclined portion FB1 and the fourth inclined portion FB2 is smaller than the inclination angle θ2 of the sixth inclined portion FB3. That is, the inclination angle θ2 of the sixth inclined portion FB3 is larger than the inclination angle θ of the third inclined portion FB1 and the fourth inclined portion FB2.

[0148] The inclination angle θ2 of the sixth inclined portion FB3 with respect to the second central region EB0 or ​​the third region EB1 may be, for example, 10° or more, or 15° or more.

[0149] FIG. 2B shows the inclination angle θ2 of the sixth inclined portion FB3 with respect to the second central region EB0 and the third region EB1 in the second internal electrode layer 32 as a representative of the inclination angle θ2 described above.

[0150] This ensures a longer path for moisture to penetrate from the outside, thereby increasing the capacitance and ensuring moisture resistance without increasing the size of the multilayer ceramic capacitor 1.

[0151] 2A and 2B , the laminate 10 has exposed portions Ep exposed from the first external electrode 40A and the second external electrode 40B, a first covered portion C1 covered by the first external electrode, and a second covered portion C2 covered by the second external electrode 40B. A distance L1 in the length direction L of the exposed portions Ep exposed from the first external electrode 40A and the second external electrode 40B corresponds to the distance L1 between the first external electrode 40A and the second external electrode 40B.

[0152] In this embodiment, the distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep is longer than the maximum distance T1, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the first covering portion C1. Also, in this embodiment, the distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep is longer than the maximum distance T1, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the second covering portion C2. Note that in this embodiment, the distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep is the maximum distance in the stacking direction T of the exposed portion Ep of the laminate 10.

[0153] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0154] The distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep is preferably 103.2% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the first covering portion C1. For example, the distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep may be 100.6% or more and 103.2% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the first covering portion C1. More preferably, the distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep may be 100.6% or more and 102.7% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the first covering portion C1. In this embodiment, the distance in the stacking direction T connecting a flat portion PA1 and a flat portion PB1 (to be described later) is the above-mentioned maximum distance T1.

[0155] The distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep is preferably 103.2% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the second covering portion C2. For example, the distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep may be 100.6% or more and 103.2% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the second covering portion C2. More preferably, the distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep may be 100.6% or more and 102.7% or less of the maximum distance T1 in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the second covering portion C2. In this embodiment, the distance in the stacking direction T connecting a flat portion PA2 and a flat portion PB2 (to be described later) is the above-mentioned maximum distance T1.

[0156] The distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep is shorter than the maximum distance T2, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the first external electrode 40A. Also, the distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep is shorter than the maximum distance T2, which is the maximum value of the distance in the stacking direction T connecting the first main surface TS1-side surface and the second main surface TS2-side surface of the second external electrode 40B.

[0157] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0158] The ratio of the thickness of the first central region EA0 of the first internal electrode layer 31 in the stacking direction T to the thickness of the first region EA1 in the stacking direction T may be set to be larger than the ratio of the distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep of the laminate 10 to the maximum distance T1 in the stacking direction T of the first covered portion C1 of the laminate 10. The ratio of the thickness of the second central region EB0 of the second internal electrode layer 32 to the thickness of the third region EB1 in the stacking direction T may be set to be larger than the ratio of the distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep of the laminate 10 to the maximum distance T1 in the stacking direction T of the second covered portion C2 of the laminate 10.

[0159] As shown in FIG. 2A , the first main surface TS1 has a first exposed surface EpsA exposed from the first external electrode 40A and the second external electrode 40B, a first covered surface C1sA covered by the first external electrode 40A, and a second covered surface C2sA covered by the second external electrode 40B.

[0160] 1 and 2A, the first exposed surface EpsA has a first flat surface PA0 parallel to the stacking direction T, a first inclined surface FC1 connecting the first flat surface PA0 to the first coated surface C1sA, and a second inclined surface FC2 connecting the first flat surface PA0 to the second coated surface C2sA. In this embodiment, a flat portion PA1 is formed on the first coated surface C1sA toward the center of the stack, and the first inclined surface FC1 connects the first flat surface PA0 to the flat portion PA1. Furthermore, a flat portion PA2 is formed on the second coated surface C2sA toward the center of the stack, and the second inclined surface FC2 connects the first flat surface PA0 to the flat portion PA2. That is, the first main surface TS1 of this embodiment has a planar portion PA1 on the first end face LS1 side, a planar portion PA2 on the second end face LS2 side, a first planar surface PA0 arranged between planar portions PA1 and PA2 and protruding from planar portions PA1 and PA2, a first inclined surface FC1 connecting the first planar surface PA0 and the planar portion PA1, and a second inclined surface FC2 connecting the first planar surface PA0 and the planar portion PA2.

[0161] As shown in FIG. 2A, the second principal surface TS2 has a second exposed surface EpsB exposed from the first external electrode 40A and the second external electrode 40B, a third covered surface C1sB covered by the first external electrode 40A, and a fourth covered surface C2sB covered by the second external electrode.

[0162] The second exposed surface EpsB has a second flat surface PB0 parallel to the stacking direction T, a third inclined surface FC3 connecting the second flat surface PB0 to the third coated surface C1sB, and a fourth inclined surface FC4 connecting the second flat surface PB0 to the fourth coated surface C2sB. In this embodiment, a flat portion PB1 is formed on the third coated surface C1sB toward the center of the stack, and the third inclined surface FC3 connects the second flat surface PB0 to the flat portion PB1. Furthermore, a flat portion PB2 is formed on the fourth coated surface C2sB toward the center of the stack, and the fourth inclined surface FC4 connects the second flat surface PB0 to the flat portion PB2. That is, the second main surface TS2 of this embodiment has a planar portion PB1 on the first end face LS1 side, a planar portion PB2 on the second end face LS2 side, a second planar surface PB0 arranged between the planar portions PB1 and PB2 and protruding from the planar portions PB1 and PB2, a third inclined surface FC3 connecting the second planar surface PB0 and the planar portion PB1, and a fourth inclined surface FC4 connecting the second planar surface PB0 and the planar portion PB2.

[0163] This makes it easier to ensure the areas of the first central region EA0 and the second central region EB0 with high coverage corresponding to the first flat surface PA0 or the second flat surface PB0, thereby increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1. Furthermore, by forming the flat surfaces, it is possible to suppress poor suction during mounting.

[0164] The distance Lt1 in the length direction L of the first inclined surface FC1 and the distance Lt2 in the length direction L of the second inclined surface FC2 are shorter than the distance Lt0 in the length direction L of the first flat surface PA0. The distance Lt1 in the length direction L of the third inclined surface FC3 and the distance Lt2 in the length direction L of the fourth inclined surface FC4 are shorter than the distance Lt0 in the length direction L of the second flat surface PB0.

[0165] This makes it easier to ensure the areas of the first central region EA0 and the second central region EB0, which have high coverage, corresponding to the first flat surface PA0 or the second flat surface PB0, and thus makes it possible to further increase the capacitance without increasing the size of the multilayer ceramic capacitor 1. Furthermore, by ensuring the areas of the flat surfaces, it is possible to suppress poor suction during mounting.

[0166] In this embodiment, the distance Lt0 of the first flat surface PA0 in the longitudinal direction L is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B. The distance Lt0 of the second flat surface PB0 in the longitudinal direction L is also shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B. Thus, the distance Lt0 in the longitudinal direction L between the first flat surface PA0 and the second flat surface PB0 is preferably within the range of the distance L1 between the first external electrode 40A and the second external electrode 40B. The end portion 40AE of the first external electrode 40A may be located on the first inclined surface FC1 and the third inclined surface FC3, or may be located on the flat portion PA1 and the flat portion PB1 closer to the first end face LS1 than the first inclined surface FC1 and the third inclined surface FC3. The end 40BE of the second external electrode 40B may be located on the second inclined surface FC2 and the fourth inclined surface FC4, or may be located on the flat surface PA2 and the flat surface PB2 closer to the second end face LS2 than the second inclined surface FC2 and the fourth inclined surface FC4. In this embodiment, the end 40AE of the first external electrode 40A is located near the boundary between the first inclined surface FC1 and the flat surface PA1 and near the boundary between the third inclined surface FC3 and the flat surface PB1. The end 40BE of the second external electrode 40B is located near the boundary between the second inclined surface FC2 and the flat surface PA2 and near the boundary between the fourth inclined surface FC4 and the flat surface PB2.

[0167] This makes it possible to increase the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0, thereby increasing the coverage and increasing the capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0168] The inclination angle φ of the first inclined surface FC1 with respect to the first flat surface PA0 is preferably 1° or more. For example, the inclination angle φ of the first inclined surface FC1 with respect to the first flat surface PA0 may be 1° or more and 10° or less. More preferably, the inclination angle φ of the first inclined surface FC1 with respect to the first flat surface PA0 may be 2° or more and 5° or less.

[0169] The inclination angle φ of the second inclined surface FC2 with respect to the first flat surface PA0 is preferably 1° or more. For example, the inclination angle φ of the second inclined surface FC2 with respect to the first flat surface PA0 may be 1° or more and 10° or less. More preferably, the inclination angle φ of the second inclined surface FC2 with respect to the first flat surface PA0 may be 2° or more and 5° or less.

[0170] The inclination angle φ of the third inclined surface FC3 with respect to the second flat surface PB0 is preferably 1° or more. For example, the inclination angle φ of the third inclined surface FC3 with respect to the second flat surface PB0 may be 1° or more and 10° or less. More preferably, the inclination angle φ of the third inclined surface FC3 with respect to the second flat surface PB0 may be 2° or more and 5° or less.

[0171] The inclination angle φ of the fourth inclined surface FC4 with respect to the second flat surface PB0 is preferably 1° or more. For example, the inclination angle φ of the fourth inclined surface FC4 with respect to the second flat surface PB0 may be 1° or more and 10° or less. More preferably, the inclination angle φ of the fourth inclined surface FC4 with respect to the second flat surface PB0 may be 2° or more and 5° or less.

[0172] In addition, in FIG. 2A, the inclination angle φ of the fourth inclined surface FC4 with respect to the second flat surface PB0 in the second main surface TS2 is shown as a representative of the inclination angles φ described above.

[0173] This allows the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 to be increased, thereby improving coverage and increasing capacitance, while preventing the size of the multilayer ceramic capacitor 1 from increasing. Specifically, by setting the inclination angle φ to 1° or more, preferably 2° or more, an area for increasing the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 can be secured. Furthermore, by setting the inclination angle φ to 10° or less, preferably 5° or less, it is possible to prevent the surface of the laminate 10 from excessively bulging in the stacking direction T and protruding outward beyond the surfaces of the external electrodes 40. More specifically, by setting the inclination angle φ within the above-described range, it becomes easy to set the relationship between the thicknesses of the first central region EA0 and the second central region and the thicknesses of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 within the range of this embodiment. Furthermore, by setting the inclination angle φ within the above-mentioned range, it becomes easy to set the relationship between the distance T0 at the center of the exposed portion of the laminate 10 and the maximum distance T1 at the covered portion of the laminate within the range of this embodiment.

[0174] The first flat surface PA0 is preferably substantially parallel to a plane perpendicular to the stacking direction T. The first flat surface PA0 is preferably substantially parallel to the planar portion PA1 and the planar portion PA2. More preferably, the first flat surface PA0 is substantially parallel to the plane perpendicular to the stacking direction T.

[0175] The second flat surface PB0 is preferably substantially parallel to a plane perpendicular to the stacking direction T. The second flat surface PB0 is preferably substantially parallel to the planar portion PB1 and the planar portion PB2. More preferably, the second flat surface PB0 is substantially parallel to the plane perpendicular to the stacking direction T.

[0176] This makes it possible to prevent the formation of portions of the multilayer ceramic capacitor 1 that are locally large in size, thereby increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0177] As shown in FIG. 2A, the step distance tf in the stacking direction T between the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 and the flat portions PA1 and PA2, i.e., the protrusion height tf (one-side bulge dimension of the laminate) of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2, is preferably smaller than the thickness tg in the stacking direction T of the first external electrode 40A and the second external electrode 40B arranged on the first main surface TS1. It is preferable that the step distance tf in the stacking direction T between the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 and the flat portions PB1 and PB2, i.e., the protrusion height tf (one-side bulge dimension of the laminate) of the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4, is smaller than the thickness tg in the stacking direction T of the first external electrode 40A and the second external electrode 40B arranged on the second main surface TS2.

[0178] This makes it possible to increase the capacitance while preventing the size of the multilayer ceramic capacitor 1 from increasing.

[0179] The protrusion height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 is preferably 2.9 μm or more and 14.8 μm or less. The protrusion height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 may be 2.9 μm or more and 12.6 μm or less. The protrusion height tf of the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 is preferably 2.9 μm or more and 14.8 μm or less. The protrusion height tf of the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 may be 2.9 μm or more and 12.6 μm or less.

[0180] The protrusion height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 is greater than the thickness Tc in the stacking direction T of the dielectric layer 20 arranged between the internal electrode layers 30. More preferably, the protrusion height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 is greater than the sum Tt (= Te + Tc) of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Even more preferably, the protrusion height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Furthermore, the protrusion height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 may be three times or more the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0181] The protrusion height tf of the second flat surface PBO formed by the third inclined surface FC3 and the fourth inclined surface FC4 is greater than the thickness Tc in the stacking direction T of the dielectric layer 20 arranged between the internal electrode layers 30. More preferably, the protrusion height tf of the second flat surface PBO formed by the third inclined surface FC3 and the fourth inclined surface FC4 is greater than the sum Tt (= Te + Tc) of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Even more preferably, the protrusion height tf of the second flat surface PBO formed by the third inclined surface FC3 and the fourth inclined surface FC4 is at least twice the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T. Furthermore, the protrusion height tf of the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4 may be three times or more the sum Tt of the thickness Te of the internal electrode layer 30 in the stacking direction T and the thickness Tc of the dielectric layer 20 in the stacking direction T.

[0182] This makes it possible to take advantage of the steps created by the inclined surfaces to secure areas where the thickness of the internal electrode layers 30 in the first central region EA0 and the second central region EB0 can be increased, thereby sufficiently increasing coverage, thereby enabling the capacitance to be increased without increasing the size of the multilayer ceramic capacitor 1.

[0183] The thickness t01 in the stacking direction T in the first flat surface PA0 region of the first main surface side outer layer portion 12 is smaller than the thickness t11 in the stacking direction T in the first coated surface C1sA region of the first main surface side outer layer portion 12 and the thickness t21 in the stacking direction T in the second coated surface C2sA region of the first main surface side outer layer portion 12.

[0184] The thickness t02 in the stacking direction T in the second flat surface PB0 region of the second main surface side outer layer portion 13 is smaller than the thickness t12 in the stacking direction T in the first coating surface C1sA region of the second main surface side outer layer portion 13 and the thickness t22 in the stacking direction T in the second coating surface C2sA region of the second main surface side outer layer portion 13.

[0185] This increases the capacitance without increasing the size of the multilayer ceramic capacitor 1, while ensuring a longer distance between the external electrode 40 and the internal electrode layer 30, thereby suppressing the concentration of the electric field, thereby suppressing a decrease in the reliability of the multilayer ceramic capacitor 1 due to electric field concentration.

[0186] Furthermore, by ensuring that the distances between thicknesses t11, t21, t12, and t22 are longer, even if a crack occurs in the laminate 10 near the end of the external electrode 40, such as near the boundary between the exposed portion Ep of the laminate 10 and the first covering portion C1 or the second covering portion C2, the crack can be prevented from reaching the internal electrode.

[0187] In this embodiment, by having the above-mentioned inclined surfaces, flat surfaces as part of the surface of the laminate 10 are arranged in a raised manner on both the first main surface TS1 and the second main surface TS2, but a flat surface as part of the surface of the laminate 10 may also be arranged in a raised manner on either the first main surface TS1 or the second main surface TS2.

[0188] 2A and 2B, the thickness in the length direction L of the first external electrode 40A at the center in the stacking direction T is greater than the thickness in the length direction L of the first external electrode 40A on the first main surface TS1 side in the stacking direction T and the thickness in the length direction L of the first external electrode 40A on the second main surface TS2 side in the stacking direction T. Also, as shown in Figures 4A and 4B, the thickness in the length direction L of the first external electrode 40A at the center in the width direction W is greater than the thickness in the length direction L of the first external electrode 40A on the first side surface WS1 side in the width direction W and the thickness in the length direction L of the first external electrode 40A on the second side surface WS2 side in the width direction W.

[0189] 2A and 2B, the thickness in the length direction L of the second external electrode 40B at the center in the stacking direction T is greater than the thickness in the length direction L of the second external electrode 40B on the first main surface TS1 side in the stacking direction T and the thickness in the length direction L of the second external electrode 40B on the second main surface TS2 side in the stacking direction T. Also, as shown in Figures 4A and 4B, the thickness in the length direction L of the second external electrode 40B at the center in the width direction W is greater than the thickness in the length direction L of the second external electrode 40B on the first side surface WS1 side in the width direction W and the thickness in the length direction L of the second external electrode 40B on the second side surface WS2 side in the width direction W.

[0190] This ensures a longer path for moisture to penetrate from the outside, thereby increasing the capacitance and ensuring moisture resistance without increasing the size of the multilayer ceramic capacitor 1.

[0191] The first internal electrode layer 31 of this embodiment preferably has the above-mentioned first central region EA0, which has higher coverage and is thicker than the first region EA1 and the second region EA2, in the first main surface side internal layer portion 112, the second main surface side internal layer portion 113, and the central internal layer portion 111. However, the first internal electrode layer 31 may have the above-mentioned first central region EA0, which has higher coverage and is thicker than the first region EA1 and the second region EA2, in at least a portion of the first main surface side internal layer portion 112 or the second main surface side internal layer portion 113. This also provides the effect of increasing capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0192] The second internal electrode layer 32 of this embodiment preferably has the above-mentioned second central region EB0, which has higher coverage and is thicker than the third region EB1 and the fourth region EB2, in the first main surface side internal layer portion 112, the second main surface side internal layer portion 113, and the central internal layer portion 111. However, the second internal electrode layer 32 may have the above-mentioned second central region EB0, which has higher coverage and is thicker than the third region EB1 and the fourth region EB2, in at least one portion of the first main surface side internal layer portion 112 or the second main surface side internal layer portion 113. This also has the effect of increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0193] In this embodiment, the first inclined portion FA1, the second inclined portion FA2, the third inclined portion FB1, the fourth inclined portion FB2, the fifth inclined portion FA3, and the sixth inclined portion FB3 are arranged in the first main surface side inner layer portion 112 and the second main surface side inner layer portion 113. However, the first inclined portion FA1, the second inclined portion FA2, the third inclined portion FB1, the fourth inclined portion FB2, the fifth inclined portion FA3, and the sixth inclined portion FB3 may be arranged in at least one portion of the first main surface side inner layer portion 112 or the second main surface side inner layer portion 113.

[0194] The first internal electrode layer 31 of this embodiment preferably has the first side surface facing electrode portion 112E, the second side surface facing electrode portion 113E, and the above-mentioned first central region EA0 in the central opposing electrode portion 111E, which has higher coverage and is thicker than the first region EA1 and the second region EA2. Although the present disclosure is not limited thereto, by having the above-mentioned first central region EA0 in the first side surface facing electrode portion 112E and the second side surface facing electrode portion 113E in addition to the central opposing electrode portion 111E, which has higher coverage and is thicker than the first region EA1 and the second region EA2, it is possible to ensure the area of ​​the first central region EA0 with high coverage, and therefore it is possible to further increase the capacitance without increasing the size of the multilayer ceramic capacitor 1. At least the central opposing electrode portion 111E may have the above-mentioned first central region EA0 which has a higher coverage and a larger thickness than the first region EA1 and the second region EA2.

[0195] The second internal electrode layer 32 of this embodiment preferably has the first side surface facing electrode portion 112E, the second side surface facing electrode portion 113E, and the above-mentioned second central region EB0 in the central opposing electrode portion 111E, which has higher coverage and is thicker than the third region EB1 and the fourth region EB2. Although the present disclosure is not limited thereto, by having the above-mentioned second central region EB0 in the first side surface facing electrode portion 112E and the second side surface facing electrode portion 113E in addition to the central opposing electrode portion 111E, which has higher coverage and is thicker than the third region EB1 and the fourth region EB2, it is possible to ensure the area of ​​the second central region EB0 with high coverage, and therefore it is possible to further increase the capacitance without increasing the size of the multilayer ceramic capacitor 1. At least the central opposing electrode portion 111E may have the second central region EB0 described above, which has a higher coverage and a larger thickness than the third region EB1 and the fourth region EB2.

[0196] 5 to 7 are diagrams showing examples of enlarged images of the cross section of the multilayer ceramic capacitor 1 of this embodiment observed with an optical microscope.

[0197] Fig. 5 is a photograph showing a portion of the cross section of the laminate 10. Fig. 5 is a cross-sectional photograph showing the upper right region of the laminate 10 in Fig. 2B, and is a cross-sectional photograph including a portion of the first main surface side inner layer portion 112. The upper left region, lower right region, and lower left region of the laminate 10 in Fig. 2B are basically configured in bilateral symmetry, vertical symmetry, and rotational symmetry with the upper right region shown in Fig. 5. Therefore, the photograph in Fig. 5 will be used to represent these regions in the following description. Fig. 5 is a cross-sectional photograph of the laminate 10 in a state in which the external electrode 40 is not arranged.

[0198] Fig. 6 is an enlarged photograph of portion VI in the photograph of Fig. 5, which is a portion including the first central region EA0 of the first internal electrode layer 31 and the second central region EB0 of the second internal electrode layer 32. Fig. 7 is an enlarged photograph of portion VII in the photograph of Fig. 5, which is a portion including the second region EA2 of the first internal electrode layer 31 and the third region EB1 of the second internal electrode layer 32.

[0199] From the optical microscope photograph of FIG. 5, it can be seen that the laminate 10 has an inner layer portion 11 and a first main surface side outer layer portion 12 constituted by a dielectric layer 20.

[0200] 5, it can be seen that in the inner layer portion 11, a portion in which the first inner electrode layer 31 and the second inner electrode layer 32 are arranged as the inner electrode layer 30 is located. In addition, it can be seen from the optical microscope photographs of FIGS. 6 and 7 that the dielectric layer 20 is arranged between the plurality of inner electrode layers 30.

[0201] From the optical microscope photograph of Figure 5, it can be seen that the laminate 10 has a region (EA, EB region) where the first opposing portion EA of the first internal electrode layer 31 and the second opposing portion EB of the second internal electrode layer 32 are present, and a region (D2 region) where the second lead portion D2 of the second internal electrode layer 32 is present.

[0202] 5, it can be seen that the laminate 10 has a region indicated by the range of distance Le0 where the first central region EA0 of the first internal electrode layer 31 and the second central region EB0 of the second internal electrode layer 32 exist, a region indicated by the range of distance Le2 where the second region EA2 of the first internal electrode layer 31 and the third region EB1 of the second internal electrode layer 32 exist, and a region indicated by the range of distance Le4 where the second inclined portion FA2 of the first internal electrode layer 31 and the third inclined portion FB1 of the second internal electrode layer 32 exist. It can also be seen that a sixth inclined portion FB3 exists in the region of the second lead portion D2 of the second internal electrode layer 32.

[0203] Furthermore, from the optical microscope photograph of Figure 5, it can be seen that the first main surface TS1 of the laminate 10 has a first flat surface PA0 parallel to the stacking direction T, a plane portion PA2, and a second inclined surface FC2 connecting the first flat surface PA0 and the plane portion PA2.

[0204] Here, the coverage of the first central region EA0 and the second central region EB0 is compared with that of the second region EA2 and the third region EB1 using FIGS. 6 and 7 . In FIGS. 6 and 7 , the black linear portions extending in the left-right direction represent the dielectric layer 20, and the white linear portions extending in the left-right direction represent the internal electrode layer 30. Furthermore, the black portions present in the middle of the white linear portions extending in the left-right direction represent void portions V where no metal material is present. Therefore, the more white portions there are, the higher the coverage. It can be seen that there are fewer void portions V in FIG. 6 compared to FIG. 7 . Therefore, it can be seen that the coverage of the first central region EA0 and the second central region EB0 shown in FIG. 6 is higher than the coverage of the second region EA2 and the third region EB1 shown in FIG. 7 .

[0205] <Measurement of Various Parameters> Hereinafter, methods for measuring various parameters will be described. Various parameters can be measured by the following methods.

[0206] <Method of Measuring Thickness of Internal Electrode Layers and Dielectric Layers> Hereinafter, a method of measuring the thickness of the internal electrode layers 30 of the multilayer ceramic capacitor 1 in the lamination direction T will be described.

[0207] First, the multilayer ceramic capacitor 1 is polished from the first side surface WS1 or the second side surface WS2 to expose the LT cross section, which exposes the opposing electrode portion 11E of the laminate 10. If necessary, the exposed cross section at the observation position is etched to remove the internal electrode layers 30 stretched by the polishing. Measurement points M1 to M6 of the exposed cross section, shown in FIG. 8, are observed using a scanning electron microscope (SEM). FIG. 8 shows an example of the LT cross section of the multilayer ceramic capacitor 1, illustrating the measurement points used to measure the thicknesses of the internal electrode layers 30 and the dielectric layers 20. For example, if only the first main surface-side inner layer portion 112 has the first central region EA0 and second central region EB0, which have high coverage and a large thickness, measurement points M1 to M3 are observed using an SEM.

[0208] Measurement points M1 to M3 are set in the first main surface side inner layer portion 112. Measurement point M1 is a portion including the first region EA1 of the first internal electrode layer 31 and the fourth region EB2 of the second internal electrode layer 32. Measurement point M2 is a portion including the first central region EA0 of the first internal electrode layer 31 and the second central region EB0 of the second internal electrode layer 32. Measurement point M3 is a portion including the second region EA2 of the first internal electrode layer 31 and the third region EB1 of the second internal electrode layer 32.

[0209] Measurement points M4 to M6 are set in the second main surface side inner layer portion 113. Measurement point M4 is a portion including the first region EA1 of the first internal electrode layer 31 and the fourth region EB2 of the second internal electrode layer 32. Measurement point M5 is a portion including the first central region EA0 of the first internal electrode layer 31 and the second central region EB0 of the second internal electrode layer 32. Measurement point M6 is a portion including the second region EA2 of the first internal electrode layer 31 and the third region EB1 of the second internal electrode layer 32.

[0210] Measurement points M1 and M4 are set in the longitudinal direction L at the center position of the distance Le1 shown in Figures 2B and 8. Measurement points M2 and M5 are set in the longitudinal direction L at the center position of the distance Le0 shown in Figures 2B and 8. Measurement points M3 and M6 are set in the longitudinal direction L at the center position of the distance Le2 shown in Figures 2B and 8.

[0211] The observation magnification when observing each measurement point is set to a magnification at which the four dielectric layers 20 and the five internal electrode layers 30 can be observed and at which the dielectric layers 20 can be clearly distinguished from the internal electrode layers 30. Fig. 9 is a diagram illustrating an example of an enlarged image by SEM of the cross section of the exposed internal layer portion at the measurement point.

[0212] When measuring the thickness of the internal electrode layers 30 of the multilayer ceramic capacitor 1, first, as shown in FIG. 9 , five straight lines La to Le extending in the lamination direction of the laminate 10 are drawn at equal intervals of a pitch S on an enlarged image of the cross section of the multilayer ceramic capacitor 1. The pitch S may be determined to be about 5 to 10 times the thickness of the internal electrode layers 30 to be measured. For example, when measuring an internal electrode having a thickness of about 0.5 μm, the pitch S is set to 2.5 μm. Next, the thickness of the internal electrode layers 30 is measured on each of the straight lines La to Le. However, if an internal electrode layer is missing on each of the straight lines La to Le and the dielectric layers 20 sandwiching the internal electrode layer 30 are connected to each other, or if the enlarged image of the measurement position is unclear, a new straight line is drawn and the thickness of the internal electrode layer 30 is measured.

[0213] 9 , the thicknesses d1, d2, d3, d4, and d5 of the internal electrode layers 30 are measured. Then, for each of the measurement points in the first main surface side internal layer portion 112 and the second main surface side internal layer portion 113, the thickness of each of the five internal electrode layers 30 is measured by the above-described method, and the average value of the thicknesses is defined as the thickness of the internal electrode layer 30 of this embodiment. For example, when measuring the thicknesses of the first central region EA0 and the second central region EB0, the thickness is measured at 25 points (5 locations x 5 layers) at measurement point M2, and the thickness is measured at 25 points (5 locations x 5 layers) at measurement point M5, and the average value of the total 50 points is defined as the thickness of the first central region EA0 and the second central region EB0 of this embodiment. For example, when measuring the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2, the thickness is measured at 25 points (5 locations x 5 layers) at each of measurement points M1, M3, M4, and M6, and the average value of a total of 100 points is used as the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 in this embodiment.

[0214] The thickness of the dielectric layer 20 is also measured in the same manner as the internal electrode layer 30. When measuring the thickness of the dielectric layer 20, as shown in Fig. 9, the thickness D1 on the line La, the thickness D2 on the line Lb, the thickness D3 on the line Lc, the thickness D4 on the line Ld, and the thickness D5 on the line Le are measured.

[0215] Then, the thickness of each of the four dielectric layers 20 is measured by the above-described method at each measurement point in the first main surface side inner layer portion 112 and each measurement point in the second main surface side inner layer portion 113, and the average value is taken as the thickness of the dielectric layer 20 of this embodiment. The thickness of the dielectric layer 20 can be measured for each of the regions corresponding to the first central region EA0 and the second central region EB0, the region corresponding to the first region EA1 and the fourth region EB2, and the region corresponding to the second region EA2 and the third region EB1.

[0216] By repeating polishing and measurement, measurements can be performed at six measurement points M1 to M6 at three positions: the center position in the width direction W of the first side surface side opposing electrode portion 112E, the center position in the width direction W of the central opposing electrode portion 111E, and the center position in the width direction W of the second side surface side opposing electrode portion 113E.

[0217] <Coverage Measurement Method> A description will be given of a method for measuring coverage as the coverage rate of the internal electrode layer 30 relative to the dielectric layer 20. Note that the measurement of coverage in this measurement method is also called measurement of line coverage.

[0218] The line coverage of the exposed LT cross section is measured using an optical microscope. The measurement points for measuring the line coverage correspond to measurement points M1 to M6 shown in Figure 8. However, the magnification for observing each measurement point is 1000 times.

[0219] 6 and 7 , the internal electrode layer 30 has a region where a conductive component is present and a region where a conductive component is not present, such as a hollow portion V. The line coverage is calculated as the ratio of the length in the length direction L of the region occupied by the conductive component that actually constitutes the internal electrode layer 30 to the length in the length direction L of the internal electrode layer 30 when the presence or absence of the conductive component is not taken into consideration, in other words, the ratio of the length in the length direction L of the internal electrode layer 30 excluding the region where the conductive component is not present to the length in the length direction L of the internal electrode layer 30 when the presence or absence of the conductive component is not taken into consideration. Then, the coverage of the internal electrode layer 30 is measured for each of the measurement points in the first main surface side internal layer portion 112 and the second main surface side internal layer portion 113, and the average value thereof is taken as the coverage of the internal electrode layer 30 in this embodiment. For example, when measuring the coverage of the first central region EA0 and the second central region EB0, the coverage of the internal electrode layer 30 is measured at measurement point M2 and measurement point M5, and the average value is used as the coverage of the first central region EA0 and the second central region EB0 in this embodiment. For example, when measuring the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2, the coverage of the internal electrode layer 30 is measured at measurement points M1, M3, M4, and M6, and the average value is used as the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 in this embodiment.

[0220] <Method of measuring distances and angles> Various distances and angles are measured using the exposed LT cross section described above. The distance and angle measurements are performed using a digital microscope.

[0221] <Manufacturing Method> Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The multilayer ceramic capacitor 1 of this embodiment may be manufactured by any method as long as it satisfies the above-described requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0222] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known.

[0223] On the dielectric sheet, the conductive paste for the internal electrode layer 30 is printed in a predetermined pattern by, for example, screen printing, gravure printing, or the like. In this way, a dielectric sheet on which the patterns of the first internal electrode layer 31 and the second internal electrode layer 32 are formed is prepared. Note that the printing method is not limited to screen printing or the like.

[0224] Here, a method for printing the conductive paste for the internal electrode layers 30 onto the dielectric sheets will be described with reference to FIGS.

[0225] 11, the dielectric sheet on which the pattern of the internal electrode layer 30 is printed is composed of a ceramic green sheet G and conductive pastes P1 and P2 arranged on the ceramic green sheet G. The conductive pastes P1 and P2 are formed in the hollow portions of the screens S1 and S2.

[0226] First, as shown in FIG. 10 , a conductive paste P1 is placed on a ceramic green sheet G using a screen S1 having a hollow portion formed in a pattern corresponding to the outer shapes of the first internal electrode layer 31 and the second internal electrode layer 32.

[0227] Next, as shown in FIG. 11 , a screen S2 having hollow portions formed in a pattern corresponding to the first central region EA0 and the second central region EB0 is used to screen-print the conductive paste P2 onto the conductive paste P1. As a result, the portions corresponding to the first central region EA0 and the second central region EB0 are thicker than the other regions. Here, for example, the right-hand portion of the conductive paste P1 and the conductive paste P2 shown in FIG. 11 is a portion P31 that will become the first internal electrode layer 31 of a multilayer ceramic capacitor, and the left-hand portion is a portion P32 that will become the second internal electrode layer 32 of another multilayer ceramic capacitor. In this manner, a dielectric sheet is prepared.

[0228] By stacking a predetermined number of dielectric sheets on which the pattern of the internal electrode layer 30 is not printed, a portion P12 that becomes the first main surface side outer layer portion 12 on the first main surface TS1 side is formed.

[0229] Next, as shown in Fig. 12 , the screen-printed dielectric sheets shown in Fig. 11 are sequentially laminated on the surface of the portion P12 that will become the first main surface side outer layer portion 12, thereby forming the portion P11 that will become the inner layer portion 11. Focusing on the portion surrounded by C in Fig. 12 , a dielectric sheet G1 on which a conductive paste P31 that will become the first internal electrode layer 31 is arranged and a dielectric sheet G2 on which a conductive paste P32 that will become the second internal electrode layer 32 is arranged are sequentially laminated alternately. Note that the portion C in Fig. 12 is cut out in a subsequent process to form one laminated chip.

[0230] A predetermined number of dielectric sheets, on the surface of which the pattern of the internal electrode layer 30 is not printed, are laminated on the surface of the portion P11 that will become the inner layer portion 11, thereby forming a portion P13 that will become the second main surface side outer layer portion 13 on the second main surface TS2 side. In this way, a laminated sheet is produced.

[0231] The laminated sheets are pressed in the height direction by means of a hydrostatic press or the like to produce a laminated block.

[0232] The laminated block is cut to a predetermined size to obtain laminated chips, and at this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0233] The laminated chip is fired to produce the laminate 10. The firing temperature, which depends on the materials of the dielectric layers 20 and the internal electrode layers 30, is preferably 900°C or higher and 1400°C or lower. Here, by adjusting the thickness of the conductive paste for the internal electrode layers 30 according to the region and adjusting the pressing conditions and firing conditions, the laminate 10 having the structure of the internal electrode layers 30 and the surface shapes of the first main surface TS1 and the second main surface TS2 of this embodiment can be obtained. For example, by adjusting the application condition, including the thickness of the conductive paste for the internal electrode layers 30, and the pressing conditions, an inclined portion such as the first inclined portion FA1 whose thickness gradually decreases can be formed, thereby obtaining the internal electrode layers 30 of this embodiment.

[0234] A conductive paste that will become a base electrode layer is applied to both end surfaces of the laminate 10 .

[0235] In this embodiment, the conductive paste is also applied to the first and second main surfaces TS1 and TS2 and the first and second side surfaces WS1 and WS2 of the laminate 10. At this time, the conductive paste is applied so that the distance L1 between the first and second external electrodes 40A and 40B is longer than the distance Lt0 in the length direction L between the first and second central regions EA0 and EB0.

[0236] A more specific example of the manufacturing method will be described. The first main surface TS1 or the second main surface TS2 of the laminate 10 has a first flat surface PA0 and a second flat surface PB0 corresponding to the positions of the first central region EA0 and the second central region EB0. A first inclined surface FC1, a second inclined surface FC2, a third inclined surface FC3, and a fourth inclined surface FC4 are formed around the first flat surface PA0 and the second flat surface PB0. Furthermore, flat portions PA1, PA2, PB1, and PB2 are formed closer to the end faces than the inclined surfaces.

[0237] Therefore, for example, the conductive paste is applied to the flat portions PA1, PA2, PB1, and PB2 that are closer to the end faces than the respective inclined faces. By applying the conductive paste to the laminate 10 in this manner, the conductive paste is applied so that the distance L1 between the first external electrode 40A and the second external electrode 40B is longer than the distance Lt0 in the longitudinal direction L between the first central region EA0 and the second central region EB0. Note that the conductive paste may be applied to portions of the end faces of the first inclined face FC1, the second inclined face FC2, the third inclined face FC3, and the fourth inclined face FC4.

[0238] The above is an example of the manufacturing method, and the method is not limited to this. The base electrode layer can also be removed after the baking treatment for adjustment.

[0239] In this embodiment, the base electrode layer is a baked layer. A conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the base electrode layer. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0240] When the unfired laminated chip and the conductive paste applied to the laminated chip are simultaneously fired, the fired layer is preferably formed by firing a material containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layer 20 as the ceramic material added. In this case, the conductive paste is applied to the unfired laminated chip, and the laminated chip and the conductive paste applied to the laminated chip are simultaneously fired to form the laminate 10 with the fired layer formed thereon.

[0241] Thereafter, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Furthermore, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and a Sn plating layer are formed as the plating layers. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by barrel plating.

[0242] When a conductive resin layer is provided as the base electrode layer, the conductive resin layer may be disposed so as to cover the baked layer. When providing the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied to the baked layer, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to thermally harden, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, the oxygen concentration is preferably 100 ppm or less.

[0243] Through these manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0244] <Experimental Examples> Seven different lots of multilayer ceramic capacitors were fabricated as samples of Experimental Examples 1 to 7, in which the thickness and coverage of the first central region EA0 and the second central region EB0 were adjusted according to the manufacturing method described in the embodiment. Additionally, samples with uniform thickness and coverage of the internal electrode layers were fabricated as comparative examples. The fabricated samples were then used to evaluate capacitance and mounting. The specific thickness and coverage of the internal electrode layers, evaluation results, etc. for each experimental example and comparative example are listed in Table 1 below.

[0245] First, according to the manufacturing method described in this embodiment, a multilayer ceramic capacitor having the following specifications was fabricated as a sample for an experimental example: Multilayer ceramic capacitor size: 1608 size Capacitance: 22 μF Rated voltage: 25 V Dielectric layer: BaTiO ３ (Thickness of dielectric layer: 1 μm) Internal electrode layer: Ni Base electrode layer: Electrode containing conductive metal (Cu) and glass component (Thickness of base electrode layer disposed on each of the first end face and second end face: 36 μm, thickness of base electrode layer disposed on each of the first main face, second main face, first side face, and second side face: 9 μm) Plating layer: Two layers formed of Ni plating layer (2 μm) and Sn plating layer (4 μm) Internal electrode layer: Ni Number of layers stacked: 550 layers Proportion of central region (high coverage portion) in opposing portion: 75%

[0246] Here, each lot was manufactured under different manufacturing conditions, and the thickness and coverage of the first central region EA0 and the second central region EB0 were adjusted, respectively. For each experimental example and comparative example, the required number of samples to be used for each evaluation was prepared. In addition, five samples for measuring the dimensions, thickness and coverage of the internal electrode layers were prepared for each experimental example and comparative example, and the average values ​​of the measurements of the dimensions, thickness and coverage of the internal electrode layers of the five samples were calculated as the dimensions, thickness and coverage values ​​of the internal electrode layers of each experimental example and comparative example.

[0247] <Method for measuring electrostatic capacitance> Using a C meter, electrostatic capacitance was measured under the conditions of a frequency of 120 Hz and an applied voltage of 0.5 Vrms. For each experimental example and comparative example, 50 samples were evaluated, and the average value was used as the electrostatic capacitance for each experimental example and comparative example.

[0248] <Mounting Evaluation> The incidence of poor suction caused by the mounter of the mounting machine when mounting the multilayer ceramic capacitor on the mounting board was evaluated. For each experimental example and comparative example, 50 samples were evaluated.

[0249] Table 1 shows the measurement results and evaluation results of Experimental Examples 1 to 7 and the Comparative Example.

[0250]

[0251] In Table 1, the measurement results are listed as the central region thickness te0, the opposing end region thickness te1, the thickness ratio te0 / te1, the central region coverage Ce0, the opposing end region coverage Ce1, the coverage difference Ce0-Ce1, the laminate bulge dimension (one side), the laminate bulge rate, and the thickness of the external electrode on the main surface side. The evaluation results are listed as the capacitance, the capacitance evaluation result, the dimension evaluation result, the rate of suction failure in the mounting evaluation, the suction failure evaluation result, and the overall evaluation.

[0252] In Table 1, the central region thickness te0 is the average of the thickness measurements of the first central region EA0 and the second central region EB0. The opposing end region thickness te1 is the average of the thickness measurements of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2. The thickness ratio is the central region thickness te0 divided by the opposing end region thickness te1.

[0253] In Table 1, the central area coverage Ce0 is the average of the coverage measurements of the first central area EA0 and the second central area EB0. The opposing end area coverage Ce1 is the average of the coverage measurements of the first area EA1, the second area EA2, the third area EB1, and the fourth area EB2. The coverage difference is the central area coverage Ce0 minus the opposing end area coverage Ce1, and is expressed in percentage points (%pt).

[0254] In Table 1, the bulge dimension (one side) of the laminate is the average of the protrusion height tf of the first flat surface PA0 formed by the first inclined surface FC1 and the second inclined surface FC2 and the protrusion height tf of the second flat surface PB0 formed by the third inclined surface FC3 and the fourth inclined surface FC4. The laminate bulge ratio is the value obtained by dividing the distance T0 in the stacking direction T at the center of the length direction L of the exposed portion Ep of the laminate 10 by the maximum distance T1 in the stacking direction T connecting the first main surface TS1 side surface (flat surface portion PA1, flat surface portion PA2) and the second main surface TS2 side surface (flat surface portion PB1, flat surface portion PB2) of the first covering portion C1 and the second covering portion C2. In this experimental example, the aforementioned maximum distance T1 was 930 μm on average. The main surface side thickness of the external electrode is the average value of the thickness of the first external electrode arranged on the first main surface TS1, the thickness of the second external electrode arranged on the first main surface TS1, the thickness of the first external electrode arranged on the second main surface TS2, and the thickness of the second external electrode arranged on the second main surface TS2.

[0255] In Table 1, the capacitance column shows the capacitance of the multilayer ceramic capacitor measured by the above-mentioned capacitance measurement method. In the capacitance evaluation results column, in this experimental example, the capacitance of 22.0 μF or more was evaluated as ◯, and the capacitance of less than 22.0 μF was evaluated as ×.

[0256] In Table 1, in the dimensional evaluation results section, if increasing the thickness of the first central region EA0 and the second central region EB0 causes the first flat surface PA0 and the second flat surface PB0 to extend outward from the first external electrode 40A or the second external electrode 40B in the stacking direction T, the evaluation result is △, and if they do not extend outward, the evaluation result is ◯.

[0257] In Table 1, the item for the rate of suction failure in mounting evaluation lists the rate of suction failure by the mounter of the mounting machine when mounting 50 multilayer ceramic capacitors for each of the comparative example and experimental examples 1 to 7. In the item for the results of evaluation of suction failure, if 1 or fewer samples out of 50 had suction failure, the evaluation result was marked as ◯; if 2 to 15 samples had suction failure, the evaluation result was marked as △; and if more than 15 samples had suction failure, the evaluation result was marked as ×. In all of the experimental examples in this case, the number of samples in which suction failure occurred was 15 or less.

[0258] In Table 1, for the overall evaluation item, if any of the evaluation results included △ (acceptable), the evaluation result was recorded as △ (acceptable); if any of the evaluation results included × (not good), the evaluation result was recorded as × (not good); and if all of the evaluation results were ◯ (good), the evaluation result was recorded as ◯ (good).

[0259] It was confirmed that a coverage difference of 2.2 percentage points or more resulted in a capacitance of 22.0 μF or more, and an improved capacitance was achieved. Based on the trends observed in the results, a coverage difference of, for example, 3.0 percentage points or more is expected to have a greater effect on increasing capacitance, and a coverage difference of 4.0 percentage points or more is expected to have an even greater effect. Based on the trends in the evaluation results of the comparative example and each experimental example, it was confirmed that the effects of this embodiment can be achieved by making the central region coverage Ce0 higher than the opposing portion end region coverage Ce1, and that the capacitance tends to increase as the central region coverage Ce0 is made higher than the opposing portion end region coverage Ce1.

[0260] It was confirmed that a thickness ratio of 101.6% or more resulted in a capacitance of 22.0 μF or more, and an improved capacitance was achieved. Based on the trends observed in the results, it is expected that a thickness ratio of, for example, 102% or more, or even 103% or more, is more preferable. This increases the coverage of the central portion and increases the capacitance. The thickness ratio may also be 111.3% or less, or 109.8% or less. Based on the trends in the evaluation results of the comparative example and each experimental example, it was confirmed that the effects of this embodiment can be achieved by increasing the central region thickness te0 relative to the opposing portion end region thickness te1, and that the capacitance tends to increase as the central region thickness te0 is increased relative to the opposing portion end region thickness te1.

[0261] However, if the thickness ratio exceeds 109.8%, the effect of improving capacitance becomes limited. Furthermore, if the thickness ratio becomes too high, the dimensions of the central region of the laminate become large, and the bulge dimension (on one side) of the laminate approaches the thickness of the main surface of the external electrodes. This makes it difficult to keep the overall dimensions of the multilayer ceramic capacitor 1 small, and also increases the likelihood of poor adhesion during mounting evaluation. Therefore, if the thickness ratio becomes too high, the effect of improving capacitance decreases, and adoption may become difficult depending on the product size and the thickness of the external electrodes.

[0262] Here, the first inclined portion FA1, the second inclined portion FA2, the third inclined portion FB1, and the fourth inclined portion FB2 of this embodiment were not observed in the sample of the comparative example, whereas the first inclined portion FA1, the second inclined portion FA2, the third inclined portion FB1, and the fourth inclined portion FB2 of this embodiment were observed in the samples of experimental examples 1 to 7. By adopting such a configuration, good evaluation results were obtained in the above evaluation.

[0263] Furthermore, in the samples of Experimental Examples 1 to 7, it was confirmed that the distance between the first central region EA0 and the second central region EB0 in the longitudinal direction L was shorter than the distance between the first external electrode 40A and the second external electrode 40B. By adopting such a configuration, good evaluation results were obtained in the above-mentioned evaluation.

[0264] Furthermore, it was confirmed that in the samples of Experimental Examples 1 to 7, the distance T0 in the stacking direction T at the center in the length direction L of the exposed portion Ep of the laminate 10 was longer than the maximum distance T1 in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the first covering portion C1 and the second covering portion C2. By adopting such a configuration, good evaluation results were obtained in the above-mentioned evaluation.

[0265] Furthermore, in the samples of Experimental Examples 1 to 6, it was confirmed that the distance T0 in the stacking direction T at the center in the longitudinal direction L of the exposed portion Ep of the laminate 10 was shorter than the maximum distance T2 in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the first external electrode 40A and the second external electrode 40B. By adopting such a configuration, better evaluation results were obtained in the above-mentioned evaluation. It is preferable that the bulge dimension (one side) of the laminate be smaller than the thickness of the main surface side of the external electrode.

[0266] The multilayer ceramic capacitor 1 according to the embodiment described above has the following advantages. In a typical multilayer ceramic capacitor, a space exists between the surface of the laminate and an imaginary plane connecting the surfaces of the first and second external electrodes. This space is always present as long as the external electrodes have a side thickness, but it does not contribute to capacitance density.

[0267] One method for improving capacitance is to increase the coverage of the internal electrode layers to increase the net effective surface area. Here, since there is a positive correlation between the coverage of the internal electrode layers and the thickness of the internal electrode layers, the thickness of the internal electrode layers must be increased in order to improve the coverage. Therefore, in order to design a laminate with the same dimensions in the stacking direction T, it was necessary to reduce the number of internal electrode layers by the amount of the increased thickness of the internal electrode layers. Therefore, the effect of increasing capacitance by increasing the thickness of the internal electrode layers is negated by the reduction in the number of internal electrode layers.

[0268] According to the present disclosure, it is possible to provide a multilayer ceramic capacitor that can increase the capacitance without increasing the size of the multilayer ceramic capacitor 1 by effectively utilizing the space that exists between the virtual plane connecting the surfaces of the first external electrode and the second external electrode and the surface of the laminate.

[0269] The multilayer ceramic capacitor 1 according to this embodiment includes a laminate 10 including a plurality of laminated dielectric layers 20, and including a first main surface TS1 and a second main surface TS2 facing in a stacking direction T, a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the stacking direction T and the width direction W; a first internal electrode layer 31 disposed on the dielectric layer 20 and exposed at the first end surface LS1; a second internal electrode layer 32 disposed on the dielectric layer 20 and exposed at the second end surface LS2; A multilayer ceramic capacitor 1 has a first external electrode 40A arranged on an end face LS1 and connected to a first internal electrode layer 31, and a second external electrode 40B arranged on a second end face LS2 and connected to a second internal electrode layer 32, wherein the first internal electrode layer 31 has a first opposing portion EA facing the second internal electrode layer 32 and a first lead portion D1 drawn from the first opposing portion EA to the first end face LS1 side, and the second internal electrode layer 32 has a second opposing portion EB facing the first internal electrode layer 31 and a second lead portion D1 drawn from the second opposing portion EB to the second end face LS2 side. The first opposing portion EA has a first region EA1 which is a region on the first end face LS1 side, a second region EA2 which is a region on the second end face LS2 side, and a first central region EA0 which is a region located between the first region EA1 and the second region EA2 and is arranged biased toward the outside of the stacked body 10 in the stacking direction T with respect to the first region EA1 and the second region EA2 and has a higher coverage than the coverage of the first region EA1 and the second region EA2. The second opposing portion EB has a third region EB1 which is a region on the second end face LS2 side, and a second central region EA0 which is located between the first region EA1 and the second region EA2 and has a higher coverage than the coverage of the first region EA1 and the second region EA2. and a second central region EB0 which is a region located between the third region EB1 and the fourth region EB2, and which is biased toward the outside of the laminate 10 in the stacking direction T with respect to the third region EB1 and the fourth region EB2, and which has a higher coverage than the coverage of the third region EB1 and the fourth region EB2; the first internal electrode layer 31 further has a first inclined portion FA1 connecting the first region EA1 and the first central region EA0, and a second inclined portion FA2 connecting the second region EA2 and the first central region EA0; and the second internal electrode layer 32 further hasThe third inclined portion FB1 connects the third region EB1 and the second central region EB0, and the fourth inclined portion FB2 connects the fourth region EB2 and the second central region EB0.

[0270] This makes it possible to provide a multilayer ceramic capacitor that can increase the capacitance without increasing the size of the multilayer ceramic capacitor.

[0271] In the multilayer ceramic capacitor 1 of this embodiment, in the longitudinal direction L, the distance of the first central region EA0 is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B, and in the longitudinal direction L, the distance of the second central region EB0 is shorter than the distance L1 between the first external electrode 40A and the second external electrode 40B.

[0272] This makes it possible to provide a multilayer ceramic capacitor that can increase the capacitance without increasing the size of the multilayer ceramic capacitor.

[0273] In the multilayer ceramic capacitor 1 of this embodiment, the laminate 10 has an exposed portion Ep exposed from the first external electrode 40A and the second external electrode 40B, a first covered portion C1 covered by the first external electrode 40A, and a second covered portion C2 covered by the second external electrode 40B, and the maximum distance T0 in the stacking direction T at the center of the longitudinal direction L of the exposed portion Ep is longer than the maximum distance T1 in the stacking direction T connecting the first main surface TS1 side surface and the second main surface TS2 side surface of the first external electrode 40A and the second external electrode 40B.

[0274] This makes it possible to provide a multilayer ceramic capacitor that can increase the capacitance without increasing the size of the multilayer ceramic capacitor.

[0275] In the multilayer ceramic capacitor 1 according to this embodiment, the first main surface TS1 has a first exposed surface EpsA exposed from the first external electrode 40A and the second external electrode 40B, a first covered surface C1sA covered by the first external electrode 40A, and a second covered surface C2sA covered by the second external electrode 40B, and the first exposed surface EpsA has a first flat surface PA0 parallel to the stacking direction T, a first inclined surface FC1 connecting the first flat surface PA0 and the first covered surface C1sA, and a second inclined surface FC2 connecting the first flat surface PA0 and the second covered surface C2sA.

[0276] This makes it easier to ensure the areas of the first central region EA0 and second central region EB0 with high coverage corresponding to the first flat surface PA0, thereby increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0277] In the multilayer ceramic capacitor 1 according to this embodiment, the distance Lt1 in the length direction L of the first inclined surface FC1 and the distance Lt2 in the length direction L of the second inclined surface FC2 are shorter than the distance Lt0 in the length direction L of the first flat surface PA0.

[0278] This makes it easier to ensure the area of ​​the first central region EA0 and second central region EB0 with high coverage corresponding to the first flat surface PA0, thereby enabling the capacitance to be increased without increasing the size of the multilayer ceramic capacitor 1.

[0279] In the multilayer ceramic capacitor 1 of this embodiment, the first internal electrode layer 31 further has a fifth inclined portion FA3 located in the first lead portion D1, and the second internal electrode layer 32 further has a sixth inclined portion FB3 located in the second lead portion D2.

[0280] This ensures a long path for moisture to penetrate from the outside, thereby increasing the capacitance and ensuring moisture resistance without increasing the size of the multilayer ceramic capacitor 1.

[0281] In the multilayer ceramic capacitor 1 of this embodiment, the inclination angle θ of the first inclined portion FA1 and the second inclined portion FA2 is smaller than the inclination angle θ2 of the fifth inclined portion FA3, and the inclination angle θ of the third inclined portion FB1 and the fourth inclined portion FB2 is smaller than the inclination angle θ2 of the sixth inclined portion FB3.

[0282] This ensures a longer path for moisture to penetrate from the outside, thereby increasing the capacitance and ensuring moisture resistance without increasing the size of the multilayer ceramic capacitor 1.

[0283] In the multilayer ceramic capacitor 1 of this embodiment, the step distance ls1 in the stacking direction T between the first region EA1 and the first central region EA0 caused by the first inclined portion FA1 is larger than the thickness Tc in the stacking direction T of the dielectric layer 20 arranged between the first internal electrode layer 31 and the second internal electrode layer 32, and the step distance ls3 in the stacking direction T between the third region EB1 and the second central region EB0 caused by the third inclined portion FB1 is larger than the thickness Tc in the stacking direction T of the dielectric layer 20 arranged between the first internal electrode layer 31 and the second internal electrode layer 32.

[0284] This allows the thickness Te of the internal electrode layer 30 in the first central region EA0 and the second central region EB0 to be increased by taking advantage of the step created by the inclined portion, thereby sufficiently increasing the coverage, thereby further increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0285] In the multilayer ceramic capacitor 1 of this embodiment, the step distance ls1 in the stacking direction T between the first region EA1 and the first central region EA0 caused by the first inclined portion FA1 is larger than the sum Tt of the thickness Te in the stacking direction T of the first internal electrode layer 31 or the second internal electrode layer 32 and the thickness Tc of the dielectric layer 20, and the step distance Ls3 in the stacking direction T between the third region EB1 and the second central region EB0 caused by the third inclined portion FB1 is larger than the sum Tt of the thickness Te in the stacking direction T of the first internal electrode layer 31 or the second internal electrode layer 32 and the thickness Tc of the dielectric layer 20.

[0286] This allows the thickness Te of the internal electrode layer in the first central region EA0 and the second central region EB0 to be increased by taking advantage of the step created by the inclined portion, thereby sufficiently increasing the coverage, thereby further increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1.

[0287] In the multilayer ceramic capacitor 1 of this embodiment, the first central region EA0, the first region EA1, and the second region EA2 have portions that are approximately parallel to a plane perpendicular to the stacking direction T, and the second central region EB0, the third region EB1, and the fourth region EB2 have portions that are approximately parallel to a plane perpendicular to the stacking direction T.

[0288] This makes it possible to prevent the formation of portions with locally increased dimensions, and to increase the capacitance without increasing the size of the multilayer ceramic capacitor 1 .

[0289] In the multilayer ceramic capacitor 1 of this embodiment, the distance Le3 in the longitudinal direction L of the first inclined portion FA1 and the distance Le4 in the longitudinal direction L of the second inclined portion FA2 are shorter than the distance Le0 in the longitudinal direction L of the first central region EA0, and the distance Le4 in the longitudinal direction L of the third inclined portion FB1 and the distance Le3 in the longitudinal direction L of the fourth inclined portion FB2 are shorter than the distance Le0 in the longitudinal direction L of the second central region EB0.

[0290] This makes it possible to ensure the areas of the first central region EA0 and the second central region EB0 with high coverage, thereby enabling the capacitance to be increased without increasing the size of the multilayer ceramic capacitor 1.

[0291] In the multilayer ceramic capacitor 1 of this embodiment, the thickness of the first inclined portion FA1 gradually decreases toward the first end face LS1, the thickness of the second inclined portion FA2 gradually decreases toward the second end face LS2, the thickness of the third inclined portion FB1 gradually decreases toward the second end face LS2, and the thickness of the fourth inclined portion FB2 gradually decreases toward the first end face LS1.

[0292] If there is a portion where the thickness of the internal electrode layer 30 changes suddenly, there is a possibility that a portion where the distance between the internal electrode layers sandwiching the dielectric layer 20 is locally short will be formed. In this case, an electric field will concentrate in that portion, which may reduce the reliability of the multilayer ceramic capacitor 1. With the above configuration, it is possible to prevent the formation of a portion where the distance between the internal electrode layers is locally short near the inclined portion, thereby increasing the capacitance without increasing the size of the multilayer ceramic capacitor 1 and suppressing a decrease in the reliability of the multilayer ceramic capacitor 1 due to electric field concentration. In addition, it is possible to prevent stress concentration in the inclined portion, which increases the capacitance without increasing the size of the multilayer ceramic capacitor 1 and further suppresses the occurrence of cracks in the laminate.

[0293] In the multilayer ceramic capacitor 1 of this embodiment, the thicknesses of the first central region EA0 and the second central region EB0 are 101.6% or more and 111.3% or less of the thicknesses of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2, and the difference in coverage between the first central region EA0 and the second central region EB0 and the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 is 2.2 percentage points or more.

[0294] This makes it possible to provide a multilayer ceramic capacitor 1 that can increase the capacitance without increasing the size of the multilayer ceramic capacitor 1 .

[0295] In the multilayer ceramic capacitor 1 according to this embodiment, the thickness of the first central region EA0 and the second central region EB0 is 101.6% or more and 109.8% or less of the thickness of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2.

[0296] This makes it possible to provide a multilayer ceramic capacitor 1 that can increase the capacitance without increasing the size of the multilayer ceramic capacitor 1 .

[0297] In the multilayer ceramic capacitor 1 according to this embodiment, the difference between the coverage of the first central region EA0 and the second central region EB0 and the coverage of the first region EA1, the second region EA2, the third region EB1, and the fourth region EB2 is 2.2 percentage points or more and 11.4 percentage points or less.

[0298] This makes it possible to provide a multilayer ceramic capacitor 1 that can increase the capacitance without increasing the size of the multilayer ceramic capacitor 1 .

[0299] The present invention is not limited to the configurations of the above-described embodiments, and can be applied by making appropriate modifications within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0300] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor 10 Laminate 20 Dielectric layer 31 First internal electrode layer 32 Second internal electrode layer 40A First external electrode 40B Second external electrode C1 First covered portion C2 Second covered portion D1 First lead portion D2 Second lead portion EA First opposing portion EA0 First central region EA1 First region EA2 Second region EB Second opposing portion EB0 Second central region EB1 Third region EB2 Fourth region Ep Exposed portion FA1 First inclined portion FA2 Second inclined portion FB1 Third inclined portion FB2 Fourth inclined portion L Length direction LS1 First end face LS2 Second end face T Stacking direction TS1 First main surface TS2 Second main surface W Width direction WS1 First side surface WS2 Second Side

Claims

1. a laminate including a plurality of stacked dielectric layers, the laminate including a first main surface and a second main surface opposing each other in a stacking direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the stacking direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the stacking direction and the width direction; a first internal electrode layer disposed on the dielectric layer and exposed at the first end surface; a second internal electrode layer disposed on the dielectric layer and exposed at the second end surface; a first external electrode disposed on the first end face and connected to the first internal electrode layer; a second external electrode disposed on the second end face and connected to the second internal electrode layer; A multilayer ceramic capacitor having the first internal electrode layer has a first opposing portion opposing the second internal electrode layer, and a first lead portion led from the first opposing portion to the first end face side, the second internal electrode layer has a second opposing portion opposing the first internal electrode layer, and a second lead portion led from the second opposing portion to the second end face side, The first opposing portion is a first region that is a region on the first end face side; a second region that is a region on the second end face side; a first central region that is located between the first region and the second region, that is biased toward the outside of the stack in the stacking direction relative to the first region and the second region, and that has a higher coverage than the coverage of the first region and the second region; The second opposing portion is a third region which is a region on the second end face side; a fourth region that is a region on the first end face side; a second central region that is located between the third region and the fourth region, that is biased toward the outside of the stack in the stacking direction relative to the third region and the fourth region, and that has a higher coverage than the coverage of the third region and the fourth region; the first internal electrode layer further has a first inclined portion connecting the first region and the first central region, and a second inclined portion connecting the second region and the first central region, the second internal electrode layer further has a third inclined portion connecting the third region and the second central region, and a fourth inclined portion connecting the fourth region and the second central region.

2. In the longitudinal direction, a distance of the first central region is shorter than a distance between the first external electrode and the second external electrode; 2. The multilayer ceramic capacitor according to claim 1, wherein a distance of the second central region in the length direction is shorter than a distance between the first external electrode and the second external electrode.

3. the laminate has an exposed portion exposed from the first external electrode and the second external electrode, a first covered portion covered by the first external electrode, and a second covered portion covered by the second external electrode, 3. The multilayer ceramic capacitor according to claim 1, wherein a distance in the stacking direction at the longitudinal center of the exposed portion is longer than a maximum distance in the stacking direction connecting the first main surface side surface and the second main surface side surface of the first covering portion and the second covering portion, and shorter than a maximum distance in the stacking direction connecting the first main surface side surface and the second main surface side surface of the first external electrode and the second external electrode.

4. 3. The multilayer ceramic capacitor according to claim 1, wherein the first main surface has a first exposed surface exposed from the first external electrode and the second external electrode, a first covered surface covered by the first external electrode, and a second covered surface covered by the second external electrode, and the first exposed surface has a first flat surface parallel to the stacking direction, a first inclined surface connecting the first flat surface and the first covered surface, and a second inclined surface connecting the first flat surface and the second covered surface.

5. 5. The multilayer ceramic capacitor according to claim 4, wherein a distance in the length direction of the first inclined surface and a distance in the length direction of the second inclined surface are shorter than a distance in the length direction of the first flat surface.

6. the first internal electrode layer further has a fifth inclined portion located in the first lead portion, 3. The multilayer ceramic capacitor according to claim 1, wherein the second internal electrode layer further has a sixth inclined portion located in the second lead portion.

7. an inclination angle of the first inclined portion and an inclination angle of the second inclined portion are smaller than an inclination angle of the fifth inclined portion; 7. The multilayer ceramic capacitor according to claim 6, wherein the inclination angles of the third inclined portion and the fourth inclined portion are smaller than the inclination angle of the sixth inclined portion.

8. a step distance in the stacking direction between the first region and the first central region caused by the first inclined portion is larger than a thickness in the stacking direction of the dielectric layer disposed between the first internal electrode layer and the second internal electrode layer, 3. The multilayer ceramic capacitor according to claim 1, wherein a step distance in the stacking direction between the third region and the second central region caused by the third inclined portion is greater than a thickness in the stacking direction of the dielectric layer disposed between the first internal electrode layer and the second internal electrode layer.

9. a step distance in the stacking direction between the first region and the first central region caused by the first inclined portion is larger than a sum of a thickness in the stacking direction of the first internal electrode layer or the second internal electrode layer and a thickness of the dielectric layer, 9. The multilayer ceramic capacitor according to claim 8, wherein a step distance in the stacking direction between the third region and the second central region caused by the third inclined portion is larger than a sum of a thickness in the stacking direction of the first internal electrode layer or the second internal electrode layer and a thickness of the dielectric layer.

10. the first central region, the first region, and the second region each have a portion that is substantially parallel to a plane perpendicular to the stacking direction; 3. The multilayer ceramic capacitor according to claim 1, wherein the second central region, the third region, and the fourth region have portions that are substantially parallel to a plane perpendicular to the stacking direction.

11. a lengthwise distance of the first inclined portion and a lengthwise distance of the second inclined portion are shorter than a lengthwise distance of the first central region; 3. The multilayer ceramic capacitor according to claim 2, wherein a length of the third inclined portion and a length of the fourth inclined portion are shorter than a length of the second central region.

12. the thickness of the first inclined portion gradually decreases toward the first end surface, the thickness of the second inclined portion gradually decreases toward the second end surface, the thickness of the third inclined portion gradually decreases toward the second end surface, 3. The multilayer ceramic capacitor according to claim 1, wherein the thickness of the fourth inclined portion gradually decreases toward the first end face.