Semiconductor device, power conversion device, and semiconductor device manufacturing method

Abstract

The present invention suppresses peeling of a member due to a temperature rise of a semiconductor device. This semiconductor device includes an active region and a termination region surrounding the active region in a plan view. In the termination region, the semiconductor device includes a first semiconductor layer of a first conductivity type, at least one second semiconductor layer of a second conductivity type provided on a surface layer of the first semiconductor layer, and an upper surface electrode covering the first semiconductor layer and the second semiconductor layer. The upper surface electrode is Schottky-connected to the first semiconductor layer. The interface between the at least one second semiconductor layer and the upper surface electrode is located deeper than the interface between the first semiconductor layer and the upper surface electrode.

Description

Semiconductor device, power conversion device, and method of manufacturing the semiconductor device

[0001] The technology disclosed in this specification relates to semiconductor technology.

[0002] In order to enable semiconductor devices to have high breakdown voltage, low loss, and be used in high-temperature environments, silicon carbide (SiC), which has a high breakdown voltage, low resistance, and excellent heat resistance compared to silicon (Si), is used and is applied to power semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), and Schottky barrier diodes (SBDs) (see, for example, Patent Document 1).

[0003] In the case of a SiC semiconductor MOSFET having a breakdown voltage of, for example, 1 kV or more and 1.2 kV or less, 2 mΩcm ２ The following on-resistance was obtained, which is less than half the resistance value of a Si semiconductor MOSFET or IGBT with the same breakdown voltage.

[0004] The reason why the use of SiC semiconductors can significantly reduce the on-resistance compared to Si semiconductors is that SiC semiconductors have a high dielectric breakdown field, and the voltage-resistant layer (drift layer) required to achieve the same withstand voltage can be made thinner compared to Si semiconductors, and further, the impurity doping amount of the voltage-resistant layer can be increased.

[0005] In the future, it will be possible to reduce the manufacturing costs of semiconductor devices by increasing the current density flowing through them to make them smaller, or by using parasitic diodes in MOSFETs to reduce the number of semiconductor devices to be installed.As a result, it is expected that the majority of IGBTs made from Si semiconductors as inverter components will be replaced by those made from SiC semiconductors.

[0006] Japanese Patent Application Laid-Open No. 2009-16603

[0007] In the termination region of a semiconductor device, when current is applied, the highest electric field occurs at the interface between the SiC semiconductor substrate and the layer deposited on its top surface. This interface has discontinuous molecular structures, reflects the surface irregularities, and contains many crystal defects, so when a high electric field is applied, leakage current occurs.

[0008] In particular, in semiconductor devices that have a region (junction barrier Schottky structure, or JBS) for flowing current during reflux operation, leakage current generates additional heat in the termination region, increasing thermal stress, which can lead to the problem of the Schottky electrodes (barrier metal and source electrode) of the JBS formed in the termination region becoming more susceptible to peeling.

[0009] The technology disclosed in the present specification has been made in consideration of the problems described above, and is a technology for suppressing peeling of components that occurs with a rise in temperature of a semiconductor device.

[0010] A semiconductor device that is a first aspect of the technology disclosed in the present specification includes an active region and a termination region that surrounds the active region in a planar view, and in the termination region, includes a first semiconductor layer of a first conductivity type, at least one second semiconductor layer of a second conductivity type that is provided on a surface layer of the first semiconductor layer, and a top surface electrode that covers the first semiconductor layer and the second semiconductor layer, the top surface electrode being in Schottky contact with the first semiconductor layer, and at least one interface between the second semiconductor layer and the top surface electrode being located deeper than the interface between the first semiconductor layer and the top surface electrode.

[0011] According to at least the first aspect of the technology disclosed in the present specification, the interface between the second semiconductor layer and the top electrode is located deeper than the interface between the first semiconductor layer and the top electrode, and adhesion is improved at that location through mechanical bonding, thereby making it possible to suppress peeling of components due to thermal stress caused by a rise in temperature of the semiconductor device.

[0012] Furthermore, objects, features, aspects, and advantages associated with the technology disclosed herein will become more apparent from the detailed description set forth below and the accompanying drawings.

[0013] 17 is an enlarged view of a region including an active region and a termination region indicated by a dashed-dotted line in FIG. 1; FIG. 18 is a cross-sectional view corresponding to the a-a' cross section in FIG. 2; FIG. 19 is a flowchart showing an example of a method for manufacturing a semiconductor device according to an embodiment; FIG. 20 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment; FIG. 21 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment; FIG. 22 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment; FIG. 23 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment; FIG. 24 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment; FIG. 25 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment; FIG. 26 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to an embodiment;

[0014] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for the purpose of explaining the technology, but these are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0015] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. The relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0016] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0017] Furthermore, in the description given in this specification, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0018] Furthermore, in the description of this specification, even if ordinal numbers such as "first" or "second" are used, these terms are used for convenience to make it easier to understand the contents of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0019] Furthermore, in the description provided in this specification, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used, but these terms are used for convenience to facilitate understanding of the contents of the embodiments and have no relation to the positions or directions when the embodiments are actually implemented.

[0020] Furthermore, in the description of the present specification, when "the upper surface of ..." or "the lower surface of ..." is used, it is intended to include not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. For example, when it is described as "B provided on the upper surface of A," it does not preclude the interposition of another component "C" between A and B.

[0021] First Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described below.

[0022] <Configuration of the Semiconductor Device> As an example of a semiconductor device according to the present embodiment, a power semiconductor device, specifically, an n-channel MOSFET made of a SiC substrate, will be described. The semiconductor device is a planar gate semiconductor device and includes a built-in Schottky barrier diode (SBD).

[0023] 1 is a plan view of a semiconductor device according to this embodiment. A source electrode 3 is formed in the center of the top surface of the semiconductor device 1, and a gate wiring 2 is formed to surround the source electrode 3. A gate pad 4 is formed in the lower center and is electrically connected to the gate wiring 2. In this embodiment, the region where unit cells are periodically arranged is defined as an active region, and the region other than the active region (the region surrounding the active region) is defined as a termination region.

[0024] Fig. 2 is an enlarged view of a region including an active region and a termination region indicated by a dashed line in Fig. 1. In an active region 13 of the semiconductor device according to this embodiment, which is made up of a MOSFET region in which a MOSFET structure is formed and an SBD region in which an SBD structure is formed, unit cells 14 (corresponding to the MOSFET region) are formed in a stripe pattern.

[0025] Fig. 3 is a cross-sectional view corresponding to the a-a' cross section in Fig. 2. As shown in Fig. 3, the termination region of the semiconductor device according to this embodiment includes an n-type SiC substrate 11, an n-type epitaxial growth layer 10 uniformly formed on the upper surface of the SiC substrate 11, an n-type n-well region 9 formed in a surface layer of the epitaxial growth layer 10, a plurality of p-type p-type semiconductor regions 7 partially formed in a surface layer of the n-well region 9, a p-type p-well region 8 partially formed in a surface layer of the n-well region 9, an interlayer insulating film 5 formed so as to cover a part of the upper surface of the p-well region 8, a barrier metal layer 6 formed so as to cover the interlayer insulating film 5, the n-well region 9, the p-type semiconductor regions 7, and the p-well region 8, a source electrode 3 formed so as to cover the barrier metal layer 6, and a drain electrode 12 formed on the lower surface of the n-type SiC substrate 11.

[0026] Here, the interface between the p-type semiconductor region 7 and the barrier metal layer 6 is formed at a deeper position than the interface between the n-well region 9 and the barrier metal layer 6 .

[0027] The interface between the barrier metal layer 6 and the p-type semiconductor region 7 and a portion of the interface between the barrier metal layer 6 and the p-well region 8 are ohmic-contacted. On the other hand, the interface between the barrier metal layer 6 and the n-well region 9 is Schottky-contacted (i.e., the source electrode 3 and the n-well region 9 are Schottky-contacted).

[0028] Here, D1 denotes the distance from the interface between the n-well region 9 and the source electrode 3 to the interface between the p-type semiconductor region 7 and the source electrode 3, and D2 denotes the distance from the interface between the n-well region 9 and the source electrode 3 to the bottom surface of the p-type semiconductor region 7. However, since a barrier metal layer 6 is formed between the n-well region 9 and the source electrode 3 in Figure 3, D1 denotes the distance from the interface between the n-well region 9 and the barrier metal layer 6 to the interface between the p-type semiconductor region 7 and the barrier metal layer 6, and D2 denotes the distance from the interface between the n-well region 9 and the barrier metal layer 6 to the bottom surface of the p-type semiconductor region 7.

[0029] In this case, the interface between the p-type semiconductor region 7 and the source electrode 3 (in FIG. 3, the interface between the p-type semiconductor region 7 and the barrier metal layer 6) is formed so as to satisfy D1>0, D2>0, and (D2÷2)>D1.

[0030] <Method of Manufacturing a Semiconductor Device> Fig. 4 is a flowchart showing an example of a method of manufacturing a semiconductor device according to this embodiment. Figs. 5 to 14 are cross-sectional views showing an example of a method of manufacturing a semiconductor device according to this embodiment.

[0031] First, as shown in an example in FIG. 5 , an epitaxial growth layer 10 made of n-type SiC is formed on the upper surface (first main surface) of an n-type SiC substrate 11 having a polytype of 4H, for example, by chemical vapor deposition (i.e., CVD) (step ST1 in FIG. 4 ).

[0032] 6, impurities are ion-implanted into the surface layer of the epitaxial growth layer 10 to form an n-well region 9 (step ST2 in FIG. 4). The impurity concentration of the n-well region 9 is controlled to be higher than the impurity concentration of the epitaxial growth layer 10.

[0033] 7, an implantation mask (not shown) is formed in a portion of the n-well region 9 using a photoresist or the like, and then p-type impurities are ion-implanted from the upper surface of the n-well region 9 to form the p-well region 8 (step ST3 in FIG. 4). Examples of p-type impurities include B (boron) and Al (aluminum). The implantation depth of the p-well region 8 is controlled so as not to deviate from the n-well region 9 (i.e., so that the implantation depth of the p-well region 8 is not deeper than the bottom surface of the n-well region 9).

[0034] Next, as shown in an example in FIG. 8, an implantation mask is formed (not shown) using photoresist or the like in a portion of the n-well region 9 (in FIG. 8, the region where the p-well region 8 is not formed), and then a portion of the upper surface of the n-well region 9 is processed using dry etching or wet etching technology to form a recess 90 (step ST4 in FIG. 4).

[0035] 9, p-type impurities are ion-implanted into the formed recess 90 to form the p-type semiconductor region 7 (step ST5 in FIG. 4). The impurity concentration of the p-type semiconductor region 7 is controlled to be higher than the impurity concentration of the p-well region 8.

[0036] Thereafter, in order to activate the region into which the ions have been implanted, the SiC substrate 11 is heat-treated at a high temperature using a heat treatment device (not shown), whereby the implanted ions are electrically activated.

[0037] 10, an interlayer insulating film 5 is formed by a deposition method such as thermal oxidation or chemical vapor deposition, and then patterned using photolithography, dry etching, or wet etching so that the interlayer insulating film 5 remains in a predetermined region (step ST6 in FIG. 4). The interlayer insulating film may have a laminated structure of two or more layers made of different materials.

[0038] Next, as shown in FIG. 11, a barrier metal layer 6 is formed using a barrier metal made of titanium or a titanium compound such as titanium nitride (TiN).

[0039] Next, as shown in FIG. 12, a film of aluminum, an aluminum alloy made of aluminum and silicon, or nickel is formed to form the source electrode 3 (step ST7 in FIG. 4).

[0040] Next, as shown in an example in FIG. 13, the lower surface (second main surface) of SiC substrate 11 of semiconductor device 1 is machined using a grinding wheel to thin SiC substrate 11 (step ST8 in FIG. 4).

[0041] Next, as shown in an example in FIG. 14, a nickel film having a thickness of about 600 nm is formed on the lower surface (second main surface) of SiC substrate 11 by appropriately using a sputtering method or the like, thereby forming drain electrode 12 (step ST9 in FIG. 4).

[0042] Regarding the nickel surface, oxidation of the outermost surface reduces the wettability of the solder alloy with nickel, resulting in a poor bonding condition during chip bonding. Therefore, the drain electrode 12 may be a laminated film made of a nickel film and gold or silver, etc., using a metal that is poorly reactive with the outside, such as gold (Au) or silver (Ag), as a protective film on the nickel surface.

[0043] Next, the effects of this embodiment will be described.

[0044] In power semiconductor devices, current typically flows through the body diode (BD) region or the SBD region during reflux operation, causing the semiconductor device itself to generate heat due to these resistance components. In particular, in semiconductor devices in which a JBS region for flowing current during reflux operation is formed in the termination region, heat also occurs in the termination region. Here, the linear expansion coefficients of the SiC substrate 11 and the barrier metal layer 6, or the linear expansion coefficients of the barrier metal layer 6 and the source electrode 3, differ from each other, and thermal stress resulting from this difference occurs at the interface between the SiC substrate 11 and the barrier metal layer 6.

[0045] This stress can cause the barrier metal layer 6 to peel off from the SiC substrate 11, or the source electrode 3 to peel off from the barrier metal layer 6. In particular, when a JBS region is provided in the termination region and a return current is actively passed through this region, as in the semiconductor device according to this embodiment, the amount of heat generated in the termination region increases compared to a semiconductor device without an SBD region. Therefore, if the barrier metal layer 6 and the source electrode 3 are formed on the flat upper surface of the SiC substrate 11, the barrier metal layer 6 and the source electrode 3 will have poor adhesion to the lateral stress, and the barrier metal layer 6 or the source electrode 3 may peel off due to thermal stress caused by a temperature rise when the semiconductor device is energized.

[0046] Therefore, as shown in this embodiment, by forming a recess 90 shallower than the depth of the p-well region 8 at the interface between the SiC substrate 11 and the barrier metal layer 6, the interface can be mechanically bonded (also called an anchoring effect, fastener effect, or anchor effect) to increase adhesion and suppress peeling, thereby improving the reliability of the semiconductor device during operation.

[0047] Furthermore, by forming the p-type semiconductor region 7 by ion implanting p-type impurities into the recess 90 of the n-well region 9, the p-type semiconductor region 7 can be formed to the same depth with lower acceleration energy compared to a structure in which ions are implanted without forming an uneven surface at the interface, thereby reducing energy costs during manufacturing. Furthermore, lowering the implantation energy reduces damage to the top surface of the SiC substrate 11 caused by ion implantation, thereby suppressing leakage current due to defects that may be formed as a result of the damage. This reduces heat generation during operation of the semiconductor device 1, improving the reliability of the semiconductor device 1.

[0048] Second Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0049] <Configuration of Semiconductor Device> In this embodiment, the power semiconductor device according to the first embodiment is applied to a power conversion device.

[0050] As a semiconductor device according to this embodiment, a power semiconductor device, an n-channel MOSFET made of a SiC substrate, will be described as an example. The semiconductor device is a planar gate semiconductor device and includes a built-in Schottky barrier diode (SBD).

[0051] 15 is a cross-sectional view of the termination region of the semiconductor device according to this embodiment, which includes an n-type SiC substrate 11, an n-type epitaxial growth layer 10, an n-type n-well region 9, a plurality of p-type semiconductor regions 7a partially formed on the surface of the n-well region 9, a p-type p-well region 8, an interlayer insulating film 5, a barrier metal layer 6, a source electrode 3, and a drain electrode 12.

[0052] 15 , as in the first embodiment, a recess 90 is formed in the upper surface of the n-well region 9. In the semiconductor device according to this embodiment, the p-type semiconductor region 7 a is formed with a width that covers the recess 90 in plan view (a range wider than the range in which the recess 90 is formed).

[0053] This formation can suppress peeling of the barrier metal layer 6 from the SiC substrate 11 in the termination region, or peeling of the source electrode 3 from the barrier metal layer 6, and can also suppress concentration of an electric field at the corners of the recess 90 formed in the n-well region 9. This can improve the reliability of the semiconductor device 1.

[0054] 9 in the first embodiment, the method for manufacturing a semiconductor device according to this embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that, when ion implanting p-type impurities to form p-type semiconductor region 7a, ion implantation is performed from a direction at an angle of 1° or more and 45° or less from the perpendicular direction to SiC substrate 11. The other manufacturing steps are the same as those shown in FIGS.

[0055] Third Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0056] <Configuration of Semiconductor Device> In this embodiment, the power semiconductor device according to the first or second embodiment is applied to a power conversion device.

[0057] As a semiconductor device according to this embodiment, a power semiconductor device, an n-channel MOSFET made of a SiC substrate, will be described as an example. The semiconductor device is a planar gate semiconductor device and includes a built-in Schottky barrier diode (SBD).

[0058] 16 is a cross-sectional view of the termination region of the semiconductor device according to this embodiment, which includes an n-type SiC substrate 11, an n-type epitaxial growth layer 10, an n-type n-well region 9, a p-type semiconductor region 7, a p-type p-well region 8, an interlayer insulating film 5, a barrier metal layer 6b formed to cover the interlayer insulating film 5, the n-well region 9, the p-type semiconductor region 7, and the p-well region 8, a source electrode 3, and a drain electrode 12.

[0059] 16, a recess 90b is formed in the upper surface of the n-well region 9. In the semiconductor device according to this embodiment, the interior angle of the bottom of the recess 90b is an obtuse angle of 90° or more. Furthermore, the barrier metal layer 6b is formed to have an inclined surface so as to follow the shape of the recess 90b.

[0060] This formation can suppress peeling of the barrier metal layer 6 b from the SiC substrate 11 in the termination region, or peeling of the source electrode 3 from the barrier metal layer 6 b, and can also suppress concentration of an electric field at the corners of the bottom of the recess 90 b formed in the n-well region 9. This can improve the reliability of the semiconductor device 1.

[0061] As in the p-type semiconductor region 7a shown in FIG. 15, the p-type semiconductor region provided below the recess 90b may be formed in an area larger than the area in which the recess 90b is formed.

[0062] <Regarding the Manufacturing Method of the Semiconductor Device> The manufacturing method of the semiconductor device according to this embodiment differs from the process of the first embodiment shown in Fig. 8 in that when forming the recess 90b, the side surface of the recess 90b is formed to be an inclined surface by wet etching or the like. The rest of the manufacturing method is the same as the processes shown in Fig. 5 to Fig. 14.

[0063] Fourth Embodiment A semiconductor device and a method for manufacturing the semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0064] <Regarding the configuration of the semiconductor device> A SiC semiconductor device will be described that, compared to the structure shown in the first embodiment, can suppress damage or peeling at the corners of the end of the recess 90 in a planar view by alleviating the concentration of electric field and stress at the corners of the end of the recess 90 in a planar view.

[0065] Fig. 17 is an enlarged view of a region including the active region and termination region of the SiC semiconductor device described above, and Fig. 18 is an enlarged view of a region including recess 90 indicated by the dashed dotted line in Fig. 17.

[0066] As shown in Figures 17 and 18, by making the shape of the end of the recess 90 in a planar view obtuse or curved (curved) compared to the first embodiment, the concentration of electric field and stress at the corner of the end of the recess 90 in a planar view can be alleviated, and damage or peeling at the corner of the end of the recess 90 in a planar view can be suppressed.

[0067] <Method of Manufacturing Semiconductor Device> In the same manufacturing process as that shown in the first embodiment, the mask for forming recess 90 in step ST4 is changed. Then, by going through the same steps as steps ST5 to ST9 shown in the first embodiment, a SiC semiconductor device having the structure shown in FIGS. 17 and 18 is formed.

[0068] Fifth Embodiment A power conversion device and a method for manufacturing the power conversion device according to this embodiment will be described. In the following description, components similar to those described in the above embodiments will be denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0069] <Configuration of the Power Conversion Device> In this embodiment, the semiconductor device according to the above-described embodiment is applied to a power conversion device. The power conversion device to which the present invention is applied is not limited to a specific application, but the following describes a case where the present invention is applied to a three-phase inverter.

[0070] FIG. 19 is a diagram conceptually illustrating an example of the configuration of a power conversion system including the power conversion device of this embodiment.

[0071] As shown in the example of FIG. 19 , the power conversion system includes a power supply 2100, a power conversion device 2200, and a load 2300. The power supply 2100 is a DC power supply and supplies DC power to the power conversion device 2200. The power supply 2100 can be configured from a variety of sources, such as a DC system, a solar cell, or a storage battery. The power supply 2100 can also be configured from a rectifier circuit connected to an AC system or an AC-DC converter. The power supply 2100 can also be configured from a DC-DC converter that converts DC power output from a DC system into a predetermined power.

[0072] The power conversion device 2200 is a three-phase inverter connected between the power supply 2100 and the load 2300. The power conversion device 2200 converts DC power supplied from the power supply 2100 into AC power, and further supplies the AC power to the load 2300.

[0073] As shown in an example in Figure 19, the power conversion device 2200 also includes a conversion circuit 2201 that converts DC power into AC power and outputs it, a drive circuit 2202 that outputs drive signals for driving each switching element of the conversion circuit 2201, and a control circuit 2203 that outputs a control signal to the drive circuit 2202 for controlling the drive circuit 2202.

[0074] The load 2300 is a three-phase electric motor driven by AC power supplied from the power conversion device 2200. The load 2300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, such as a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0075] The power conversion device 2200 will be described in detail below. The conversion circuit 2201 includes a switching element and a freewheeling diode (not shown). The switching element performs a switching operation to convert DC power supplied from the power supply 2100 into AC power, which is then supplied to the load 2300.

[0076] There are various specific circuit configurations for the conversion circuit 2201, but the conversion circuit 2201 according to this embodiment is a two-level three-phase full-bridge circuit, and includes six switching elements and six freewheeling diodes connected in anti-parallel to each of the switching elements.

[0077] The semiconductor device according to any of the above-described embodiments is applied to at least one of the switching elements and freewheeling diodes in the conversion circuit 2201. Six switching elements are connected in series in groups of two to form upper and lower arms, each of which constitutes a phase (i.e., U phase, V phase, and W phase) of a full-bridge circuit. The output terminals of each of the upper and lower arms (i.e., the three output terminals of the conversion circuit 2201) are connected to the load 2300.

[0078] The drive circuit 2202 generates drive signals for driving the switching elements of the conversion circuit 2201, and further supplies the drive signals to the control electrodes of the switching elements of the conversion circuit 2201. Specifically, based on control signals output from a control circuit 2203 (described later), the drive circuit 2202 outputs drive signals for turning the switching elements on and off to the control electrodes of the respective switching elements.

[0079] When the switching element is maintained in the on state, the drive signal is a voltage signal (i.e., an on signal) that is equal to or greater than the threshold voltage of the switching element, and when the switching element is maintained in the off state, the drive signal is a voltage signal (i.e., an off signal) that is equal to or less than the threshold voltage of the switching element.

[0080] The control circuit 2203 controls the switching elements of the conversion circuit 2201 so that a desired power is supplied to the load 2300. Specifically, the control circuit 2203 calculates the time (i.e., on-time) that each switching element of the conversion circuit 2201 should be in the on-state based on the power to be supplied to the load 2300. For example, the conversion circuit 2201 can be controlled by PWM control that modulates the on-time of the switching element according to the voltage to be output.

[0081] Then, the control circuit 2203 outputs a control command (i.e., a control signal) to the drive circuit 2202 so that an ON signal is output to a switching element that should be in an ON state at each point in time, and an OFF signal is output to a switching element that should be in an OFF state at each point in time. Based on the control signal, the drive circuit 2202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.

[0082] In the power conversion device 2200 according to this embodiment, a semiconductor device according to any of the embodiments described above is applied as the switching element of the conversion circuit 2201, and therefore the on-resistance can be stabilized after a current cycle.

[0083] In this embodiment, an example has been described in which the semiconductor device in any of the above-described embodiments is applied to a two-level three-phase inverter, but the application example is not limited to this, and the semiconductor device in any of the above-described embodiments can be applied to various power conversion devices.

[0084] Although the present embodiment has been described with respect to a two-level power conversion device, the semiconductor device according to any of the above-described embodiments may be applied to a three-level or multilevel power conversion device. When power is supplied to a single-phase load, the semiconductor device according to any of the above-described embodiments may be applied to a single-phase inverter.

[0085] Furthermore, when power is supplied to a DC load or the like, the semiconductor device according to any of the above-described embodiments can be applied to a DC-DC converter or an AC-DC converter.

[0086] Furthermore, a power conversion device to which the semiconductor device according to any of the above-described embodiments is applied is not limited to a case in which the load is an electric motor, and can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, for example. Furthermore, a power conversion device to which the semiconductor device according to any of the above-described embodiments is applied can also be used as a power conditioner in a solar power generation system, a power storage system, or the like.

[0087] <Method for Manufacturing Power Converter> Next, a method for manufacturing the power converter according to this embodiment will be described.

[0088] First, a semiconductor device is manufactured by the manufacturing method described in the above-described embodiment. Then, a conversion circuit 2201 including the semiconductor device is provided as a component of a power conversion device. The conversion circuit 2201 is a circuit for converting input power and outputting it.

[0089] The power conversion device further includes a driver circuit 2202. The driver circuit 2202 is a circuit for outputting a driver signal to the semiconductor device for driving the semiconductor device. The power conversion device further includes a control circuit 2203. The control circuit 2203 is a circuit for outputting a control signal to the driver circuit 2202 for controlling the driver circuit 2202.

[0090] The semiconductor switching elements used in the embodiments described above are not limited to switching elements made of silicon (Si) semiconductors. For example, the semiconductor switching elements may be made of a non-Si semiconductor material having a wider band gap than a Si semiconductor.

[0091] Examples of wide band gap semiconductors that are non-Si semiconductor materials include silicon carbide, gallium nitride-based materials, and diamond.

[0092] Switching elements made of wide bandgap semiconductors can be used in high voltage regions where unipolar operation is difficult with Si semiconductors, and can significantly reduce the switching loss that occurs during switching operation, thereby enabling a significant reduction in power loss.

[0093] Furthermore, switching elements made of wide bandgap semiconductors have low power loss and high heat resistance, which means that when configuring a power module with a cooling unit, it is possible to reduce the size of the heat dissipation fins of the heat sink, thereby enabling further miniaturization of the semiconductor module.

[0094] Furthermore, switching elements made of wide bandgap semiconductors are suitable for high-frequency switching operations. Therefore, when applied to converter circuits that require higher frequencies, increasing the switching frequency also enables the size of reactors or capacitors connected to the converter circuit to be reduced.

[0095] Therefore, the same effect can be obtained even when the semiconductor switching elements in the above-described embodiments are made of a wide-gap semiconductor such as silicon carbide.

[0096] <Regarding the Effects Produced by the Multiple Embodiments Described Above> Next, examples of the effects produced by the multiple embodiments described above will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the multiple embodiments described above, but these may be replaced with other specific configurations exemplified in the present specification to the extent that similar effects are produced. In other words, for convenience, only one of the associated specific configurations may be described as a representative below, but the representatively described specific configuration may be replaced with another associated specific configuration.

[0097] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations illustrated in different embodiments may be combined to produce the same effect.

[0098] According to the embodiment described above, the semiconductor device includes an active region 13 and a termination region surrounding the active region 13 in a planar view. The termination region includes a first semiconductor layer of a first conductivity type (n-type), a second semiconductor layer of a second conductivity type (p-type), and a top electrode. Here, the first semiconductor layer corresponds to, for example, an n-well region 9. The second semiconductor layer corresponds to, for example, at least one of a p-type semiconductor region 7, a p-type semiconductor region 7a, and a p-well region 8. The top electrode corresponds to, for example, a source electrode 3. At least one p-type semiconductor region 7 is provided on the surface layer of the n-well region 9. The source electrode 3 covers the n-well region 9 and the p-type semiconductor region 7. The source electrode 3 is connected to the n-well region 9 via a Schottky junction. Furthermore, at least one interface between the p-type semiconductor region 7 and the source electrode 3 (if a barrier metal layer 6 is present, the interface between the barrier metal layer 6 and the p-type semiconductor region 7) is located deeper than the interface between the n-well region 9 and the source electrode 3 (if a barrier metal layer 6 is present, the interface between the barrier metal layer 6 and the n-well region 9).

[0099] With this configuration, the interface between the p-type semiconductor region 7 and the source electrode 3 is located deeper than the interface between the n-well region 9 and the source electrode 3, and the mechanical bonding at this location improves adhesion, thereby making it possible to suppress peeling of the source electrode 3 from the barrier metal layer 6 or the n-well region 9 due to thermal stress caused by a rise in the temperature of the semiconductor device, thereby improving the reliability of the semiconductor device during operation.

[0100] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0101] Furthermore, according to the embodiment described above, when the distance from the interface between the n-well region 9 and the source electrode 3 (or, if a barrier metal layer 6 is present, the interface between the barrier metal layer 6 and the n-well region 9) to the interface between the p-type semiconductor region 7 and the source electrode 3 (or, if a barrier metal layer 6 is present, the interface between the barrier metal layer 6 and the p-type semiconductor region 7), is defined as D1, and the distance from the interface between the n-well region 9 and the source electrode 3 (or, if a barrier metal layer 6 is present, the interface between the barrier metal layer 6 and the n-well region 9) to the underside of the p-type semiconductor region 7 is defined as D2, the interface between the p-type semiconductor region 7 and the source electrode 3 (or, if a barrier metal layer 6 is present, the interface between the barrier metal layer 6 and the p-type semiconductor region 7) is formed so as to satisfy D1 > 0, D2 > 0, and (D2 ÷ 2) > D1. With this configuration, peeling between the source electrode 3 and the n-well region 9 (or, if a barrier metal layer 6 is used, the interface between the source electrode 3 and the barrier metal layer 6 or the barrier metal layer 6 and the n-well region 9) due to thermal stress occurring during operation of the semiconductor device can be suppressed without impairing the characteristics of the JBS.

[0102] Furthermore, according to the embodiment described above, a Schottky barrier diode structure is provided in the active region 13. This configuration not only has the effect of suppressing peeling of the source electrode 3 in the termination region, but also makes it possible to suppress the growth of stacking faults in the SiC substrate 11 in the active region.

[0103] Furthermore, according to the embodiment described above, the active region 13 has a MOSFET structure. The regions having the MOSFET structure and the regions having the Schottky barrier diode structure are periodically arranged in a striped pattern in a plan view. With this configuration, the on-resistance of the semiconductor device during energization can be reduced.

[0104] Furthermore, according to the embodiment described above, a recess 90 (or recess 90b) is formed in the upper surface of the n-well region 9. The p-type semiconductor region 7a is provided so as to cover an area larger than the area in which the recess 90 (or recess 90b) is formed. With this configuration, it is possible to suppress the concentration of an electric field at the corners of the recess 90 formed in the n-well region 9. This makes it possible to improve the reliability of the semiconductor device 1.

[0105] Furthermore, according to the embodiment described above, the side surfaces of the recess 90b are inclined. This configuration can suppress the concentration of the electric field at the corners of the bottom of the recess 90b formed in the n-well region 9. This can improve the reliability of the semiconductor device 1.

[0106] Furthermore, according to the embodiment described above, the power conversion device includes the semiconductor device described above, and includes conversion circuit 2201 that converts and outputs input power, drive circuit 2202 that outputs a drive signal to drive the semiconductor device, and control circuit 2203 that outputs a control signal to drive circuit 2202 for controlling drive circuit 2202. With this configuration, the interface between p-type semiconductor region 7 and source electrode 3 is located deeper than the interface between n-well region 9 and source electrode 3, improving adhesion through mechanical bonding at that location, thereby suppressing peeling of source electrode 3 from barrier metal layer 6 or n-well region 9 due to thermal stress caused by a rise in temperature of the semiconductor device. This improves the reliability of the semiconductor device during operation.

[0107] According to the embodiment described above, in the method for manufacturing a semiconductor device, at least one p-type semiconductor region 7 of a second conductivity type is provided in the surface layer of an n-well region 9 of a first conductivity type in the termination region. Then, a source electrode 3 is provided in the termination region to cover the n-well region 9 and the p-type semiconductor region 7. Here, the source electrode 3 is connected to the n-well region 9 by a Schottky junction. Furthermore, at least one interface between the p-type semiconductor region 7 and the source electrode 3 is located deeper than the interface between the n-well region 9 and the source electrode 3.

[0108] With this configuration, the interface between the p-type semiconductor region 7 and the source electrode 3 is located deeper than the interface between the n-well region 9 and the source electrode 3, and the mechanical bonding at this location improves adhesion, thereby making it possible to suppress peeling of the source electrode 3 from the barrier metal layer 6 or the n-well region 9 due to thermal stress caused by a rise in the temperature of the semiconductor device, thereby improving the reliability of the semiconductor device during operation.

[0109] Unless otherwise specified, the order in which the processes are performed can be changed.

[0110] Furthermore, even if other configurations shown as examples in this specification are appropriately added to the above configuration, that is, even if other configurations in this specification that were not mentioned as the above configuration are appropriately added, the same effect can be achieved.

[0111] Furthermore, according to the above-described embodiment, a method for manufacturing a power conversion device includes a conversion circuit 2201 having a semiconductor device manufactured by the above-described manufacturing method, which converts and outputs input power. A drive circuit 2202 is also provided, which outputs a drive signal to the semiconductor device for driving the semiconductor device. A control circuit 2203 is also provided, which outputs a control signal to the drive circuit 2202 for controlling the drive circuit 2202. With this configuration, the interface between the p-type semiconductor region 7 and the source electrode 3 is located deeper than the interface between the n-well region 9 and the source electrode 3, improving adhesion through mechanical bonding at that location. This makes it possible to suppress peeling of the source electrode 3 from the barrier metal layer 6 or the n-well region 9 due to thermal stress caused by a rise in the temperature of the semiconductor device. This improves the reliability of the semiconductor device during operation.

[0112] <Regarding Modifications of the Multiple Embodiments Described Above> In the multiple embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limiting.

[0113] Therefore, countless modifications and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component from at least one embodiment and combining it with a component from another embodiment.

[0114] Furthermore, in at least one embodiment described above, when a material name or the like is stated without being specifically specified, unless a contradiction arises, it is assumed that the material in question includes other additives, such as alloys.

[0115] Furthermore, unless a contradiction arises, when it is stated in the above-described embodiments that "one" component is provided, "one or more" of that component may be provided.

[0116] Furthermore, each component in the embodiments described above is a conceptual unit, and the scope of the technology disclosed in this specification includes cases where one component is made up of multiple structures, cases where one component corresponds to a part of a structure, and even cases where multiple components are provided in one structure.

[0117] Furthermore, each of the components in the embodiments described above includes structures having other structures or shapes as long as they perform the same function.

[0118] Furthermore, the descriptions in this specification are incorporated by reference for all purposes related to the present technology, and none of them are admitted to be prior art.

[0119] Various aspects of the present disclosure are summarized below as appendices.

[0120] (Supplementary Note 1) A semiconductor device comprising: an active region; and a termination region surrounding the active region in a planar view; wherein the termination region comprises: a first semiconductor layer of a first conductivity type; at least one second semiconductor layer of a second conductivity type provided on a surface layer of the first semiconductor layer; and a top surface electrode covering the first semiconductor layer and the second semiconductor layer, wherein the top surface electrode is in Schottky contact with the first semiconductor layer; and at least one interface between the second semiconductor layer and the top surface electrode is located deeper than an interface between the first semiconductor layer and the top surface electrode.

[0121] (Supplementary Note 2) The semiconductor device according to Supplementary Note 1, wherein, when a distance from an interface between the first semiconductor layer and the top electrode to an interface between the second semiconductor layer and the top electrode is D1, and a distance from the interface between the first semiconductor layer and the top electrode to a lower surface of the second semiconductor layer is D2, the interface between the second semiconductor layer and the top electrode is formed so as to satisfy D1>0, D2>0, and (D2÷2)>D1.

[0122] (Supplementary Note 3) The semiconductor device according to Supplementary Note 1 or 2, wherein the active region has a Schottky barrier diode structure.

[0123] (Supplementary Note 4) The semiconductor device according to Supplementary Note 3, wherein the active region has a MOSFET structure, and regions having the MOSFET structure and regions having the Schottky barrier diode structure are periodically arranged in a striped pattern in a plan view.

[0124] (Supplementary Note 5) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein a recess is formed in an upper surface of the first semiconductor layer, and the second semiconductor layer is provided so as to cover an area larger than the area in which the recess is formed.

[0125] (Supplementary Note 6) The semiconductor device according to Supplementary Note 5, wherein a side surface of the recess is an inclined surface.

[0126] (Supplementary Note 7) The semiconductor device according to Supplementary Note 1 or 2, wherein at least one corner of an end of the second semiconductor layer in plan view has an obtuse angle or a curved surface.

[0127] (Supplementary Note 8) A power conversion device comprising: a conversion circuit having the semiconductor device according to any one of Supplementary Notes 1 to 7, and converting and outputting input power; a drive circuit outputting a drive signal to the semiconductor device for driving the semiconductor device; and a control circuit outputting a control signal to the drive circuit for controlling the drive circuit.

[0128] (Supplementary Note 9) A method for manufacturing a semiconductor device including an active region and a termination region surrounding the active region in a planar view, wherein in the termination region, at least one second semiconductor layer of a second conductivity type is provided on a surface layer of a first semiconductor layer of a first conductivity type, a top surface electrode covering the first semiconductor layer and the second semiconductor layer is provided, the top surface electrode being in Schottky contact with the first semiconductor layer, and at least one interface between the second semiconductor layer and the top surface electrode being located deeper than an interface between the first semiconductor layer and the top surface electrode.

[0129] REFERENCE SIGNS LIST 1 semiconductor device, 2 gate wiring, 3 source electrode, 4 gate pad, 5 interlayer insulating film, 6 barrier metal layer, 6b barrier metal layer, 7 p-type semiconductor region, 7a p-type semiconductor region, 8 p-well region, 9 n-well region, 10 epitaxial growth layer, 11 SiC substrate, 12 drain electrode, 13 active region, 14 unit cell, 90 recess, 90b recess, 2100 power supply, 2200 power conversion device, 2201 conversion circuit, 2202 drive circuit, 2203 control circuit, 2300 load.

Claims

1. an active region and a termination region surrounding the active region in a plan view; In the termination region, a first semiconductor layer of a first conductivity type; At least one second semiconductor layer of a second conductivity type is provided on a surface layer of the first semiconductor layer; a top electrode covering the first semiconductor layer and the second semiconductor layer; the upper electrode is in Schottky contact with the first semiconductor layer; at least one interface between the second semiconductor layer and the top electrode is located deeper than an interface between the first semiconductor layer and the top electrode; Semiconductor device.

2. 2. The semiconductor device according to claim 1, a distance from an interface between the first semiconductor layer and the upper electrode to an interface between the second semiconductor layer and the upper electrode is defined as D1; When the distance from the interface between the first semiconductor layer and the upper electrode to the lower surface of the second semiconductor layer is D2, an interface between the second semiconductor layer and the upper electrode is formed so as to satisfy D1>0, D2>0, and (D2÷2)>D1; Semiconductor device.

3. 3. The semiconductor device according to claim 1, The active region has a Schottky barrier diode structure. Semiconductor device.

4. 4. The semiconductor device according to claim 3, The active region has a MOSFET structure, a region having a MOSFET structure and a region having a Schottky barrier diode structure are periodically arranged in a striped pattern in a plan view; Semiconductor device.

5. 3. The semiconductor device according to claim 1, a recess formed in an upper surface of the first semiconductor layer; the second semiconductor layer is provided to cover an area larger than an area in which the recess is formed; Semiconductor device.

6. 6. The semiconductor device according to claim 5, The side surface of the recess is an inclined surface. Semiconductor device.

7. 3. The semiconductor device according to claim 1, At least one corner of the end of the second semiconductor layer in a plan view has an obtuse angle or a curved surface. Semiconductor device.

8. a conversion circuit including the semiconductor device according to claim 1 or 2, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal to the semiconductor device for driving the semiconductor device; a control circuit that outputs a control signal to the drive circuit for controlling the drive circuit, Power conversion device.

9. A method for manufacturing a semiconductor device including an active region and a termination region surrounding the active region in a plan view, In the termination region, at least one second semiconductor layer of a second conductivity type is provided on a surface layer of a first semiconductor layer of a first conductivity type; providing a top electrode covering the first semiconductor layer and the second semiconductor layer; the upper electrode is in Schottky contact with the first semiconductor layer; at least one interface between the second semiconductor layer and the top electrode is located deeper than an interface between the first semiconductor layer and the top electrode; A method for manufacturing a semiconductor device.