Silicon carbide epitaxial substrate, method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device

Abstract

This silicon carbide epitaxial substrate has a silicon carbide substrate, a buffer layer and a drift layer. The buffer layer is provided on the silicon carbide substrate. The drift layer is provided on the buffer layer. The density of basal plane dislocations in the buffer layer is 10 dislocations / cm2 or less. The density of basal plane dislocations in the drift layer is 1 dislocation / cm2 or less. The value obtained by dividing the density of basal plane dislocations in the buffer layer by the density of basal plane dislocations in the drift layer is 1 to 100.

Description

Silicon carbide epitaxial substrate, silicon carbide semiconductor device manufacturing method, and silicon carbide semiconductor device

[0001] The present disclosure relates to a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide semiconductor device, and a silicon carbide semiconductor device. This application claims priority to Japanese Patent Application No. 2023-105807, filed on June 28, 2023. The entire contents of this Japanese patent application are incorporated herein by reference.

[0002] Japanese Patent Laid-Open Publication No. 2018-113303 (Patent Document 1) describes a SiC epitaxial wafer having a SiC single crystal substrate and an epitaxial layer provided on the SiC single crystal substrate. The epitaxial layer has a basal plane dislocation density of 0.1 / cm, which extends from the SiC single crystal substrate to the outer surface. ２ The following is the result.

[0003] Japanese Patent Application Laid-Open No. 2018-113303

[0004] A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate, a buffer layer, and a drift layer. The buffer layer is provided on the silicon carbide substrate. The drift layer is provided on the buffer layer. The buffer layer has a basal plane dislocation density of 10 / cm. ２ The density of basal plane dislocations in the drift layer is 1 / cm ２ The value obtained by dividing the density of basal plane dislocations in the buffer layer by the density of basal plane dislocations in the drift layer is 1 or more and 100 or less.

[0005] FIG. 1 is a plan view schematic diagram showing the configuration of a silicon carbide epitaxial substrate according to this embodiment. FIG. 2 is a cross-sectional view schematic diagram taken along line II-II in FIG. 1. FIG. 3 is a cross-sectional view schematic diagram showing the configuration of a photoluminescence imaging device. FIG. 4 is a plan view schematic diagram showing photoluminescence images of first basal plane dislocations and second basal plane dislocations. FIG. 5 is a plan view schematic diagram showing measurement positions for the first density and the second densities. FIG. 6 is a cross-sectional view schematic diagram showing the configuration of a silicon carbide epitaxial substrate manufacturing device according to this embodiment. FIG. 7 is a flow diagram showing an outline of a method for manufacturing a silicon carbide epitaxial substrate according to this embodiment. FIG. 8 is a cross-sectional view schematic diagram showing a step of preparing a silicon carbide substrate. FIG. 9 is a cross-sectional view schematic diagram showing the change over time in temperature inside a reaction chamber. FIG. 10 is a cross-sectional view schematic diagram showing the change over time in the flow rates of hydrogen gas and silane gas. FIG. 11 is a cross-sectional view schematic diagram showing the step of forming a buffer layer on a silicon carbide substrate. FIG. 12 is a flowchart schematically illustrating a method for manufacturing a silicon carbide semiconductor device according to the present embodiment. FIG. 13 is a cross-sectional view schematically illustrating a step of preparing a silicon carbide epitaxial substrate. FIG. 14 is a cross-sectional view schematically illustrating a step of forming a body region. FIG. 15 is a cross-sectional view schematically illustrating a step of forming a source region. FIG. 16 is a cross-sectional view schematically illustrating a step of forming a trench in a first main surface of a silicon carbide epitaxial layer. FIG. 17 is a cross-sectional view schematically illustrating a step of forming a gate insulating film. FIG. 18 is a cross-sectional view schematically illustrating a step of forming a gate electrode and an interlayer insulating film. FIG. 19 is a cross-sectional view schematically illustrating a configuration of a silicon carbide semiconductor device according to the present embodiment. FIG. 20 is a first photoluminescence image according to a comparative example. FIG. 21 is a first photoluminescence image according to an example. FIG. 22 is a second photoluminescence image according to a comparative example. FIG. 23 is a second photoluminescence image according to an example.

[0006] [Problem to be Solved by the Present Disclosure] An object of the present disclosure is to provide a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide semiconductor device, and a silicon carbide semiconductor device that are capable of suppressing deterioration in the reliability of the silicon carbide semiconductor device. [Advantages of the Present Disclosure] According to the present disclosure, it is possible to provide a silicon carbide epitaxial substrate, a method for manufacturing a silicon carbide semiconductor device, and a silicon carbide semiconductor device that are capable of suppressing deterioration in the reliability of the silicon carbide semiconductor device.

[0007] [Outline of Embodiments of the Present Disclosure] First, an outline of embodiments of the present disclosure will be described. In the crystallographic descriptions in this specification, individual orientations are represented by [ ], collective orientations by < >, individual planes by ( ), and collective planes by {}. A negative crystallographic index is usually represented by placing a "-" (bar) above the number, but in this specification, a negative crystallographic index is represented by placing a negative sign before the number.

[0008] (1) A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate, a buffer layer, and a drift layer. The buffer layer is provided on the silicon carbide substrate. The drift layer is provided on the buffer layer. The buffer layer has a basal plane dislocation density of 10 / cm. ２ The density of basal plane dislocations in the drift layer is 1 / cm ２ The value obtained by dividing the density of basal plane dislocations in the buffer layer by the density of basal plane dislocations in the drift layer is equal to or greater than 1 and equal to or less than 100. This makes it possible to suppress deterioration in the reliability of silicon carbide semiconductor devices manufactured using the silicon carbide epitaxial substrate.

[0009] (2) A silicon carbide epitaxial substrate according to the present disclosure includes a silicon carbide substrate, a buffer layer, and a drift layer. The buffer layer is provided on the silicon carbide substrate. The drift layer is provided on the buffer layer. The buffer layer has a basal plane dislocation density of 10 / cm. ２ The density of basal plane dislocations in the drift layer is 0 / cm ２ This makes it possible to suppress deterioration in the reliability of a silicon carbide semiconductor device manufactured using a silicon carbide epitaxial substrate.

[0010] (3) In the silicon carbide epitaxial substrate according to (1) or (2), the buffer layer may have a thickness of 0.5 μm or more and 10 μm or less, thereby suppressing holes from being injected into basal plane dislocations in the silicon carbide substrate.

[0011] (4) In the silicon carbide epitaxial substrate according to any one of (1) to (3), the drift layer may constitute a main surface, and the main surface may have a diameter of 150 mm or more.

[0012] (5) In the silicon carbide epitaxial substrate according to (4) above, the main surface may be inclined at an off angle of 1° or more and 8° or less with respect to the {0001} plane.

[0013] (6) In the silicon carbide epitaxial substrate according to any one of (1) to (5) above, the density of basal plane dislocations in the buffer layer is 0.01 dislocations / cm ２ It may be more than that.

[0014] (7) A method for manufacturing a silicon carbide semiconductor device according to the present disclosure includes the following steps: preparing a silicon carbide epitaxial substrate according to any one of (1) to (6) above; forming an electrode on the silicon carbide epitaxial substrate; and thereby suppressing deterioration in the reliability of silicon carbide semiconductor device 400.

[0015] (8) A silicon carbide semiconductor device according to the present disclosure includes the silicon carbide epitaxial substrate according to (2) above and an electrode provided on the silicon carbide epitaxial substrate, thereby preventing deterioration in reliability of the silicon carbide semiconductor device.

[0016] [Details of the embodiment of the present disclosure] Hereinafter, details of the embodiment of the present disclosure will be described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[0017] (Silicon Carbide Epitaxial Substrate) FIG. 1 is a plan view schematic showing the configuration of a silicon carbide epitaxial substrate according to this embodiment. FIG. 2 is a cross-sectional view schematic taken along line II-II in FIG. 1. As shown in FIGS. 1 and 2, the silicon carbide epitaxial substrate 100 according to this embodiment mainly includes a silicon carbide substrate 10 and a silicon carbide epitaxial layer 20. The silicon carbide substrate 10 has a second main surface 2. The second main surface 2 is the back surface of the silicon carbide epitaxial substrate 100. The silicon carbide epitaxial layer 20 is provided on the silicon carbide substrate 10. The silicon carbide epitaxial layer 20 is in contact with the silicon carbide substrate 10. The silicon carbide epitaxial layer 20 has a first main surface 1. The first main surface 1 is the front surface of the silicon carbide epitaxial substrate 100. Silicon carbide epitaxial substrate 100 has an outer peripheral side surface 5. Outer peripheral side surface 5 is continuous with first main surface 1 and second main surface 2.

[0018] As shown in FIG. 1 , silicon carbide epitaxial substrate 100 has an outer peripheral edge 8. Outer peripheral edge 8 has, for example, an orientation flat 6 and an arc-shaped portion 7. Orientation flat 6 extends along a first direction 101. As shown in FIG. 1 , orientation flat 6 is linear when viewed along a line perpendicular to first main surface 1. Arc-shaped portion 7 is continuous with orientation flat 6. Arc-shaped portion 7 is arc-shaped when viewed along a line perpendicular to first main surface 1. When viewed along a line perpendicular to first main surface 1, center O of first main surface 1 is the center of a circle that includes an arc along arc-shaped portion 7.

[0019] 1 , when viewed along a line perpendicular to the first main surface 1, the first main surface 1 extends along each of a first direction 101 and a second direction 102. When viewed along a line perpendicular to the first main surface 1, the second direction 102 is a direction perpendicular to the first direction 101.

[0020] The first direction 101 is, for example, the <11-20> direction. The first direction 101 may be, for example, the [11-20] direction. The first direction 101 may be a direction obtained by projecting the <11-20> direction onto the first main surface 1. From another perspective, the first direction 101 may be, for example, a direction including a <11-20> direction component.

[0021] The second direction 102 is, for example, the <1-100> direction. The second direction 102 may be, for example, the [1-100] direction. The second direction 102 may be, for example, a direction obtained by projecting the <1-100> direction onto the first main surface 1. From another perspective, the second direction 102 may be, for example, a direction including a <1-100> direction component. A direction perpendicular to each of the first direction 101 and the second direction 102 is defined as a third direction 103.

[0022] As shown in FIG. 1 , the diameter W1 of the first main surface 1 is, for example, 150 mm (6 inches). The diameter W1 may be 150 mm (6 inches) or more, or may be 200 mm (8 inches) or more. The diameter W1 may be, for example, 400 mm (16 inches) or less. The diameter W1 is the longest linear distance between two different points on the outer circumferential edge 8.

[0023] As used herein, 6 inches refers to 150 mm or 152.4 mm (6 inches x 25.4 mm / inch). 8 inches refers to 200 mm or 203.2 mm (8 inches x 25.4 mm / inch). 16 inches refers to 400 mm or 406.4 mm (16 inches x 25.4 mm / inch).

[0024] As shown in Fig. 1, the first main surface 1 is composed of an outer peripheral region 11 and a central region 12. The outer peripheral region 11 is a region within 3 mm from the outer peripheral edge 8. When viewed along a line perpendicular to the first main surface 1, the distance E between the outer peripheral edge 8 and the boundary between the outer peripheral region 11 and the central region 12 is 3 mm. From another perspective, the width (distance E) of the outer peripheral region 11 in the direction extending radially from the center O of the first main surface 1 (radial direction) is 3 mm.

[0025] The central region 12 is surrounded by the outer peripheral region 11. The central region 12 is continuous with the outer peripheral region 11. The central region 12 is a region whose distance from the outer peripheral edge 8 is greater than 3 mm.

[0026] 2 , silicon carbide substrate 10 has third main surface 3. Third main surface 3 is opposite second main surface 2. At third main surface 3, silicon carbide substrate 10 is in contact with silicon carbide epitaxial layer 20. Second main surface 2 is spaced apart from silicon carbide epitaxial layer 20. The polytype of silicon carbide constituting silicon carbide substrate 10 is, for example, 4H. Similarly, the polytype of silicon carbide constituting silicon carbide epitaxial layer 20 is, for example, 4H.

[0027] As shown in Fig. 2, silicon carbide epitaxial layer 20 has a buffer layer 41 and a drift layer 42. Buffer layer 41 is provided on silicon carbide substrate 10. Buffer layer 41 is in contact with silicon carbide substrate 10. Drift layer 42 is provided on buffer layer 41. Drift layer 42 is in contact with buffer layer 41. Buffer layer 41 is located between silicon carbide substrate 10 and drift layer 42. Drift layer 42 constitutes first main surface 1. First main surface 1 is provided on the side opposite interface 9 between buffer layer 41 and drift layer 42. At outer circumferential edge 8, first main surface 1 is continuous with outer circumferential side surface 5.

[0028] As shown in FIG. 2 , the first main surface 1 is a surface inclined with respect to the {0001} plane. The inclination angle (off angle θ) of the first main surface 1 with respect to the {0001} plane is, for example, 1° or more and 8° or less. Specifically, the first main surface 1 may be a surface inclined with respect to the (0001) plane by the off angle θ. The first main surface 1 may be a surface inclined with respect to the (000-1) plane by the off angle θ. The inclination direction (off direction) of the first main surface 1 with respect to the {0001} plane is, for example, the <11-20> direction. The upper limit of the off angle θ may be, for example, 7° or less, 6° or less, or 5° or less. The lower limit of the off angle θ may be, for example, 2° or more, or 3° or more.

[0029] 2 , silicon carbide epitaxial substrate 100 includes a plurality of basal plane dislocations 30. Each of the plurality of basal plane dislocations 30 is located in the basal plane. The plurality of basal plane dislocations 30 includes a first basal plane dislocation 31, a second basal plane dislocation 32, and a third basal plane dislocation 33.

[0030] First basal plane dislocations 31 reach first main surface 1. First basal plane dislocations 31 may reach both second main surface 2 and first main surface 1, or both outer peripheral side surface 5 and first main surface 1. First basal plane dislocations 31 may extend continuously from second main surface 2 to first main surface 1, or may extend continuously from outer peripheral side surface 5 to first main surface 1. An end of first basal plane dislocation 31 is located on first main surface 1. At least a portion of first basal plane dislocation 31 is located in drift layer 42. First basal plane dislocations 31 penetrate, for example, silicon carbide substrate 10, buffer layer 41, and drift layer 42.

[0031] First basal plane dislocation 31 is composed of, for example, first portion 61, second portion 62, and third portion 63. First portion 61 is a portion of basal plane dislocation 30 in silicon carbide substrate 10. First portion 61 reaches both second main surface 2 and third main surface 3. First portion 61 extends continuously from second main surface 2 to third main surface 3.

[0032] The second portion 62 is continuous with the first portion 61. Specifically, the second portion 62 is continuous with an end portion of the first portion 61. The second portion 62 is a portion of the basal plane dislocations 30 in the buffer layer 41. The second portion 62 reaches both the third main surface 3 and the interface 9. The second portion 62 extends continuously from the third main surface 3 to the interface 9.

[0033] The third portion 63 is continuous with the second portion 62. Specifically, the third portion 63 is continuous with the end of the second portion 62. The third portion 63 is located opposite the first portion 61 with respect to the second portion 62. From another perspective, the second portion 62 is located, for example, between the third portion 63 and the first portion 61. The third portion 63 is a portion of the basal plane dislocations 30 in the drift layer 42. The third portion 63 reaches both the interface 9 and the first main surface 1. The third portion 63 extends continuously from the interface 9 to the first main surface 1.

[0034] The second basal plane dislocation 32 reaches the interface 9. The second basal plane dislocation 32 may reach both the second main surface 2 and the interface 9, or may reach both the outer peripheral side surface 5 and the interface 9. The second basal plane dislocation 32 may extend continuously from the second main surface 2 to the interface 9, or may extend continuously from the outer peripheral side surface 5 to the interface 9. The end of the second basal plane dislocation 32 is located at the interface 9. The second basal plane dislocation 32 is a basal plane dislocation 30 that does not reach the inside of the drift layer 42. At least a portion of the second basal plane dislocation 32 is located in the buffer layer 41. The second basal plane dislocation 32 penetrates, for example, the silicon carbide substrate 10 and the buffer layer 41. The second basal plane dislocation 32 is composed of, for example, a first portion 61 and a second portion 62.

[0035] Third basal plane dislocation 33 is present in silicon carbide substrate 10. Third basal plane dislocation 33 reaches third main surface 3. Third basal plane dislocation 33 may reach both second main surface 2 and third main surface 3, or may reach both outer peripheral side surface 5 and third main surface 3. Third basal plane dislocation 33 may extend continuously from second main surface 2 to third main surface 3, or may extend continuously from outer peripheral side surface 5 to third main surface 3. An end of third basal plane dislocation 33 is located on third main surface 3. Third basal plane dislocation 33 is a basal plane dislocation that does not reach the interior of silicon carbide epitaxial layer 20. Third basal plane dislocation 33 penetrates silicon carbide substrate 10, for example. Third basal plane dislocation 33 is constituted by first portion 61, for example.

[0036] Silicon carbide epitaxial substrate 100 includes a first threading edge dislocation 68 and a second threading edge dislocation 69. At interface 9, first threading edge dislocation 68 is continuous with second basal plane dislocation 32. First threading edge dislocation 68 is continuous with an end of second basal plane dislocation 32. First threading edge dislocation 68 reaches interface 9. First threading edge dislocation 68 may reach both interface 9 and first main surface 1, or may reach both interface 9 and outer peripheral side surface 5. First threading edge dislocation 68 may extend continuously from interface 9 to first main surface 1, or may extend continuously from interface 9 to outer peripheral side surface 5. The extension direction of first threading edge dislocation 68 is, for example, along the <0001> direction. First threading edge dislocation 68 is a threading edge dislocation formed by transformation of second basal plane dislocation 32.

[0037] In the third main surface 3, the second threading edge dislocation 69 is continuous with the third basal plane dislocation 33. The second threading edge dislocation 69 reaches the third main surface 3. The second threading edge dislocation 69 may reach both the third main surface 3 and the first main surface 1, or may reach both the third main surface 3 and the outer peripheral side surface 5. The second threading edge dislocation 69 may extend continuously from the third main surface 3 to the first main surface 1, or may extend continuously from the third main surface 3 to the outer peripheral side surface 5. The extension direction of the second threading edge dislocation 69 is, for example, along the <0001> direction. The second threading edge dislocation 69 is a threading edge dislocation formed by transformation of the third basal plane dislocation 33.

[0038] The first thickness T1 is, for example, 0.5 μm or more and 10 μm or less. The first thickness T1 may be, for example, 1 μm or more, or 3 μm or more. The upper limit of the first thickness T1 may be, for example, 8 μm or less, or 5 μm or less. The second thickness T2 is, for example, 5 μm or more and 30 μm or less.

[0039] Silicon carbide substrate 10 contains an n-type impurity such as nitrogen (N). The conductivity type of silicon carbide substrate 10 is, for example, n-type. Buffer layer 41 and drift layer 42 each contain an n-type impurity such as nitrogen. The conductivity type of buffer layer 41 and drift layer 42 is, for example, n-type.

[0040] The n-type impurity concentration of the buffer layer 41 is higher than the n-type impurity concentration of the drift layer 42. The n-type impurity concentration of the buffer layer 41 is, for example, 1×10 １８ cm －３ The n-type impurity concentration of the buffer layer 41 is, for example, 1×10 １７ cm －３ 1x10 or more １９ cm －３ It may be the following:

[0041] The n-type impurity concentration of the drift layer 42 is, for example, 8×10 １５ cm －３ The n-type impurity concentration of the drift layer 42 is, for example, 1×10 １５ cm －３ 5x10 or more １６ cm －３ It may be the following:

[0042] The n-type impurity concentration of silicon carbide substrate 10 is higher than the n-type impurity concentration of drift layer 42. The n-type impurity concentration of silicon carbide substrate 10 is, for example, 7×10 １８ cm －３ is.

[0043] Next, a method for measuring the n-type impurity concentration will be described. The n-type impurity concentration of the buffer layer 41 and the n-type impurity concentration of the drift layer 42 are each measured using, for example, a mercury probe-type C (Capacitance)-V (Voltage) measurement device. A mercury probe-type CV measurement device such as a Four Dimensions CV measurement device (model number: CVmap92A) can be used. The n-type impurity concentration of the buffer layer 41 and the n-type impurity concentration of the drift layer 42 are each measured by bringing the mercury probe into contact with the first main surface 1. The measurement diameter of the mercury probe is approximately 1.2 mm. The measurement speed is approximately one minute per point.

[0044] The n-type impurity concentration of silicon carbide substrate 10 is measured by, for example, secondary ion mass spectrometry (SIMS). For SIMS, for example, an IMS7f secondary ion mass spectrometer manufactured by Cameca Corporation can be used. The measurement conditions for SIMS are, for example, O2 as the primary ion. ＋ The measurement conditions can be such that the primary ion energy is 8 keV.

[0045] (Density of Basal Plane Dislocations) The density of basal plane dislocations 30 in drift layer 42 is set to a first density. From another perspective, the first density is the density of first basal plane dislocations 31 in silicon carbide epitaxial substrate 100. The first density is 1 / cm ２ The first density is, for example, 0.001 particles / cm ２ or more, and may be 0.005 particles / cm ２ The first density may be, for example, 0.5 particles / cm ２ It may be 0.3 particles / cm or less. ２ It may be the following:

[0046] The first density is 0 particles / cm ２ Drift layer 42 may be free of basal plane dislocations 30. From another perspective, silicon carbide epitaxial substrate 100 may be free of first basal plane dislocations 31 (see FIG. 2 ).

[0047] The density of basal plane dislocations 30 in buffer layer 41 is set to a second density. From another perspective, the second density is the density of first basal plane dislocations 31 and second basal plane dislocations 32 in silicon carbide epitaxial substrate 100. The second density is 10 / cm ２ The second density is, for example, 0.01 particles / cm ２ It may be 0.05 pieces / cm or more. ２ The second density may be, for example, 5 particles / cm ２ or less, or 1 piece / cm ２ It may be 0.1 particles / cm or less. ２ It may be the following:

[0048] The first density is equal to or less than the second density. The value obtained by dividing the second density by the first density is set to a first value. When the first density is 0 counts / cm ２ If the first value is greater than 1, the first value is greater than or equal to 100. The first value may be, for example, greater than or equal to 2, or greater than or equal to 5. The first value may be, for example, less than or equal to 50, less than or equal to 30, or less than or equal to 10.

[0049] The density of basal plane dislocations 30 in silicon carbide substrate 10 is set to a third density. From another perspective, the third density is the density of first basal plane dislocations 31, second basal plane dislocations 32, and third basal plane dislocations 33 in silicon carbide epitaxial substrate 100. The third density is, for example, about 10 / cm. ２ The third density is, for example, 5 particles / cm ２ More than 2000 pieces / cm ２ It may be 100 pieces / cm or less. ２ More than 2000 pieces / cm ２ The value obtained by dividing the third density by the second density is set to the second value. The second value is, for example, equal to or greater than 100 and equal to or less than 10,000.

[0050] Next, a device for measuring the density of basal plane dislocations 30 will be described. The density of basal plane dislocations 30 can be measured using, for example, a photoluminescence imaging device (model number: PLI-200) manufactured by Photon Design Inc. FIG. 3 is a schematic diagram showing the configuration of the photoluminescence imaging device. As shown in FIG. 3, the photoluminescence imaging device 200 mainly includes an excitation light generation unit 220 and an imaging unit 230.

[0051] The excitation light generation unit 220 has a light source unit 221, a light guiding unit 222, and a filter unit 223. The light source unit 221 can generate excitation light LE having energy higher than the band gap of hexagonal silicon carbide. The light source unit 221 is, for example, a mercury-xenon lamp. The light guiding unit 222 can guide the light emitted from the light source unit 221 so that the light is irradiated onto the first main surface 1 of the silicon carbide epitaxial substrate 100. The light guiding unit 222 has, for example, an optical fiber. As shown in FIG. 3 , the excitation light generation unit 220 may be arranged on both sides of the near-infrared objective lens 237.

[0052] The filter section 223 selectively transmits light having a specific wavelength corresponding to an energy higher than the bandgap of hexagonal silicon carbide. The wavelength corresponding to the bandgap of hexagonal silicon carbide is typically about 390 nm. Therefore, a bandpass filter that specifically transmits light having a wavelength of, for example, about 313 nm is used as the filter section 223. The transmission wavelength range of the filter section 223 may be, for example, 290 nm to 370 nm, 300 nm to 330 nm, or 300 nm to 320 nm.

[0053] Imaging unit 230 mainly includes a control unit 238, a first stage 239, a near-infrared objective lens 237, a color image sensor 236, and a light-receiving filter (not shown). Control unit 238 controls the displacement operation of first stage 239 and the imaging operation by color image sensor 236, and is, for example, a personal computer. First stage 239 supports silicon carbide epitaxial substrate 100 so that first main surface 1 is exposed. First stage 239 is, for example, an XY stage that displaces the position of first main surface 1.

[0054] Near-infrared objective lens 237 is disposed above first main surface 1. The magnification of near-infrared objective lens 237 is, for example, 4.5 times. Color image sensor 236 receives photoluminescence light emitted from silicon carbide epitaxial substrate 100. The light-receiving filter selectively transmits light having wavelengths longer than a specific wavelength. The light-receiving filter is disposed between color image sensor 236 and first main surface 1. The transmission wavelength range of the light-receiving filter is, for example, 390 nm or more.

[0055] Next, a method for measuring the first density and the second density will be described. First, excitation light generation unit 220 is used to irradiate first main surface 1 of silicon carbide epitaxial substrate 100 with excitation light LE. This causes photoluminescence light LL to be generated from silicon carbide epitaxial substrate 100. The wavelength of excitation light LE is, for example, 313 nm. The intensity of excitation light LE is, for example, 0.1 mW / cm. ２ More than 2W / cm ２ The irradiation time of the excitation light LE is, for example, 5 seconds.

[0056] Next, the photoluminescent light is detected by the color image sensor. Specifically, photoluminescent light LL generated in silicon carbide epitaxial substrate 100 passes through a light-receiving filter and reaches color image sensor 236. The wavelength of photoluminescent light LL that reaches color image sensor 236 is, for example, 390 nm or more. The photoluminescent light LL that reaches color image sensor 236 is detected by color image sensor 236.

[0057] The color image sensor 236 is, for example, a CCD (charge-coupled device) image sensor. The type of CCD element is, for example, a back-illuminated deep depletion type. The CCD image sensor is, for example, an excelon (trademark) manufactured by Teledyne. The imaging wavelength range is, for example, 310 nm or more and 1024 nm or less. The element format is, for example, 1024 ch x 1024 ch. The image area is, for example, 13.3 mm x 13.3 mm. The element size is, for example, 13 μm x 13 μm. The number of pixels is, for example, 480 pixels x 640 pixels. The image size is, for example, 1.9 mm x 2.6 mm.

[0058] The color image sensor 236 may be, for example, a CMOS (complementary metal-oxide semiconductor) image sensor. The CMOS image sensor is, for example, an ORCA (trademark)-Fusion manufactured by Hamamatsu Photonics K.K. The imaging wavelength range is, for example, 350 nm or more and 1000 nm or less. The effective element size is 14.98 mm × 14.98 mm. The pixel size is 6.5 μm × 6.5 μm. A black-and-white imaging sensor may be used instead of the color image sensor 236.

[0059] 4 is a plan view schematic diagram showing photoluminescence images of first basal plane dislocations 31 and second basal plane dislocations 32. A photoluminescence imaging device is used to acquire a photoluminescence image of first main surface 1 of silicon carbide epitaxial substrate 100. First basal plane dislocations 31 and second basal plane dislocations 32 are each identified based on the photoluminescence image.

[0060] As shown in FIG. 4 , in the photoluminescence image, each of the first basal plane dislocations 31 and the second basal plane dislocations 32 appears darker (blacker) than the areas other than the first basal plane dislocations 31 and the second basal plane dislocations 32.

[0061] In the photoluminescence image, the second portions 62 appear darker (blacker) than the regions other than the first basal plane dislocations 31 and the second basal plane dislocations 32. When viewed along a line perpendicular to the first main surface 1, the shape of the second portions 62 is streaky. When viewed along a line perpendicular to the first main surface 1, the shape of the second portions 62 is linear or curved.

[0062] The length of the second portion 62 in the short direction of the second portion 62 when viewed along a straight line perpendicular to the first main surface 1 is defined as a first width H1. The first width H1 is, for example, not less than 1 μm and not more than 10 μm.

[0063] When viewed along a line perpendicular to the first main surface 1, the length of the second portion 62 in the off direction (first direction 101) is defined as a second length A2. When the thickness of the buffer layer 41 is T1 and the off angle of the first main surface 1 is θ, the second length A2 is ideally T1 / tan θ. For example, when T1 is 10 μm and θ is 4°, the second length A2 is ideally approximately 140 μm. In a photoluminescence image, the second length A2 may be equal to or greater than 0.9 × T1 / tan θ and equal to or less than 1.1 × T1 / tan θ.

[0064] 4 , in the photoluminescence image, the third portion 63 appears darker (blacker) than the second portion 62. When viewed along a line perpendicular to the first main surface 1, the third portion 63 has a streaky shape. When viewed along a line perpendicular to the first main surface 1, the third portion 63 has a linear or curved shape. At the end of the third portion 63, the third portion 63 is continuous with the second portion 62. When viewed along a line perpendicular to the first main surface 1, the second portion 62 may be inclined with respect to the third portion 63.

[0065] The length of the third portion 63 in the short direction of the third portion 63 when viewed along a straight line perpendicular to the first main surface 1 is set to a second width H2. The second width H2 is, for example, not less than 1 μm and not more than 10 μm.

[0066] When viewed along a straight line perpendicular to the first main surface 1, the length of the third portion 63 in the first direction 101 (off direction) is defined as a third length A3. When the thickness of the drift layer 42 is T2 and the off angle of the first main surface 1 is θ, the third length A3 is ideally T2 / tan θ. For example, when T2 is 10 μm and θ is 4°, the third length A3 is ideally approximately 140 μm. In a photoluminescence image, the third length A3 may be equal to or greater than 0.9 × T2 / tan θ and equal to or less than 1.1 × T2 / tan θ.

[0067] In the photoluminescence image, a black streak-like portion is determined to be the second portion 62. A streak-like portion that is connected to the second portion 62 and is darker than the second portion 62 is determined to be the third portion 63. If the second portion 62 is connected to the third portion 63, the second portion 62 and the third portion 63 are determined to be the first basal plane dislocation 31. If the second portion 62 is not connected to the third portion 63, the second portion 62 is determined to be the second basal plane dislocation 32.

[0068] Next, the measurement positions of the first density and the second density will be described. Fig. 5 is a schematic plan view showing the measurement positions of the first density and the second density. As shown in Fig. 5, a plurality of square regions 50 are arranged in the central region 12. Each of the plurality of square regions 50 is arranged inside the boundary between the peripheral region 11 and the central region 12.

[0069] The plurality of square regions 50 are arranged in the central region 12 along each of a first straight line 91, a second straight line 92, and two third straight lines 93 so as to maximize the number of the plurality of square regions 50. The first straight line 91 is a straight line that passes through the center O and is parallel to a first direction 101. The second straight line 92 is a straight line that passes through the center O and is parallel to a second direction 102. The two third straight lines 93 are two straight lines that pass through the center O and bisect the angle formed by the first straight line 91 and the second straight line 92.

[0070] Of the multiple square regions 50, one square region 50 is centered at center O. The center of each of the multiple square regions 50 is located on any of a first line 91, a second line 92, and two third lines 93.

[0071] When viewed along a line perpendicular to the first main surface 1, the shape of each of the plurality of square regions 50 is substantially square. The length of one side of each of the plurality of square regions 50 (first length A1) is 0.51 cm. The area of ​​each of the plurality of square regions 50 is 0.26 cm. ２ The diameter W1 (see FIG. 1 ) of the first main surface 1 is, for example, 150 mm. The number of square regions 50 is, for example, 91. When viewed along a line perpendicular to the first main surface 1, one side of each of the plurality of square regions 50 is parallel to the direction in which the orientation flat 6 extends.

[0072] In each of all square regions 50, the number of first basal plane dislocations 31 and the number of second basal plane dislocations 32 are measured. In each of all square regions 50, the number of first basal plane dislocations 31 is divided by the area of ​​the square region 50 to determine the density of first basal plane dislocations 31. In each of all square regions 50, the number of second basal plane dislocations 32 is divided by the area of ​​the square region 50 to determine the density of second basal plane dislocations 32.

[0073] The average value of the density of the first basal plane dislocations 31 in all the square regions 50 is set to the first density. The sum of the density of the first basal plane dislocations 31 and the density of the second basal plane dislocations 32 is calculated in all the square regions 50. The average value of this sum in all the square regions 50 is set to the second density.

[0074] Next, a method for measuring the third density will be described. The third density is determined using, for example, molten potassium hydroxide (KOH). Specifically, second main surface 2 of silicon carbide substrate 10 is etched with molten KOH. As a result, silicon carbide regions near basal plane dislocations exposed at second main surface 2 are etched, forming etch pits at second main surface 2. The value obtained by dividing the number of etch pits formed at second main surface 2 by the measured area of ​​second main surface 2 corresponds to the third density.

[0075] The temperature of the KOH melt is, for example, about 500°C or higher and 530°C or lower. The etching time is, for example, about 1 minute or higher and 10 minutes or lower. After etching, the etch pits formed on second main surface 2 are observed using a Normarski differential interference microscope. When viewed along a line perpendicular to second main surface 2, elliptical etch pits correspond to basal plane dislocations.

[0076] (Apparatus for manufacturing silicon carbide epitaxial substrate) Figure 6 is a cross-sectional schematic diagram showing the configuration of an apparatus for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment. As shown in Figure 6, the apparatus for manufacturing silicon carbide epitaxial substrate 100 is, for example, a hot-wall horizontal CVD (Chemical Vapor Deposition) apparatus. Apparatus 250 for manufacturing silicon carbide epitaxial substrate 100 mainly includes reaction chamber 201, gas supply unit 235, flow rate control unit 245, heating element 203, quartz tube 204, heat insulating material (not shown), and induction heating coil (not shown).

[0077] The heating element 203 has, for example, a cylindrical shape, and defines a reaction chamber 201 therein. The heating element 203 is made of, for example, graphite. The heating element 203 is provided inside a quartz tube 204. A heat insulating material surrounds the outer periphery of the heating element 203. The induction heating coil is wound, for example, along the outer periphery of the quartz tube 204. The induction heating coil is configured so that an alternating current can be supplied to it from an external power source (not shown). This causes the heating element 203 to be induction heated. As a result, the reaction chamber 201 is heated by the heating element 203.

[0078] Reaction chamber 201 is formed by being surrounded by an inner wall surface 205 of heating element 203. Reaction chamber 201 is provided with a susceptor 210 that holds silicon carbide substrate 10. Susceptor 210 is made of, for example, silicon carbide. Silicon carbide substrate 10 is placed on susceptor 210. Susceptor 210 is placed on second stage 206. Second stage 206 is rotatably supported by a rotation shaft 209. Rotation of second stage 206 causes susceptor 210 to rotate.

[0079] Manufacturing apparatus 250 for silicon carbide epitaxial substrate 100 further includes gas inlet 207 and gas outlet 208. Gas outlet 208 is connected to an exhaust pump (not shown). Arrows in FIG. 6 indicate the flow of gas. Gas is introduced into reaction chamber 201 from gas inlet 207 and exhausted from gas exhaust outlet 208. The pressure inside reaction chamber 201 is adjusted by balancing the amount of gas supplied and the amount of gas exhausted.

[0080] The gas supply unit 235 is configured to be able to supply a mixed gas containing a source gas, a dopant gas, and a carrier gas to the reaction chamber 201. Specifically, the gas supply unit 235 includes, for example, a first gas supply unit 231, a second gas supply unit 232, a third gas supply unit 233, and a fourth gas supply unit 234.

[0081] The first gas supply unit 231 is configured to be able to supply a first gas containing, for example, carbon atoms. The first gas supply unit 231 is, for example, a gas cylinder filled with the first gas. The first gas is, for example, propane (C ３ H ８ The first gas is, for example, methane (CH ４ ) gas, ethane (C ２ H ６ ) gas, acetylene (C ２ H ２ ) gas, ethylene (C ２ H ４ ) gas, etc.

[0082] The second gas supply unit 232 is configured to be able to supply a second gas containing, for example, silane gas. The second gas supply unit 232 is, for example, a gas cylinder filled with the second gas. The second gas is, for example, silane (SiH ４ The second gas may be a mixture of silane gas and a gas other than silane.

[0083] The third gas supply unit 233 is configured to be able to supply a third gas containing, for example, ammonia gas. The third gas supply unit 233 is, for example, a gas cylinder filled with the third gas. The third gas is a doping gas containing nitrogen atoms (N). Ammonia gas is more susceptible to thermal decomposition than nitrogen gas having a triple bond. The third gas may be nitrogen gas.

[0084] The fourth gas supply unit 234 is configured to be able to supply a fourth gas (carrier gas) such as hydrogen, for example. The fourth gas supply unit 234 is, for example, a gas cylinder filled with hydrogen.

[0085] The flow rate control unit 245 is configured to be able to control the flow rate of the mixed gas supplied from the gas supply unit 235 to the reaction chamber 201. Specifically, the flow rate control unit 245 may include a first gas flow rate control unit 241, a second gas flow rate control unit 242, a third gas flow rate control unit 243, and a fourth gas flow rate control unit 244. Each control unit may be, for example, an MFC (Mass Flow Controller). The flow rate control unit 245 is disposed between the gas supply unit 235 and the gas inlet 207. In other words, the flow rate control unit 245 is disposed in a flow path connecting the gas supply unit 235 and the gas inlet 207.

[0086] (Method for manufacturing silicon carbide epitaxial substrate) Next, a method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment will be described. FIG. 7 is a flow chart schematically showing the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment. As shown in FIG. 7, the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment mainly includes a step (S10) of preparing a silicon carbide substrate, a step (S20) of hydrogen etching the silicon carbide substrate, a step (S30) of lowering the temperature in the reaction chamber, a step (S40) of forming a buffer layer on the silicon carbide substrate, and a step (S50) of forming a drift layer on the buffer layer.

[0087] First, a step (S10) of preparing a silicon carbide substrate is carried out. Specifically, a silicon carbide single crystal of polytype 4H is produced, for example, by sublimation deposition. Next, the silicon carbide single crystal is sliced, for example, by a wire saw, to prepare silicon carbide substrate 10.

[0088] FIG. 8 is a cross-sectional schematic view showing the step (S10) of preparing a silicon carbide substrate. As shown in FIG. 8 , silicon carbide substrate 10 has second main surface 2 and third main surface 3. Third main surface 3 is opposite to second main surface 2. Third main surface 3 is a surface inclined with respect to the {0001} plane. The inclination angle (off angle θ) of third main surface 3 with respect to the {0001} plane is, for example, 1° or more and 8° or less. Silicon carbide substrate 10 has a diameter of, for example, 150 mm or more. Silicon carbide substrate 10 has a thickness (third thickness T3) of, for example, 200 μm or more and 600 μm or less. Silicon carbide substrate 10 has a plurality of basal plane dislocations 30.

[0089] Next, a step (S20) of hydrogen etching the silicon carbide substrate is performed. Silicon carbide substrate 10 is placed on susceptor 210. Next, reaction chamber 201 is depressurized. Specifically, the pressure in reaction chamber 201 is reduced from atmospheric pressure to, for example, 1×10 －２ The pressure is reduced to about Pa. Next, the temperature inside the reaction chamber 201 starts to rise. Specifically, the temperature inside the reaction chamber 201 is raised from the standby temperature (for example, 600°C) of the reaction chamber 201 to a first temperature E1. The first temperature E1 is, for example, 1600°C or higher and 1700°C or lower. The first temperature E1 may be, for example, 1600°C or higher and 1620°C or lower. During the temperature rise, hydrogen (H ２ ) gas is introduced into the reaction chamber 201. During the temperature increase, silane gas is introduced into the reaction chamber 201 from the second gas supply unit 232.

[0090] 9 is a schematic diagram showing the change in temperature over time inside reaction chamber 201. As shown in FIG. 9, from first point in time C1 to second point in time C2, the temperature inside reaction chamber 201 is maintained at, for example, first temperature E1. First point in time C1 is, for example, the point in time when the temperature inside reaction chamber 201 reaches first temperature E1. From first point in time C1 to second point in time C2, the pressure inside reaction chamber 201 is set to, for example, 1 kPa or more and 10 kPa or less.

[0091] FIG. 10 is a schematic diagram showing the time variations of the flow rates of hydrogen gas and silane gas. In FIG. 10 , the flow rate of silane gas is indicated by a dashed line. As shown in FIG. 10 , the flow rate of hydrogen gas (hydrogen flow rate) is maintained at a first flow rate B1 from a first point in time C1 to a second point in time C2. The first flow rate B1 is, for example, 150 slm. The flow rate of silane gas (silane flow rate) is maintained at a second flow rate B2 from the first point in time C1 to the second point in time C2. The second flow rate B2 is, for example, 35 sccm or more and 40 sccm or less. As described above, hydrogen etching is performed on the third main surface 3 of the silicon carbide substrate 10 from the first point in time C1 to the second point in time C2. This allows foreign matter adhering to the third main surface 3 to be removed. As a result, the surface roughness of the third main surface 3 can be reduced.

[0092] In the step (S20) of hydrogen etching the silicon carbide substrate, if first temperature E1 is excessively high, third main surface 3 is etched excessively. In this case, the surface roughness of third main surface 3 becomes excessively large. On the other hand, if first temperature E1 is excessively low, foreign matter adhering to third main surface 3 may not be removed before the step (S20) of hydrogen etching the silicon carbide substrate. As a result, the surface roughness of third main surface 3 becomes excessively large. According to the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment, first temperature E1 is, for example, 1600°C or higher and 1700°C or lower. As a result, the surface roughness of third main surface 3 can be reduced. First temperature E1 may be, for example, 1600°C or higher and 1620°C or lower. This allows the surface roughness of third main surface 3 to be more effectively reduced.

[0093] In the step (S20) of hydrogen etching the silicon carbide substrate, silane gas is supplied, causing the supplied silane to react with carbon constituting reaction chamber 201. As a result, a silicon carbide layer is deposited on third main surface 3 while hydrogen etching is being performed, thereby further reducing the surface roughness of third main surface 3.

[0094] Next, a step (S30) of lowering the temperature inside the reaction chamber is performed. As shown in Fig. 9 , from second point C2 to third point C3, the temperature inside reaction chamber 201 is lowered from first temperature E1 to second temperature E2. Second temperature E2 is, for example, 1550°C or higher and 1560°C or lower. The time from second point C2 to third point C3 is, for example, 5 minutes or higher and 10 minutes or lower.

[0095] As shown in Figure 10, at second point C2, the supply of silane gas is stopped. As a result, the silane flow rate decreases from second flow rate B2 to 0 sccm within approximately one second from second point C2. From the point at which the silane flow rate decreases to 0 sccm until third point C3, the silane flow rate is maintained at 0 sccm. From second point C2 to third point C3, the flow rate of hydrogen gas gradually decreases. From second point C2 to third point C3, the flow rate of hydrogen gas decreases from first flow rate B1 to fourth flow rate B4. The fourth flow rate B4 is, for example, 130 slm.

[0096] Next, the step (S40) of forming a buffer layer on the silicon carbide substrate is performed. FIG. 11 is a cross-sectional schematic view showing the step (S40) of forming a buffer layer on the silicon carbide substrate. As shown in FIG. 11 , buffer layer 41 is formed on third main surface 3 of silicon carbide substrate 10. Specifically, at third point C3, supply of source gas and dopant gas to reaction chamber 201 is started. More specifically, for example, silane gas, propane gas, and ammonia gas start to be supplied to reaction chamber 201. As a result, a mixed gas containing, for example, silane, propane, ammonia, and hydrogen is introduced into reaction chamber 201. In reaction chamber 201, each gas is thermally decomposed.

[0097] 10, from the third point C3 to the fourth point C4, the silane flow rate increases from 0 sccm to the third flow rate B3. The time from the third point C3 to the fourth point C4 is, for example, 1 second. From the fourth point C4 to the fifth point C5, the silane flow rate is maintained at the third flow rate B3. From the third point C3 to the fifth point C5, the hydrogen flow rate is maintained at the fourth flow rate B4. As shown in FIG. 9, from the third point C3 to the fifth point C5, the temperature inside the reaction chamber 201 is maintained at the second temperature E2.

[0098] Between the fourth point C4 and the fifth point C5, the flow rates of silane and propane are controlled so that the C / Si ratio is 1.0 or more and 1.1 or less. The C / Si ratio is the ratio of the number of carbon (C) atoms in the first gas (propane gas) introduced into the reaction chamber 201 to the number of silicon (Si) atoms in the second gas (silane gas) introduced into the reaction chamber 201. The flow rate of ammonia is, for example, 10 sccm or more and 500 sccm or less.

[0099] From third point C3 to fifth point C5, the pressure inside reaction chamber 201 is maintained at, for example, 2 kPa or more and 6 kPa or less. As a result, buffer layer 41 is formed on silicon carbide substrate 10 as shown in FIG. 11 . Some of the plurality of basal plane dislocations 30 in silicon carbide substrate 10 may be inherited by buffer layer 41. From another perspective, second basal plane dislocations 32 may be formed in the step (S40) of forming a buffer layer on the silicon carbide substrate. At least some of the plurality of basal plane dislocations 30 in silicon carbide substrate 10 are converted into second threading edge dislocations 69 in buffer layer 41. In buffer layer 41, basal plane dislocations 30 converted into second threading edge dislocations 69 are third basal plane dislocations 33.

[0100] In the step (S40) of forming a buffer layer on a silicon carbide substrate, if second temperature E2 is excessively high, the energy applied to silicon carbide substrate 10 becomes excessively large. In this case, multiple basal plane dislocations 30 are likely to be inherited by buffer layer 41. As a result, the number of second basal plane dislocations 32 increases. On the other hand, if second temperature E2 is excessively low, buffer layer 41 having a 4H polytype may not be formed. According to the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment, second temperature E2 is 1550°C or higher and 1560°C or lower. This makes it possible to form buffer layer 41 having a 4H polytype while suppressing an increase in the number of second basal plane dislocations 32.

[0101] In the step (S40) of forming a buffer layer on a silicon carbide substrate, if the silane flow rate is excessively high, the growth rate of buffer layer 41 becomes excessively fast. In this case, multiple basal plane dislocations 30 are likely to be inherited by buffer layer 41. As a result, the number of second basal plane dislocations 32 increases. On the other hand, if the silane flow rate is excessively low, buffer layer 41 having a 4H polytype may not be formed. According to the method for manufacturing silicon carbide epitaxial substrate 100 of this embodiment, second flow rate B2 is, for example, 35 sccm or more and 40 sccm or less. This makes it possible to form buffer layer 41 having a 4H polytype while suppressing an increase in the number of second basal plane dislocations 32.

[0102] If the surface of third main surface 3 is excessively rough, multiple basal plane dislocations 30 are likely to be inherited by buffer layer 41. In other words, the density of basal plane dislocations 30 increases in buffer layer 41. According to the method for manufacturing silicon carbide epitaxial substrate 100 according to this embodiment, the surface roughness of third main surface 3 is reduced in the step (S20) of hydrogen etching the silicon carbide substrate. This makes it possible to suppress an increase in the density of basal plane dislocations 30 in buffer layer 41.

[0103] Next, the step (S50) of forming a drift layer on the buffer layer is performed. In the step (S50) of forming a drift layer on the buffer layer, the C / Si ratio is, for example, 1.25 or more and 1.35 or less. In the step (S50) of forming a drift layer on the buffer layer, the flow rate of the first gas (propane gas) is, for example, 40 sccm. The flow rate of the second gas (silane gas) is, for example, 100 sccm. The flow rate of the third gas (ammonia gas) is, for example, 0.2 sccm. The flow rate of the fourth gas (hydrogen gas) is, for example, 150 slm. In the step (S50) of forming a drift layer on the buffer layer, the temperature inside the reaction chamber 201 is, for example, 1600° C. The pressure inside the reaction chamber 201 is, for example, 2 kPa or more and 6 kPa or less.

[0104] In this manner, drift layer 42 is formed on buffer layer 41. Some of second basal plane dislocations 32 may be inherited by drift layer 42. From another perspective, first basal plane dislocations 31 may be formed in the step (S50) of forming a drift layer on the buffer layer. At least some of the multiple basal plane dislocations 30 are converted into first threading edge dislocations 68 in drift layer 42. In drift layer 42, basal plane dislocations 30 converted into first threading edge dislocations 68 become second basal plane dislocations 32. The concentration of n-type impurities in buffer layer 41 is higher than the concentration of n-type impurities in drift layer 42. In this manner, silicon carbide epitaxial substrate 100 (see FIGS. 1 and 2 ) according to this embodiment is manufactured.

[0105] (Method of Manufacturing Silicon Carbide Semiconductor Device) Next, a method of manufacturing silicon carbide semiconductor device 400 according to this embodiment will be described. Fig. 12 is a flowchart that schematically shows the method of manufacturing silicon carbide semiconductor device 400 according to this embodiment. As shown in Fig. 12, the method of manufacturing silicon carbide semiconductor device 400 according to this embodiment mainly includes a step (S1) of preparing a silicon carbide epitaxial substrate and a step (S2) of forming an electrode on the silicon carbide epitaxial substrate.

[0106] First, there is performed a step (S1) of preparing silicon carbide epitaxial substrate 100. Fig. 13 is a cross-sectional view schematically showing the step (S1) of preparing silicon carbide epitaxial substrate 100. As shown in Fig. 13, silicon carbide epitaxial substrate 100 according to the present embodiment is prepared.

[0107] Next, a step (S2) of forming an electrode on silicon carbide epitaxial substrate is performed. Specifically, the following processing is performed on silicon carbide epitaxial substrate 100. First, ions are implanted into silicon carbide epitaxial substrate 100.

[0108] 14 is a schematic cross-sectional view showing a step of forming a body region. In the step of forming the body region, p-type impurities such as aluminum are ion-implanted into second main surface 2 of silicon carbide epitaxial layer 20. This forms body region 113 having p-type conductivity. Portions where body region 113 is not formed become drift layer 42 and buffer layer 41. The thickness of body region 113 is, for example, 0.9 μm. Silicon carbide epitaxial layer 20 includes buffer layer 41, drift layer 42, and body region 113.

[0109] Next, a step of forming a source region is performed. FIG. 15 is a schematic cross-sectional view showing the step of forming the source region. Specifically, n-type impurities such as phosphorus are ion-implanted into the body region 113. This forms a source region 114 having n-type conductivity. The thickness of the source region 114 is, for example, 0.4 μm. The concentration of the n-type impurities in the source region 114 is higher than the concentration of the p-type impurities in the body region 113.

[0110] Next, a p-type impurity such as aluminum is ion-implanted into the source region 114 to form a contact region 118. The contact region 118 is formed to penetrate the source region 114 and the body region 113 and to be in contact with the drift layer 42. The concentration of the p-type impurity in the contact region 118 is higher than the concentration of the n-type impurity in the source region 114.

[0111] Next, activation annealing is performed to activate the implanted impurities. The temperature of the activation annealing is, for example, 1500° C. or higher and 1900° C. or lower. The activation annealing time is, for example, about 30 minutes. The atmosphere of the activation annealing is, for example, an argon atmosphere.

[0112] Next, a step of forming trenches in first main surface 1 of silicon carbide epitaxial layer 20 is carried out. FIG. 16 is a cross-sectional schematic diagram showing the step of forming trenches in first main surface 1 of silicon carbide epitaxial layer 20. A mask 117 having openings is formed on first main surface 1 configured from source region 114 and contact region 118. Using mask 117, source region 114, body region 113, and part of drift layer 42 are removed by etching. As an etching method, for example, inductively coupled plasma reactive ion etching can be used. Specifically, for example, SF is used as a reactive gas. ６ or science fiction ６ and O ２ The etching is performed by inductively coupled plasma reactive ion etching using a mixed gas of SiO 2 and SiO 2 . The etching forms a recess in the first main surface 1 .

[0113] Next, thermal etching is performed on the recesses. The thermal etching can be performed, for example, by heating the first main surface 1 with the mask 117 formed thereon in an atmosphere containing a reactive gas having at least one type of halogen atom. The at least one type of halogen atom contains at least one of chlorine (Cl) atoms and fluorine (F) atoms. The atmosphere can be, for example, Cl ２ , BCl ３ , S.F. ６ or CF ４ For example, a mixed gas of chlorine gas and oxygen gas is used as the reactive gas, and thermal etching is performed at a heat treatment temperature of, for example, 700°C or higher and 1000°C or lower. The reactive gas may contain a carrier gas in addition to the above-mentioned chlorine gas and oxygen gas. The carrier gas may be, for example, nitrogen gas, argon gas, or helium gas.

[0114] 16 , a trench 56 is formed in the first main surface 1 by thermal etching. The trench 56 is defined by a sidewall surface 53 and a bottom wall surface 54. The sidewall surface 53 is formed by the source region 114, the body region 113, and the drift layer 42. The bottom wall surface 54 is formed by the drift layer 42. Next, the mask 117 is removed from the first main surface 1.

[0115] Next, a step of forming a gate insulating film is performed. FIG. 17 is a schematic cross-sectional view showing the step of forming a gate insulating film. Specifically, silicon carbide epitaxial substrate 100 having trench 56 formed in first main surface 1 is heated in an oxygen-containing atmosphere at a temperature of, for example, 1300° C. or higher and 1400° C. or lower. This forms gate insulating film 115 that is in contact with drift layer 42 at bottom wall surface 54, in contact with drift layer 42, body region 113, and source region 114 at sidewall surface 53, and in contact with source region 114 and contact region 118 at first main surface 1.

[0116] Next, a step of forming a gate electrode is performed. FIG. 18 is a schematic cross-sectional view showing the step of forming a gate electrode and an interlayer insulating film. The gate electrode 127 is formed inside the trench 56 so as to be in contact with the gate insulating film 115. The gate electrode 127 is disposed inside the trench 56 and is formed on the gate insulating film 115 so as to face each of the sidewall surface 53 and the bottom wall surface 54 of the trench 56. The gate electrode 127 is formed by, for example, a low pressure chemical vapor deposition (LPCVD) method.

[0117] Next, an interlayer insulating film 126 is formed. The interlayer insulating film 126 is formed so as to cover the gate electrode 127 and to be in contact with the gate insulating film 115. The interlayer insulating film 126 is formed by, for example, chemical vapor deposition. The interlayer insulating film 126 is made of, for example, a material containing silicon dioxide. Next, the interlayer insulating film 126 and part of the gate insulating film 115 are etched so as to form openings over the source region 114 and the contact region 118. As a result, the contact region 118 and the source region 114 are exposed from the gate insulating film 115.

[0118] Next, a step of forming a source electrode is performed. The source electrode 116 is formed so as to be in contact with each of the source region 114 and the contact region 118. The source electrode 116 is formed by, for example, a sputtering method. The source electrode 116 is made of a material containing, for example, Ti (titanium), Al (aluminum), and Si (silicon).

[0119] Next, alloying annealing is performed. Specifically, the source electrode 116 in contact with each of the source region 114 and the contact region 118 is maintained at a temperature of, for example, 900° C. or higher and 1100° C. or lower for about 5 minutes. As a result, at least a portion of the source electrode 116 is silicided. This forms the source electrode 116 in ohmic contact with the source region 114. The source electrode 116 may also form an ohmic contact with the contact region 118.

[0120] Next, the source wiring 119 is formed. The source wiring 119 is electrically connected to the source electrode 116. The source wiring 119 is formed so as to cover the source electrode 116 and the interlayer insulating film 126.

[0121] Next, a step of forming a drain electrode is carried out. First, silicon carbide substrate 10 is polished at second main surface 2. This reduces the thickness of silicon carbide substrate 10. Next, drain electrode 123 is formed. Drain electrode 123 is formed so as to be in contact with second main surface 2. In this manner, silicon carbide semiconductor device 400 according to this embodiment is manufactured.

[0122] 19 is a cross-sectional schematic diagram showing the configuration of a silicon carbide semiconductor device 400 according to this embodiment. The silicon carbide semiconductor device 400 is, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The silicon carbide semiconductor device 400 mainly includes a silicon carbide epitaxial substrate 100, a gate electrode 127, a gate insulating film 115, a source electrode 116, a drain electrode 123, a source wiring 119, and an interlayer insulating film 126. The silicon carbide epitaxial substrate 100 includes a buffer layer 41, a drift layer 42, a body region 113, a source region 114, and a contact region 118. Silicon carbide semiconductor device 400 may be, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0123] Next, silicon carbide epitaxial substrate 100 according to this embodiment, a method for manufacturing silicon carbide semiconductor device 400, and the effects of silicon carbide semiconductor device 400 will be described.

[0124] When a forward current flows in a semiconductor device such as a MOSFET or an IGBT, basal plane dislocations 30 may expand while forming Shockley stacking faults. It is believed that Shockley stacking faults are formed by the injection of holes into the basal plane dislocations 30. The stacking faults expand as the forward current flows. The stacking faults degrade the forward characteristics (on-state voltage) of the semiconductor device. Therefore, the stacking faults reduce the reliability of the semiconductor device.

[0125] In order to suppress deterioration of the reliability of a semiconductor device, the semiconductor device may be manufactured using a silicon carbide epitaxial substrate 100 having a low density of basal plane dislocations 30 in the drift layer 42. In this case, it is believed that the recombination of holes and electrons before the holes are injected into the basal plane dislocations 30 can suppress the formation of stacking faults. However, even when a semiconductor device is manufactured using a silicon carbide epitaxial substrate 100 having a low density of basal plane dislocations 30 in the drift layer 42, the reliability of the semiconductor device may deteriorate. The inventors have conducted extensive research into measures to suppress deterioration of the reliability of semiconductor devices, and have arrived at the following findings.

[0126] First, the inventors focused on the density of basal plane dislocations 30 in buffer layer 41. Photoluminescence measurement is sometimes used to measure the density of basal plane dislocations 30 in drift layer 42. However, with conventional photoluminescence measurement, it has been difficult to identify basal plane dislocations 30 in buffer layer 41. As a result of extensive research, the inventors discovered that it is possible to identify basal plane dislocations 30 in buffer layer 41 by optimizing the transmission wavelength range of the light-receiving filter in the photoluminescence imaging device and the irradiation time of excitation light irradiated on silicon carbide epitaxial substrate 100.

[0127] Second, the inventors have found that even when the density of basal plane dislocations 30 in drift layer 42 is sufficiently reduced, the reliability of the semiconductor device deteriorates if the density of basal plane dislocations 30 in buffer layer 41 is excessively high. When a forward current flows in the semiconductor device, holes may be injected into basal plane dislocations 30 in buffer layer 41 before holes and electrons recombine. In this case, it is believed that stacking faults are formed as a result of the expansion of basal plane dislocations 30 in buffer layer 41.

[0128] In silicon carbide epitaxial substrate 100 according to this embodiment, the density (second density) of basal plane dislocations 30 in buffer layer 41 is 10 / cm ２This is as follows. Therefore, it is possible to prevent the density of basal plane dislocations 30 in buffer layer 41 from becoming excessively high. This makes it possible to prevent deterioration of the forward characteristics in silicon carbide semiconductor device 400 manufactured using silicon carbide epitaxial substrate 100 according to this embodiment. As a result, it is possible to prevent deterioration in the reliability of silicon carbide semiconductor device 400.

[0129] In the silicon carbide epitaxial substrate 100 according to this embodiment, the density (first density) of basal plane dislocations 30 in the drift layer 42 is 1 / cm ２ This is as follows. Therefore, it is possible to prevent the density of basal plane dislocations 30 in drift layer 42 from becoming excessively high. This makes it possible to prevent deterioration of the forward characteristics in silicon carbide semiconductor device 400 manufactured using silicon carbide epitaxial substrate 100 according to this embodiment. As a result, it is possible to prevent deterioration in the reliability of silicon carbide semiconductor device 400.

[0130] If the thickness of buffer layer 41 is excessively thin, holes may be injected into basal plane dislocations 30 in silicon carbide substrate 10 when a forward current flows in silicon carbide semiconductor device 400. In this case, the forward characteristics of silicon carbide semiconductor device 400 deteriorate. In silicon carbide epitaxial substrate 100 according to this embodiment, buffer layer 41 has a thickness (first thickness T1) of 0.5 μm or more. This makes it possible to suppress holes from being injected into basal plane dislocations 30 in silicon carbide substrate 10. This makes it possible to suppress deterioration in the reliability of silicon carbide semiconductor device 400.

[0131] According to the method for manufacturing silicon carbide semiconductor device 400 in accordance with the present embodiment, the above-described silicon carbide epitaxial substrate 100 is prepared. An electrode (gate electrode 127) is formed on silicon carbide epitaxial substrate 100. This makes it possible to suppress deterioration in the reliability of silicon carbide semiconductor device 400.

[0132] Silicon carbide semiconductor device 400 according to the present embodiment has silicon carbide epitaxial substrate 100 described above, and an electrode (gate electrode 127) provided on silicon carbide epitaxial substrate 100. This makes it possible to suppress deterioration in the reliability of silicon carbide semiconductor device 400.

[0133] (Sample Preparation) Silicon carbide epitaxial substrates 100 according to Samples 1 to 11 were prepared. Silicon carbide epitaxial substrates 100 according to Samples 1 to 4 are comparative examples. Silicon carbide epitaxial substrates 100 according to Samples 5 to 11 are examples.

[0134] Silicon carbide epitaxial substrates 100 according to Samples 1 to 11 were manufactured in accordance with the above-described method for manufacturing silicon carbide epitaxial substrate 100. Specifically, silicon carbide epitaxial substrates 100 according to Samples 1 to 11 were manufactured using the conditions in Table 1 below.

[0135]

[0136] Table 1 shows the manufacturing conditions for silicon carbide epitaxial substrates 100 according to Samples 1 to 11. As shown in Table 1, in manufacturing silicon carbide epitaxial substrates 100 according to Samples 1 to 4, first temperature E1 was set to 1640° C. or higher and 1660° C. or lower. In manufacturing silicon carbide epitaxial substrates 100 according to Samples 5 to 11, first temperature E1 was set to 1600° C. or higher and 1620° C. or lower.

[0137] Second flow rate B2 was set to 0 sccm in the manufacture of silicon carbide epitaxial substrates 100 according to Samples 1 to 4. In other words, silane gas was not supplied in the step (S20) of hydrogen etching the silicon carbide substrate in the manufacture of silicon carbide epitaxial substrates 100 according to Samples 1 to 4. Second flow rate B2 was set to 10 sccm in the manufacture of silicon carbide epitaxial substrates 100 according to Samples 5 to 11.

[0138] In manufacturing silicon carbide epitaxial substrates 100 according to Samples 1 to 4, second temperature E2 was set to 1610° C. or higher and 1630° C. or lower. In manufacturing silicon carbide epitaxial substrates 100 according to Samples 5 to 11, second temperature E2 was set to 1550° C. or higher and 1560° C. or lower.

[0139] In the manufacture of silicon carbide epitaxial substrates 100 according to Samples 1 to 4, third flow rate B3 was set to 40 sccm or more and 45 sccm or less. In the manufacture of silicon carbide epitaxial substrates 100 according to Samples 5 to 11, third flow rate B3 was set to 35 sccm or more and 40 sccm or less.

[0140] In the manufacture of silicon carbide epitaxial substrates 100 according to Samples 1 to 4, the C / Si ratio was set to 0.95. In the manufacture of silicon carbide epitaxial substrates 100 according to Samples 5 to 11, the C / Si ratio was set to 1.0 or more and 1.1 or less.

[0141] In the manufacture of silicon carbide epitaxial substrates 100 according to Samples 1 to 11, the first flow rate B1 was set to 150 slm. The fourth flow rate B4 was set to 130 slm. In the manufacture of silicon carbide epitaxial substrates 100 according to Samples 1 to 11, the third density was set to 100 particles / cm. ２ More than 2000 pieces / cm ２ A silicon carbide substrate 10 having the following structure was used.

[0142] (Evaluation Method) Using the above-described method for measuring the first density and the second density, the density of basal plane dislocations 30 in buffer layer 41 (second density), the density of basal plane dislocations 30 in drift layer 42 (first density), and the value obtained by dividing the second density by the first density (first value) were measured for silicon carbide epitaxial substrates 100 according to samples 1 to 11.

[0143] A photoluminescence imaging device (model number: PLI-200) manufactured by Photon Design Inc. was used to measure each of the first density and the second density. Excitation light was irradiated onto first main surface 1 of silicon carbide epitaxial substrate 100. As a result, photoluminescence light was generated from silicon carbide epitaxial substrate 100. The photoluminescence light was detected by a color image sensor. The wavelength of the excitation light was 313 nm. The intensity of the excitation light was 0.1 mW / cm. ２ More than 2W / cm ２ The irradiation time of the excitation light was 5 seconds, and the transmission wavelength range of the light receiving filter was 390 nm or more.

[0144] A photoluminescence image was taken of each of the plurality of square regions 50 on the first main surface 1. The length of one side of each of the plurality of square regions 50 (first length A1) was set to 0.51 cm. The area of ​​each of the plurality of square regions 50 was set to 0.26 cm. ２ Based on the captured photoluminescence images, the number of first basal plane dislocations 31 and the number of second basal plane dislocations 32 were measured in each of the plurality of square regions 50.

[0145] In each of the plurality of square regions 50, the density of the first basal plane dislocations 31 was calculated by dividing the number of first basal plane dislocations 31 by the area of ​​the square region 50. In each of the plurality of square regions 50, the density of the second basal plane dislocations 32 was calculated by dividing the number of second basal plane dislocations 32 by the area of ​​the square region 50. The average value of the densities of the first basal plane dislocations 31 in all of the square regions 50 was determined as the first density. The sum of the densities of the first basal plane dislocations 31 and the second basal plane dislocations 32 in all of the square regions 50 was calculated. The average value of this sum in all of the square regions 50 was determined as the second density.

[0146] (Evaluation results)

[0147]

[0148] Table 2 shows the second density, the first density, and the value (first value) obtained by dividing the first density by the second density in silicon carbide epitaxial substrates 100 according to Samples 1 to 11. As shown in Table 2, in silicon carbide epitaxial substrates 100 according to Samples 1 to 4, the second density was 24 particles / cm ２ In silicon carbide epitaxial substrates 100 according to samples 5 to 11, the second density was 2 particles / cm ２ It was as follows.

[0149] As shown in Table 2, in silicon carbide epitaxial substrates 100 according to Samples 1 to 4, the value (first value) obtained by dividing the second density by the first density was greater than 100. In silicon carbide epitaxial substrates 100 according to Samples 5, 6, and 11, the value (first value) obtained by dividing the second density by the first density was 30 or less. In silicon carbide epitaxial substrate 100 according to Sample 7, the first density was 0 particles / cm ２ Therefore, the first value was not calculated.

[0150] As described above, it was confirmed that the method for manufacturing silicon carbide epitaxial substrate 100 according to the example can reduce the second density compared to the method for manufacturing silicon carbide epitaxial substrate 100 according to the comparative example.

[0151] (Sample Preparation) Next, an evaluation was carried out on the method for identifying basal plane dislocations 30. Specifically, a silicon carbide epitaxial substrate 100 according to Sample 12 was prepared. The silicon carbide epitaxial substrate 100 according to Sample 12 is the silicon carbide epitaxial substrate 100 according to this embodiment (see FIGS. 1 and 2 ).

[0152] (Evaluation Method) For silicon carbide epitaxial substrate 100 according to Sample 12, a photoluminescence imaging device (model number: PLI-200) manufactured by Photon Design Inc. was used to acquire a photoluminescence image of first main surface 1 of silicon carbide epitaxial substrate 100 according to Sample 12. Specifically, a photoluminescence image according to a comparative example and a photoluminescence image according to an example were acquired.

[0153] The photoluminescence images were acquired according to the above-described method for measuring the first and second densities. In acquiring the photoluminescence images of the comparative example, the transmission wavelength range of the light receiving filter was set to 750 nm or more. The irradiation time of the excitation light LE was set to 1 second. In acquiring the photoluminescence images of the example, the transmission wavelength range of the light receiving filter was set to 390 nm or more. The irradiation time of the excitation light LE was set to 5 seconds.

[0154] (Evaluation Results) Fig. 20 is a first photoluminescence image according to a comparative example. Fig. 21 is a first photoluminescence image according to an example. The photoluminescence image shown in Fig. 20 and the photoluminescence image shown in Fig. 21 are images showing substantially the same portion of first main surface 1 of silicon carbide epitaxial substrate 100 according to sample 12.

[0155] As shown in Figure 20, in the first photoluminescence image of the comparative example, the third portion 63 of the basal plane dislocation 30 appears brighter (whiter) than the area other than the third portion 63. In the first photoluminescence image of the comparative example, the second portion 62 is not displayed. As shown in Figure 21, in the first photoluminescence image of the example, the second portion 62 and the third portion 63 of the basal plane dislocation 30 appear darker (blacker) than the area other than the basal plane dislocation 30. In the first photoluminescence image of the example, the third portion 63 appears darker (blacker) than the second portion 62.

[0156] Fig. 22 is a second photoluminescence image according to a comparative example. Fig. 23 is a second photoluminescence image according to an example. The photoluminescence image shown in Fig. 22 and the photoluminescence image shown in Fig. 23 are images showing substantially the same portion of first main surface 1 of silicon carbide epitaxial substrate 100 according to sample 12.

[0157] As shown in Fig. 22, the second photoluminescence image of the comparative example does not show the basal plane dislocations 30. As shown in Fig. 23, in the second photoluminescence image of the example, the second portions 62 of the basal plane dislocations 30 appear darker (blacker) than the region other than the basal plane dislocations 30.

[0158] As described above, it was confirmed that the method for identifying basal plane dislocations 30 according to the example can identify second basal plane dislocations 32.

[0159] The embodiments and examples disclosed herein are illustrative in all respects and should not be considered limiting. The scope of the present invention is defined by the claims, not by the embodiments and examples described above, and is intended to include any modifications within the scope of the claims that are equivalent to the claims.

[0160] 1 First main surface (main surface), 2 Second main surface, 3 Third main surface, 5 Outer peripheral side surface, 6 Orientation flat, 7 Arc-shaped portion, 8 Outer peripheral edge, 9 Interface, 10 Silicon carbide substrate, 11 Outer peripheral region, 12 Central region, 20 Silicon carbide epitaxial layer, 30 Basal plane dislocation, 31 First basal plane dislocation, 32 Second basal plane dislocation, 33 Third basal plane dislocation, 41 Buffer layer, 42 Drift layer, 50 Square region, 53 Side wall surface, 54 Bottom wall surface, 56 Trench, 61 First portion, 62 Second portion, 63 Third portion, 68 First threading edge dislocation, 69 Second threading edge dislocation, 91 First straight line, 92 Second straight line, 93 Third straight line, 100 Silicon carbide epitaxial substrate, 101 First direction, 102 Second direction, 103 Third direction, 113 Body region, 114 Source region, 115 Gate insulating film, 116 Source electrode, 117 Mask, 118 Contact region, 119 Source wiring, 123 Drain electrode, 126 Interlayer insulating film, 127 Gate electrode (electrode), 200 Photoluminescence imaging device, 201 Reaction chamber, 203 Heating element, 204 Quartz tube, 205 Inner wall surface, 206 Second stage, 207 Gas inlet, 208 Gas exhaust port, 209 Rotation shaft, 210 Susceptor, 220 Excitation light generation unit, 221 Light source section, 222 Light guide section, 223 Filter section, 230 Imaging unit, 231 First gas supply section, 232 Second gas supply section, 233 Third gas supply section, 234 Fourth gas supply section, 235 Gas supply section, 236 color image sensor, 237 near-infrared objective lens, 238 control unit, 239 first stage, 241 first gas flow rate control unit, 242 second gas flow rate control unit, 243 third gas flow rate control unit, 244 fourth gas flow rate control unit, 245 flow rate control unit, 250 manufacturing apparatus, 400 silicon carbide semiconductor device, A1 first length, A2 second length, A3 third length, B1 first flow rate, B2 second flow rate, B3 third flow rate, B4 fourth flow rate, C1 first point in time, C2 second point in time, C3 third point in time, C4 fourth point in time, C5 fifth point in time, E distance, E1 first temperature, E2 second temperature, H1 first width, H2 second width, LE excitation light, LL photoluminescence light, O center, T1 first thickness, T2 second thickness, T3 third thickness, W1 diameter, θ off angle.

Claims

1. Silicon carbide substrate and A buffer layer provided on the silicon carbide substrate, The buffer layer comprises a drift layer provided on the buffer layer, The density of basal plane dislocations in the buffer layer is 10 dislocations / cm³. ２ The following: The density of basal plane dislocations in the drift layer is 1 dislocation / cm³. ２ The following: A silicon carbide epitaxial substrate in which the ratio of the density of basal plane dislocations in the buffer layer to the density of basal plane dislocations in the drift layer is between 1 and 100.

2. Silicon carbide substrate and A buffer layer provided on the silicon carbide substrate, The buffer layer comprises a drift layer provided on the buffer layer, The density of basal plane dislocations in the buffer layer is 10 dislocations / cm³. ２ The following: The density of basal plane dislocations in the drift layer is 0 dislocations / cm³. ２ This is a silicon carbide epitaxial substrate.

3. The silicon carbide epitaxial substrate according to claim 1 or claim 2, wherein the thickness of the buffer layer is 0.5 μm or more and 10 μm or less.

4. The aforementioned drift layer constitutes the main surface, The silicon carbide epitaxial substrate according to claim 1 or claim 2, wherein the diameter of the main surface is 150 mm or more.

5. The silicon carbide epitaxial substrate according to claim 4, wherein the main surface is inclined with respect to the {0001} plane at an off-angle of 1° to 8°.

6. The density of basal plane dislocations in the buffer layer is 0.01 dislocations / cm³. ２ The silicon carbide epitaxial substrate according to claim 1 or claim 2.

7. A step of preparing a silicon carbide epitaxial substrate according to claim 1 or claim 2, A method for manufacturing a silicon carbide semiconductor device, comprising the step of forming electrodes on the silicon carbide epitaxial substrate.

8. The silicon carbide epitaxial substrate according to claim 2, A silicon carbide semiconductor device comprising electrodes provided on the silicon carbide epitaxial substrate.