Power Conversion Equipment

Abstract

The power conversion device (100) includes a plurality of switching elements (Q) connected in series between a pair of first input / output terminals (T1, T2), a plurality of drive circuits (150), and at least one speed control circuit (120) connected to at least one of the plurality of switching elements (Q). Each switching element (Q) is turned on and off by a gate voltage applied to a gate terminal from the corresponding drive circuit (120). Each speed control circuit (120) includes a storage element (121) electrically connected between a first main terminal and a second main terminal of the corresponding switching element (Q), a rectifier element (122) connected between the first main terminal and the storage element (121) in a direction in which a current flows through the storage element (121), and a first resistance element (123) electrically connected between a connection point of the rectifier element (122) and the storage element (121) and the gate terminal of the corresponding switching element (Q).

Description

[Technical field]

[0001] The present disclosure relates to a power conversion device. [Background technology]

[0002] Japanese Patent Laid-Open Publication No. 2000-36731 (Patent Document 1) discloses a power converter in which power semiconductor switching elements (hereinafter also simply referred to as "switching elements") are connected in series to form a main circuit arm. The same gate signal is input to multiple switching elements connected in series, and the switching timing of each switching element is aligned, thereby realizing the high speed and high voltage rating of a low-voltage switching element.

[0003] However, in the above power conversion device, if there is variation in the switching timing of multiple switching elements due to characteristic variations in each switching element or gate driver, a "voltage imbalance" may occur in the multiple switching elements. "Voltage imbalance" refers to a situation in which voltage is not evenly borne by multiple switching elements Q connected in series, resulting in an imbalance in the output voltages of the switching elements Q. Voltage imbalance may lead to voltage breakdown of the switching elements.

[0004] The power conversion device described in Patent Document 1 includes a correction circuit that corrects the voltage imbalance by adjusting the delay time of a gate signal applied to each switching element. The correction circuit has a delay time generating circuit that delays the gate signal applied to each switching element, and a delay time controller that adjusts the delay time of the next gate signal of each delay time generating circuit. The delay time controller detects the output voltage of each switching element in the off state, and is configured to increase the delay time of the next gate signal of the delay generating circuit for a switching element whose voltage difference with the switching element having the lowest output voltage is equal to or greater than a predetermined value. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2000-36731 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, in the case of switching elements that are driven at high speed, such as SiC (silicon carbide) or GaN (gallium nitride), it is difficult to detect the output voltage of the switching element by the above-mentioned correction circuit and adjust the delay time of the gate signal applied to the switching element quickly and with high accuracy. In this way, the power conversion device described in Patent Document 1 has a problem that the voltage balance cannot be appropriately suppressed depending on the characteristics of the switching element. Therefore, when designing the power conversion device, a high safety factor must be taken and each switching element must be made to withstand a higher voltage than necessary. There is a concern that the high withstand voltage of the switching elements will increase the power loss (switching loss and conduction loss) generated in the switching elements.

[0007] The present disclosure has been made to solve such problems, and its main objective is to provide a power conversion device that can reliably suppress voltage imbalance among multiple switching elements connected in series. [Means for solving the problem]

[0008] A power conversion device according to an aspect of the present disclosure includes a pair of first input / output terminals to which a first voltage is applied, a plurality of switching elements connected in series between the pair of first input / output terminals, a plurality of drive circuits for controlling the on / off of each of the plurality of switching elements, and at least one speed control circuit connected to at least one of the plurality of switching elements. Each of the plurality of switching elements has a gate terminal, a first main terminal on a high potential side, a second main terminal on a low potential side, and a diode connected in anti-parallel between the first main terminal and the second main terminal. Each switching element is turned on and off by a gate voltage applied to the gate terminal from a corresponding drive circuit. Each speed control circuit includes a storage element electrically connected between the first main terminal and the second main terminal of the corresponding switching element, a rectifying element connected between the first main terminal and the storage element in a direction in which a current flows through the storage element, and a first resistance element electrically connected between a connection point of the rectifying element and the storage element and a gate terminal of the corresponding switching element. Effect of the Invention

[0009] According to the present disclosure, it is possible to provide a power conversion device that can reliably suppress voltage imbalance among a plurality of switching elements connected in series. [Brief description of the drawings]

[0010] [Figure 1] 1 is a main circuit configuration diagram of a power conversion device according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing a configuration example of a speed regulator circuit. [Diagram 3] FIG. 13 is a diagram illustrating an increase in gate voltage caused by a speed regulator circuit. [Figure 4] FIG. 11 is a main circuit configuration diagram of a power conversion device according to a first modified example of the first embodiment. [Diagram 5] FIG. 11 is a main circuit configuration diagram of a power conversion device according to a second modification of the first embodiment. [Figure 6] FIG. 11 is a main circuit configuration diagram of a power conversion device according to a second embodiment. [Figure 7]FIG. 2 is a diagram illustrating a current path when only a switching element Q1 is on. [Figure 8] FIG. 13 is a diagram illustrating a current path when only a switching element Q2 is on. [Figure 9] FIG. 11 is a main circuit configuration diagram of a power conversion device according to a first modified example of the second embodiment. [Figure 10] FIG. 11 is a main circuit configuration diagram of a power conversion device according to a second modification of the second embodiment. [Figure 11] FIG. 4 is a diagram showing a first modified example of the speed regulator circuit. [Figure 12] FIG. 11 is a diagram showing a second modified example of the speed regulator circuit. [Figure 13] FIG. 13 is a diagram showing a third modified example of the speed regulator circuit. [Figure 14] FIG. 13 is a diagram showing a first modified example of a drive circuit. [Figure 15] FIG. 13 is a diagram showing a second modified example of the drive circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference characters, and their description will not be repeated in principle.

[0012] Embodiment 1 <Example of power conversion device configuration> 1 is a main circuit configuration diagram of a power conversion device according to a first embodiment of the present disclosure. A power conversion device 100 according to the first embodiment is a chopper circuit configured to perform bidirectional power conversion between a DC power source 1 and a DC power source 2.

[0013] The DC power supply 1 supplies DC power to the power conversion device 100. The DC power supply 1 can be configured from various sources, for example, a DC system, a solar cell, or a storage battery. Alternatively, the DC power supply 1 may be configured from a rectifier circuit or an AC / DC converter connected to an AC system. Alternatively, the DC power supply 1 may be configured from a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0014] The DC power supply 2 is driven by DC power supplied from the power conversion device 100. The DC power supply 2 is, for example, a load. The DC power supply 2 may be configured by a DC / AC converter that converts the DC power output from the power conversion device 100 into AC power and supplies it to the load.

[0015] The power conversion device 100 transmits power between a DC power supply 1 and a DC power supply 2. In one aspect, the power conversion device 100 steps down a voltage V1 input from the DC power supply 1 and outputs the voltage V1 to the DC power supply 2. In another aspect, the power conversion device 100 steps up a voltage V2 input from the DC power supply 2 and outputs the voltage V2 to the DC power supply 1.

[0016] As shown in FIG. 1, the power conversion device 100 includes a pair of input / output terminals T1, T2, a pair of input / output terminals T3, T4, positive electrode wires PL1, PL2, a negative electrode wire NL1, a DC link capacitor 101, a bridge circuit 110, a current control reactor 102, and a filter capacitor 103.

[0017] The pair of input / output terminals T1, T2 are connected to a DC power supply 1. A voltage V1 of the DC power supply 1 is applied to the pair of input / output terminals T1, T2. The pair of input / output terminals T3, T4 are connected to a DC power supply 2. A voltage V2 of the DC power supply 2 is applied to the pair of input / output terminals T3, T4. The pair of input / output terminals T1, T2 corresponds to one embodiment of a "pair of first input / output terminals". The pair of input / output terminals T3, T4 corresponds to one embodiment of a "pair of second input / output terminals".

[0018] The positive wire PL1 is connected to the input / output terminal T1. The negative wire NL1 is connected to the input / output terminals T2 and T4. The DC link capacitor 101 is connected between the positive wire PL1 and the negative wire NL1, and functions as a smoothing capacitor.

[0019] The bridge circuit 110 includes a plurality of (four in this embodiment) power semiconductor switching elements (hereinafter also simply referred to as “switching elements”) Q1 to Q4 and a plurality of (four in this embodiment) drive circuits (DC) 150.

[0020] The multiple switching elements Q1 to Q4 are connected in series between the positive electrode wire PL1 and the negative electrode wire NL1. In the following, when the switching elements Q1 to Q4 are not particularly distinguished from each other, they may be collectively referred to as "switching element Q." In FIG. 1, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as the switching element Q, but any voltage-driven semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) may be used.

[0021] The switching element Q has a drain which is a first main terminal on the high potential side, a source which is a second main terminal on the low potential side, a gate terminal which is a control terminal, and a diode connected in anti-parallel between the drain and source. Hereinafter, the voltage of the gate terminal with respect to the source (gate-source voltage) will be referred to as the "gate voltage Vgs", and the voltage of the drain with respect to the source (drain-source voltage) will be referred to as the "drain voltage Vds". The drain voltage Vds will also be referred to as the "output voltage".

[0022] The diode is a freewheel diode provided to pass a return current (freewheel current) when the corresponding switching element Q is off. If the switching element Q is a MOSFET, the diode may be configured as a parasitic diode (body diode). If the switching element Q is an IGBT that does not have a built-in diode, the diode is configured as a diode connected inversely parallel to the IGBT.

[0023] The drain of switching element Q1 is connected to the positive electrode wire PL1, and the source of switching element Q1 is connected to the drain of switching element Q2. The source of switching element Q2 is connected to node ND1. The drain of switching element Q3 is connected to node ND1, and the source of switching element Q3 is connected to the drain of switching element Q4. The source of switching element Q4 is connected to negative electrode wire NL1. That is, node ND1 corresponds to the connection point of switching element Q2 and switching element Q3.

[0024] In the bridge circuit 110, two switching elements Q1, Q2 connected in series between the positive electrode wire PL1 and the node ND1 constitute an "upper arm 112," and two switching elements Q3, Q4 connected in series between the node ND1 and the negative electrode wire NL1 constitute a "lower arm 114." The switching elements Q1, Q2 correspond to an embodiment of a "first switching element." The switching elements Q3, Q4 correspond to an embodiment of a "second switching element." In the example of FIG. 1, each arm is composed of two switching elements Q, but the number of switching elements Q constituting each arm may be two or more.

[0025] A first end of the current control reactor 102 is connected to the node ND1, and a second end of the current control reactor 102 is connected to the positive wire PL2. The positive wire PL2 is connected to the input / output terminal T3. That is, the pair of input / output terminals T3, T4 are electrically connected to both ends of the lower arm 114. In this specification, "electrically connected" refers to a direct connection or a connection state in which electrical energy can be transmitted by a connection via another element.

[0026] The filter capacitor 103 is connected between the positive electrode wire PL2 and the negative electrode wire NL1. The current control reactor 102 and the filter capacitor 103 form an LC filter.

[0027] The plurality of drive circuits 150 are provided corresponding to the plurality of switching elements Q1 to Q4, respectively. The plurality of drive circuits 150 are connected to the controller 104 so as to be able to communicate with each other.

[0028] The controller 104 includes a processing circuit (not shown) that executes a predetermined program. The processing circuit includes, for example, a CPU (Central Processing Unit), a memory, and an input / output interface. A program is stored in advance in a partial area of ​​the memory, and the CPU executes the program to control the operation of the power conversion device 100. The input / output interface inputs and outputs signals and data between the processing circuit and the outside.

[0029] Alternatively, at least a part of the processing circuitry can be configured using a circuit such as an FPGA (Field Programmable Gate Array) or an ASIC (Application Specific Integrated Circuit), etc. Alternatively, at least a part of the processing circuitry can be configured using an analog circuit.

[0030] Various signals including the terminal voltage of the DC link capacitor 101, the terminal voltage of the filter capacitor 103, and the detection value of the current flowing through the current control reactor 102 are input to the controller 104. Based on the various input signals, the controller 104 generates gate signals that are control signals for controlling the on / off of the multiple switching elements Q1 to Q4. Specifically, the controller 104 generates a gate signal of H (logical high) level during a period when the switching element Q should be on, and generates a gate signal of L (logical low) level during a period when the switching element Q should be off.

[0031] Each of the multiple drive circuits 150 drives the corresponding switching element Q in accordance with a gate signal provided from the controller 104, thereby controlling the on / off of the switching element Q. Specifically, each drive circuit 150 is configured to apply an on-gate voltage Vgon to the gate terminal of the corresponding switching element Q in response to an H-level gate signal, and to apply an off-gate voltage Vgoff to the gate terminal of the corresponding switching element Q in response to an L-level gate signal.

[0032] The on-gate voltage Vgon is set to a voltage that is sufficiently higher than the gate threshold voltage Vth of the switching element Q. The off-gate voltage Vgoff is set to a voltage that is lower than the gate threshold voltage Vth of the switching element Q. In addition, when the switching element Q is in the off state, the gate voltage Vgs is lower than the gate threshold voltage Vth of the switching element Q (Vgs <Vth)。

[0033] <Operation of power conversion device> Next, the operation of the power conversion device 100 shown in FIG. 1 will be described.

[0034] When transmitting power from the DC power source 1 to the DC power source 2, the power conversion device 100 steps down the DC voltage V1 input from the DC power source 1 to a pair of input / output terminals T1, T2, and outputs it to the DC power source 2 via a pair of input / output terminals T3, T4. In this case, the switching elements Q3, Q4 constituting the lower arm 114 of the bridge circuit 110 are fixed to the off state. The switching elements Q1, Q2 constituting the upper arm 112 of the bridge circuit 110 are synchronously controlled to be turned on and off by a gate signal from the controller 104.

[0035] Specifically, the gate signal is set to H level and L level at a constant frequency f. When the gate signal is set to H level, the switching elements Q1 and Q2 are turned on, and when the gate signal is set to L level, the switching elements Q1 and Q2 are turned off.

[0036] When the switching elements Q1 and Q2 are turned on, a current flows through a path from the positive wire PL1 to the negative wire NL1 via the switching elements Q1 and Q2, the current control reactor 102, and the DC power supply 2, and electric power is transmitted to the DC power supply 2 and electromagnetic energy is stored in the current control reactor 102. When the switching elements Q1 and Q2 are turned off, a current flows through a path from the second end of the current control reactor 102 to the first end of the current control reactor 102 via the DC power supply 2 and the diodes of the switching elements Q3 and Q4, and electric power is transmitted to the DC power supply 2 and electromagnetic energy of the current control reactor 102 is released. By adjusting the duty ratio, which is the ratio between the time that the gate signal is at the H level and one cycle (1 / f), it is possible to adjust the voltage between the terminals of the DC power supply 2 to a desired DC voltage.

[0037] When transmitting power from the DC power source 2 to the DC power source 1, the power conversion device 100 boosts the DC voltage V2 input from the DC power source 2 to a pair of input / output terminals T3, T4, and outputs the boosted voltage to the DC power source 1 via a pair of input / output terminals T1, T2. In this case, the switching elements Q1, Q2 constituting the upper arm 112 of the bridge circuit 110 are fixed to the off state. The switching elements Q3, Q4 constituting the lower arm 114 of the bridge circuit 110 are synchronously controlled to be turned on and off by a gate signal from the controller 104.

[0038] Specifically, the gate signal is set to H level and L level at a constant frequency f. When the gate signal is set to H level, the switching elements Q3 and Q4 are turned on, and when the gate signal is set to L level, the switching elements Q3 and Q4 are turned off.

[0039] When the switching elements Q3 and Q4 are turned on, a current flows through a path from the DC power supply 2 to the negative wire NL1 via the positive electrode wire PL2, the current control reactor 102, and the switching elements Q3 and Q4, and electromagnetic energy is stored in the current control reactor 102. When the switching elements Q3 and Q4 are turned off, the current flowing from the current control reactor 102 to the switching elements Q3 and Q4 is commutated from the current control reactor 102 to the diodes of the switching elements Q1 and Q2, and a current flows through the path from the positive electrode wire PL1 and the DC power supply 1 to the negative electrode wire NL1, transmitting power to the DC power supply 1 and discharging electromagnetic energy from the current control reactor 102. By adjusting the duty ratio of the gate signal, it is possible to adjust the voltage V1 of the DC power supply 1 to a desired DC voltage.

[0040] In this manner, by synchronously controlling the on / off of the switching elements Q1, Q2 constituting the upper arm 112 and synchronously controlling the on / off of the switching elements Q3, Q4 constituting the lower arm 114, the power conversion device 100 transmits power between the DC power sources 1 and 2. By configuring each of the upper arm 112 and the lower arm 114 with a plurality of switching elements Q connected in series, it is possible to realize a bridge circuit 110 having high withstand voltage characteristics using low withstand voltage switching elements.

[0041] However, on the other hand, by connecting multiple switching elements Q in series, a "voltage imbalance" may occur in the multiple switching elements Q due to differences in characteristics between the switching elements Q and the drive circuit 150. "Voltage imbalance" refers to a situation in which voltage is not evenly borne by the multiple switching elements Q connected in series, resulting in imbalance in the output voltages of the switching elements Q.

[0042] For example, if the timing of turning off the switching elements Q1 and Q2 constituting the upper arm 112 differs, causing the switching element Q1 to turn off first and the switching element Q2 to turn on, a high voltage will be applied only to the switching element Q1. If a voltage exceeding the element's withstand voltage is applied to the switching element Q1, there is a risk that the switching element Q1 will be destroyed.

[0043] In order to suppress such a voltage imbalance, in the first embodiment, a speed regulator circuit 120 is connected to at least one switching element Q of the multiple switching elements Q1 to Q4 connected in series. In the example of Fig. 1, the speed regulator circuit 120 is connected to all of the multiple switching elements Q1 to Q4.

[0044] The speed regulation circuit 120 is configured to increase (shift) the gate voltage Vgs of the corresponding switching element Q according to the output voltage of the switching element Q. The increase (shift amount) ΔVgs of the gate voltage is added to the on-gate voltage Vgon and the off-gate voltage Vgoff applied from the drive circuit 150 to the gate terminal of the switching element Q, respectively. This increases the on-gate voltage Vgon and the off-gate voltage Vgoff. By increasing the on-gate voltage Vgon and the off-gate voltage Vgoff, it is possible to adjust the time from when a gate signal is applied to the switching element Q to when the switching element Q actually switches during turn-on and / or turn-off of the switching element Q.

[0045] <Configuration example of speed control circuit> 2 is a diagram showing an example of the configuration of the speed regulation circuit 120. As shown in FIG. 2, the speed regulation circuit 120 includes a power storage element 121, a rectification element 122, and a resistance element 123.

[0046] The storage element 121 is electrically connected between the drain and source of the switching element Q. The storage element 121 is, for example, a capacitor. The storage element 121 has, for example, a capacitance value approximately equal to the output capacitance of the switching element Q. The output capacitance of the switching element Q corresponds to the sum of the gate-drain capacitance and the drain-source capacitance.

[0047] The rectifying element 122 is connected between the drain of the switching element Q and the first end of the storage element 121. That is, the rectifying element 122 and the storage element 121 are connected in series between the drain and source of the switching element Q. The rectifying element 122 is, for example, a diode. The anode of the rectifying element 122 is connected to the drain of the switching element Q, and the cathode of the rectifying element 122 is connected to the first end of the storage element 121. That is, the rectifying element 122 is connected in a direction in which a current flows into the storage element 121.

[0048] The resistive element 123 is electrically connected between a connection point of the rectifying element 122 and the storage element 121 and a gate terminal of the switching element Q. The resistance value of the resistive element 123 is larger than the resistance value of the gate resistor Rg included in the drive circuit 150. The resistive element 123 has a resistance value of, for example, several kΩ. The resistive element 123 corresponds to one example of a “first resistive element”.

[0049] The drive circuit 150 includes a gate driver (GD) 151 and a gate resistor Rg. The gate driver 151 is connected to a gate terminal of the switching element Q via the gate resistor Rg. The gate driver 151 receives a gate signal from the controller 104 (FIG. 1) and controls the on / off of the switching element Q in accordance with the gate signal. The gate driver 151 is connected to a first terminal of the gate resistor Rg. A second terminal of the gate resistor Rg is connected to the gate terminal of the switching element Q.

[0050] Here, in FIG. 2, it is assumed that the switching element Q is switching. When switching element Q is turned off, the drain voltage Vds of switching element Q starts to rise. The drain voltage Vds of switching element Q is applied to the series circuit of rectification element 122 and storage element 121. A current flows into storage element 121 via rectification element 122, so that charge is stored in storage element 121. As a result of this charging of storage element 121, the voltage between the terminals of storage element 121 rises to a voltage equal to the drain voltage Vds of switching element Q.

[0051] Subsequently, when switching element Q is turned on, drain voltage Vds starts to decrease. However, due to the action of rectifying element 122, the charge stored in power storage element 121 is not discharged, and as a result, the terminal-to-terminal voltage of power storage element 121 does not decrease. In other words, the terminal-to-terminal voltage of power storage element 121 is held at the drain voltage Vds when switching element Q is in the off state. Therefore, when the drain voltage Vds (output voltage) of switching element Q increases due to a voltage imbalance, the terminal-to-terminal voltage of power storage element 121 also increases in accordance with this increase in output voltage.

[0052] 2, a current flows through a path from the storage element 121 to the source of the switching element Q via the resistance element 123, the gate terminal of the switching element Q, the gate resistor Rg, and the gate driver 151. A voltage equivalent to the voltage drop across the gate resistor Rg is applied between the gate terminal and the source of the switching element Q. As a result, the gate voltage Vgs increases (shifts) by the voltage drop across the gate resistor Rg.

[0053] Fig. 3 is a diagram for explaining the rise in gate voltage Vgs due to the speed regulation circuit 120. Fig. 3 shows the waveform of the gate voltage Vgs of the switching element Q. The dotted line in the figure shows the waveform of the gate voltage Vgs of the switching element Q to which the speed regulation circuit 120 is not connected. The solid line in the figure shows the waveform of the gate voltage Vgs of the switching element Q to which the speed regulation circuit 120 is connected.

[0054] Focusing on the waveform of the gate voltage Vgs indicated by the dotted line, when an on-gate voltage Vgon is applied to the gate terminal of switching element Q1 at time t1, the gate voltage Vgs rises while charging the input capacitance of switching element Q. The input capacitance of switching element Q corresponds to the sum of the gate-source capacitance and the gate-drain capacitance. When the gate voltage Vgs exceeds the gate threshold voltage Vth (time t2), switching element Q begins to turn on. When switching element Q begins to turn on, the drain voltage Vds begins to decrease. The gate voltage Vgs rises to the on-gate voltage Vgon.

[0055] When the off-gate voltage Vgoff is applied to the gate terminal of the switching element Q1 at time t3, the gate-source capacitance of the switching element Q is discharged, so that the gate voltage Vgs gradually decreases. When the gate voltage Vgs becomes less than the gate threshold voltage Vth (time t4), the switching element Q starts to turn off. When the switching element Q starts to turn off, the drain voltage Vds starts to rise. The gate voltage Vgs decreases to the off-gate voltage Vgoff. Hereinafter, the time from the timing when the switching element Q turns on (time t2) to the timing when it turns off (time t4) is referred to as the "on time Ton."

[0056] 2, in a configuration in which the speed regulator circuit 120 is connected to the switching element Q, the gate voltage Vgs rises by the voltage drop of the gate resistor Rg. Note that the amount of rise in the gate voltage ΔVgs increases as the inter-terminal voltage of the storage element 121 increases, that is, as the output voltage of the switching element Q in the off state increases.

[0057] Referring to the waveform of the gate voltage Vgs shown by the solid line, the increase amount of the gate voltage ΔVgs is added to the off-gate voltage Vgoff and the on-gate voltage Vgon applied to the gate terminal of the switching element Q. This raises the on-gate voltage Vgon and the off-gate voltage Vgoff. As a result, at time t5, which is earlier than time t2, the gate voltage Vgs exceeds the gate threshold voltage Vth, and the switching element Q starts to turn on. Also, at time t6, which is later than time t4, the gate voltage Vgs becomes less than the gate threshold voltage Vth, and the switching element Q starts to turn off.

[0058] By connecting the speed regulating circuit 120 to the switching element Q in this manner, the timing at which the switching element Q turns on is advanced and the timing at which the switching element Q turns off is delayed. As a result, the on-time Ton of the switching element Q connected to the speed regulating circuit 120 is longer than the on-time Ton of the switching element Q not connected to the speed regulating circuit 120. Although not shown in the drawings, the speed regulating circuit 120 may be configured to lengthen the on-time Ton of the switching element Q by advancing the timing at which the switching element Q turns on or delaying the timing at which the switching element Q turns off.

[0059] The length of the on-time Ton of the switching element Q to which the speed regulation circuit 120 is connected depends on the gate voltage rise amount ΔVgs. The larger the gate voltage rise amount ΔVgs, the longer the on-time Ton of the switching element Q. As described above, the gate voltage rise amount ΔVgs increases as the terminal voltage of the storage element 121 (the output voltage of the switching element Q in the off state) increases. Therefore, as the terminal voltage of the storage element 121 (the output voltage of the switching element Q in the off state) increases, the on-time Ton of the switching element Q becomes longer. Conversely, as the terminal voltage of the storage element 121 (the output voltage of the switching element Q in the off state) decreases, the on-time Ton of the switching element Q becomes shorter.

[0060] Here, assume that a voltage imbalance occurs between the switching elements Q1 and Q2 that configure the upper arm 112. In the following, the drain voltage Vds of the switching element Q1 is set to Vds1, and the drain voltage Vds of the switching element Q2 is set to Vds2. In addition, the on-time Ton of the switching element Q1 is set to Ton1, and the on-time Ton of the switching element Q2 is set to Ton2.

[0061] In the case where the relationship Vds1 > Vds2 exists in the off-state switching elements Q1 and Q2, a relationship Ton1 > Ton2 is generated for the on-time Ton of the switching elements Q1 and Q2 by the speed control circuits 120 connected to each of the switching elements Q1 and Q2.

[0062] When Ton1 > Ton2, when synchronously controlling the on / off of the switching elements Q1 and Q2, while the switching element Q1 is on, there is a time when the switching element Q2 is off. A high voltage is applied only to the switching element Q2 during this time. Therefore, as Vds2 increases, Vds1 decreases. As a result, the difference between Vds1 and Vds2 becomes smaller, and the voltage imbalance of the switching elements Q1 and Q2 is suppressed.

[0063] In addition, when the relationship Vds1 < Vds2 occurs due to the increase in Vds2, in contrast to the above-described operation, a relationship Ton1 < Ton2 is generated for the on-time Ton of the switching elements Q1 and Q2 by the speed control circuit 120. Therefore, when synchronously controlling the on / off of the switching elements Q1 and Q2, while the switching element Q2 is on, there is a time when the switching element Q1 is off, so a high voltage is applied only to the switching element Q1. As a result, as Vds1 increases, Vds2 decreases. Since the difference between Vds1 and Vds2 becomes smaller, the voltage imbalance of the switching elements Q1 and Q2 is suppressed.

[0064] Similarly, even when a voltage imbalance occurs in the switching elements Q3 and Q4 constituting the lower arm 114, the voltage imbalance can be suppressed by the speed control circuits 120 connected to each of the switching elements Q3 and Q4.

[0065] <Effect of Embodiment 1> As described above, according to the power conversion device 100 of the first embodiment, by connecting the speed regulator circuit 120 to each of the multiple switching elements Q connected in series, the increase in the gate voltage ΔVgs of the switching element Q can be increased in response to an increase in the output voltage of the switching element Q in the off state, thereby lengthening the on-time Ton of the switching element Q.

[0066] According to this, when a voltage imbalance occurs among multiple switching elements Q, the on-time Ton of the switching element Q with a large output voltage becomes longer than the on-time Ton of the switching element Q with a small output voltage, so that the voltage burden of the switching element Q with a small output voltage can be increased. As a result, the voltage imbalance among the multiple switching elements Q can be suppressed.

[0067] Moreover, the power conversion device 100 according to the first embodiment does not require a correction circuit (a delay time generating circuit and a delay time controller) for adjusting the delay time of the gate signal applied to each switching element, as compared with the power conversion device described in Patent Document 1. Therefore, it is possible to suppress the voltage imbalance of a plurality of switching elements driven at high speed. As a result, when designing the power conversion device, it is possible to suppress the withstand voltage of each switching element from being made larger than necessary, taking into account the safety factor. As a result, it is possible to suppress an increase in power loss occurring in each switching element, and improve the power conversion efficiency.

[0068] First modified example of the first embodiment. In the first embodiment, an example configuration in which the speed regulator circuit 120 is connected to each of the multiple switching elements Q1 to Q4 connected in series has been described. However, even if the speed regulator circuit 120 is connected to at least one of the switching elements Q1 to Q4, the voltage imbalance occurring in the arm including the at least one switching element can be suppressed.

[0069] Fig. 4 is a main circuit configuration diagram of a power conversion device according to a first modified example of the first embodiment. A power conversion device 100 according to the first modified example differs from the power conversion device 100 shown in Fig. 1 in that a speed regulation circuit 120 is connected only to one switching element Q. In the example of Fig. 4, the speed regulation circuit 120 is connected only to the switching element Q1, but the speed regulation circuit 120 may be connected to any one of the switching elements Q2 to Q4.

[0070] 4, the gate voltage Vgs of the switching element Q1 increases in response to an increase in the drain voltage Vds1 of the switching element Q1 due to the action of the speed regulator circuit 120. The increase amount ΔVgs of the gate voltage of the switching element Q1 changes in response to the drain voltage Vds1. The length of the on-time Ton1 of the switching element Q1 changes in response to the increase amount ΔVgs of the gate voltage.

[0071] Therefore, when the drain voltages Vds of the switching elements Q1 and Q2 constituting the upper arm 112 have a relationship of Vds1>Vds2, the on-times Ton of the switching elements Q1 and Q2 have a relationship of Ton1>Ton2. According to this, when the on-off of the switching elements Q1 and Q2 is synchronously controlled, there is a time when the switching element Q1 is on while the switching element Q2 is off, and a high voltage is applied only to the switching element Q2. As Vds2 rises and Vds1 falls, the voltage imbalance of the switching elements Q1 and Q2 is suppressed.

[0072] Furthermore, as Vds1 drops and Vds2 rises, the increase in the gate voltage of the switching element Q1, ΔVgs, decreases, and the on-time Ton1 of the switching element Q1 becomes shorter. This reduces the difference between Ton1 and Ton2, and shortens the time that a high voltage is applied only to the switching element Q2. As a result, the increase in Vds2 is suppressed. In this way, the voltage imbalance of the switching elements Q1 and Q2 is suppressed.

[0073] In the example of Fig. 4, since the speed regulator circuit 120 is not connected to the switching elements Q3, Q4 constituting the lower arm 114, the gate voltages Vgs of the switching elements Q3, Q4 cannot be increased. Therefore, the voltage imbalance of the switching elements Q3, Q4 cannot be suppressed. However, when using the power conversion device 100 only in a mode in which the switching elements Q3, Q4 are fixed in the off state (a mode in which power is transmitted from the DC power source 1 to the DC power source 2), it is possible to apply the configuration example shown in Fig. 4.

[0074] Second modified example of embodiment 1. In the first embodiment, the power conversion device 100 has been described that includes the bridge circuit 110 in which each arm is configured by a series circuit of two switching elements Q. However, the voltage imbalance can also be suppressed in a configuration in which the power conversion device 100 includes the bridge circuit 110 in which each arm is configured by a series circuit of three or more switching elements Q.

[0075] 5 is a main circuit configuration diagram of a power converter according to a second modified example of Embodiment 1. Power converter 100 according to the second modified example differs from power converter 100 shown in FIG.

[0076] 5, the bridge circuit 110 includes six switching elements Q1 to Q6 and six drive circuits 150. The six switching elements Q1 to Q6 are connected in series between a positive electrode wire PL1 and a negative electrode wire NL1.

[0077] The drain of switching element Q1 is connected to the positive electrode wire PL1, and the source of switching element Q1 is connected to the drain of switching element Q2. The source of switching element Q2 is connected to the drain of switching element Q3. The source of switching element Q3 is connected to node ND1. The drain of switching element Q4 is connected to node ND1, and the source of switching element Q4 is connected to the drain of switching element Q5. The source of switching element Q5 is connected to the drain of switching element Q6. The source of switching element Q6 is connected to the negative electrode wire NL1. In other words, node ND1 corresponds to the connection point of switching element Q3 and switching element Q4.

[0078] In bridge circuit 110, three switching elements Q1 to Q3 connected in series between positive electrode wire PL1 and node ND1 constitute an upper arm 112, and three switching elements Q4 to Q6 connected in series between node ND1 and negative electrode wire NL1 constitute a lower arm 114. Switching elements Q1 to Q3 correspond to an embodiment of a "first switching element," and switching elements Q4 to Q6 correspond to an embodiment of a "second switching element."

[0079] The six drive circuits 150 are provided corresponding to the six switching elements Q1 to Q6, respectively. The multiple drive circuits 150 are communicably connected to the controller 104. Each drive circuit 150 drives the corresponding switching element Q in accordance with a gate signal provided by the controller 104, thereby controlling the on / off of the switching element Q.

[0080] The operation of the power conversion device 100 according to the second modification is basically the same as the operation of the power conversion device 100 according to the first embodiment. That is, when power is transmitted from the DC power source 1 to the DC power source 2, the switching elements Q4 to Q6 constituting the lower arm 114 of the bridge circuit 110 are fixed to the OFF state. The switching elements Q1 to Q3 constituting the upper arm 112 of the bridge circuit 110 are synchronously controlled to be ON and OFF by a gate signal from the controller 104. When power is transmitted from the DC power source 2 to the DC power source 1, the switching elements Q1 to Q3 constituting the upper arm 112 of the bridge circuit 110 are fixed to the OFF state. The switching elements Q4 to Q6 constituting the lower arm 114 of the bridge circuit 110 are synchronously controlled to be ON and OFF by a gate signal from the controller 104.

[0081] If the number of switching elements Q constituting the upper arm 112 is a and the number of speed regulating circuits 120 connected to the switching elements Q is b, then it is preferable that b is greater than or equal to a-1 and less than or equal to a, where a is an integer greater than or equal to 2. In the example of Fig. 5, the speed regulating circuits 120 can be connected to all of the three switching elements Q1 to Q3 constituting the upper arm 112. Alternatively, the speed regulating circuits 120 can be connected to two switching elements Q of the three switching elements Q1 to Q3.

[0082] In the upper arm 112, the voltage at the connection point n1 between the switching element Q1 and the switching element Q2 and the voltage at the connection point n2 between the switching element Q2 and the switching element Q3 vary independently of each other. The voltage at the connection point n1 varies mainly in response to the drain voltage Vds of the switching element Q1. The voltage at the connection point n2 varies mainly in response to the drain voltage Vds of the switching element Q3.

[0083] In order to accommodate voltage fluctuations at connection point n1, it is necessary to connect the speed regulator circuit 120 to at least one of the switching elements Q1 and Q2. In order to accommodate voltage fluctuations at connection point n2, it is necessary to connect the speed regulator circuit 120 to at least one of the switching elements Q2 and Q3. However, a configuration in which the speed regulator circuit 120 is connected only to switching element Q2 cannot accommodate voltage fluctuations at connection points n1 and n2, which are independent of each other. Therefore, as shown in FIG. 5, a number of speed regulator circuits 120 corresponding to the number of connection points of the switching elements Q in the upper arm 112 is required.

[0084] Similarly, in the lower arm 114, when the number of switching elements Q constituting the lower arm 114 is c and the number of speed regulating circuits 120 connected to the switching elements Q is d, it is preferable that d is equal to or greater than c-1 and equal to or less than c. Here, c is an integer equal to or greater than 2. In the example of FIG. 5, the speed regulating circuits 120 can be connected to all of the three switching elements Q4 to Q6 constituting the lower arm 114. Alternatively, the speed regulating circuits 120 can be connected to two switching elements Q of the three switching elements Q4 to Q6. Note that the number b of the speed regulating circuits 120 connected to the upper arm 112 and the number d of the speed regulating circuits 120 connected to the lower arm 114 do not necessarily have to be the same.

[0085] Embodiment 2 Fig. 6 is a main circuit configuration diagram of power conversion device 100 according to embodiment 2. As shown in Fig. 6, power conversion device 100 according to embodiment 2 differs from power conversion device 100 according to embodiment 1 shown in Fig. 1 in that it includes a voltage holding element 105.

[0086] A first end of the voltage holding element 105 is connected to a connection point n1 between the switching element Q1 and the switching element Q2. A second end of the voltage holding element 105 is connected to a connection point n3 between the switching element Q3 and the switching element Q4. The voltage holding element 105 is, for example, a capacitor. The capacitance of the voltage holding element 105 is smaller than the capacitance of the DC link capacitor 101. The voltage holding element 105 may be formed of a storage battery.

[0087] The voltage holding element 105 has a function of holding the sum of the drain voltages Vds (output voltages) of the switching elements Q2 and Q3 connected in series between the connection point n1 and the connection point n3. In addition, since the DC link capacitor 101 has a function of holding the voltage of the DC power source 1 (corresponding to the sum of the drain voltages Vds (output voltages) of the switching elements Q1 to Q4), the voltage holding element 105 secondarily has a function of holding the sum of the drain voltages Vds (output voltages) of the switching elements Q2 and Q3. As will be described later, the voltage holding element 105, together with the speed regulation circuit 120, has an effect of suppressing the voltage imbalance of the switching elements Q1 to Q4. The voltage holding element 105 corresponds to one embodiment of the "first voltage holding element".

[0088] The operation of the power conversion device 100 according to the second embodiment is the same as that of the power conversion device 100 according to the first embodiment. That is, the power conversion device 100 transmits power between the DC power sources 1 and 2 by synchronously controlling the on / off of the switching elements Q1, Q2 constituting the upper arm 112 and synchronously controlling the on / off of the switching elements Q3, Q4 constituting the lower arm 114.

[0089] However, the power conversion device 100 shown in FIG. 6 can also output three levels of DC voltage, V1 (the voltage of DC power supply 1), V1 / 2, and 0, to the DC power supply 2 by switching between a first mode in which switching elements Q1 and Q2 are turned on, a second mode in which switching elements Q1 and Q3 are turned on, and a third mode in which switching elements Q3 and Q4 are turned on.

[0090] 6, it is assumed that a voltage imbalance occurs between the switching elements Q1 and Q2 constituting the upper arm 112. In the following, the drain voltage Vds of the switching element Q1 is set to Vds1, and the drain voltage Vds of the switching element Q2 is set to Vds2. In addition, the on-time Ton of the switching element Q1 is set to Ton1, and the on-time Ton of the switching element Q2 is set to Ton2.

[0091] In the case where the relationship Vds1>Vds2 exists for the switching elements Q1, Q2 in the off state, the speed regulator circuit 120 connected to each of the switching elements Q1, Q2 creates a relationship Ton1>Ton2 during the on-time Ton of the switching elements Q1, Q2. As a result, when the on-off of the switching elements Q1, Q2 is synchronously controlled, there is a time when the switching element Q1 is on while the switching element Q2 is off. During this time, a current path as shown in FIG. 7 is formed in the power conversion device 100.

[0092] FIG. 7 is a diagram for explaining a current path in a state where only the switching element Q1 is on. As shown in FIG. 7, the switching element Q1 is on and the switching element Q2 is off. The switching elements Q3 and Q4 are fixed to the off state. In this case, as shown by an arrow A2 in FIG. 7, a current flows through a path from the positive electrode wire PL1 to the negative electrode wire NL1 via the switching element Q1, the voltage holding element 105, the diode of the switching element Q3, the current control reactor 102, and the DC power supply 2. This current causes a charge to be stored in the voltage holding element 105, and the voltage between the terminals of the voltage holding element 105 increases. Then, with the increase in the voltage between the terminals of the voltage holding element 105, the drain voltage Vds1 of the switching element Q1 after turning off decreases. This suppresses the voltage imbalance of the switching elements Q1 and Q2.

[0093] When the drain voltage Vds1 of the switching element Q1 in the off state drops, the increase amount ΔVgs of the gate voltage of the switching element Q1 decreases due to the action of the speed regulator circuit 120 connected to the switching element Q1. When Vds1 and Vds2 are balanced and the on-time Ton1 of the switching element Q1 becomes equal to the on-time Ton2 of the switching element Q2, the current shown in FIG. 7 stops flowing.

[0094] On the contrary, in the case where there is a relationship of Vds1 < Vds2 in the off-state switching elements Q1 and Q2, a relationship of Ton1 < Ton2 is generated in the on-time Ton of the switching elements Q1 and Q2 by the speed control circuits 120 connected to the respective switching elements Q1 and Q2. As a result, when synchronously controlling the on / off of the switching elements Q1 and Q2, there is a time when the switching element Q1 is off while the switching element Q2 is on. During this time, a current path as shown in FIG. 8 is formed in the power conversion device 100.

[0095] FIG. 8 is a diagram for explaining a current path in a state where only the switching element Q2 is on. As shown in FIG. 8, the switching element Q1 is off and the switching element Q2 is on. The switching elements Q3 and Q4 are fixed in the off state. In this case, as indicated by arrow A3 in FIG. 8, a current flows through a path from the voltage holding element 105, through the switching element Q2, the current control reactor 102, the DC power supply 2, the negative electrode wire NL1, and the diode of the switching element Q4, and back to the voltage holding element 105. The charge stored in the voltage holding element 105 is discharged by this current, and the voltage between the terminals of the voltage holding element 105 decreases. Then, due to the decrease in the voltage between the terminals of the voltage holding element 105, the drain voltage Vds2 of the switching element Q2 after turn-off decreases. Thereby, the voltage imbalance between the switching elements Q1 and Q2 is suppressed.

[0096] When the drain voltage Vds2 of the off-state switching element Q2 decreases, the amount of increase ΔVgs of the gate voltage of the switching element Q2 decreases due to the action of the speed control circuit 120 connected to the switching element Q2. When Vds1 and Vds2 are balanced and the on-time Ton2 of the switching element Q2 becomes equal to the on-time Ton1 of the switching element Q1, the current shown in FIG. 8 no longer flows.

[0097] <Effects of Embodiment 2> As described above, according to power conversion device 100 according to the second embodiment, by providing voltage holding element 105 that holds the sum of the output voltages of switching elements Q2, Q3, when a voltage imbalance occurs in switching elements Q1, Q2, voltage holding element 105 is charged or discharged by the action of speed regulation circuit 120. As the inter-terminal voltage of voltage holding element 105 rises or falls, the output voltages of switching elements Q1, Q2 rise or fall, thereby suppressing the voltage imbalance in switching elements Q1, Q2.

[0098] Similarly, when a voltage imbalance occurs in switching elements Q3, Q4, voltage holding element 105 is charged or discharged by the action of speed regulator circuit 120. As the inter-terminal voltage of voltage holding element 105 rises or falls, the output voltage of switching elements Q3, Q4 rises or falls, thereby suppressing the voltage imbalance of switching elements Q3, Q4.

[0099] In the power conversion device 100 according to the first embodiment, the speed regulation circuit 120 varies the on-time Ton of the switching elements Q1, Q2, thereby making it possible to suppress a voltage imbalance between the switching elements Q1, Q2.

[0100] In contrast, in the power conversion device 100 according to the second embodiment, the voltage holding element 105 is charged or discharged depending on the length of the on-time Ton of the switching elements Q1 and Q2, thereby making it possible to more efficiently suppress the voltage imbalance of the switching elements Q1 and Q2.

[0101] First modified example of embodiment 2. Fig. 9 is a main circuit configuration diagram of a power conversion device 100 according to a first modified example of the second embodiment. The power conversion device 100 according to the first modified example differs from the power conversion device 100 shown in Fig. 6 in that a speed regulation circuit 120 is connected only to one switching element Q. In the example of Fig. 9, the speed regulation circuit 120 is connected only to the switching element Q1, but the speed regulation circuit 120 may be connected to any one of the switching elements Q2 to Q4.

[0102] The power conversion device 100 shown in Fig. 9 is obtained by adding a voltage holding element 105 to the power conversion device 100 shown in Fig. 4. In the power conversion device 100 shown in Fig. 4, the speed regulation circuit 120 is connected only to the switching element Q1, so that the voltage imbalance of the switching elements Q1 and Q2 constituting the upper arm 112 can be suppressed.

[0103] In contrast, in the power conversion device 100 shown in FIG. 9, the voltage holding element 105 holds the sum of the output voltages of the switching elements Q2 and Q3, and secondarily has the function of holding the sum of the output voltages of the switching elements Q1 and Q4. Therefore, not only the voltage imbalance of the switching elements Q1 and Q2 constituting the upper arm 112, but also the voltage imbalance of the switching elements Q3 and Q4 constituting the lower arm 114 can be suppressed.

[0104] Specifically, the voltage imbalance between switching elements Q3 and Q4 appears as an increase or decrease in the voltage between the terminals of voltage holding element 105. This increase or decrease in the voltage between the terminals of voltage holding element 105 increases or decreases the drain voltage Vds of switching element Q1. Speed ​​regulator circuit 120 connected to switching element Q1 operates to suppress the increase or decrease in drain voltage Vds, thereby making it possible to suppress the voltage imbalance between switching elements Q3 and Q4.

[0105] Second variant of embodiment 2. In the second embodiment, the power conversion device 100 has been described that includes the bridge circuit 110 in which each arm is configured by a series circuit of two switching elements Q. However, the voltage imbalance can also be suppressed in a configuration in which the power conversion device 100 includes the bridge circuit 110 in which each arm is configured by a series circuit of three or more switching elements Q.

[0106] 10 is a main circuit configuration diagram of power conversion device 100 according to a second modification of Embodiment 2. Power conversion device 100 according to the second modification differs from power conversion device 100 shown in FIG. 8 in the configuration of bridge circuit 110.

[0107] 10, the bridge circuit 110 includes six switching elements Q1 to Q6 and six drive circuits 150. The six switching elements Q1 to Q6 are connected in series between a positive electric wire PL1 and a negative electric wire NL1.

[0108] The power conversion device 100 includes voltage holding elements 105 and 106. A first end of the voltage holding element 105 is connected to a connection point n1 between the switching element Q1 and the switching element Q2. A second end of the voltage holding element 105 is connected to a connection point n4 between the switching element Q5 and the switching element Q6. A first end of the voltage holding element 106 is connected to a connection point n2 between the switching element Q2 and the switching element Q3. A second end of the voltage holding element 106 is connected to a connection point n3 between the switching element Q4 and the switching element Q5. That is, the first end and the second end of the voltage holding element 105 are symmetrical with respect to a node ND1 which is a connection point between the upper arm 112 and the lower arm 114. The first end and the second end of the voltage holding element 106 are symmetrical with respect to a node ND1 which is a connection point between the upper arm 112 and the lower arm 114.

[0109] The voltage holding elements 105 and 106 are, for example, capacitors. The capacitances of the voltage holding elements 105 and 106 are smaller than the capacitance of the DC link capacitor 101. The voltage holding elements 105 and 106 may be composed of storage batteries. The number of voltage holding elements connected to the bridge circuit 110 is equal to the number of connection points of the switching elements Q that configure each arm of the bridge circuit 110. The voltage holding elements 1-5 and 106 correspond to an example of a "first voltage holding element".

[0110] The voltage holding element 105 has the function of holding the sum of the drain voltages Vds (output voltages) of the switching elements Q2 to Q5 connected in series between the connection point n1 and the connection point n4. The voltage holding element 106 has the function of holding the sum of the drain voltages Vds (output voltages) of the switching elements Q3 and Q4 connected in series between the connection point n2 and the connection point n3. The voltage holding element 106 secondarily has the function of holding the sum of the drain voltages Vds of the switching elements Q2 and Q5. The voltage holding element 106 secondarily has the function of holding the sum of the drain voltages Vds of the switching elements Q1 and Q6. The voltage holding elements 105 and 106, together with the speed regulation circuit 120, have the effect of suppressing the voltage imbalance of the switching elements Q1 to Q4.

[0111] The operation of the power conversion device 100 according to the second modification is basically the same as the operation of the power conversion device 100 according to the second embodiment. That is, when power is transmitted from the DC power source 1 to the DC power source 2, the switching elements Q4 to Q6 constituting the lower arm 114 of the bridge circuit 110 are fixed to the OFF state. The switching elements Q1 to Q3 constituting the upper arm 112 of the bridge circuit 110 are synchronously controlled to be ON and OFF by a gate signal from the controller 104. When power is transmitted from the DC power source 2 to the DC power source 1, the switching elements Q1 to Q3 constituting the upper arm 112 of the bridge circuit 110 are fixed to the OFF state. The switching elements Q4 to Q6 constituting the lower arm 114 of the bridge circuit 110 are synchronously controlled to be ON and OFF by a gate signal from the controller 104.

[0112] If the number of pairs of two switching elements Q that are symmetrical with respect to node ND1, which is the connection point between upper arm 112 and lower arm 114, is e, and the number of speed regulating circuits 120 connected to bridge circuit 110 is f, then f is preferably equal to or greater than e-1 and equal to or less than 2e, where e is an integer equal to or greater than 2. Furthermore, when f=e-1, it is preferable that each speed regulating circuit 120 is connected to one of the two switching elements Q in each of the e-1 pairs.

[0113] As shown in FIG. 10, when the number e of pairs of two switching elements Q having symmetry with respect to the node ND1 is three, the number f of the speed regulation circuits 120 is preferably two or more and six or less.

[0114] 10 shows an example of a connection of the speed regulator circuit 120 when f=e-1. In this connection example, the speed regulator circuit 120 is connected to one switching element Q6 of the pair of switching elements Q1 and Q6, and one switching element Q4 of the pair of switching elements Q3 and Q4. The e-1 pairs to which the speed regulator circuit 120 is connected can be arbitrarily selected from the e pairs.

[0115] In the upper arm 112, the voltage at the connection point n1 between the switching elements Q1 and Q2 and the voltage at the connection point n2 between the switching elements Q2 and Q3 fluctuate independently of each other. As described in Fig. 5, in order to accommodate the voltage fluctuations at the connection points n1 and n2, the number of speed regulation circuits 120 corresponding to the number of connection points of the switching elements Q1 to Q3 (i.e., two) is required. Similarly, in the lower arm 114, in order to accommodate the voltage fluctuations at the connection points n3 and n4, the number of speed regulation circuits 120 corresponding to the number of connection points of the switching elements Q4 to Q6 (i.e., two) is required.

[0116] However, in the power conversion device 100 shown in FIG. 10, each of the voltage holding elements 105 and 106 has the function of holding the sum of the drain voltages Vds (output voltages) of a pair of two switching elements Q that are symmetrical with respect to the node ND1. Therefore, a rise or fall in the output voltage of one of the two switching elements Q constituting one pair appears as a fall or rise in the other switching element Q. By connecting a speed regulation circuit 120 to one switching element Q, when the rise in the output voltage of the switching element Q is suppressed by the action of the speed regulation circuit 120, the fall in the output voltage of the other switching element Q is suppressed accordingly. In this way, even when the number of speed regulation circuits 120 is two, the action of the voltage holding elements 105 and 106 makes it possible to suppress the voltage imbalance of the switching elements Q1 to Q6.

[0117] Embodiment 3 In the third embodiment, a description will be given of other configuration examples of the speed regulation circuit 120. Some configuration examples of the speed regulation circuit 120 described below, including combinations thereof, can be appropriately applied to the speed regulation circuit 120 of the power conversion device 100 according to the first and second embodiments and the modified examples described above, within a range in which no inconvenience or contradiction occurs.

[0118] Fig. 11 is a diagram showing a first modified example of the speed regulating circuit 120. As shown in Fig. 11, the speed regulating circuit 120 according to the first modified example differs from the speed regulating circuit 120 shown in Fig. 2 in that it includes a plurality of Zener diodes 124. In the example of Fig. 11, the speed regulating circuit 120 includes four Zener diodes 124, but the number of Zener diodes 124 may be a number other than four or may be a single number.

[0119] The multiple Zener diodes 124 are connected in series with the resistance element 123 between the connection point of the rectification element 122 and the storage element 121 and the gate terminal of the switching element Q. The multiple Zener diodes 124 clamp the gate voltage Vgs of the switching element Q.

[0120] In the first modification, a current flows through a path from the storage element 121 through the resistive element 123, the multiple Zener diodes 124, the gate resistor Rg, and the gate driver 151 to the source of the switching element Q. The gate voltage Vgs rises (shifts) by a voltage equivalent to the voltage drop of the gate resistor Rg. The multiple Zener diodes 124 hold the raised gate voltage Vgs.

[0121] Fig. 12 is a diagram showing a second modified example of the speed regulating circuit 120. As shown in Fig. 12, the speed regulating circuit 120 according to the second modified example differs from the speed regulating circuit 120 shown in Fig. 2 in that it includes a Zener diode 125.

[0122] The anode of the Zener diode 125 is connected to the gate terminal of the switching element Q, and the cathode of the Zener diode 125 is connected to the source of the switching element Q. In the example of Fig. 12, the speed regulator circuit 120 includes one Zener diode 125, but the number of Zener diodes 125 may be multiple. The multiple Zener diodes 125 are connected in series between the gate terminal and the source of the switching element Q.

[0123] In the second modification, a current flows through a path from the storage element 121 through the resistive element 123, the gate resistor Rg, and the gate driver 151 to the source of the switching element Q. The gate voltage Vgs rises (shifts) by a voltage equivalent to the voltage drop of the gate resistor Rg. The Zener diode 125 holds the gate voltage Vgs.

[0124] Fig. 13 is a diagram showing a third modified example of the speed regulator circuit 120. As shown in Fig. 13, the speed regulator circuit 120 according to the fourth configuration example is obtained by replacing the Zener diode 125 in the speed regulator circuit 120 according to the third configuration example shown in Fig. 12 with a resistance element 126. The resistance element 126 has the function of holding the gate voltage Vgs, similar to the Zener diode 125. Note that a series circuit of the Zener diode 125 and the resistance element 126 may be connected between the gate terminal and the source of the switching element Q.

[0125] Embodiment 4 In the fourth embodiment, a description will be given of another configuration example of the drive circuit 150. The configuration examples of the drive circuit 150 described below can be appropriately applied to the drive circuit 150 of the power conversion device 100 according to the first and second embodiments and the modified examples described above, within a range in which no inconvenience or contradiction occurs.

[0126] Fig. 14 is a diagram showing a first modified example of the drive circuit 150. As shown in Fig. 14, the drive circuit 150 according to the first modified example differs from the drive circuit 150 shown in Fig. 2 in that it includes an on-gate resistor Rgon, an off-gate resistor Rgoff, and a diode Dg instead of the gate resistor Rg.

[0127] A first end of the on-gate resistor Rgon is connected to the gate driver 151, and a second end of the on-gate resistor Rgon is connected to the anode of the diode Dg. The cathode of the diode Dg is connected to the gate terminal of the switching element Q.

[0128] A first end of the off-gate resistor Rgoff is connected to the gate driver 151, and a second end of the off-gate resistor Rgoff is connected to the gate terminal of the switching element Q. The series circuit of the on-gate resistor Rgon and the diode Dg and the off-gate resistor Rgoff are connected in parallel between the gate driver 151 and the gate terminal of the switching element Q. The on-gate resistor Rgon corresponds to one embodiment of a "first gate resistor", and the off-gate resistor Rgoff corresponds to one embodiment of a "second gate resistor".

[0129] The gate driver 151 applies an on-gate voltage Vgon to the gate terminal of the switching element Q via an on-gate resistor Rgon and a diode Dg. The gate driver 151 applies an off-gate voltage Vgoff to the gate terminal of the switching element Q via an off-gate resistor Rgoff.

[0130] In the first modification, the resistance value of the off-gate resistor Rgoff is set to be larger than the resistance value of the on-gate resistor Rgon. In this way, when the switching element Q is in the off state, if a current flows through a path from the power storage element 121 to the source of the switching element Q via the resistance element 123, the off-gate resistor Rgoff, and the gate driver 151, the voltage drop of the off-gate resistor Rgoff can be increased. This increases the amount of increase ΔVgs in the gate voltage of the switching element Q, making it easier to adjust the on-time Ton according to the output voltage of the switching element Q.

[0131] Fig. 15 is a diagram showing a second modified example of the drive circuit 150. As shown in Fig. 15, the drive circuit 150 according to the second modified example differs from the drive circuit 150 shown in Fig. 2 in that it includes a voltage hold circuit 170.

[0132] The voltage holding circuit 170 includes a voltage holding element 172, a resistance element 174, and a Zener diode 176. A first end of the voltage holding element 172 is connected to the gate terminal of the switching element Q, and a second end of the voltage holding element 172 is connected to a first end of a gate resistor Rg. A second end of the gate resistor Rg is connected to the gate driver 151. The voltage holding element 172 is, for example, a capacitor. The voltage holding element 172 corresponds to one embodiment of a "second voltage holding element".

[0133] A first end of resistive element 174 is connected to a first end of voltage holding element 172 and a first end of resistive element 123. A second end of resistive element 174 is connected to a second end of voltage holding element 172. Resistive element 174 corresponds to one example of a "second resistive element."

[0134] An anode of the Zener diode 126 is connected to a first end of the gate resistor Rg, and a cathode of the Zener diode 125 is connected to the gate terminal of the switching element Q. Note that, although the voltage holding circuit 170 includes one Zener diode 126 in the example of Fig. 15, the number of Zener diodes 126 may be multiple. The multiple Zener diodes 126 are connected in series between the gate terminal of the switching element Q and the gate resistor Rg.

[0135] In the second modification, a current flows through a path from the storage element 121 to the source of the switching element Q via the resistance element 123, the voltage holding circuit 170, the gate resistor Rg, and the gate driver 151. A voltage equivalent to the sum of the voltage drops of the voltage holding circuit 170 and the gate resistor Rg is applied between the gate terminal and the source of the switching element Q, so that the gate voltage Vgs rises (shifts) by the sum of the voltage drops of the voltage holding circuit 170 and the gate resistor Rg. The voltage holding element 172 of the voltage holding circuit 170 has a function of holding the increase amount ΔVgs of the gate voltage. The resistance element 174 functions as a current limiting element for limiting the magnitude of the current flowing from the storage element 121 to the drive circuit 150. The Zener diode 176 has a function of holding the voltage between the terminals of the voltage holding element 172 so that it does not exceed the breakdown voltage of the Zener diode 176.

[0136] In the above-described first and second embodiments, the power conversion device 100 has been described as a chopper circuit that transmits power between the DC power sources 1 and 2, but the power conversion device 100 according to the present disclosure may have a configuration including the bridge circuit 110. The power conversion device 100 may be, for example, a single-phase inverter circuit in which two bridge circuits 110 are connected in parallel, or a three-phase inverter circuit in which three bridge circuits 110 are connected in parallel.

[0137] Furthermore, in the present disclosure, within the scope of the disclosure, each embodiment can be modified or omitted as appropriate, for example by freely combining each embodiment.

[0138] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. Unless there is a contradiction, at least two of the embodiments disclosed herein may be combined. The technical scope of the present disclosure is indicated by the claims, not the description of the above-mentioned embodiments, and is intended to include all modifications within the meaning and scope of the claims. [Explanation of symbols]

[0139] 1,2 DC power supply, 100 power conversion device, 101 DC link capacitor, 102 current control reactor, 103 filter capacitor, 104 controller, 105, 106, 172 voltage holding element, 110 bridge circuit, 112 upper arm, 114 lower arm, 120 speed control circuit, 121 storage element, 122 rectifier element, 123, 126, 174 resistance element, 124, 125, 176 Zener diode, 150 drive circuit, 151 gate driver, 170 voltage holding circuit, PL1, PL2 positive wire, NL1 negative power supply, Q, Q1 to Q6 switching elements, Rg gate resistor, Rgon on gate resistor, Rgoff off gate resistor, Dg diode, T1 to T4 input / output terminal, Ton on time.

Claims

1. A pair of first input / output terminals to which a first voltage is applied; A plurality of switching elements connected in series between the pair of first input / output terminals; A plurality of drive circuits for respectively controlling on / off of the plurality of switching elements; At least one speed control circuit respectively connected to at least one of the plurality of switching elements; and Each of the plurality of switching elements has a gate terminal, a first main terminal on the high potential side, a second main terminal on the low potential side, and a diode connected in antiparallel between the first main terminal and the second main terminal, and is turned on and off by a gate voltage applied to the gate terminal from a corresponding drive circuit. Each speed control circuit A power storage element electrically connected between the first main terminal and the second main terminal of the corresponding switching element; A rectifying element connected between the first main terminal and the power storage element in a direction in which current flows through the power storage element; And a first resistance element electrically connected between a connection point of the rectifying element and the power storage element and the gate terminal of the corresponding switching element. The power conversion device, wherein a resistance value of the first resistance element is larger than a resistance value of a gate resistance included in a drive circuit of the corresponding switching element.

2. In each of the speed control circuits, a voltage across the terminals of the power storage element is held at a voltage between the first main terminal and the second main terminal in an off state of the corresponding switching element, and A current corresponding to the voltage across the terminals of the power storage element flows through the first resistance element and the gate terminal and into the drive circuit of the corresponding switching element, thereby increasing the gate voltage applied to the gate terminal of the corresponding switching element. The power conversion device according to claim 1.

3. A bridge circuit including an upper arm and a lower arm connected in series between the pair of first input / output terminals; and A pair of second input / output terminals connected to both ends of the lower arm and to which a second voltage lower than the first voltage is applied. The power conversion device further includes The plurality of switching elements A plurality of first switching elements constituting the upper arm; and A plurality of second switching elements constituting the lower arm. The at least one speed control circuit is respectively connected to at least one of the plurality of first switching elements and the plurality of second switching elements. The power conversion device according to claim 1.

4. The at least one speed regulation circuit is at least one first speed regulation circuit respectively connected to at least one of the plurality of first switching elements, and at least one second speed regulation circuit respectively connected to at least one of the plurality of second switching elements, the power conversion device according to claim 3.

5. When the number of the plurality of first switching elements is a and the number of the at least one first speed regulation circuit is b, b is greater than or equal to a - 1 and less than or equal to a, When the number of the plurality of second switching elements is c and the number of the at least one second speed regulation circuit is d, d is greater than or equal to c - 1 and less than or equal to c, the power conversion device according to claim 4.

6. A first end is connected to a first connection point of two adjacent first switching elements, a second end is connected to a second connection point of two adjacent second switching elements, and further includes at least one first voltage holding element for holding a voltage between the first connection point and the second connection point, For each of the at least one first voltage holding element, the first connection point to which the first end is connected and the second connection point to which the second end is connected are symmetric with respect to a connection point of the upper arm and the lower arm, the power conversion device according to claim 3.

7. When the number of pairs of the first switching element and the second switching element having symmetry with respect to a connection point of the upper arm and the lower arm is e and the number of the at least one speed regulation circuit is f, f is greater than or equal to e - 1 and less than or equal to 2e, When f = e - 1, each speed regulation circuit is connected to either the first switching element or the second switching element in each of the e - 1 pairs, the power conversion device according to claim 6.

8. The gate resistance included in the drive circuit of the corresponding switching element is a first gate resistance for turn-on connected to the gate terminal of the corresponding switching element, and a second gate resistance for turn-off connected to the gate terminal of the corresponding switching element, The resistance value of the second gate resistance is greater than the resistance value of the first gate resistance, the power conversion device according to any one of claims 1 to 7.

9. Each of the at least one speed control circuit is The power conversion device according to any one of claims 1 to 7, further comprising at least one Zener diode connected in series with the first resistance element between the connection point of the rectifying element and the power storage element and the gate terminal of the corresponding switching element.

10. Each of the at least one speed control circuit is The power conversion device according to any one of claims 1 to 7, further comprising a Zener diode electrically connected between the gate terminal of the corresponding switching element and the second main terminal.

11. Each of the at least one speed control circuit is The power conversion device according to any one of claims 1 to 7, further comprising a second resistance element electrically connected between the gate terminal of the corresponding switching element and the second main terminal.

12. The power conversion device according to any one of claims 1 to 7, further comprising at least one holding circuit provided corresponding to each of the at least one speed control circuit for holding the shift amount of the gate voltage applied to the gate terminal of the corresponding switching element. Each holding circuit A second voltage holding element connected between the drive circuit of the corresponding switching element and the gate terminal, The power conversion device according to any one of claims 1 to 7, comprising a second resistance element connected in parallel with the second voltage holding element.

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