Semiconductor device and communication system

Abstract

A semiconductor device (1) comprises: a communication unit (11) configured to receive, from the outside, communication data (RX) transmitted by serial communication; and a register (11A). The communication data includes first data (RW) for designating a read or a write, and second data (AM) capable of designating a read-back when the first data designates a write. When the first data designates the write, the communication unit only reads a number of bytes of data of an address designated by the second data in the register, the number being designated by the second data, and transmits the data to the outside.

Description

Semiconductor device and communication system

[0001] The present disclosure relates to a semiconductor device and a communication system.

[0002] Semiconductor devices having a serial communication function are used in a variety of applications.

[0003] An example of circuit technology relating to serial communication is disclosed in Japanese Patent Application Laid-Open No. 2003-222299.

[0004] Japanese Patent Application Laid-Open No. 2017-224946

[0005] [Summary] Conventionally, when a read command is issued by transmitting data via serial communication, data is read from a semiconductor device, but when a write command is issued, only the write is performed and no reading is performed.

[0006] An object of the present disclosure is to provide a semiconductor device that can effectively perform reading even when a writing command is issued using serial communication.

[0007] For example, a semiconductor device according to one aspect of the present disclosure includes: a communication unit configured to receive communication data transmitted by serial communication from an external device; and a register, wherein the communication data includes first data specifying a read or a write; and second data capable of specifying a readback when the first data specifies a write; and wherein, when the first data specifies the write, the communication unit is configured to read out the number of bytes of data specified by the second data from an address in the register, and transmit the data to the external device.

[0008] FIG. 1 is a diagram illustrating a configuration of a communication system according to an exemplary embodiment of the present disclosure. FIG. 2 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. FIG. 3 is a diagram illustrating a data configuration of received data RX when writing is performed using a semiconductor device as a target device. FIG. 4 is a diagram illustrating a register map related to setting a readback address in a register. FIG. 5 is a diagram illustrating an example of storing multiple readback address data in a register. FIG. 6 is a diagram illustrating a register map related to setting the number of readback bytes in a register. FIG. 7 is a diagram illustrating an example of storing multiple byte number data in a register. FIG. 8 is a diagram illustrating a readback process when readback setting data AM=1. FIG. 9 is a diagram illustrating a readback process when readback setting data AM=2. FIG. 10 is a diagram illustrating a readback process when readback setting data AM=3.

[0009] DETAILED DESCRIPTION Exemplary embodiments of the present disclosure will now be described with reference to the drawings.

[0010] 1 is a diagram illustrating a configuration of a communication system 5 according to an exemplary embodiment of the present disclosure. The communication system 5 includes an MCU (Micro Controller Unit) 2, a CAN (Controller Area Network) transceiver 3, a CAN transceiver 4, and a plurality of semiconductor devices 1. The communication system 5 is, as an example, for use in a vehicle.

[0011] Communication between the MCU 2 and the CAN transceiver 3 is performed using UART (Universal Asynchronous Receiver / Transmitter). UART is a protocol for exchanging serial data between two devices. With UART, bidirectional communication is performed between the sending and receiving sides using two lines.

[0012] Communication between the CAN transceivers 3 and 4 is performed via a CAN bus 30. CAN is a serial communication protocol standardized by international standards such as ISO11898.

[0013] The CAN transceiver 3 has a TXD (transmit data input) terminal 3A and an RXD (receive data output) terminal 3B. The CAN transceiver 3 outputs data input to the TXD terminal 3A to the CAN bus 30, and outputs data input from the CAN bus 30 from the RXD terminal 3B.

[0014] The CAN transceiver 4 and the semiconductor device 1 are connected via a bus BS1. The bus BS1 is used for UART communication. The CAN transceiver 4 has an RXD terminal 4A and a TXD terminal 4B. The CAN transceiver 4 outputs data input to the TXD terminal 4B to the CAN bus 30, and outputs data input from the CAN bus 30 from the RXD terminal 4A.

[0015] The semiconductor device 1 is an IC (integrated circuit) in which circuits with predetermined functions are integrated, and is configured as, for example, an LED (light emitting diode) driver IC. The semiconductor device 1 has an RX (received data input) terminal 1A and a TX (transmitted data output) terminal 1B.

[0016] The RX terminals 1A of the multiple semiconductor devices 1 are commonly connected to the RXD terminal 4A. The TX terminals 1B of the multiple semiconductor devices 1 are commonly connected to the TXD terminal 4B. Communication of receive data RX and transmit data TX is possible via the bus BS1. The receive data RX and transmit data TX are serial data conforming to UART. The receive data RX output from the RXD terminal 4A is input to the RX terminal 1A. The transmit data TX output from the TX terminal 1B is input to the TXD terminal 4B.

[0017] 2. Configuration of the Semiconductor Device> Fig. 2 is a block diagram of a semiconductor device 1 according to an embodiment of the present disclosure. The semiconductor device 1 includes a communication unit 11. Note that Fig. 2 illustrates only functional blocks related to communication functions in the communication system 5, and other functional blocks may also be included. For example, if the semiconductor device 1 is an LED driver, it includes a functional block related to LED driving.

[0018] The communication unit 11 performs UART communication with the CAN transceiver 4. The communication unit 11 has a register 11A. Received data RX is input to the communication unit 11 via an RX terminal 1A. The communication unit 11 outputs transmitted data TX via a TX terminal 1B. If the received data RX instructs a read, the communication unit 11 reads data from the register 11A and transmits it as transmitted data TX. If the received data RX instructs a write, the communication unit 11 writes data to the register 11A. However, in this embodiment, as will be described later, the communication unit 11 may also read even if a write is instructed. Reading data from the register 11A and outputting it as transmitted data TX is called readback.

[0019] 3. Structure of Received Data FIG. 3 is a diagram showing the data structure of received data RX when writing is performed with the semiconductor device 1 as the target device.

[0020] In UART, communication is carried out in data units called frames. As shown in Fig. 3, a frame FR is made up of bit data from a start bit S to a stop bit P. The start bit S is at a low level, and the stop bit P is at a high level. A predetermined number of bits of bit data are placed between the start bit S and the stop bit P. In the example of Fig. 3, 8 bits of bit data are placed. In other words, a frame FR is made up of 10 bits of bit data.

[0021] As shown in FIG. 3, the received data RX includes, from the beginning, a synchronization frame SYNC, a read / write frame RWD, a data number frame NOD, a register address frame ADD, a data frame DAT, a CRC (Cyclic Redundancy Check) lower frame CRL, and a CRC upper frame CRH.

[0022] The synchronization frame SYNC is bit data for setting the baud rate in the semiconductor device.

[0023] The Read / Write etc. frame RWD includes a device address DA, a Read / Write bit RW, and the like.

[0024] The device address DA is bit data indicating the address of the target device (semiconductor device) (5-bit data in the example of FIG. 3). The read / write bit RW is bit data indicating read or write.

[0025] The data number frame NOD includes frame number data ND and readback setting data AM. The frame number data ND is 6-bit data, and is bit data indicating the number of frames in the data frame DAT. The readback setting data AM is 2-bit data, and is data that sets the mode of the readback process when writing is instructed by the Read / Write bit RW. The readback setting data AM can take values ​​from 0 to 3. Note that the readback setting data AM may be, for example, 3 or more bits. The mode set by the readback setting data AM will be described later.

[0026] The register address frame ADD includes address data AD, which is bit data indicating an address in the register 11 A. The data frame DAT includes write data DT, which is bit data for writing to the register 11 A. The CRC lower frame CRL and the CRC upper frame CRH are bit data indicating an error detection code to be added to the write data DT.

[0027] 4. Readback Settings Now, the settings related to readback in the register 11A will be described. Fig. 4 is a diagram showing a register map related to setting the readback address in the register 11A. The register map shows the correspondence between addresses and stored data. The register 11A can store 8 bits of data per address.

[0028] 4, readback address data RBADDR is stored in a first predetermined address (0x03 as an example here). The readback address data RBADDR is data indicating the address (readback address) from which data is read from register 11A during readback, and is 8-bit data here.

[0029] 4 shows data stored in three consecutive addresses starting from a second predetermined address (0x78 as an example). Here, as an example, error data ERR1 to ERR8 are stored for each bit in the second predetermined address (0x78), and predetermined data is stored in an address incremented from the second predetermined address (0x79) and incremented further to an address (0x7A).

[0030] By setting the second predetermined address as the readback address using the readback address data RBADDR, it is possible to read back at least the data stored at the second predetermined address (error data ERR1 to ERR8). The readback address data RBADDR can be rewritten via UART communication, making the readback address variable.

[0031] 5, a plurality of readback address data, such as readback address data RBADDR1 and RBADDR2, may be set in the register 11A. This allows a plurality of readback addresses to be set, for example, by setting 0x78 as readback address data RBADDR1 and 0x88 as readback address data RBADDR2, as shown in FIG. 5. Furthermore, a plurality of readback address data can be rewritten.

[0032] 6 is a diagram showing a register map for setting the readback byte count in register 11A. As shown in FIG. 6, byte count data BYTNUM is stored at a third predetermined address (0x05, for example). The byte count data BYTNUM indicates the number of bytes (readback byte count) read from register 11A during readback, and is 3-bit data here. For example, when BYTNUM = 0, the readback byte count is 1 byte; when BYTNUM = 1, the readback byte count is 2 bytes; when BYTNUM = 2, the readback byte count is 3 bytes. Since the byte count data BYTNUM can be rewritten via UART communication, the readback byte count is variable.

[0033] 7, multiple byte count data, such as byte count data BYTNUM1 and BYTNUM2, may be set in the register 11A. This allows multiple readback byte counts to be set. Also, multiple byte count data can be rewritten.

[0034] 5. Readback Processing Next, the readback processing performed in the semiconductor device 1 will be described with reference to Figures 8 to 10. Figures 8 to 10 respectively show received data RX input to the communication unit 11 and transmitted data TX output from the communication unit 11. Note that in all cases in Figures 8 to 10, a write is instructed by the read / write bit RW.

[0035] 8 shows a case where the readback setting data AM = 1 in the received data RX. Here, AM = 1 indicates a readback processing mode setting in which one byte of data is read from the readback address set by the readback address data RBADDR (FIG. 4). The number of bytes, 1 byte, here may be a fixed setting or may be set, for example, by the byte number data BYTNUM1 (FIG. 7).

[0036] When the communication unit 11 receives the received data RX up to the CRC upper frame CRH, it writes the data to the register 11A based on the write data DT included in the received data RX. At the same time, the communication unit 11 reads one byte of data from the readback address set by the readback address data RBADDR and outputs the transmit data TX as a readback frame RB. The readback frame RB contains the readback data RD[7:0] (1 byte). As shown in FIG. 4, when the readback address data RBADDR is set to 0x78, the error data ERR1 to ERR8 become the readback data RD.

[0037] After outputting the readback frame RB, the communication unit 11 outputs a CRC lower frame CRCLF and a CRC upper frame CRCHF as transmission data TX. The CRC lower frame CRCLF and the CRC upper frame CRCHF are bit data indicating an error detection code added to the readback data RD. Thereafter, the transmission data TX goes into a high impedance state (Hi-z).

[0038] 9 shows a case where the readback setting data AM=2 in the received data RX. Here, AM=2 indicates a readback processing mode setting in which three bytes of data are read from the readback address set by the readback address data RBADDR (FIG. 4). The number of bytes, 3, may be a fixed setting or may be set, for example, by the byte count data BYTNUM2 (FIG. 7). The three bytes of data are data stored in three consecutive addresses from the readback address set by the readback address data RBADDR. In the example of FIG. 4, this is data (such as error data) stored at 0x78, 0x79, and 0x7A.

[0039] In the case of Fig. 9, as in the case of Fig. 8, the communication unit 11 writes to the register 11A based on the write data DT. At the same time, the communication unit 11 reads three bytes of data from the readback address set by the readback address data RBADDR and outputs the transmit data TX as readback frames RB1, RB2, and RB3. The readback frames RB1, RB2, and RB3 contain the readback data RD1, RD2, and RD3, respectively. In the example shown in Fig. 4, the data stored at 0x78 is readback data RD1, the data stored at 0x79 is readback data RD2, and the data stored at 0x7A is readback data RD3.

[0040] After outputting the readback frames RB1, RB2, and RB3, the communication unit 11 outputs a CRC lower frame CRCLF and a CRC upper frame CRCHF as transmission data TX. The CRC lower frame CRCLF and the CRC upper frame CRCHF are bit data indicating error detection codes added to the readback data RD1, RD2, and RD3.

[0041] 5, the readback address data referenced by the communication unit 11 may be changed depending on the value of the readback setting data AM. For example, when AM=1, the readback address data ABADDR1 is referenced, and when AM=2, the readback address data ABADDR2 is referenced.

[0042] 10 shows a case where the readback setting data AM in the received data RX is set to 3. Here, AM=3 indicates the mode setting of the readback process for reading out written data.

[0043] 10, writing to the register 11A is performed based on the write data DT included in the received data RX at an address specified by the address data AD included in the received data RX. The number of data frames DAT containing the write data DT is specified by the frame number data ND included in the data number frame NOD. Writing is performed at consecutive addresses starting from the address specified by the address data AD according to the number specified by the frame number data ND.

[0044] After writing, the communication unit 11 reads from the register 11A the number of bytes of data corresponding to the number specified by the frame number data ND from the address specified by the address data AD, and outputs the transmission data TX as a readback frame RB. At this time, data is read from consecutive addresses starting from the address specified by the address data AD. The number of readback frames RB is the number specified by the frame number data ND.

[0045] After outputting the readback frame RB, the communication unit 11 outputs a CRC lower frame CRCLF and a CRC upper frame CRCHF as transmission data TX. The CRC lower frame CRCLF and the CRC upper frame CRCHF are bit data indicating an error detection code added to the readback data RD. Thereafter, the transmission data TX goes into a high impedance state (Hi-z).

[0046] In such a readback processing mode, the data written to the register 11A can be read back.

[0047] If AM=0, it is possible to specify a normal mode in which readback is not performed, in which case readback is not performed and only writing is performed.

[0048] <6. Others> In addition to the above-described embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0049] <7. Supplementary Note> As described above, a semiconductor device (1) according to one aspect of the present disclosure includes: a communication unit (11) configured to receive communication data (RX) transmitted by serial communication from an external device; and a register (11A), wherein the communication data includes first data (RW) specifying a read or a write, and second data (AM) capable of specifying a readback when the first data specifies a write, and wherein, when the first data specifies the write, the communication unit is configured to read out the number of bytes of data in the register at an address specified by the second data, and transmit the data to the external device (first configuration).

[0050] With this configuration, when a write is specified by communication data, the desired number of bytes of data can be read from the desired address, thereby solving the problem of being able to read effectively even when a write is instructed using serial communication.

[0051] In addition, in the above first configuration, the address specified by the second data (AM) may be configured to be an address set by predetermined address data (RBADDR) stored in the register (second configuration).

[0052] In the second configuration, the address data (RBADDR1, RBADDR2) may be stored in a plurality of pieces in the register, and the address data may be selected from the plurality of pieces of address data by the second data (third configuration).

[0053] In addition, in the second or third configuration, the register may be configured so that error data (ERR1 to ERR8) is stored at the address set by the predetermined address data (RBADDR) (fourth configuration).

[0054] In addition, in any of the second to fourth configurations, the communication unit may be configured to read the data stored in multiple consecutive addresses from the address set by the specified address data (RBADDR) according to the number of bytes (fifth configuration).

[0055] Furthermore, in any of the first to fifth configurations, the number of bytes specified by the second data (AM) may be the number of bytes set by a predetermined byte number data (BYTNUM) stored in the register (sixth configuration).

[0056] In addition, in the sixth configuration, a configuration may be adopted in which a plurality of the byte number data (BYTNUM1, BYTNUM2) are stored in the register, and the byte number data is selected from the plurality of byte number data by the second data (seventh configuration).

[0057] Furthermore, in any of the first to seventh configurations, when the first data specifies the write, the communication unit may be configured to write to the register based on write data (DT) included in the communication data, and the second data (AM) may be configured to be capable of specifying a mode for reading the data written to the register and transmitting it to the outside (eighth configuration).

[0058] In any one of the first to eighth configurations, the second data (AM) may be configured to be capable of specifying a normal mode in which the readback is not performed (ninth configuration).

[0059] In addition, in any of the first to ninth configurations, the communication data may include a second frame (NOD) indicating the number of frames of a first frame (DAT) containing write data (DT), and the second data (AM) may be included in the second frame (tenth configuration).

[0060] In the tenth configuration, the serial communication may be UART communication (eleventh configuration).

[0061] Furthermore, a communication system (5) according to one aspect of the present disclosure includes a semiconductor device (1) having any one of the first to eleventh configurations described above, and a transmitting device (4) configured to transmit the communication data (twelfth configuration).

[0062] The present disclosure can be used, for example, in an in-vehicle communication system.

[0063] REFERENCE SIGNS LIST 1 semiconductor device 1A RX terminal 1B TX terminal 3 CAN transceiver 3A TXD terminal 3B RXD terminal 4 CAN transceiver 4A RXD terminal 4B TXD terminal 5 communication system 11 communication unit 11A register 30 CAN bus

Claims

1. A communication unit configured to receive communication data transmitted via serial communication from an external source, Registers and Equipped with, The aforementioned communication data is The first data specifies whether to read or write, The first data specifies a write operation, and the second data specifies a readback operation. Includes, The communication unit is a semiconductor device that, when the first data specifies the write operation, reads data from the address specified by the second data in the register for the number of bytes specified by the second data and transmits it to the outside.

2. The semiconductor device according to claim 1, wherein the address specified by the second data is an address set by predetermined address data stored in the register.

3. Multiple copies of the address data are stored in the register. The semiconductor device according to claim 2, wherein the address data is selected from the plurality of address data by the second data.

4. The semiconductor device according to claim 2, wherein in the register, error data is stored for the address set by the predetermined address data.

5. The semiconductor device according to claim 2, wherein the communication unit reads out the data stored in a plurality of consecutive addresses starting from the address set by the predetermined address data, in accordance with the number of bytes.

6. The semiconductor device according to claim 1, wherein the number of bytes specified by the second data is the number of bytes set by predetermined byte data stored in the register.

7. The byte count data is stored in multiple locations in the register. The semiconductor device according to claim 6, wherein the byte count data is selected from the plurality of byte count data based on the second data.

8. When the first data specifies the write operation, the communication unit writes to the register based on the write data included in the communication data. The semiconductor device according to claim 1, wherein the second data can specify a mode for reading the data written to the register and transmitting it to the outside.

9. The semiconductor device according to claim 1, wherein the second data can specify a normal mode in which the readback is not performed.

10. The aforementioned communication data includes a second frame indicating the number of frames in the first frame containing the written data. The semiconductor device according to claim 1, wherein the second data is included in the second frame.

11. The semiconductor device according to claim 10, wherein the serial communication is UART communication.

12. A communication system comprising a semiconductor device according to any one of claims 1 to 11, and a transmitting device configured to transmit the communication data.