Semiconductor device

Abstract

The present invention ensures sufficient withstand voltage characteristics.　A control conductive pattern (13d) includes a connection region (13d1) electrically connected to a control electrode (15a1), and, in a plan view, is adjacent to the opposite side of a chip region of a terminal region of an output conductive pattern (13c). Furthermore, the terminal region of the output conductive pattern (13c) has a recess (13c3) recessed from a first side to a second side on the +X direction side, in a plan view. The connection region (13d1) of the control conductive pattern (13d) is provided in the recess (13c3). The connection region (13d1) of the control conductive pattern (13d) is separated from the output terminal (63a).

Description

Semiconductor Devices

[0001] The present invention relates to a semiconductor device.

[0002] A semiconductor device has a substrate including a circuit pattern on which semiconductor chips are arranged (see, for example, Patent Document 1). The semiconductor device is sealed with a sealing member (see, for example, Patent Documents 2 and 3). The semiconductor device may further include a heat sink on which a plurality of substrates on which semiconductor chips are arranged are arranged, and a wiring member electrically connected to the conductive pattern of the substrate, and these may be housed in a case (see, for example, Patent Document 4).

[0003] International Publication No. 2022-137811 Japanese Patent Application Laid-Open No. 2021-180234 Japanese Patent Application Laid-Open No. 2022-046369 International Publication No. 2022-130951

[0004] An object of the present invention is to provide a semiconductor device that ensures sufficient voltage resistance characteristics.

[0005] According to one aspect of the present invention, there is provided a semiconductor device comprising: a first semiconductor chip including a control electrode provided on a side portion in a first direction on a front surface thereof; an output conductive pattern including a rectangular first portion having sides extending in the first direction and in a second direction perpendicular to the first direction, and in which the first semiconductor chip is arranged; and a second portion connected to the side of the first portion in the first direction and extending from a first side of the side in the first direction to a second side; an output terminal arranged on the second portion of the output conductive pattern; and a control conductive pattern including a connection portion electrically connected to the control electrode and adjacent to the second portion of the output conductive pattern on an opposite side to the first portion in a plan view, wherein the second portion of the output conductive pattern has a recess adjacent to the first portion on the first side in a plan view and recessed from the first side toward the second side, and the connection portion of the control conductive pattern is provided in the recess.

[0006] Alternatively, one output terminal may be provided and disposed at a center of the width of the second portion of the output conductive pattern in the second direction, or at least two output terminals may be provided and disposed side by side in the second direction on the second portion of the output conductive pattern.

[0007] The control electrode may be provided at the center of the side of the front surface of the first semiconductor chip. The width of the first semiconductor chip in the second direction may be equal to or less than half the width of the first portion of the output conductive pattern in the second direction, and two first semiconductor chips may be arranged side by side in the second direction on the first portion of the output conductive pattern.

[0008] The first semiconductor chip may further include an output electrode provided on the front surface, and may further include a second semiconductor chip including a diode element arranged adjacent to the first semiconductor chip on the opposite side of the first semiconductor chip from the second portion of the output conductive pattern, and the second semiconductor chip may be electrically connected to the output electrode of the first semiconductor chip and the first portion of the output conductive pattern.

[0009] Furthermore, the width of the first semiconductor chip in the second direction may be less than or equal to the width of the first portion of the output conductive pattern in the second direction, and one first semiconductor chip may be arranged in the first portion of the output conductive pattern.

[0010] The semiconductor device may further include a wire connecting the connection portion of the control conductive pattern and the control electrode of the first semiconductor chip, and the shortest distance from the wire to the output terminal of the at least two output terminals that is closest to the connection portion may be 1.5 mm or more in a planar view.

[0011] The first semiconductor chip may have a withstand voltage of 1200 V. The first semiconductor chip may be an insulated gate bipolar transistor. The first semiconductor chip may further include a wire connecting the connection portion of the control conductive pattern and the control electrode of the first semiconductor chip, and the shortest distance from the wire to the output terminal of the at least two output terminals that is closest to the connection portion may be 2.2 mm or more in plan view.

[0012] The first semiconductor chip may have a withstand voltage of 1700 V. The first semiconductor chip may be a reverse conducting insulated gate bipolar transistor.

[0013] The control electrode may be provided on the first side or the second side of the center of the side of the front surface, and the second portion of the output conductive pattern may include a connecting region electrically connected to another external output conductive pattern.

[0014] The recess included in the second portion of the output conductive pattern may have a U-shape in plan view with an opening facing the first side, and the connecting region may be included along the recess at an end of the recess on the first side.

[0015] The recess included in the second portion of the output conductive pattern may be provided on the first side from a center of a width of the first portion of the output conductive pattern in the second direction, and the recess included in the second portion of the output conductive pattern may be L-shaped in a plan view, with an opening facing the first side and the first direction.

[0016] The above summary of the invention does not list all of the necessary features of the present invention, and subcombinations of these features may also constitute inventions.

[0017] According to the disclosed technique, sufficient voltage resistance characteristics are ensured and deterioration of reliability can be suppressed. The above and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accompanying drawings which show preferred embodiments of the present invention as examples.

[0018] 1 is a plan view of a semiconductor device. FIG. 2 is a side view of a semiconductor device. FIG. 3 is a plan view of a semiconductor device according to a first embodiment (when the case is removed). FIG. 4 is a plan view of a semiconductor unit included in the semiconductor device according to the first embodiment. FIG. 5 is a plan view of an insulating circuit board included in the semiconductor device according to the first embodiment. FIG. 6 is a cross-sectional view of an insulating circuit board included in the semiconductor device according to the first embodiment. FIG. 7 is a plan view of a semiconductor unit included in a semiconductor device of a reference example. FIG. 8 is a plan view of a semiconductor device according to a second embodiment (when the case is removed). FIG. 9 is a plan view of a semiconductor unit included in a semiconductor device according to the second embodiment. FIG. 10 is a graph showing the terminal-to-wire distance required to suppress discharge with respect to voltage. FIG. 11 is a plan view of a semiconductor unit included in a semiconductor device according to a third embodiment. FIG. 12 is a plan view of a semiconductor unit included in a semiconductor device according to a fourth embodiment.

[0019] Hereinafter, embodiments will be described with reference to the drawings. In the following description, the terms "front surface" and "top surface" refer to the X-Y plane facing upward (+Z direction) in the semiconductor device 1 shown in the drawings. Similarly, "top" refers to the upward direction (+Z direction) in the semiconductor device 1 shown in the drawings. The terms "back surface" and "bottom surface" refer to the X-Y plane facing downward (-Z direction) in the semiconductor device 1 shown in the drawings. Similarly, "bottom" refers to the downward direction (-Z direction) in the semiconductor device 1 shown in the drawings. Similar orientations will be used in other drawings as necessary. The term "high position" refers to the upper position (+Z direction) in the semiconductor device 1 shown in the drawings. Similarly, the term "low position" refers to the lower position (-Z direction) in the semiconductor device 1 shown in the drawings. The terms "front surface," "top surface," "top," "back surface," "bottom surface," "bottom," and "side surface" are merely convenient expressions for specifying relative positional relationships and do not limit the technical concept of the present invention. For example, "up" and "down" do not necessarily mean the vertical direction relative to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. In the following description, "main component" refers to a component containing 80 vol% or more. "Approximately the same" means that the difference is within a range of ±10%. "Perpendicular," "orthogonal," and "parallel" mean that the difference is within a range of ±10°.

[0020] [First embodiment] A semiconductor device will be described with reference to Figs. 1 to 3. Fig. 1 is a plan view of the semiconductor device. Fig. 2 is a side view of the semiconductor device. Fig. 3 is a plan view of the semiconductor device of the first embodiment (when the case is removed). Fig. 2 is a side view of the semiconductor device 1 of Fig. 1 as viewed in the +Y direction. Fig. 3 is a plan view of the semiconductor device 1 of Fig. 1 when the case 20 is removed. However, in the semiconductor device 1 of Fig. 3, the semiconductor units included in the semiconductor device 1 are omitted.

[0021] The semiconductor device 1 includes a case 20. The case 20 is attached to a heat dissipation base plate 30, which will be described later, to which the semiconductor units 10a to 10f are joined. When attached to the heat dissipation base plate 30, the case 20 houses the semiconductor units 10a to 10f. The case 20 includes a lower storage section 21 and an upper storage section 22.

[0022] The lower storage section 21 has a rectangular parallelepiped shape. In a plan view, the lower storage section 21 is surrounded on all four sides by long side walls 21 a, short side walls 21 b, long side walls 21 c, and short side walls 21 d. The opening of the lower storage section 21 is surrounded by the long side walls 21 a, short side walls 21 b, long side walls 21 c, and short side walls 21 d and includes a lower front surface 21 e.

[0023] The lower front surface 21e includes control terminal regions 21e1 to 21e5. The control terminal region 21e1 is provided on the edge of the lower front surface 21e, close to the short side wall 21b, on the long side wall 21c side. The control terminal region 21e2 is provided on the edge of the lower front surface 21e, close to the long side wall 21c, adjacent to the control terminal region 21e1 in the +X direction. The control terminal region 21e3 is provided on the edge of the lower front surface 21e, close to the long side wall 21c, adjacent to the control terminal region 21e2 in the +X direction. The control terminal region 21e4 is provided on the edge of the lower front surface 21e, close to the short side wall 21b, on the long side wall 21a side, facing the control terminal region 21e1. The control terminal region 21e5 is provided on the edge of the lower front surface 21e on the long sidewall 21a side, adjacent to the control terminal region 21e4 in the +X direction. Furthermore, the control terminal region 21e5 faces the control terminal region 21e2.

[0024] Each of the control terminal areas 21e1 to 21e5 exposes a control wiring member 64. The connection portions of the tips of the wiring members 64 are exposed and bent from the control terminal areas 21e1 to 21e5. The control terminal areas 21e1 to 21e5 may house nuts that face the connection portions of the bent wiring members 64.

[0025] An upper storage section 22 is provided on the lower front surface 21e of the lower storage section 21. The upper storage section 22 also has a rectangular parallelepiped shape. In a plan view, the upper storage section 22 is surrounded on all four sides by long side walls 22a, short side walls 22b, long side walls 22c, and short side walls 22d. The upper storage section 22 includes an upper front surface 22e in an opening surrounded by the long side walls 22a, short side walls 22b, long side walls 22c, and short side walls 22d. The long side walls 22a and 22c may have the same length as the long side walls 21a and 21c of the lower storage section 21.

[0026] The upper storage section 22 is provided integrally with the lower front surface 21e of the lower storage section 21 at the center in the ±Y direction of the lower front surface 21e. The area of ​​the lower front surface 21e of the lower storage section 21 where the upper storage section 22 is formed is open. The long side walls 22a, 22c are integrally connected to the lower front surface 21e of the lower storage section 21. The short side walls 22b, 22d are integrally connected to the short side walls 21b, 21d of the lower storage section 21 and form the same plane.

[0027] On the upper front surface 22e, output, output, positive, negative, positive, and negative wiring members 63, 63, 61, 62, 61, 62 (connection portions thereof) are respectively provided from the short side wall 22b toward the short side wall 22d (along the +X direction). The output, output, positive, negative, positive, and negative wiring members 63, 63, 61, 62, 61, 62 are also bent to face the upper front surface 22e. In this case, as shown in FIG. 1 , the output wiring member 63 is bent in the −Y direction. The positive, negative, positive, and negative wiring members 61, 62, 61, 62 are also bent in the −Y direction. The upper front surface 22e may also accommodate nuts that face the connection portions of the bent wiring members 63, 63, 61, 62, 61, 62.

[0028] The case 20 having the above configuration may be made of a thermoplastic resin, such as polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0029] 3, the semiconductor device 1 includes a heat dissipation base plate 30, a plurality of semiconductor units 10a to 10f provided on the heat dissipation base plate 30, control wiring units 50a to 50e, and wiring members 61, 62, and 63 for positive, negative, and output electrodes. The semiconductor units 10a to 10f each have the same configuration. When there is no need to distinguish between the semiconductor units 10a to 10f, they will be referred to as semiconductor unit 10. When there is no need to distinguish between the control wiring units 50a to 50e, they will be referred to as control wiring unit 50. Details of the semiconductor unit 10 will be described later.

[0030] The semiconductor device 1 has a case 20 attached to a heat dissipating base plate 30. The case 20 covers the semiconductor unit 10 on the heat dissipating base plate 30, the control wiring unit 50, and the wiring members 61, 62, and 63.

[0031] The heat dissipating base plate 30 includes a rectangular upper surface 31 (see FIG. 3) and lower surface 32 (see FIG. 2) in a plan view, and long sides 30a, short sides 30b, long sides 30c, and short sides 30d surrounding the upper surface 31 on all four sides. The heat dissipating base plate 30 is made of a metal with excellent thermal conductivity. Such metals may be, for example, aluminum, iron, silver, copper, magnesium, or an alloy containing at least one of these. The heat dissipating base plate 30 is primarily composed of copper. The surface of the heat dissipating base plate 30 may be plated to improve corrosion resistance. Examples of plating materials used in this case include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy.

[0032] A cooler (not shown) may be attached to the lower surface 32 of the heat dissipation base plate 30 of the semiconductor device 1 via thermal grease. This improves the heat dissipation performance of the semiconductor device 1. Examples of the thermal grease include silicone mixed with a metal oxide filler. Examples of the cooler include a heat sink and a water-cooled cooling device. The heat sink may have multiple fins formed thereon. The multiple fins may be formed directly on the lower surface 32 of the heat dissipation base plate 30. The heat sink may be made of, for example, aluminum, iron, silver, copper, or an alloy containing at least one of these materials, all of which have excellent thermal conductivity.

[0033] The wiring members 61, 62, and 63 are wires for positive, negative, and output, respectively, connected to the semiconductor units 10a to 10f. The wiring members 61, 62, and 63 are parallel to the long sides 30a and 30c of the heat dissipating base plate 30, and extend from the semiconductor unit 10a toward the semiconductor unit 10f.

[0034] The wiring member 61 includes a positive terminal 61a joined to each of the semiconductor units 10a to 10f. The wiring member 62 includes a negative terminal 62a joined to each of the semiconductor units 10a to 10f. The wiring member 63 includes one output terminal 63a corresponding to each of the semiconductor units 10a to 10f. The output terminals 63a are joined to each of the semiconductor units 10a to 10f. The wiring member 63 may include one or more output terminals 63a for each of the semiconductor units 10a to 10f. In this example, the wiring member 63 includes one output terminal 63a for each of the semiconductor units 10a to 10f. The joining of the wiring members 61, 62, and 63 to the semiconductor units 10a to 10f may be, for example, solder joining or ultrasonic joining. When the case 20 is attached to the heat dissipating base plate 30, the connecting portions of the wiring members 61, 62, 63 are pulled out (inserted through) from the upper front surface 22e of the upper storage section 22 of the case 20 and bent.

[0035] The wiring members 61, 62, and 63 are made of a metal with excellent conductivity. Such a metal may be, for example, silver, copper, nickel, or an alloy containing at least one of these. The surfaces of the wiring members 61, 62, and 63 may be plated to improve corrosion resistance. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy. The output terminals 63a and 63b of the wiring member 63 will be described later.

[0036] The control wiring units 50a, 50b, and 50c are disposed on the heat dissipation base plate 30 on the +Y direction side of the semiconductor units 10a, 10b, and 10c in Fig. 3, along the long side 30c. The control wiring units 50d and 50e are disposed on the heat dissipation base plate 30 on the -Y direction side of the semiconductor units 10a and 10b in Fig. 3, along the long side 30a.

[0037] Such a control wiring unit 50 has an insulating plate 51, a wiring board 52 provided on the insulating plate 51, and a control wiring member 64 joined onto the wiring board 52. Of the control wiring units 50, the control wiring units 50b and 50e may each be formed with one set of the wiring board 52 and the control wiring member 64. The other control wiring units 50 may each be formed with two sets of the wiring board 52 and the control wiring member 64.

[0038] The insulating plate 51 is made of ceramics with good thermal conductivity. Such ceramics may be made of, for example, a composite material whose main components are aluminum oxide and zirconium oxide added to the aluminum oxide, or a material whose main component is silicon nitride. The insulating plate 51 is rectangular in plan view. The corners may be round-chamfered or C-chamfered.

[0039] The wiring board 52 is made of a metal with excellent conductivity. Examples of such metals include silver, copper, nickel, or an alloy containing at least one of these. The surface of the wiring board 52 may be plated to improve corrosion resistance. Examples of plating materials used in this case include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy. The wiring board 52 for the insulating board 51 may be formed by forming a metal plate on the front surface of the insulating board 51 and then subjecting this metal plate to etching or other processing. Alternatively, the wiring board 52 may be cut out from a metal plate in advance and pressure-bonded to the front surface of the insulating board 51. The wiring board 52 shown in FIG. 3 is an example. The number, shape, size, and other factors of the wiring boards 52 may be appropriately selected as needed.

[0040] The control wiring member 64 is made of a metal with excellent conductivity. Such metals are, for example, silver, copper, nickel, or an alloy containing at least one of these. The surface of the wiring member 64 may be plated to improve corrosion resistance. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy. Such wiring member 64 is, for example, in the shape of a strip, and has a substantially uniform thickness overall.

[0041] The lower end of the wiring member 64 is joined to the wiring board 52. This joining is performed using a joining material. Alternatively, ultrasonic joining may be used. The joining material may be, for example, solder or a metal sintered body. Lead-free solder is used as the solder. Lead-free solder is primarily composed of an alloy containing at least two of tin, silver, copper, zinc, antimony, indium, and bismuth. The solder may also contain additives. Examples of additives include nickel, germanium, cobalt, and silicon. The addition of additives to the solder improves its wettability, gloss, and bonding strength, thereby improving reliability. The sintering material used in the metal sintered body is, for example, powder of silver, iron, copper, aluminum, titanium, nickel, tungsten, molybdenum, or an alloy containing any of these.

[0042] When the case 20 is attached to the heat dissipating base plate 30, the connecting portions of the wiring members 64 are pulled out (inserted through) from the control terminal areas 21e1 to 21e5 of the upper storage section 22 of the case 20, and the pulled out portions are bent.

[0043] Next, the semiconductor unit 10 included in the semiconductor device 1 will be described with reference to FIGS. 4 to 6. FIG. 4 is a plan view of a semiconductor unit included in the semiconductor device of the first embodiment. FIG. 5 is a plan view of an insulating circuit board included in the semiconductor device of the first embodiment, and FIG. 6 is a cross-sectional view of the insulating circuit board included in the semiconductor device of the first embodiment. Note that FIG. 5 omits the control conductive patterns 13d, 13e and the sense conductive patterns 13f, 13g from the insulating circuit board 11 included in the semiconductor unit 10 shown in FIG. 4. FIG. 5 also indicates the connection region 13d1 of the control conductive pattern 13d with a dashed line. FIG. 6 is a cross-sectional view taken along the dashed-dotted line Y-Y in FIG. 5.

[0044] The semiconductor units 10 are arranged on the heat dissipating base plate 30 with their long sides 30a and 30c parallel to each other, and adjacent semiconductor units 10 are electrically connected to each other by wires (not shown). The semiconductor unit 10 includes at least an insulating circuit board 11, semiconductor chips 15a and 15b, and semiconductor chips 16a and 16b. Furthermore, as will be described later, main current wires 17a and 17b and control wires 18a1, 18a2, 18b1, and 18b2 are wired.

[0045] The insulating circuit boards 11 are arranged in a row on the upper surface 31 of the heat dissipating base plate 30 along the long sides 30a, 30c of the heat dissipating base plate 30. The insulating circuit boards 11 may be joined to the upper surface 31 of the heat dissipating base plate 30 via a joining member (not shown). Examples of the joining member include the solder and sintered metal described above, as well as brazing filler metal. The brazing filler metal contains, for example, at least one of an aluminum alloy, a titanium alloy, a magnesium alloy, a zirconium alloy, and a silicon alloy as its main component. The insulating circuit boards 11 can be joined by brazing using such a joining member.

[0046] The insulating circuit board 11 has an insulating plate 12, a plurality of conductive patterns formed on the front surface of the insulating plate 12, and a metal plate 14 formed on the back surface of the insulating plate 12. Note that the cross-sectional view of the insulating circuit board 11 shown in FIG. 6 can be referred to for the metal plate 14. The insulating plate 12 and the metal plate 14 are rectangular in plan view. The corners of the insulating plate 12 and the metal plate 14 may be round-chamfered or C-chamfered. The size of the metal plate 14 is such that it is formed over the entire back surface of the insulating plate 12 except for the outer periphery of the insulating plate 12 in plan view.

[0047] The insulating plate 12 has a rectangular shape in a plan view, and is surrounded on all four sides by long sides 12a, short sides 12b, long sides 12c, and short sides 12d, in that order. Here, the long sides 12a and 12c are parallel to the ±Y direction, and the short sides 12b and 12d are parallel to the ±X direction. The insulating plate 12 is mainly composed of a material that has insulating properties and excellent thermal conductivity. Such a material may be ceramic or insulating resin. Examples of ceramics include aluminum oxide, aluminum nitride, and silicon nitride. Examples of insulating resins include paper-phenolic substrates, paper-epoxy substrates, glass composite substrates, and glass-epoxy substrates.

[0048] The plurality of conductive patterns are primarily composed of a metal with excellent conductivity. Such metals are, for example, copper, aluminum, or an alloy primarily composed of at least one of these. Furthermore, the surfaces of the plurality of conductive patterns may be plated to improve corrosion resistance. Examples of plating materials used in this case include nickel, nickel-phosphorus alloy, and nickel-boron alloy. The number, shape, size, and other characteristics of the plurality of conductive patterns may be appropriately selected as needed.

[0049] The plurality of conductive patterns include a positive conductive pattern 13a, a negative conductive pattern 13b, an output conductive pattern 13c, control conductive patterns 13d and 13e, and sense conductive patterns 13f and 13g.

[0050] The positive conductive pattern 13a includes a chip region 13a1 and a terminal region 13a2 (see FIG. 5). The chip region 13a1 is rectangular in plan view and is disposed on the long side 12a of the insulating plate 12, parallel to the long side 12a. The chip region 13a1 is closer to the short side 12d than the center of the insulating plate 12 in the ±Y direction. The width of the chip region 13a1 in the ±X direction may be approximately half the width of the insulating plate 12 in the same direction. On the −Y direction side of the chip region 13a1, two semiconductor chips 15b are bonded by bonding members 19 side by side in the ±X direction, with their control electrodes 15b1 facing the short side 12d. Furthermore, a semiconductor chip 16b is disposed on the chip region 13a adjacent to the semiconductor chip 15b on the +Y direction side by bonding members 19. The bonding members 19 may be, for example, the solder or sintered metal described above.

[0051] The terminal region 13a2 is connected to the −Y-direction end of the chip region 13a1 and extends from that end in the +X-direction (toward the long side 12c) in parallel to the short sides 12b and 12d. The +X-direction end of the terminal region 13a2 extends further in the +X-direction than the +X-direction end of the chip region 13a1. A positive terminal 61a of the wiring member 61 is joined to the terminal region 13a2.

[0052] The negative conductive pattern 13b is disposed adjacent in the +X direction to a portion of the positive conductive pattern 13a that includes the terminal region 13a2 on the −Y direction side (see FIG. 5 ). The negative conductive pattern 13b is adjacent to both the positive conductive pattern 13a and the chip region 13c1 of the output conductive pattern 13c. The negative conductive pattern 13b is generally rectangular in plan view and includes a portion that protrudes in the −X direction from the +Y direction (short side 12b) side of the end portion on the −X direction (long side 12a). This protruding portion of the negative conductive pattern 13b is disposed between the terminal region 13a2 of the positive conductive pattern 13a and the chip region 13c1 of the output conductive pattern 13c. A negative terminal 62a of the wiring member 62 is joined to the negative conductive pattern 13b. The negative terminal 62a and the positive terminal 61a are disposed parallel to each other in the ±X directions and in a line.

[0053] The output conductive pattern 13c includes a chip region 13c1 and a terminal region 13c2 (see FIG. 5). The chip region 13c1 is approximately the same size as the chip region 13a1 of the positive conductive pattern 13a. The chip region 13c1 has sides extending in the +Y direction and in the −X direction perpendicular to the +Y direction, forming a rectangular shape in a plan view, and is disposed on the long side 12c side of the insulating plate 12 and parallel to the long side 12c. The chip region 13c1 is closer to the short side 12b than the center of the insulating plate 12 in the ±Y directions. That is, the chip region 13c1 is located closer to the short side 12b than the chip region 13a1 of the positive conductive pattern 13a. The width of the chip region 13c1 in the ±X directions may be approximately half the width of the insulating plate 12 in the same direction. Two semiconductor chips 15a are bonded in parallel to the chip region 13c1 on the +Y direction side with their control electrodes 15a1 facing the short side 12b via bonding members 19. That is, the two semiconductor chips 15a are arranged with their control electrodes 15a1 facing the first direction (+Y direction) opposite the negative conductive pattern 13b (toward the short side 12b). Furthermore, a semiconductor chip 16a is bonded to the two semiconductor chips 15a on the -Y direction side of the chip region 13a1 via bonding members 19, adjacent to the chip region 13a1.

[0054] The terminal region 13c2 is connected to the end of the chip region 13c1 in the +Y direction. The terminal region 13c2 extends from the +X direction side (first side) of the end to the -X direction side (second side). The terminal region 13c2 is parallel to the short sides 12b and 12d and extends to the long side 12a. An output terminal 63a of the wiring member 63 is joined to the terminal region 13c2. The output terminal 63a is located at the center of the width of the terminal region 13c2 in the ±X directions.

[0055] The terminal region 13c2 includes a recess 13c3. The recess 13c3 is recessed from the +X direction side (first side) to the −X direction side (second side) relative to the terminal region 13c2 of the output conductive pattern 13c in a plan view. The recess 13c3 has a U-shape with an opening facing the +X direction side in a plan view. The recess 13c3 may be located in the terminal region 13c2 between the center line C and the end A of the chip region 13c1. It is preferable that the position of the recess 13c3 be closer to the end A and closer to the chip region 13c1.

[0056] The terminal region 13c2 also includes a coupling region 13c4. The coupling region 13c4 is connected when the semiconductor unit 10 is wired to another semiconductor unit 10 that is adjacent to the semiconductor unit 10 on the +X-direction side of the semiconductor unit 10. The coupling region 13c4 is located along the recess 13c3 of the terminal region 13c2 and is included at the end of the recess 13c3 on the +X-direction side (first side).

[0057] The control conductive pattern 13d includes a connection region 13d1 at its end. The connection region 13d1 is disposed in a recess 13c3 of the output conductive pattern 13c. The control conductive pattern 13d is substantially L-shaped in plan view, and extends from the connection region 13d1 along the outer edge of the terminal region 13c2 of the output conductive pattern 13c, parallel to the long side 12c and the short side 12b, and to the long side 12a.

[0058] The control conductive pattern 13e includes a connection region 13e1 at its end. The connection region 13e1 is disposed adjacent to the terminal region 13a2 of the positive conductive pattern 13a in the −X direction. The control conductive pattern 13e is generally L-shaped in plan view, and extends from the connection region 13e1 along the outer edges of the terminal region 13a2 of the positive conductive pattern 13a and the negative conductive pattern 13b, parallel to the short side 12d, to the long side 12c.

[0059] The sense conductive pattern 13f is parallel to the long side 12c and the short side 12b along the control conductive pattern 13d and extends to the long side 12a. The end of the sense conductive pattern 13f on the long side 12c side is electrically connected to the output electrode 15a2 of the semiconductor chip 15a by a sense wire 18a3. The sense conductive pattern 13g is parallel to the long side 12a and the short side 12d along the control conductive pattern 13e and extends to the long side 12c. The end of the sense conductive pattern 13g on the long side 12a side is electrically connected to the output electrode 15b2 of the semiconductor chip 15b by a sense wire 18b3.

[0060] The metal plate 14 has a smaller area than the insulating plate 12 and is rectangular like the insulating plate 12. The corners may be rounded or chamfered. The metal plate 14 is smaller than the insulating plate 12 and is formed on the entire surface of the insulating plate 12 except for the edges. The metal plate 14 is primarily composed of a metal with excellent thermal conductivity. The metal may be, for example, copper, aluminum, or an alloy containing at least one of these. In the semiconductor device 1 of this embodiment, the metal plate 14 is primarily composed of copper. A plating process may be performed to improve the corrosion resistance of the metal plate 14. Examples of plating materials used in this process include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy.

[0061] As the insulating circuit board 11 having such a configuration, for example, a DCB (Direct Copper Bonding) board, an AMB (Active Metal Brazed) board, or a resin insulating board can be used.

[0062] The semiconductor chips 15a and 15b are made primarily of silicon and include the same type of switching elements, such as insulated gate bipolar transistors (IGBTs). The withstand voltage of the semiconductor chips 15a and 15b is 1200V.

[0063] The semiconductor chips 15a and 15b each have a collector electrode as an input electrode on their back surface, and gate electrodes as control electrodes 15a1 and 15b1 and emitter electrodes as output electrodes 15a2 and 15b2 on their front surfaces. The control electrodes 15a1 and 15b1 may be provided at the center of one side of the front surface of the semiconductor chips 15a and 15b. Alternatively, the control electrodes 15a1 and 15b1 do not necessarily have to be provided at the center of one side of the front surface of the semiconductor chips 15a and 15b, and may be offset from the center in the ±X directions. The width of the semiconductor chips 15a and 15b in the ±X directions may be less than half the width in the same direction of a chip region 13c1 of the output conductive pattern 13c, which will be described later.

[0064] The semiconductor chips 16a and 16b are made primarily of silicon and include the same type of diode elements. The diode elements are, for example, free wheeling diodes (FWDs) such as Schottky barrier diodes (SBDs) and P-intrinsic-N (PiN) diodes. The semiconductor chips 16a and 16b each have an output electrode (cathode electrode) as a main electrode on the back surface and input electrodes 16a1 and 16b1 (anode electrodes) as main electrodes on the front surface.

[0065] The semiconductor chips 15a and 15b have control electrodes 15a1 and 15b1 facing the short sides 12b and 12d, and are bonded in parallel to the output conductive pattern 13c and the positive conductive pattern 13a, respectively. That is, the control electrode 15a1 is provided on the side of the front surface of the semiconductor chip 15a in the +Y direction. The control electrode 15b1 is provided on the side of the front surface of the semiconductor chip 15b in the -Y direction. The semiconductor chip 16a is bonded to the output conductive pattern 13c adjacent to the semiconductor chip 15a in the -Y direction. The semiconductor chip 16b is bonded to the positive conductive pattern 13a adjacent to the semiconductor chip 15b in the +Y direction. The bonding here can be achieved using the aforementioned solder or a sintered metal.

[0066] The output electrode 15a2 of the semiconductor chip 15a, the input electrode 16a1 of the semiconductor chip 16a, and the negative electrode conductive pattern 13b are electrically connected by a main current wire 17a. The control electrode 15a1 of the semiconductor chip 15a and the connection region 13c3 of the control conductive pattern 13d are electrically connected by control wires 18a1 and 18a2, respectively. The end of the sense conductive pattern 13f and the output electrode 15a2 of the semiconductor chip 15a are electrically connected by a sense wire 18a3.

[0067] The output electrode 15b2 of the semiconductor chip 15b, the input electrode 16b1 of the semiconductor chip 16b, and the output conductive pattern 13c are electrically connected by a main current wire 17b. The control electrode 15b1 of the semiconductor chip 15b and the control conductive pattern 13e are electrically connected by control wires 18b1 and 18b2. The end of the sense conductive pattern 13g and the output electrode 15b2 of the semiconductor chip 15b are electrically connected by a sense wire 18b3.

[0068] The main current wires 17a and 17b, the control wires 18a1, 18a2, 18b1, and 18b2, and the sense wires 18a3 and 18b3 are primarily made of a material with excellent conductivity. Such materials include, for example, gold, copper, aluminum, or an alloy containing at least one of these. Preferably, the main current wires 17a and 17b and the control wires 18a1, 18a2, 18b1, and 18b2 are made of an aluminum alloy containing a trace amount of silicon. The main current wires 17a and 17b have a larger diameter than the control wires 18a1, 18a2, 18b1, and 18b2 and the sense wires 18a3 and 18b3.

[0069] Here, a semiconductor unit 100 of a reference example in comparison with the semiconductor unit 10 will be described with reference to FIG. 7. FIG. 7 is a plan view of a semiconductor unit included in the semiconductor device of the reference example. In the semiconductor device of the reference example, the semiconductor unit 100 is applied instead of the semiconductor unit 10 in the semiconductor device 1 of the first embodiment. The semiconductor unit 100 differs only in the shape of the circuit pattern of the semiconductor unit 10. The other configurations and wiring are the same as those of the semiconductor unit 10.

[0070] The semiconductor unit 100 also includes a plurality of conductive patterns, including a positive conductive pattern 103a, a negative conductive pattern 103b, an output conductive pattern 103c, control conductive patterns 103d and 103e, and sense conductive patterns 103f and 103g.

[0071] The positive conductive pattern 103a is provided on the long side 12a of the insulating plate 12, separated from the short sides 12b and 12d, and is configured to be parallel to the long side 12a and the short side 12d and to form a generally L-shape. A positive terminal 61a of the wiring member 61 is joined to the positive conductive pattern 103a. The positive terminal 61a of the wiring member 61 is joined to the short side 12d of the positive conductive pattern 103a.

[0072] The negative electrode conductive pattern 103b is provided on the long side 12c side of the insulating plate 12 and separated from the short sides 12b and 12d. The negative electrode conductive pattern 103b is joined to the negative electrode terminal 62a of the wiring member 62. The negative electrode terminal 62a of the wiring member 62 is joined to the short side 12d side of the negative electrode conductive pattern 103b.

[0073] The output conductive pattern 103c is substantially L-shaped in plan view and includes portions parallel to the long side 12c and short side 12b of the insulating plate 12. The output conductive pattern 103c is provided on the long side 12c side of the insulating plate 12 and separated from the short side 12d. The output conductive pattern 103c faces the short side 12b and has a recess on the long side 12c side. As in the first embodiment, one output terminal 63a of the wiring member 63 is joined to the output conductive pattern 103c. The output terminal 63a of the wiring member 63 is joined to the center of the width of the output conductive pattern 103c in the ±X directions.

[0074] The control conductive patterns 103d and 103e each have a substantially L-shape in a plan view. The control conductive pattern 103d includes a connection region 103d1 disposed in a recess of the output conductive pattern 103c, and is provided adjacent to the output conductive pattern 103c on the +Y direction side and parallel to the short side 12b. The control conductive pattern 103e is provided adjacent to the positive conductive pattern 103a and the negative conductive pattern 103b in the -Y direction and parallel to the short side 12d.

[0075] The sense conductive patterns 103f and 103g are substantially L-shaped in plan view. The sense conductive patterns 103f are provided on the long side 12c and short side 12b sides and parallel to the long side 12c and short side 12b. The sense conductive patterns 103g are provided on the long side 12a and short side 12d sides and parallel to the long side 12a and short side 12d.

[0076] In the semiconductor unit 100 described above, the wiring member 63 is joined to the output conductive pattern 103c by one output terminal 63a. In recent years, semiconductor chips 15a have become higher in voltage and current. In particular, the output terminal 63a that outputs a high voltage needs to have sufficient withstand voltage characteristics with respect to the connection region 103d1 of the control conductive pattern 103d. In order to ensure sufficient withstand voltage characteristics, it is necessary to ensure a sufficient distance between the output terminal 63a and the connection region 103d1 of the control conductive pattern 103d.

[0077] The semiconductor device 1 includes a semiconductor chip 15a, an output conductive pattern 13c, an output terminal 63a, and a control conductive pattern 13d. The semiconductor chip 15a includes a control electrode 15a1 provided on a side of the front surface in the first direction (+Y direction).

[0078] The output conductive pattern 13c includes a chip region 13c1 and a terminal region 13c2. The chip region 13c1 has sides extending in a first direction (+Y direction) and a second direction (-X direction) perpendicular to the first direction, and the semiconductor chip 15a is disposed in the chip region 13c1.

[0079] The terminal region 13c2 is connected to a side of the chip region 13c1 in the first direction (+Y direction) and extends in a second direction (-X direction) from a first side (+X direction) of the side of the chip region 13c1 in the first direction (+Y direction) to a second side (-X direction) of the side of the chip region 13c1 in the first direction (+Y direction). The output terminal 63a is disposed in the terminal region 13c2 of the output conductive pattern 13c.

[0080] The control conductive pattern 13d includes a connection region 13d1 electrically connected to the control electrode 15a1. The control conductive pattern 13d is adjacent to the side of the terminal region 13c2 opposite to the chip region 13c1 in plan view.

[0081] Furthermore, the terminal region 13c2 of the output conductive pattern 13c has a recess 13c3 that is recessed from the first side to the second side on the +X direction side of the terminal region 13c2, adjacent to the chip region 13c1 in plan view. The connection region 13d1 of the control conductive pattern 13d is provided in the recess 13c3.

[0082] The connection region 13d1 of the control conductive pattern 13d is farther away from the output terminal 63a than in the reference example, for example. Therefore, a sufficient voltage resistance characteristic can be ensured between the connection region 13d1 of the control conductive pattern 13d and the output terminal 63a. As a result, the occurrence of failures in the semiconductor chip 15a is suppressed, and a decrease in the reliability of the semiconductor device 1 is suppressed.

[0083] Second Embodiment In the second embodiment, the wiring member 63 of the first embodiment includes at least two output terminals for each semiconductor unit 10. Although it is also possible to include three or more output terminals, for the sake of explanation, a configuration with two output terminals will be described here. First, a semiconductor device in this case will be described with reference to FIG. 8. FIG. 8 is a plan view of the semiconductor device of the second embodiment (with the case removed).

[0084] 1 and 2. However, the wiring member 63 included in the semiconductor device 1 of the second embodiment has two output terminals 63a and 63b corresponding to each of the semiconductor units 10a to 10f. The output terminals 63a and 63b are bonded to the semiconductor units 10a to 10f, respectively.

[0085] Next, a semiconductor unit 10 included in a semiconductor device 1 according to a second embodiment will be described with reference to FIGS. 9 and 10. FIG. 9 is a plan view of the semiconductor unit included in the semiconductor device according to the second embodiment, and FIG. 10 is a plan view of an insulating circuit board included in the semiconductor device according to the second embodiment. Note that FIG. 10 omits the control conductive patterns 13d, 13e and the sense conductive patterns 13f, 13g from the insulating circuit board 11 included in the semiconductor unit 10 shown in FIG. 10 also indicates a connection region 13d1 of the control conductive pattern 13d with a dashed line.

[0086] In the semiconductor unit 10 of the second embodiment, as shown in FIGS. 9 and 10, two output terminals 63a and 63b are arranged side by side in the ±X direction in the terminal region 13c2 of the output conductive pattern 13c included in the insulating circuit board 11 of the first embodiment.

[0087] As described above, semiconductor chips 15a have become increasingly higher in voltage and current in recent years. Therefore, using two output terminals 63a and 63b makes it easier for current to flow through the wiring member 63 compared to using only one output terminal 63a. However, in this case, the distance between the output terminals 63a and 63b must be at least a certain distance. If the distance between the output terminals 63a and 63b is narrow, heat generated by the output terminals 63a and 63b due to current flow can cause thermal interference. Therefore, by providing a certain distance between the output terminals 63a and 63b, the temperatures of the output terminals 63a and 63b can be lowered, thereby lowering the temperature of the semiconductor unit 10. The number of output terminals is not limited to two, but may be three or more. The three output terminals are arranged side by side in the ±X direction on the terminal portion 13c2 of the output conductive pattern 13c. Even in this case, the distance between each output terminal must be at least a certain distance.

[0088] Because the output terminals 63a and 63b must be spaced apart at least a certain distance on the lower arm side of the semiconductor unit 10, there is a concern that the shortest distance D1 between the output terminal 63a, which is closest to the connection portion 13d1, and the control wire 18a1 may become too close. If the shortest distance D1 becomes too small, partial discharge may occur when a voltage is applied to the output terminal 63a. This may result in a short circuit between the output terminal 63a and the control wire 18a1, increasing the likelihood of failure of the semiconductor chip 15a. Note that even when there are three or more output terminals, there is a concern that the shortest distance D1 between the output terminal closest to the connection portion 13d1 and the control wire 18a1 may become too small.

[0089] However, in the second embodiment, the connection region 13d1 of the control conductive pattern 13d included in the insulating circuit board 11 is spaced away from the output terminal 63a toward the long side 12c. This allows the shortest distance D1 between the control wire 18a1 and the output terminal 63a to be increased. As a result, even when a voltage is applied to the output terminal 63a, partial discharge does not occur between the control wire 18a1 and the output terminal 63a, preventing a short circuit between the output terminal 63a and the control wire 18a1. As a result, the occurrence of failures in the semiconductor chip 15a is suppressed.

[0090] On the upper arm side of the semiconductor unit 10, the wiring member 61 has only one positive electrode terminal 61a, and therefore the position can be changed as needed. Therefore, the shortest distance D2 between the control wire 18b1 and the positive electrode terminal 61a can be sufficiently secured, and a short circuit does not occur between the control wire 18b1 and the positive electrode terminal 61a.

[0091] Next, the shortest distance D1 between the control wire 18a1 and the output terminal 63a will be described using Fig. 11. Fig. 11 is a graph showing the terminal-to-wire distance required to suppress discharge relative to the voltage. The horizontal axis of Fig. 11 represents the applied voltage [V], and the vertical axis represents the terminal-to-wire distance [mm] required to suppress discharge relative to the voltage.

[0092] According to the graph in Figure 11, as the applied voltage increases, the terminal-to-wire distance required to suppress discharge also increases accordingly. The withstand voltage of the semiconductor chip 15a is 1200V. According to the graph in Figure 11, the distance required for this voltage is approximately 1.5 mm. In the cases of Figures 9 and 10, the actual shortest distance D1 was approximately 2.5 mm. Because this is greater than 1.5 mm, the occurrence of partial discharge from the output terminal 63a to the control wire 18a1 is suppressed.

[0093] Therefore, in the semiconductor device 1 of the second embodiment, the connection region 13d1 of the control conductive pattern 13d is separated from the output terminal 63a. This ensures sufficient voltage resistance characteristics between the connection region 13d1 of the control conductive pattern 13d and the output terminal 63a. Furthermore, the output terminals 63a and 63b can be spaced apart. As a result, the ease with which current flows through the wiring member 63 of the output terminals 63a and 63b is improved, while the occurrence of failures in the semiconductor chip 15a is suppressed, and a decrease in the reliability of the semiconductor device 1 is suppressed.

[0094] Third Embodiment In a second embodiment, a case where a semiconductor chip is different from that in the second embodiment will be described with reference to Fig. 12. Fig. 12 is a plan view of a semiconductor unit included in a semiconductor device of the third embodiment.

[0095] 12 also includes at least an insulating circuit board 11 and semiconductor chips 15a and 15b. Furthermore, in the semiconductor unit 10, main current wires 17a and 17b, control wires 18a1, 18a2, 18b1, and 18b2, and sense wires 18a3 and 18b3 are wired, similarly to the semiconductor units 10 of the first and second embodiments. Furthermore, in the semiconductor unit 10, positive and negative terminals 61a and 62a of wiring members 61 and 62, and two output terminals 63a and 63b of wiring member 63 are respectively connected, similarly to the semiconductor unit 10 of the second embodiment.

[0096] However, the semiconductor chips 15a and 15b included in the semiconductor unit 10 of this embodiment are RC (Reverse Conducting)-IGBTs (Reverse Conducting Insulated Gate Bipolar Transistors), and the withstand voltage of these semiconductor chips 15a and 15b is 1700V.

[0097] The width of the semiconductor chip 15a in the ±X directions is equal to or less than the width of the chip region 13c1 of the output conductive pattern 13c in the ±X directions. The width of the semiconductor chip 15b in the same direction is also equal to or less than the width of the chip region 13a1 of the positive conductive pattern 13a in the same direction. Two semiconductor chips 15a are joined to the chip region 13c1 of the output conductive pattern 13c side by side in the ±Y directions via bonding members 19. Two semiconductor chips 15b are joined to the chip region 13a1 of the positive conductive pattern 13a side by side in the ±Y directions via bonding members 19.

[0098] Furthermore, the control electrode 15a1 of the semiconductor chip 15a and the connection region 13d1 of the control conductive pattern 13d are electrically connected by a control wire 18a1. In this embodiment, the connection region 13d1 of the control conductive pattern 13d is also provided in the recess 13c3 of the output conductive pattern 13c. Therefore, the connection region 13d1 of the control conductive pattern 13d is separated from the output terminal 63a. Therefore, the shortest distance D1 between the control wire 18a1 connecting the connection region 13d1 of the control conductive pattern 13d and the output terminal 63a, which is closest to the connection portion 13d1, of the two output terminals 63a and 63b, can be made longer than a predetermined distance. As described above, the withstand voltage of the semiconductor chip 15a is 1700V. According to FIG. 11, the terminal-to-wire distance at which discharge occurs at 1700V is approximately 2.2 mm. In the case of Figure 12, the actual shortest distance D1 is approximately 3.18 mm, which is greater than 2.2 mm. Therefore, sufficient voltage resistance characteristics can be ensured between the connection region 13d1 of the control conductive pattern 13d and the output terminal 63a. Furthermore, the occurrence of partial discharge between the output terminal 63a and the control wire 18a1 is suppressed, and short-circuiting between the output terminal 63a and the control wire 18a1 is prevented. As a result, the ease of current flow in the output terminals 63a and 63b is improved, while the occurrence of failures in the semiconductor chip 15a is suppressed, and a decrease in the reliability of the semiconductor device 1 is suppressed.

[0099] In this example, the semiconductor chips 15a and 15b are described as RC-IGBTs. Instead of RC-IGBTs, power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) primarily composed of silicon carbide may be used for the semiconductor chips 15a and 15b. In this power MOSFET, the body diode functions as the FWD. The semiconductor chips 15a and 15b each have a drain electrode as an input electrode on the back surface, and a gate electrode as a control electrode and a source electrode as an output electrode on the front surface.

[0100] [Fourth Embodiment] In a fourth embodiment, a case in which the recess 13c3 of the output conductive pattern 13c is different from that in the third embodiment will be described with reference to Fig. 13. Fig. 13 is a plan view of a semiconductor unit included in a semiconductor device of the fourth embodiment.

[0101] 13 also includes at least an insulating circuit board 11 and semiconductor chips 15a and 15b, similar to the semiconductor unit 10 of the third embodiment. Furthermore, the semiconductor unit 10 is wired with main current wires 17a and 17b, control wires 18a1 and 18a2, and sense wires 18a3 and 18b3, similar to the semiconductor unit 10 of the third embodiment. Furthermore, similar to the semiconductor unit 10 of the second embodiment, the semiconductor unit 10 is bonded with positive and negative terminals 61a and 62a of wiring members 61 and 62 and output terminals 63a and 63b of wiring member 63.

[0102] However, the shape of the recess 13c3 of the output conductive pattern 13c included in the semiconductor unit 10 of this embodiment is different from that of the second embodiment. The recess 13c3 is recessed from the +X direction side (first side) to the −X direction side (second side) relative to the terminal region 13c2 of the output conductive pattern 13c in a plan view. The recess 13c3 is formed by cutting out the corners of the terminal region 13a2 in a plan view. Such a recess 13c3 has an L-shape facing the +X direction and the +Y direction in a plan view. In this case, the recess 13c3 may also be located in the terminal region 13c2 between the center line C and the end A of the chip region 13c1. It is preferable that the recess 13c3 be located closer to the end A and closer to the chip region 13c1.

[0103] The control conductive pattern 13d is L-shaped according to the shape of the recess 13c3. A connection region 13d1 of the control conductive pattern 13d is disposed in the recess 13c3 of the output conductive pattern 13c. The control conductive pattern 13d extends from the connection region 13d1 along the outer edge of the terminal region 13c2 of the output conductive pattern 13c, in parallel with the long side 12c and the short side 12b, to the long side 12a.

[0104] Even in this case, the connection region 13d1 of the control conductive pattern 13d is separated from the output terminal 63a, which is closest to the connection portion 13d1, of the two output terminals 63a, 63b. Therefore, the shortest distance D1 between the connection region 13d1 of the control conductive pattern 13d and the output terminal 63a of the control wire 18a1 connecting the connection region 13d1 of the control conductive pattern 13d and the control electrode 15a1 of the semiconductor chip 15a can be made longer than a predetermined distance. Therefore, sufficient voltage resistance characteristics can be ensured between the connection region 13d1 of the control conductive pattern 13d and the output terminal 63a. Furthermore, the output terminals 63a and 63b can be spaced apart. As a result, the ease of current flow in the output terminals 63a, 63b is improved, the occurrence of failures in the semiconductor chip 15a is suppressed, and a decrease in the reliability of the semiconductor device 1 is suppressed.

[0105] In this example, RC-IGBTs are used for the semiconductor chips 15a and 15b. In this case, similar to the first embodiment, semiconductor chips 15a and 15b including switching elements may be used together with semiconductor chips 16a and 16b including diode elements.

[0106] The foregoing merely illustrates the principles of the present invention. Further, since numerous modifications and changes will be apparent to those skilled in the art, the present invention is not limited to the exact construction and application shown and described above, and all corresponding modifications and equivalents are deemed to be within the scope of the present invention as defined by the appended claims and their equivalents.

[0107] 1 Semiconductor device 10, 10a to 10f Semiconductor unit 11 Insulated circuit board 12 Insulating plate 12a, 12c Long side 12b, 12d Short side 13a Positive conductive pattern 13a1 Chip area 13a2 Terminal area 13b Negative conductive pattern 13c Output conductive pattern 13c1 Chip area 13c2 Terminal area 13c3 Recess 13c4 Connection area 13d, 13e Control conductive pattern 13d1, 13e1 Connection area 13f, 13g Sense conductive pattern 14 Metal plate 15a, 15b Semiconductor chip 15a1, 15b1 Control electrode 15a2, 15b2 Output electrode 16a, 16b Semiconductor chip (diode) 16a1, 16b1 Input electrode 17a, 17b Main current wire 18a1, 18a2, 18b1, 18b2 Control wires 18a3, 18b3 Sense wires 19 Joint member 20 Case 21 Lower storage section 21a, 21c Long side walls 21b, 21d Short side walls 21e Lower front surface 21e1 to 21e5 Terminal area 22 Upper storage section 22a, 22c Long side walls 22b, 22d Short side walls 22e Upper front surface 30 Heat dissipation base plate 30a, 30c Long sides 30b, 30d Short sides 31 Upper surface 32 Lower surface 50, 50a to 50e Control wiring unit 51 Insulating plate 52 Wiring board 61 to 64 Wiring members (for positive electrode, negative electrode, output, control) 61a Positive electrode terminal 62a: negative terminal 63a, 63b: output terminals

Claims

1. A semiconductor device comprising: a first semiconductor chip including a control electrode provided on a side portion in a first direction on its front surface; an output conductive pattern including a rectangular first portion having sides extending in the first direction and a second direction perpendicular to the first direction, in which the first semiconductor chip is arranged, and a second portion connected to the side of the first portion in the first direction and extending from a first side of the side in the first direction to a second side; an output terminal arranged on the second portion of the output conductive pattern; and a control conductive pattern including a connection portion electrically connected to the control electrode and adjacent to the second portion of the output conductive pattern on the opposite side to the first portion in a planar view, wherein the second portion of the output conductive pattern has a recess adjacent to the first portion on the first side in a planar view and recessed from the first side toward the second side, and the connection portion of the control conductive pattern is provided in the recess.

2. The semiconductor device according to claim 1, wherein one output terminal is provided, and the one output terminal is disposed at a center portion of the width in the second direction of the second portion of the output conductive pattern.

3. The semiconductor device according to claim 1, wherein at least two of the output terminals are provided, and the at least two output terminals are arranged side by side in the second direction on the second portion of the output conductive pattern.

4. The semiconductor device according to claim 3, wherein the control electrode is provided at the center of the side portion of the front surface of the first semiconductor chip.

5. The semiconductor device described in claim 4, wherein the width of the first semiconductor chip in the second direction is less than half the width of the first portion of the output conductive pattern in the second direction, and two of the first semiconductor chips are arranged side by side in the second direction on the first portion of the output conductive pattern.

6. The semiconductor device described in claim 5, wherein the first semiconductor chip further includes an output electrode provided on the front surface, and further includes a second semiconductor chip including a diode element arranged on the first portion of the output conductive pattern adjacent to the side of the first semiconductor chip opposite the second portion of the output conductive pattern, and the second semiconductor chip is electrically connected to the output electrode of the first semiconductor chip and the first portion of the output conductive pattern.

7. The semiconductor device according to claim 4, wherein the width in the second direction of the first semiconductor chip is less than or equal to the width in the second direction of the first portion of the output conductive pattern, and one first semiconductor chip is arranged in the first portion of the output conductive pattern.

8. The semiconductor device according to claim 5 or 7, further comprising a wire connecting the connection portion of the control conductive pattern and the control electrode of the first semiconductor chip, wherein the shortest distance from the wire to the output terminal closest to the connection portion among the at least two output terminals in a planar view is 1.5 mm or more.

9. The semiconductor device according to claim 5 or 7, wherein the withstand voltage of the first semiconductor chip is 1200V.

10. The semiconductor device according to claim 5 or 7, wherein the first semiconductor chip is an insulated gate bipolar transistor.

11. The semiconductor device according to claim 5 or 7, further comprising a wire connecting the connection portion of the control conductive pattern and the control electrode of the first semiconductor chip, wherein the shortest distance from the wire to the output terminal closest to the connection portion among the at least two output terminals in a planar view is 2.2 mm or more.

12. The semiconductor device according to claim 5 or 7, wherein the withstand voltage of the first semiconductor chip is 1700V.

13. The semiconductor device according to claim 5 or 7, wherein the first semiconductor chip is a reverse conducting insulated gate bipolar transistor.

14. The semiconductor device according to claim 1, wherein the control electrode is provided on the first side or the second side of the center of the side portion of the front surface.

15. The semiconductor device according to claim 1, wherein the second portion of the output conductive pattern includes a coupling region electrically connected to another external output conductive pattern.

16. The semiconductor device according to claim 15, wherein the recess included in the second portion of the output conductive pattern has a U-shape with an opening facing the first side in a plan view.

17. The semiconductor device according to claim 16, wherein the connection region is included along the recess at an end of the recess on the first side.

18. The semiconductor device according to claim 1, wherein the recess included in the second portion of the output conductive pattern is provided on the first side from the center of the width of the first portion of the output conductive pattern in the second direction.

19. The semiconductor device according to claim 15, wherein the recess included in the second portion of the output conductive pattern has an L-shape with an opening facing the first side and the first direction in a plan view.

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