Quantum device and production method for multilayer wiring board

Abstract

This quantum device comprises: a multilayer wiring board provided with a first wiring that includes a superconducting material, a second wiring that includes a normal conductive material, and a via that is connected to the second wiring and includes a normal conductive material; and a quantum chip that is provided on a first surface of the multilayer wiring board and is electrically connected to the first wiring and the via. The via is formed so as to penetrate from the first surface to a second surface of the multilayer wiring board, and the second wiring is formed so as to be exposed to the second surface of the multilayer wiring board. This configuration makes it possible to reduce the loss of high-frequency signals while ensuring the cooling performance of the quantum device.　

Description

Quantum device and method for manufacturing multilayer wiring board

[0001] The present invention relates to a quantum device and a method for manufacturing a multilayer wiring board.

[0002] Striplines are known as transmission lines for high-frequency signals. For example, a high-frequency signal delay line is known, which is a stripline in which the signal wiring is made of a superconducting material and the ground wiring is made of a normal-conducting material (see, for example, Patent Document 1). It is also known that both the signal wiring and the ground wiring are made of a superconducting material (see, for example, Patent Document 2). It is also known that the signal wiring is made of an internal normal-conducting film and an outer superconducting film, and the ground wiring is made of a superconducting film on the circuit pattern side and a normal-conducting film on the opposite side (see, for example, Patent Document 3).

[0003] JP-A No. 5-226901 Special Publication No. 2020-535660 JP-A No. 10-224110

[0004] Development of superconducting quantum computers equipped with quantum devices that operate in a superconducting state at cryogenic temperatures is underway. A proposed quantum device configuration involves mounting a quantum chip on a multilayer wiring substrate. In this case, to reduce high-frequency signal loss, it is conceivable to form the signal and ground wiring on the multilayer wiring substrate from a superconducting material. However, superconducting materials have extremely high thermal resistance at cryogenic temperatures. Therefore, when a multilayer wiring substrate is placed on a cooling plate to cool the quantum chip to cryogenic temperatures, the thermal resistance of the signal and ground wiring becomes so high that the quantum chip may not be able to be cooled to cryogenic temperatures.

[0005] One aspect of the present invention aims to reduce the loss of high frequency signals while ensuring the cooling performance of quantum devices.

[0006] In one aspect, a quantum device comprises a multilayer wiring substrate having a first wiring including a superconducting material, a second wiring including a normal conducting material, and a via connected to the second wiring and including a normal conducting material; and a quantum chip provided on a first surface of the multilayer wiring substrate and electrically connected to the first wiring and the via, wherein the via is formed penetrating from the first surface to a second surface of the multilayer wiring substrate, and the second wiring is formed exposed on the second surface of the multilayer wiring substrate.

[0007] In one aspect, a quantum device comprises a multilayer wiring board having a first wiring including a superconducting material, a second wiring including a superconducting material with a magnetic material added thereto, and a via connected to the second wiring and including a superconducting material with a magnetic material added thereto; and a quantum chip provided on a first surface of the multilayer wiring board and electrically connected to the first wiring and the via, wherein the via is formed to penetrate from the first surface to a second surface of the multilayer wiring board, and the second wiring is formed to be exposed on the second surface of the multilayer wiring board.

[0008] In one aspect, a method for manufacturing a multilayer wiring board includes the steps of: forming a laminate in which signal wiring containing a superconducting material and multiple ground wirings containing a normal conducting material are stacked with an insulating layer sandwiched between them, the laminate having a first ground wiring exposed on a first surface of the laminate and a second ground wiring exposed on a second surface opposite the first surface; and forming ground vias containing a normal conducting material in the laminate to connect the first ground wiring and the second ground wiring.

[0009] As one aspect, loss can be reduced while ensuring cooling performance.

[0010] FIG. 1 is a cross-sectional view of a quantum device according to a first embodiment. FIG. 2(a) is a plan view of a quantum bit provided on a quantum chip according to the first embodiment. FIG. 2(b) is a plan view of a Josephson junction device. FIG. 2(c) is a cross-sectional view taken along the line A-A of FIG. 2(b). FIGS. 3(a) to 3(d) are exploded plan views of a printed circuit board according to the first embodiment. FIG. 4(a) is a cross-sectional view of the printed circuit board at a location corresponding to the line A-A of FIG. 3(a). FIG. 4(b) is a cross-sectional view of the printed circuit board at a location corresponding to the line B-B of FIG. 3(a). FIGS. 5(a) to 5(c) are cross-sectional views showing a first method for manufacturing a printed circuit board according to the first embodiment. FIGS. 6(a) to 6(c) are cross-sectional views showing a second method for manufacturing a printed circuit board according to the first embodiment. FIG. 7 is a cross-sectional view of a strip line used for simulation. FIG. 8 shows the results of a simulation of the insertion loss of a high-frequency signal transmitted through a strip line. FIG. 9 is a cross-sectional view showing a cooling structure of a quantum device according to the first embodiment. FIGS. 10(a) and 10(b) are cross-sectional views of a printed circuit board according to a modified example of the first embodiment. FIGS. 11(a) to 11(e) are exploded plan views of a printed circuit board according to a second embodiment. FIG. 12(a) is a cross-sectional view of the printed circuit board at a location corresponding to A-A in FIG. 11(a), and FIG. 12(b) is a cross-sectional view of the printed circuit board at a location corresponding to B-B in FIG. 11(a). FIG. 13(a) is a cross-sectional view showing a first manufacturing method of a printed circuit board according to the second embodiment, and FIG. 13(b) is a cross-sectional view showing a second manufacturing method. FIGS. 14(a) and 14(b) are cross-sectional views showing a first method of forming a two-layer ground wiring according to the second embodiment, and FIGS. 14(c) to 14(e) are cross-sectional views showing a second manufacturing method. FIG. 15 is a cross-sectional view showing a cooling structure for a quantum device according to the second embodiment. FIGS. 16(a) and 16(b) are cross-sectional views of a printed circuit board according to a modified example of the second embodiment. 17(a) and 17(b) are cross-sectional views showing a first method for forming a two-layer ground wiring in a modified example of Example 2, and FIGS. 17(c) to 17(e) are cross-sectional views showing a second method for forming the same. FIG. 18 is a cross-sectional view showing a cooling structure for a quantum device according to a modified example of Example 2. FIG. 19 is a diagram showing current density versus distance from the surface of a conductor. FIGS. 20(a) and 20(b) are cross-sectional views of a printed circuit board in Example 3.

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0012] FIG. 1 is a cross-sectional view of a quantum device 100 according to a first embodiment. As shown in FIG. 1, the quantum device 100 according to the first embodiment includes a printed circuit board 10, a package substrate 30, an interposer 40, and a quantum chip 50. The package substrate 30 is mounted on the printed circuit board 10 by a bonding material 60. The interposer 40 is mounted on the package substrate 30 by a bonding material 61. The pitch of the bonding material 61 is smaller than the pitch of the bonding material 60. For example, the pitch of the bonding material 60 is about 1 mm, and the pitch of the bonding material 61 is about 200 μm. The bonding materials 60 and 61 are solder, for example, Sn—Ag—Cu solder or Sn—Cu solder.

[0013] The quantum chip 50 is mounted on the interposer 40 by a bonding material 62. The bonding material 62 has a lower bonding temperature than the bonding materials 60 and 61, and is, for example, an indium (In) bump or a gold (Au) bump. By using In bumps as the bonding material 62, the temperature when mounting the quantum chip 50 on the interposer 40 can be kept lower than when solder is used. For example, the bonding temperature when solder is used is about 200°C (heating time is about 5 minutes), whereas when In bumps are used, the bonding temperature can be kept as low as about 140°C. When ultrasonic Au bonding is used, the bonding temperature can be kept as low as about 200°C (heating time is about 3 seconds). The quantum chip 50 includes, for example, a quantum bit having a Josephson junction element.

[0014] FIG. 2(a) is a plan view of a quantum bit 51 provided in a quantum chip 50 in Example 1, FIG. 2(b) is a plan view of a Josephson junction device 56, and FIG. 2(c) is a cross-sectional view taken along line A-A in FIG. 2(b). In FIG. 2(a), the conductive films are hatched for clarity. As shown in FIGS. 2(a) to 2(c), the quantum bit 51 includes a quantum bit device 52, a resonator 53, and a filter 54. The quantum bit device 52 includes a Josephson junction device 56 connected between electrodes 55a and 55b. In the Josephson junction device 56, superconducting films 57a and 57b overlap with each other via an insulating film 58. The superconducting films 57a and 57b are, for example, aluminum (Al) films. The insulating film 58 is, for example, aluminum oxide (Al ２ O ３ ) films. The superconducting films 57a and 57b are made of a superconducting material to which no magnetic material is added. The Josephson junction element 56 is connected between the electrodes 55a and 55b, with the superconducting film 57a connected to the electrode 55a and the superconducting film 57b connected to the electrode 55b. The quantum bit element 52 includes a transmon including the Josephson junction element 56 and a capacitor made of the electrodes 55a and 55b connected in parallel to the Josephson junction element 56. The resonator 53 includes, for example, a coplanar line having a meander structure, and one end of the resonator 53 is electrostatically coupled to the quantum bit element 52. The other end of the resonator 53 is connected to the readout unit 59 via the filter 54.

[0015] 1 , if the temperature becomes high when mounting the quantum chip 50 on the interposer 40, the thickness of the insulating film 58 of the Josephson junction element 56 may change, resulting in changes in the characteristics of the quantum bit element 52. Therefore, the package substrate 30 is mounted on the printed circuit board 10 using a bonding material 60, and the interposer 40 is mounted on the package substrate 30 using a bonding material 61. After that, the quantum chip 50 is mounted on the interposer 40 using a bonding material 62 made of In bumps, Au bumps, or the like. This prevents the temperature of the quantum chip 50 from rising and suppresses changes in the characteristics of the quantum bit element 52. Note that, as shown in FIG. 1 , a cover chip 63 may be provided to cover the quantum chip 50.

[0016] A cable 65 is connected to the printed circuit board 10 via a connector 64. One end of the cable 65 is connected to the connector 64, and the other end is connected to an external device such as a high-frequency generator or a high-frequency receiver. A high-frequency (e.g., 1 GHz to 10 GHz) electrical signal transmitted and received between the quantum chip 50 and the external device is transmitted through the cable 65, connector 64, printed circuit board 10, bonding material 60, package substrate 30, bonding material 61, interposer 40, and bonding material 62.

[0017] 3(a) to 3(d) are exploded plan views of the printed circuit board 10 in Example 1. FIG. 4(a) is a cross-sectional view of the printed circuit board 10 at a location corresponding to A-A in FIG. 3(a), and FIG. 4(b) is a cross-sectional view of the printed circuit board 10 at a location corresponding to B-B in FIG. 3(a). FIG. 3(a) to 3(d) are plan views of each layer viewed from above. In FIG. 3(a) to 3(d), the signal wiring 13, ground wiring 14a, 14b, and 14c, signal via 16, ground via 17, and land 18 are hatched for clarity.

[0018] As shown in FIGS. 3A to 3D and 4A and 4B, the printed circuit board 10 includes a signal wiring 13, multiple ground wirings 14a, 14b, and 14c, and multiple insulating layers 15a, 15b, and 15c. The ground wiring 14a (third wiring) is exposed on the upper surface 11 (first surface) of the printed circuit board 10. The ground wiring 14c (second wiring) is exposed on the lower surface 12 (second surface) of the printed circuit board 10. The signal wiring 13 (first wiring) and the ground wiring 14b (fourth wiring) are provided inside the printed circuit board 10. At least a portion of the signal wiring 13 overlaps both the ground wirings 14a and 14c in a plan view. The insulating layer 15a is a layer located between the ground wiring 14a and the ground wiring 14b. The insulating layer 15b is a layer located between the ground wiring 14b and the signal wiring 13. The insulating layer 15c is a layer located between the signal wiring 13 and the ground wiring 14c.

[0019] The signal wiring 13 has an upper surface facing the ground wiring 14b via the insulating layer 15b, and a lower surface facing the ground wiring 14c via the insulating layer 15c, and is sandwiched between the ground wiring 14b and the ground wiring 14c. As a result, the signal wiring 13 and the ground wirings 14b and 14c form a strip line 19.

[0020] The printed circuit board 10 further includes a signal via 16 connected to the signal wiring 13, a ground via 17 connected to the ground wirings 14a, 14b, and 14c, and a land 18 connected to the signal via 16. The land 18 is provided and exposed on the top surface 11 of the printed circuit board 10. The signal via 16 is provided on the printed circuit board 10 from the land 18 to the signal wiring 13. The ground via 17 is provided so as to penetrate from the top surface 11 to the bottom surface 12 of the printed circuit board 10.

[0021] The signal wiring 13 is made of a superconducting material. A superconducting material is a material that becomes superconducting at extremely low temperatures (e.g., several tens of mK). Examples of superconducting materials used for the signal wiring 13 include aluminum (Al), titanium nitride (TiN), and niobium (Nb). The superconducting material of the signal wiring 13 does not contain any magnetic material. The ground wirings 14a, 14b, and 14c are made of a normal conducting material. A normal conducting material is a material that does not become superconducting at extremely low temperatures (e.g., several tens of mK). Examples of normal conducting materials used for the ground wirings 14a, 14b, and 14c include copper (Cu) and silver (Ag).

[0022] The insulating layers 15a, 15b, and 15c are made of, for example, epoxy resin, phenolic resin, or glass epoxy resin. The signal vias 16 and lands 18 are made of a superconducting material (e.g., Al, TiN, or Nb) or a normal conducting material (e.g., Cu or Ag). The ground vias 17 are made of a normal conducting material (e.g., Cu or Ag).

[0023] The width W of the signal wiring 13 is several tens of μm to one hundred and several tens of μm, for example, 50 μm to 150 μm. The length L of the signal wiring 13 is several centimeters to several tens of cm, for example, 5 cm to 20 cm. The thickness of the signal wiring 13 and the ground wirings 14a, 14b, and 14c is several tens of μm, for example, 10 μm to 50 μm. The thickness of the insulating layers 15a, 15b, and 15c is several tens of μm to one hundred and several tens of μm, for example, 80 μm to 120 μm. The thickness of the conductor on the inner wall of the ground via 17 is, for example, about 25 μm, and the diameter D1 of the through hole inside the ground via 17 is, for example, about 100 μm. The diameter D2 of the land 18 is, for example, about 400 μm. The distance I between the land 18 and the ground wiring 14a is, for example, about 100 μm.

[0024] [Method of Manufacturing Printed Circuit Board] FIGS. 5( a ) to 5 ( c ) are cross-sectional views illustrating a first method of manufacturing the printed circuit board 10 according to the first embodiment. As shown in FIG. 5( a ), a cured insulating layer 70a is prepared, with a ground wiring 14a formed on its upper surface and a ground wiring 14b formed on its lower surface. Similarly, a cured insulating layer 70b is prepared, with a signal wiring 13 formed on its upper surface and a ground wiring 14c formed on its lower surface. The insulating layers 70a and 70b are formed by curing a thermosetting resin (e.g., glass epoxy resin). The ground wirings 14a, 14b, and 14c are formed, for example, by attaching a conductive foil made of a normal conducting material (e.g., Cu foil) to the surfaces of the insulating layers 70a and 70b and then patterning the foil. The signal wiring 13 is formed, for example, by attaching a conductive foil made of a superconducting material (e.g., Al foil) to the surface of the insulating layer 70b and then patterning the foil. A semi-cured insulating layer 71a is sandwiched between the insulating layers 70a and 70b. The insulating layer 71a is made of a thermosetting resin (e.g., glass epoxy resin) in a semi-cured state and serves as an adhesive. The semi-cured state means that the curing process has been stopped halfway. The cured resin is also called a core, and the semi-cured resin is also called a prepreg. The components of the cured resin and the semi-cured resin may be the same.

[0025] Insulating layers 70a, 71a, and 70b are stacked with insulating layer 71a sandwiched therebetween, and then pressure and temperature are applied in the stacking direction to harden insulating layer 71a. As a result, as shown in FIG. 5B , a laminate 72 is formed in which insulating layers 15a, 15b, and 15c are provided between signal wiring 13 and ground wirings 14a, 14b, and 14c. The laminate 72 has the ground wiring 14a exposed on an upper surface 73 and the ground wiring 14c exposed on a lower surface 74. In the stacking direction of the laminate 72, the signal wiring 13 faces the ground wiring 14c with the insulating layer 15c sandwiched between them. The ground wiring 14b faces the signal wiring 13 with the insulating layer 15b sandwiched between them, and the signal wiring 13 is sandwiched between the ground wiring 14c and the ground wiring 14c.

[0026] 5( c), holes 75 reaching the signal wiring 13 are formed by, for example, laser processing, and a superconducting film or a normal conducting film is embedded in the holes 75 by, for example, plating to form the signal vias 16 and lands 18. For example, through holes 76 penetrating the laminate 72 from the upper surface 73 to the lower surface 74 are formed by drilling, and a normal conducting film is formed on the inner surface of the through holes 76 by, for example, plating to form the ground vias 17. In this manner, the printed circuit board 10 is formed.

[0027] 6( a ) to 6 ( c ) are cross-sectional views illustrating a second manufacturing method for the printed circuit board 10 according to the first embodiment. As shown in FIG. 6( a ), an insulating layer 70 c is formed, with a ground wiring 14 b formed on its upper surface and a signal wiring 13 formed on its lower surface. The insulating layer 70 c, the ground wiring 14 b, and the signal wiring 13 are formed by the same method as in the first manufacturing method. Insulating layers 71 b and 71 c are disposed on both sides of the insulating layer 70 c, and conductive foils 77 a and 77 b (e.g., Cu foil) made of a normal-conducting material are disposed on the outer surfaces of the insulating layers 71 b and 71 c. As in the first manufacturing method, the insulating layers 71 b and 71 c are made of a semi-cured thermosetting resin (e.g., glass epoxy resin) and serve as an adhesive.

[0028] Conductive foils 77a and 77b, insulating layers 71b and 71c, and insulating layer 70c are stacked, and pressure and temperature are applied in the stacking direction to harden the insulating layers 71b and 71c. The conductive foils 77a and 77b are then patterned. As a result, as shown in FIG. 6B , a laminate 72 is formed in which insulating layers 15a, 15b, and 15c are provided between the signal wiring 13 and the ground wirings 14a, 14b, and 14c. The laminate 72 has the ground wiring 14a exposed on an upper surface 73 and the ground wiring 14c exposed on a lower surface 74. In the stacking direction of the laminate 72, the signal wiring 13 faces the ground wiring 14c with the insulating layer 15c sandwiched between them. The ground wiring 14b faces the signal wiring 13 with the insulating layer 15b sandwiched between them, and the signal wiring 13 is sandwiched between the ground wiring 14c and the ground wiring 14c.

[0029] 6C, the signal vias 16, the ground vias 17, and the lands 18 are formed in the same manner as described in FIG. 5C. In this manner, the printed circuit board 10 is formed.

[0030] [Simulation] Figure 7 is a cross-sectional view of a strip line 90 on which a simulation was performed. As shown in Figure 7, the strip line 90 has ground wiring 92 provided on the top and bottom surfaces of a dielectric layer 93, and a signal wiring 91 provided inside. The insertion loss S21 of the strip line 90 was simulated. The simulation conditions were as follows: Signal wiring 91: an aluminum (Al) layer or copper (Cu) layer with a thickness T1 of 30 µm, a width W of 100 µm, and a length of 10 cm Ground wiring 92: an aluminum (Al) layer or copper (Cu) layer with a thickness T2 of 30 µm Dielectric layer 93: a thickness T3 of 100 µm, a dielectric constant of 3.3, and a dielectric loss tangent of 0.004 Temperature: 10 mK

[0031] 8 shows the simulation results of the insertion loss S21 of a high-frequency signal transmitted through the strip line 90. In FIG. 8, the horizontal axis represents frequency [GHz], and the vertical axis represents insertion loss S21 [dB / 10 cm]. The solid line shows the simulation results when both the signal wiring 91 and the ground wiring 92 are Al layers. The dashed line shows the simulation results when the signal wiring 91 is an Al layer and the ground wiring 92 is a Cu layer. The dashed line shows the simulation results when the signal wiring 91 is a Cu layer and the ground wiring 92 is an Al layer. The dotted line shows the simulation results when both the signal wiring 91 and the ground wiring 92 are Cu layers.

[0032] As shown in Figure 8, when both the signal wiring 91 and the ground wiring 92 were made of Al layers (solid line), the insertion loss S21 was significantly reduced compared to when both the signal wiring 91 and the ground wiring 92 were made of Cu layers (dotted line). This is thought to be because Cu is a normal conductor, while Al is a superconducting material, and at a temperature of 10 mK, Al becomes superconducting, reducing its electrical resistance. When the signal wiring 91 was made of Al layers and the ground wiring 92 was made of Cu layers (dashed line), the insertion loss S21 was worse than when both the signal wiring 91 and the ground wiring 92 were made of Al layers (solid line), but was lower than when both were made of Cu layers (dotted line). When the signal wiring 91 was made of Cu layers and the ground wiring 92 was made of Al layers (dashed line), the insertion loss S21 was also lower than when both the signal wiring 91 and the ground wiring 92 were made of Cu layers (dotted line). From the simulation results, it can be seen that the reduction in insertion loss S21 is more effective when both the signal wiring 91 and the ground wiring 92 are made of superconducting material, but sufficient effect can also be obtained when only the signal wiring 91 is made of superconducting material.

[0033] It is known that superconducting materials have extremely high thermal resistance at cryogenic temperatures and are completely insulated at absolute zero, while quantum chips are cooled to cryogenic temperatures to operate in a superconducting state.

[0034] FIG. 9 is a cross-sectional view showing the cooling structure of the quantum device 100 according to the first embodiment. For ease of explanation of cooling, FIG. 9 illustrates the printed circuit board 10 as a combination of FIGS. 4( a) and 4(b). As shown in FIG. 9, the printed circuit board 10 is placed on the upper surface of a cooling plate 66. As a result, the ground wiring 14c exposed on the lower surface 12 of the printed circuit board 10 comes into contact with the cooling plate 66. The cooling plate 66 is, for example, a copper plate with a thickness of approximately 1 cm. The cooling plate 66 is cooled by a refrigerator (not shown) capable of cooling to approximately 10 mK. Therefore, by placing the printed circuit board 10 on the cooling plate 66, heat is transferred between the quantum chip 50 and the cooling plate 66 via the ground wiring 14a, ground vias 17, and ground wiring 14c of the printed circuit board 10, as indicated by arrow 67. This allows the quantum chip 50 to be cooled to extremely low temperatures (e.g., several tens of mK), enabling the quantum chip 50 to operate in a superconducting state.

[0035] To reduce high-frequency signal loss, it is conceivable to form the signal wiring 13, ground wiring 14a, 14b, 14c, signal via 16, ground via 17, and land 18 of the printed circuit board 10 all from a superconducting material (e.g., Al). However, because the printed circuit board 10 is also cooled to cryogenic temperatures by the cooling plate 66, the signal wiring 13 and ground wiring 14a, 14b, 14c, etc. are also cooled to cryogenic temperatures. If the ground wiring 14a, 14b, 14c, and ground via 17 are made of a superconducting material, the thermal resistance of the ground wiring 14a, 14b, 14c, and ground via 17 increases when cooled to cryogenic temperatures. Therefore, heat transfer as indicated by arrow 67 becomes difficult, and the quantum chip 50 may not be cooled to cryogenic temperatures.

[0036] Therefore, in Example 1, the signal wiring 13 is formed of a superconducting material, while the ground wiring 14a, 14b, 14c and the ground via 17 are formed of a normal-conducting material. As a result, even when the ground wiring 14a, 14b, 14c and the ground via 17 are cooled to an extremely low temperature, their thermal resistance is kept lower than when they are formed of a superconducting material. This makes it possible to cool the quantum chip 50 to an extremely low temperature. Furthermore, by forming the signal wiring 13 from a superconducting material, the signal wiring 13 is cooled to an extremely low temperature and its electrical resistance is reduced, thereby reducing the loss of high-frequency signals as shown in FIG. 8.

[0037] 10(a) and 10(b) are cross-sectional views of a printed circuit board 10a according to a modification of the first embodiment. As shown in FIGS. 10(a) and 10(b), the printed circuit board 10a according to the modification of the first embodiment has a ground wiring 14c, an insulating layer 15c, a ground wiring 14b, an insulating layer 15b, a signal wiring 13, an insulating layer 15a, and a ground wiring 14a stacked in this order from the bottom surface 12 to the top surface 11. Therefore, the signal wiring 13 has its top surface facing the ground wiring 14a via the insulating layer 15a, its bottom surface facing the ground wiring 14b via the insulating layer 15b, and is sandwiched between the ground wiring 14a and the ground wiring 14b. Therefore, a strip line 19 is formed by the signal wiring 13 and the ground wirings 14a and 14b. The remaining configuration is the same as that of the first embodiment, and therefore a description thereof will be omitted.

[0038] As described above, according to the first embodiment and its modifications, the signal wiring 13 is formed of a superconducting material. This reduces high-frequency signal loss. Furthermore, as shown in FIGS. 4( b) and 10( b), the ground wiring 14 a exposed on the upper surface 11 of the printed circuit board 10, 10 a and the ground wiring 14 c exposed on the lower surface 12 are connected by a ground via 17. The ground wiring 14 a, 14 c and the ground via 17 are formed of a normal-conducting material. As a result, as described in FIG. 9, even when the printed circuit board 10, 10 a is cooled to a cryogenic temperature in an attempt to cool the quantum chip 50 provided on the printed circuit board 10, 10 a to a cryogenic temperature, heat transfer between the quantum chip 50 and the cooling plate 66 is maintained. Therefore, the quantum chip 50 can be cooled to a cryogenic temperature. Thus, according to the first embodiment and its modifications, high-frequency signal loss can be reduced while maintaining cooling performance.

[0039] 4(a) and 10(a), in the first embodiment and its modifications, the signal wiring 13 faces one of the ground wirings 14a, 14c and the ground wiring 14b, and is sandwiched between them. This forms a strip line 19 that transmits a high-frequency signal to the quantum chip 50. By using the ground wiring 14a or 14c as one of the ground wirings that form the strip line 19, the printed circuit boards 10, 10a can be made smaller.

[0040] In addition, in the first embodiment and its modified examples, the signal via 16 connected to the signal wiring 13 is made of a superconducting material or a normal conducting material. When the signal via 16 is made of a superconducting material, the loss of high-frequency signals can be further reduced. When the signal via 16 is made of a normal conducting material, it can be formed simultaneously with the ground via 17, thereby reducing manufacturing costs.

[0041] Furthermore, according to the manufacturing method of Example 1 and its modified examples, a laminate 72 is formed in which signal wiring 13 containing a superconducting material and ground wirings 14a, 14b, and 14c containing a normal-conducting material are stacked with insulating layers 15a, 15b, and 15c sandwiched therebetween, as shown in Figures 5(b) and 6(b). The ground wiring 14a is exposed on an upper surface 73 of the laminate 72, and the ground wiring 14c is exposed on a lower surface 74. As shown in Figures 5(c) and 6(c), ground vias 17 containing a normal-conducting material that connect the ground wiring 14a and the ground wiring 14c are formed in the laminate 72. This allows for the production of printed circuit boards 10 and 10a that can ensure cooling performance even when cooled to extremely low temperatures and reduce high-frequency signal loss.

[0042] 5B and 6B, the signal wiring 13 faces the ground wiring 14c and the ground wiring 14b, forming a laminate 72 sandwiched therebetween. In a modification of the first embodiment, the signal wiring 13 faces the ground wiring 14a and the ground wiring 14b, forming a laminate 72 sandwiched therebetween, as shown in FIG. 10A. This forms a strip line 19 that transmits high-frequency signals.

[0043] In addition, in Example 1, as shown in FIG. 5A, an insulating layer 71a is sandwiched between an insulating layer 70a on which the ground wiring 14a is formed and an insulating layer 70b on which the ground wiring 14c and the signal wiring 13 are formed. In a modified example of Example 1, as shown in FIG. 10A, an insulating layer 71a is sandwiched between an insulating layer 70a on which the ground wiring 14a and the signal wiring 13 are formed and an insulating layer 70b on which the ground wiring 14c is formed. Thereafter, as shown in FIG. 5B, the insulating layer 71a is cured to form a laminate 72. This makes it possible to easily form the printed circuit boards 10, 10a.

[0044] In addition, in Example 1 and its modified examples, as shown in Fig. 6(a), an insulating layer 70c on which insulating layers 71b, 71c and signal wiring 13 are formed is sandwiched between conductive foils 77a, 77b, and the insulating layer 70c is sandwiched between insulating layers 71b, 71c. Thereafter, as shown in Fig. 6(b), the insulating layers 71b, 71c are hardened, and then the conductive foils 77a, 77b are processed to form ground wiring 14a, 14c, thereby forming the laminate 72. This allows the printed circuit boards 10, 10a to be easily formed.

[0045] 11(a) to 11(e) are exploded plan views of the printed circuit board 10b in Example 2. FIG. 12(a) is a cross-sectional view of the printed circuit board 10b at a location corresponding to A-A in FIG. 11(a), and FIG. 12(b) is a cross-sectional view of the printed circuit board 10b at a location corresponding to B-B in FIG. 11(a). FIGS. 11(a), 11(b), 11(d), and 11(e) are plan views of the layers viewed from above, and FIG. 11(c) is a plan view of the ground wiring 14b viewed from below. In FIGS. 11(a) to 11(e), the signal wiring 13, the ground wirings 14a, 14b, and 14c, the signal via 16, the ground via 17, and the land 18 are hatched for clarity.

[0046] 11(a) to 11(e) and 12(a) and 12(b), in a printed circuit board 10b according to the second embodiment, a ground wiring 14b includes a first layer 21 and a second layer 22. The first layer 21 is provided on a surface 23 of the second layer 22 on the side of the signal wiring 13. The first layer 21 is made of a superconducting material, such as Al. The second layer 22 is made of a normal conducting material, such as Cu.

[0047] The first layer 21 is not provided over the entire surface 23 of the second layer 22, but is provided on a portion of the surface 23 with an area larger than that of the signal wiring 13 so as to overlap the signal wiring 13 in a planar view. The first layer 21 has, for example, a rectangular shape that is point-symmetrical with respect to a point overlapping the center point of the signal wiring 13 in a planar view. The length L1 from a line overlapping the center line of the signal wiring 13 in the width direction (Y direction) of the signal wiring 13 to the end of the first layer 21 in the Y direction is at least three times, and may be at least five times, the width W of the signal wiring 13. As an example, when the width W of the signal wiring 13 is 80 μm, the length L1 is 500 μm. The length L2 from a point overlapping the tip of the signal wiring 13 in the length direction (X direction) of the signal wiring 13 to the end of the first layer 21 in the X direction is also at least three times, and may be at least five times, the width W of the signal wiring 13. In other words, the first layer 21 is provided on the surface 23 of the second layer 22 from the point where it overlaps with the signal wiring 13 over a range of at least three times the width W of the signal wiring 13, and may be provided over a range of at least five times the width W of the signal wiring 13.

[0048] Like the ground wiring 14b, the ground wiring 14c also includes a first layer 24 and a second layer 25. The first layer 24 is provided on a surface 26 of the second layer 25 on the signal wiring 13 side. The first layer 24 is made of a superconducting material, such as Al. The second layer 25 is made of a normal conducting material, such as Cu.

[0049] The first layer 24 is not provided over the entire surface 26 of the second layer 25, but is provided on a part of the surface 26 with an area larger than that of the signal wiring 13 so as to overlap the signal wiring 13 in a plan view. Like the first layer 21 of the ground wiring 14b, the first layer 24 has a rectangular shape that is point-symmetric with respect to a point that overlaps the center point of the signal wiring 13 in a plan view. Like the first layer 21 of the ground wiring 14b, the first layer 24 is provided on the surface 26 of the second layer 25 from the point where it overlaps the signal wiring 13 over a range that is three or more times the width W of the signal wiring 13, and may be provided over a range that is five or more times the width W of the signal wiring 13.

[0050] The ground via 17 is connected to the ground wirings 14a, 14b, and 14c, and in the ground wirings 14b and 14c, it is connected to at least the second layers 22 and 25. The other configurations of the quantum device according to the second embodiment are the same as those of the quantum device 100 according to the first embodiment, and therefore will not be illustrated or described again.

[0051] [Method of Manufacturing Printed Circuit Board] FIG. 13A is a cross-sectional view showing a first method of manufacturing a printed circuit board 10b according to the second embodiment. As shown in FIG. 13A, an insulating layer 80a is prepared, having a ground wiring 14a formed on its upper surface and a ground wiring 14b including a first layer 21 and a second layer 22 formed on its lower surface. An insulating layer 80b is also prepared, having a signal wiring 13 formed on its upper surface and a ground wiring 14c including a first layer 24 and a second layer 25 formed on its lower surface. An insulating layer 81a is then sandwiched between the insulating layers 80a and 80b. The same steps as those shown in FIGS. 5B and 5C of the first embodiment are then performed. This completes the printed circuit board 10b according to the second embodiment.

[0052] Here, a method for forming the two-layer ground wiring 14b, 14c will be described. Since the ground wiring 14b, 14c are formed by the same method, the ground wiring 14b will be described as an example. Figures 14(a) and 14(b) are cross-sectional views showing a first method for forming the two-layer ground wiring 14b in Example 2, and Figures 14(c) to 14(e) are cross-sectional views showing a second method for forming the two-layer ground wiring 14b in Example 2.

[0053] In the first forming method, first, as shown in FIG. 14( a), a conductive film 83a made of a normal-conducting material (e.g., conductive foil (Cu foil)) is attached to the upper surface of the insulating layer 80a. A conductive film 87, which is an integrated film of a superconducting material 85 (e.g., Al film) and a normal-conducting material 86 (e.g., Cu film), is attached to the lower surface of the insulating layer 80a. The conductive film 87 is formed by, for example, forming the film 85 on the surface of the conductive foil 86 by plating. Next, as shown in FIG. 14( b), the conductive film 83a on the upper surface of the insulating layer 80a is patterned to form the ground wiring 14a. The conductive film 87 on the lower surface of the insulating layer 80a is patterned to form the ground wiring 14b having a two-layer structure consisting of a first layer 21 and a second layer 22.

[0054] In the second forming method, first, as shown in FIG. 14( c), conductive films 83b, 83c (e.g., conductive foil (Cu foil)) made of a normal-conducting material are attached to the upper and lower surfaces of the insulating layer 80a. Next, as shown in FIG. 14( d), a film 82 made of a superconducting material (e.g., an Al film) is formed on the surface of the conductive film 83c attached to the lower surface of the insulating layer 80a by plating using a plating resist 84 as a mask. As shown in FIG. 14( e), the conductive film 83b on the upper surface of the insulating layer 80a is patterned to form the ground wiring 14a. After removing the plating resist 84, the conductive film 83c on the lower surface of the insulating layer 80a is patterned to form the two-layer ground wiring 14b having a first layer 21 and a second layer 22. By forming the ground wiring 14b using the second forming method, the first layer 21 can be formed with high positional accuracy.

[0055] FIG. 13(b) is a cross-sectional view showing a second manufacturing method for a printed circuit board 10b according to the second embodiment. As shown in FIG. 13(b), an insulating layer 80c is prepared, with a ground wiring 14b including a first layer 21 and a second layer 22 formed on its upper surface and a signal wiring 13 formed on its lower surface. The ground wiring 14b and the signal wiring 13 are formed by a method similar to the first forming method shown in FIGS. 14(a) and 14(b) or the second forming method shown in FIGS. 14(c) to 14(e). Insulating layers 81b and 81c are disposed on both sides of the insulating layer 80c, and a conductive film 83a made of a normal conducting material is disposed on the outer side of the insulating layer 81b. A conductive film 87, which is an integrated film 85 made of a superconducting material and a film 86 made of a normal conducting material, is disposed on the outer side of the insulating layer 81c. The same processes as those shown in FIGS. 6(b) and 6(c) for the first embodiment are then performed. This completes the printed circuit board 10b according to the second embodiment.

[0056] FIG. 15 is a cross-sectional view showing the cooling structure of the quantum device 200 according to the second embodiment. For ease of explanation of cooling, the printed circuit board 10b in FIG. 15 is a combination of FIGS. 12(a) and 12(b). As shown in FIG. 15, the printed circuit board 10b is placed on the upper surface of the cooling plate 66. As a result, the second layer 25 of the ground wiring 14c exposed on the lower surface 12 of the printed circuit board 10b contacts the cooling plate 66. The second layer 25 of the ground wiring 14c, the ground via 17, and the ground wiring 14a are made of normal conducting materials, thereby maintaining low thermal resistance even when cooled to extremely low temperatures. Because the ground via 17 is connected to the second layer 25 of the ground wiring 14c, heat transfer between the quantum chip 50 and the cooling plate 66, as indicated by the arrow 67, is maintained even when cooled to extremely low temperatures. This allows the quantum chip 50 to be cooled to extremely low temperatures.

[0057] 16(a) and 16(b) are cross-sectional views of a printed circuit board 10c according to a modification of Example 2. As shown in Figures 16(a) and 16(b), in the printed circuit board 10c according to the modification of Example 2, the first layer 21 of the ground wiring 14b is provided on the entire surface of the second layer 22 facing the signal wiring 13. The first layer 24 of the ground wiring 14c is provided on the entire surface of the second layer 25 facing the signal wiring 13. The other configurations are the same as those of Example 2, and therefore will not be described again.

[0058] 17(a) and 17(b) are cross-sectional views showing a first method for forming the ground wiring 14b having a two-layer structure in a modified example of Example 2, and FIGS. 17(c) to 17(e) are cross-sectional views showing a second method for forming the ground wiring 14b having a two-layer structure in a modified example of Example 2.

[0059] In the first formation method, as shown in FIG. 17( a), a conductive film 83a made of a normal conducting material is attached to the upper surface of the insulating layer 80a. A conductive film 87, which is an integrated film 85 made of a superconducting material and a film 86 made of a normal conducting material, is attached to the lower surface of the insulating layer 80a. The conductive film 87 may be formed by using a conductive foil as the film 85 and plating the entire upper surface of the film 86, or by using a conductive foil as the film 86 and plating the entire upper surface of the film 86. Next, as shown in FIG. 17( b), the conductive film 83a on the upper surface of the insulating layer 80a is patterned to form the ground wiring 14a. The conductive film 87 on the lower surface of the insulating layer 80a is patterned to form the ground wiring 14b having a two-layer structure consisting of a first layer 21 and a second layer 22.

[0060] In the second formation method, as shown in FIG. 17( c), conductive films 83b, 83c made of a normal-conducting material are attached to the upper and lower surfaces of the insulating layer 80a. Next, as shown in FIG. 17( d), a film 82 made of a superconducting material is formed by plating over the entire surface of the conductive film 83c attached to the lower surface of the insulating layer 80a. As shown in FIG. 17( e), the conductive film 83b on the upper surface of the insulating layer 80a is patterned to form the ground wiring 14a. The film 82 and the conductive film 83c on the lower surface of the insulating layer 80a are patterned to form the ground wiring 14b having a two-layer structure consisting of a first layer 21 and a second layer 22.

[0061] In the case of forming the ground wiring 14c, in the first forming method, the film 85 made of the superconducting material and the film 86 made of the normal conducting material are interchanged and attached to the insulating layer of the cured resin. In the second forming method, a conductive foil made of the superconducting material is used for the conductive film 83c, and the film 82 made of the normal conducting material is formed on the surface of the conductive film 83c by plating.

[0062] FIG. 18 is a cross-sectional view showing the cooling structure of a quantum device 210 according to a modified example of the second embodiment. For ease of explanation of cooling, FIG. 18 illustrates the printed circuit board 10c as a combination of FIGS. 16(a) and 16(b). As shown in FIG. 18, the printed circuit board 10c is disposed on the upper surface of the cooling plate 66. As a result, similar to the second embodiment, the second layer 25 of the ground wiring 14c exposed on the lower surface 12 of the printed circuit board 10c contacts the cooling plate 66. Because the ground via 17 is connected to the second layer 25 of the ground wiring 14c, heat transfer as indicated by the arrow 67 between the quantum chip 50 and the cooling plate 66 is maintained even when cooled to an extremely low temperature, similar to the second embodiment. Therefore, the quantum chip 50 can be cooled to an extremely low temperature.

[0063] In the second embodiment and its modifications, as in the first embodiment and its modifications, the signal wiring 13 is formed of a superconducting material. This reduces the loss of high-frequency signals. Furthermore, as shown in FIGS. 12(b) and 16(b), the ground wiring 14a exposed on the upper surface 11 of the printed circuit boards 10b and 10c and the ground wiring 14c exposed on the lower surface 12 are connected by a ground via 17. The ground wiring 14a and 14c and the ground via 17 are formed of a normal-conducting material. This allows the quantum chip 50 to be cooled to an extremely low temperature. Therefore, loss can be reduced while maintaining cooling performance.

[0064] In Example 2 and its modified example, as shown in FIGS. 12( a) and 16( a), the ground wiring 14b includes a first layer 21 and a second layer 22, and the ground wiring 14c includes a first layer 24 and a second layer 25. The first layers 21 and 24 are made of a superconducting material and are provided opposite the signal wiring 13. The second layers 22 and 25 are made of a normal conducting material and are provided on the opposite side of the signal wiring 13 from the first layers 21 and 24. In other words, in Example 2, as shown in FIGS. 11( c) and 11(d), the second layers 22 and 25 are made of a normal conducting material and are provided around the first layers 21 and 24 in a plan view. This means that the first layers 21 and 24 made of a superconducting material are present in the electromagnetic field of the strip line 19 through which the high-frequency signal is transmitted, thereby further reducing the loss of the high-frequency signal. In addition, the ground wiring 14c has a second layer 25 made of a normal conductive material exposed on the underside 12 of the printed circuit boards 10b and 10c, and the ground via 17 is connected to at least the second layer 25 of the ground wiring 14c, thereby ensuring cooling of the quantum chip 50.

[0065] 11(c) and 11(e) in Example 2 and its modified examples, the first layers 21 and 24 are provided to cover an area from the signal wiring 13 at least three times the width W of the signal wiring 13 in a plan view. Because the electromagnetic field of the strip line 19 is concentrated within a range from the signal wiring 13 to three times the width W of the signal wiring 13, providing the first layers 21 and 24 from the signal wiring 13 to an area at least three times the width W of the signal wiring 13 can further reduce high-frequency signal loss. From the viewpoint of reducing high-frequency signal loss, the first layers 21 and 24 may be provided within a range from the signal wiring 13 to at least four, six, or eight times the width W of the signal wiring 13. For example, the lengths L1 and L2 in FIG. 11(c) may be 300 μm or more, 400 μm or more, or 500 μm or more.

[0066] 16( a) and 16(b), in a modification of the second embodiment, the first layer 21 of the ground wiring 14b is provided on the entire surface of the second layer 22 facing the signal wiring 13. The first layer 24 of the ground wiring 14c is provided on the entire surface of the second layer 25 facing the signal wiring 13. This makes it easy to form the ground wirings 14b and 14c having a two-layer structure consisting of the first layers 21 and 24 and the second layers 22 and 25.

[0067] According to the manufacturing methods of Example 2 and its modified examples, a laminate 72 is formed in which the signal wiring 13 faces the ground wiring 14c and the ground wiring 14b and is sandwiched between them, as shown in FIGS. 12( a) and 16(a) (see also FIGS. 5(b) and 6(b)). In this case, the ground wiring 14b includes a first layer 21 and a second layer 22, and the ground wiring 14c includes a first layer 24 and a second layer 25. The first layers 21 and 24 are made of a superconducting material and are disposed opposite the signal wiring 13. The second layers 22 and 25 are made of a normal conducting material and are disposed on the opposite side of the first layers 21 and 24 from the signal wiring 13. This allows the first layers 21 and 24, made of a superconducting material, to be present within the electromagnetic field of the strip line 19, thereby further reducing high-frequency signal loss.

[0068] Although the second embodiment and its modified example show an example in which the ground wiring 14b includes the first layer 21 and the second layer 22, and the ground wiring 14c includes the first layer 24 and the second layer 25, the present invention is not limited to this example. Either the ground wiring 14b or 14c may include the first layer and the second layer.

[0069] 13(a) and 13(b), the laminate 72 is formed using insulating layers 80a, 80b and an insulating layer 81a, or using insulating layer 80c and insulating layers 81b, 81c (see also FIGS. 5(b) and 6(b)). As shown in FIGS. 14(a), 14(b), 17(a), and 17(b), the ground wiring 14b is formed by attaching a conductive film 87, which is an integrated film of a film 85 made of a superconducting material and a film 86 made of a normal-conducting material, to the insulating layer 80a, and by making the film 85 the first layer 21 and the film 86 the second layer 22. Alternatively, as shown in FIGS. 14(c) to 14(e) and 17(c) to 17(e), the ground wiring 14b is formed by attaching a conductive film 83c, which is a normal-conducting film, to the insulating layer 80a, and then forming a film 82 made of a superconducting material on the surface of the conductive film 83c, with the film 82 serving as the first layer 21 and the conductive film 83c serving as the second layer 22. This facilitates the formation of a two-layer ground wiring 14b. As described above, when forming the ground wiring 14c, in FIGS. 14(a), 14(b), 17(a), and 17(b), the film 85 made of a superconducting material and the film 86 made of a normal-conducting material are interchanged and attached to the insulating layer of cured resin. In FIGS. 14(c) to 14(e) and 17(c) to 17(e), the conductive film 83c is formed by using a superconducting material and then forming a film 82 made of a normal-conducting material on its surface by plating.

[0070] [Thickness of the First Layer of the Ground Wiring] It is known that high-frequency signals flow in a concentrated manner near the surface of a conductor, with almost no flow in the center of the conductor. The range from the surface of the conductor where high-frequency signals flow in a concentrated manner is defined by the skin depth d according to the following equation (1): In formula (1), d is the skin depth [m]. f is the frequency [Hz]. μ is the magnetic permeability [H / m]. σ is the electrical conductivity [S / m]. As an example, when the conductor is Cu, at room temperature, the skin depth d is about 2.07 μm when the frequency of the high-frequency signal is 1 GHz, and about 0.66 μm when it is 10 GHz. When the conductor is Al, at room temperature, the skin depth d is about 2.62 μm when the frequency of the high-frequency signal is 1 GHz, and about 0.83 μm when it is 10 GHz.

[0071] Fig. 19 is a diagram showing the current density versus the distance from the surface of a conductor. In Fig. 19, the horizontal axis represents the distance from the surface of the conductor, expressed in units of skin depth d. The vertical axis represents the current density, with the current density at the surface of the conductor being expressed as 1. As shown in Fig. 19, the current density decreases at a rate of 1 / e from the surface of the conductor to the inside. ｄ Therefore, the current density at a distance of 3d from the surface of the conductor is attenuated by about 95% relative to the surface of the conductor, by about 98% at a distance of 4d, by about 99% at a distance of 5d, and by about 99.75% at a distance of 6d.

[0072] At extremely low temperatures, σ (electrical conductivity) in formula (1) becomes large, and in the case of Cu, for example, at about 10 mK, σ can become approximately 100 times larger than at room temperature. In this case, the skin depth d becomes approximately 0.21 μm at 1 GHz and approximately 0.07 μm at 10 GHz.

[0073] For superconducting materials such as Al, σ becomes more than 10,000 times larger at around 10 mK than at room temperature. For example, when σ becomes 10,000 times larger, the skin depth d becomes approximately 0.026 μm at 1 GHz and approximately 0.008 μm at 10 GHz. In this case, 3d is approximately 0.078 μm at 1 GHz and approximately 0.024 μm at 10 GHz, 4d is approximately 0.104 μm at 1 GHz and approximately 0.032 μm at 10 GHz, 5d is approximately 0.13 μm at 1 GHz and approximately 0.04 μm at 10 GHz, and 6d is approximately 0.16 μm at 1 GHz and approximately 0.048 μm at 10 GHz.

[0074] From the above, it can be said that in a conductor made of a superconducting material, most of the high-frequency signal flows within a range of 0.01 μm from the surface of the conductor at extremely low temperatures. In other words, the penetration depth of the high-frequency signal transmitted through the strip line into the ground wiring is approximately 0.01 μm.

[0075] In the second embodiment and its modified example, the ground wiring 14b includes a second layer 22 made of Cu and a first layer 21 made of Al provided on a surface 23 of the second layer 22 facing the signal wiring 13. The ground wiring 14c includes a second layer 25 made of Cu and a first layer 24 made of Al provided on a surface 26 of the second layer 25 facing the signal wiring 13. High-frequency signals transmitted through the strip line 19 penetrate into the regions of the ground wirings 14b and 14c on the signal wiring 13 side. From the viewpoint of reducing loss, it is preferable that most of the high-frequency signals flow through the first layers 21 and 24 made of Al and that almost none of the high-frequency signals flow through the second layers 22 and 25 made of Cu. Therefore, in order to prevent high-frequency signals from penetrating the second layers 22 and 25, considering the above-mentioned skin depth d, it is preferable that the thicknesses of the first layers 21 and 24 be 0.01 μm or more.

[0076] Therefore, in Example 2 and its modified examples, the thickness of the first layers 21, 24 of the ground wirings 14b, 14c is set to 0.01 μm or more. This further reduces the loss of high-frequency signals. From the viewpoint of reducing loss, the thickness of the first layers 21, 24 is preferably 0.05 μm or more, more preferably 0.1 μm or more, even more preferably 0.5 μm or more, and even more preferably 1.0 μm or more. In other words, the thickness of the first layers 21, 24 is preferably three times or more, more preferably four times or more, even more preferably five times or more, and even more preferably six times or more of the skin depth d calculated by the above formula (1). It is known that the proximity effect occurring at the interface between a normal metal and a superconducting metal is on the order of 0.1 μm. Therefore, by setting the thickness of the first layers 21, 24 to 0.5 μm or more, the influence of the proximity effect can be suppressed, and it can be said that the electrical characteristics of high-frequency signals are largely determined by the characteristics of the superconducting material forming the first layers 21, 24.

[0077] Although the first and second embodiments and their modifications have been described with reference to the case where the signal wiring provided on the printed circuit board contains a superconducting material and the ground wiring and ground vias contain a normal-conducting material, the present invention is not limited to this case. For example, the signal wiring provided on the package substrate in FIG. 1 may contain a superconducting material, and the ground wiring and ground vias may contain a normal-conducting material.

[0078] 20(a) and 20(b) are cross-sectional views of a printed circuit board 10d according to the third embodiment. As shown in FIGS. 20(a) and 20(b), the printed circuit board 10d according to the third embodiment has ground wiring 34a, 34b, 34c and a ground via 37 made of a superconducting material with a magnetic material added thereto, instead of the ground wiring 14a, 14b, 14c and the ground via 17 made of a normal conducting material. For example, the ground wiring 34a, 34b, 34c and the ground via 37 are made of aluminum (Al), titanium nitride (TiN), or niobium (Nb) with at least one of iron (Fe), gadolinium (Gd), nickel (Ni), and cobalt (Co) added as a magnetic material. The amount of magnetic material added is extremely small (e.g., approximately 0.01 atm %). The other configurations of the quantum device according to the third embodiment are the same as those of the quantum device 100 according to the first embodiment, and therefore illustrations and descriptions thereof are omitted.

[0079] According to the third embodiment, the ground wiring 34a, 34b, 34c and the ground via 37 are formed of a superconducting material doped with a magnetic material. It is known that a superconducting material doped with a magnetic material has a superconducting transition temperature (Tc) of, for example, about 10 mK (see, for example, Introduction to Solid State Physics, 8th Edition, Charles Kittel, Chapter 10: Superconductivity, p. 278). That is, a superconducting material doped with a magnetic material has a lower superconducting transition temperature than a superconducting material not doped with a magnetic material. The Josephson junction element 56 provided in the quantum chip 50 is formed of a superconducting material not doped with a magnetic material. Therefore, the ground wiring 34a, 34b, 34c and the ground via 37 are prevented from increasing in thermal resistance when cooling the quantum chip 50 to operate it in a superconducting state. Therefore, during the process of cooling the quantum chip 50, heat transfer between the quantum chip 50 and the cooling plate 66 is maintained, allowing the quantum chip 50 to be cooled to an extremely low temperature. Furthermore, after the quantum chip 50 has been cooled to an extremely low temperature, the ground wirings 34a, 34b, and 34c are cooled to their superconducting transition temperature, causing the ground wirings 34a, 34b, and 34c to enter a superconducting state, thereby reducing high-frequency signal loss. Furthermore, for cooling aimed at achieving a temperature of around 10 mK, beryllium (Be) (Tc = 26 mK) or tungsten (W) (Tc = 12 mK) may be used in addition to a superconductor with a trace amount of magnetic material added.

[0080] In Example 3, the signal wiring 13 and the ground wiring 34b may be interchanged, as in the modified example of Example 1 shown in Figures 10(a) and 10(b). As in Example 2 shown in Figures 12(a) and 12(b) and the modified example of Example 2 shown in Figures 16(a) and 16(b), the ground wirings 34b and 34c may include a first layer of a superconducting material and a second layer of a superconducting material to which a magnetic material is added.

[0081] Although the third embodiment exemplifies a case in which the signal wiring provided on the printed circuit board includes a superconducting material and the ground wiring and ground vias include a superconducting material to which a magnetic material has been added, the present invention is not limited to this. For example, the signal wiring provided on the package substrate in FIG. 1 may include a superconducting material, and the ground wiring and ground vias may include a superconducting material to which a magnetic material has been added.

[0082] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

[0083] 10, 10a, 10b, 10c, 10d...printed circuit board, 11...upper surface, 12...lower surface, 13...signal wiring, 14a, 14b, 14c...ground wiring, 15a, 15b, 15c...insulating layer, 16...signal via, 17...ground via, 18...land, 19...strip line, 21...first layer, 22...second layer, 23...surface, 24...first layer, 25...second layer, 26...surface, 30...package substrate, 34a, 34b, 34c...ground wiring, 37...ground via, 40...interposer, 50...quantum chip, 51...qubit, 52...qubit element, 53...resonator, 54...filter, 55a, 55b...electrode, 56...Josephson junction element, 57a, 57b...superconducting film, 58...insulating film, 59...readout unit, 60, 61, 62...bonding material, 63...cover chip, 64...connector, 65...cable, 66...cooling plate, 70a, 70b, 70c...insulating layer (cured resin), 71a, 71b, 71c...insulating layer (semi-cured resin), 72...laminated body, 73...upper surface, 74...lower surface, 75...hole, 76...through hole, 77a, 77b...conductive foil, 80a, 80b, 80c...insulating layer (cured resin), 81a, 81b, 81c...insulating layer (semi-cured resin), 82...film, 83a, 83b, 83c...conductive film, 84...plating resist, 85...film, 86...film, 87...conductive film, 90...strip line, 91...signal wiring, 92...ground wiring, 93...dielectric layer, 100, 200, 210...quantum device

Claims

1. a multilayer wiring substrate including a first wiring including a superconducting material, a second wiring including a normal conducting material, and a via connected to the second wiring and including a normal conducting material; a quantum chip provided on a first surface of the multilayer wiring substrate and electrically connected to the first wiring and the via; the via is formed penetrating from the first surface to the second surface of the multilayer wiring board, The second wiring is formed so as to be exposed on the second surface of the multilayer wiring substrate.

2. The quantum device according to claim 1 , wherein the first wiring is a signal wiring and the second wiring is a ground wiring.

3. a third wiring formed on the first surface of the multilayer wiring board and including a normal conducting material; The quantum device according to claim 1 , wherein the via connects the second wiring and the third wiring to each other.

4. The quantum device according to claim 3 , wherein the first wiring is provided inside the multilayer wiring substrate and at least a portion of the first wiring overlaps both the second wiring and the third wiring in a plan view.

5. the first wiring is provided opposite one of the second wiring and the third wiring, a fourth wiring that faces the first wiring and sandwiches the first wiring between the fourth wiring and the one wiring; The quantum device according to claim 3 , wherein the first wiring, the one wiring, and the fourth wiring form a strip line.

6. At least one of the one wiring and the fourth wiring comprises a first layer including a superconducting material and provided opposite to the first wiring, and a second layer including a normal conducting material and provided on the opposite side of the first wiring with respect to the first layer, The quantum device of claim 5 , wherein the via connects to the second layer.

7. At least one of the one wiring and the fourth wiring includes a first layer including a superconducting material and provided opposite to the first wiring, and a second layer including a normal conducting material and provided around the first layer in a plan view, The quantum device of claim 5 , wherein the via connects to the second layer.

8. The quantum device according to claim 6 , wherein the first layer is provided so as to cover an area from the first wiring to a distance at least three times the width of the first wiring in a plan view.

9. a multilayer wiring board including a first wiring including a superconducting material, a second wiring including a superconducting material to which a magnetic material is added, and a via connected to the second wiring and including a superconducting material to which a magnetic material is added; a quantum chip provided on a first surface of the multilayer wiring substrate and electrically connected to the first wiring and the via; the via is formed penetrating from the first surface to the second surface of the multilayer wiring board, The second wiring is formed so as to be exposed on the second surface of the multilayer wiring substrate.

10. forming a laminate in which a signal wiring including a superconducting material and a plurality of ground wirings including a normal conducting material are stacked with an insulating layer sandwiched therebetween, the laminate having a first ground wiring among the plurality of ground wirings exposed on a first surface thereof and a second ground wiring among the plurality of ground wirings exposed on a second surface opposite to the first surface; and forming a ground via containing a normal conducting material in the laminate to connect the first ground wiring and the second ground wiring.