Time-division multiplexing system slave, method, and program
Patent Information
- Application Number
- JP2025538052
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Filing Date
- 2023-07-28
- Publication Date
- 2025-02-06
AI Technical Summary
Conventional time division multiplexing systems face increased power consumption and circuit scale due to the need for high impedance circuits and additional output terminals, which is not efficiently managed.
A time division multiplexing system with a master and multiple slaves forming a ring-type network, where output availability information is transmitted and reset between slaves, allowing data transmission without increasing the number of terminals or circuit size, and using a smart speaker device configuration with specific terminal connections and data formats to manage power consumption.
This approach suppresses power consumption increases without expanding the number of terminals or circuit size, optimizing the system's efficiency and reducing operational costs.
Abstract
Description
Time division multiplexing system slave, method and program
[0001] SUMMARY OF THE INVENTION An embodiment of the present invention relates to a time division multiplexed system slave, a method, and a program.
[0002] In a conventional time division multiplexing system (TDM system), a slave is known that has a total of four terminals: a system clock input terminal, an output flag input terminal, an output flag output terminal, and a data output terminal (see, for example, Patent Document 1).
[0003] U.S. Patent No. 8,619,821
[0004] However, in the above-described conventional time division multiplexing system, it was necessary to increase the number of terminals for outputting the output flags of the subsequent slaves. Furthermore, since all output terminals were connected, a high impedance (Hi-Z) circuit was required, which not only increased the circuit size but also increased the load capacitance and power consumption. The present invention was made in consideration of the above, and aims to provide a time division multiplexing system, slave, method, and program that can suppress increases in power consumption without increasing the number of terminals or the circuit size.
[0005] In one embodiment of the time division multiplexing system, the system has one master and multiple slaves, and the master and the multiple slaves form a ring-type communication network. When a slave transmits data including output enable information to a subsequent slave or master, if the output enable information received from the previous slave is set to an output enable state, the slave resets the output enable information to an output disable state and outputs its own data sequentially, and sets the output enable information to an output enable state and outputs it prior to the timing at which the subsequent slave transmits data.
[0006] According to the time division multiplexing system, slave, method and program of the present invention, it is possible to suppress an increase in power consumption without increasing the number of terminals or the circuit scale.
[0007] FIG. 1 is a schematic block diagram of a smart speaker device having a time division multiplexing system according to an embodiment. FIG. 2 is a diagram illustrating the configuration of an example of an audio processing unit. FIG. 3 is a diagram illustrating a communication system between an MPU and an audio processing unit. FIG. 4 is a diagram illustrating an example of a data format of time division multiplexed data according to an embodiment. FIG. 5 is a data format of an example of slot data corresponding to each slave. FIG. 6 is a diagram illustrating a detailed data format of slot data. FIG. 7 is a diagram illustrating a data transfer state. FIG. 8 is a flowchart of a slave data transfer process.
[0008] Next, an embodiment will be described with reference to the drawings. Fig. 1 is a block diagram showing the general configuration of a smart speaker device having a time division multiplexing system according to the embodiment. The smart speaker device 10 includes an MPU 11, a memory unit 12, a wireless communication interface (I / F) unit 13, a wired communication interface (I / F) unit 14, an audio processing unit 15, an operation input unit 16, a display unit 17, an audio output unit 18, and a power supply unit 19.
[0009] The MPU 11 controls the entire smart speaker device 10. The memory unit 12 includes a RAM, which is a volatile memory that functions as a work table, a flash memory, which is a non-volatile memory that stores various data in an updatable manner, and the like.
[0010] The wireless communication interface (I / F) unit 13 includes Wi-Fi, Bluetooth (registered trademark), etc., and communicates with a smartphone, a personal computer, etc. via a wireless communication network.
[0011] The wired communication interface (I / F) unit 14 includes Ethernet or the like, and communicates with a smartphone, a personal computer, or the like via a wired communication network via a communication cable.
[0012] The audio processing unit 15 processes the input audio, converts it into input audio data, and outputs it to the MPU 11. The operation input unit 16 has a plurality of operators such as a touch panel and operation buttons, and allows the user to perform various operations.
[0013] The display unit 17 has an LED indicator and displays various information. The audio output unit 18 performs digital / analog conversion of audio data input from the MPU 11 and outputs the audio from a speaker.
[0014] 2 is a diagram illustrating the configuration of an example of the audio processing unit 15. The audio processing unit 15 includes a plurality of (four in the example of FIG. 2) microphone units 21-1 to 21-4 that function as slaves.
[0015] Each of the microphone units 21-1 to 21-4 includes a microphone 21A, an analog / digital converter 21B that performs analog / digital conversion of the output of the microphone 21A and outputs it as input audio data, and a controller 21C that controls data transmission and the like.
[0016] 3 is an explanatory diagram of the communication system between the MPU and the audio processing unit. The MPU 11 functioning as the master has a system clock output terminal O_SCK, a frame clock output terminal O_WS, and a data input terminal SDI. The master MPU 11 outputs a system clock signal SCK from the system clock output terminal O_SCK and a frame clock signal WS from the frame clock output terminal O_WS.
[0017] Here, the system clock signal SCK is connected to the clock input terminals I_SCK of all slaves. The frame clock signal WS from the MPU 11 functioning as the master is connected only to the data input terminal I_DT of the first-stage slave SL1, i.e., the microphone unit 21-1.
[0018] Each of the slaves SL1 to SL3 (microphone units 21-1 to 21-3 in the example of FIG. 2) except for the final-stage slave (microphone unit 21-4 in the example of FIG. 2) outputs data to be transmitted from the output terminal O_DT to the data input terminal I_DT of the subsequent-stage slave. Furthermore, the output terminal O_DT of only the final-stage slave (microphone unit 21-64 in the example of FIG. 2) is connected to the data input terminal SDI of the MPU functioning as the master.
[0019] In this case, the clock frequency fsck, which is the frequency of the system clock signal SCK, is given by fsck=fs×M×N, where M is the number of slaves, fs is the frame clock frequency, and N is the bit width of one slot.
[0020] Furthermore, the MPU 11 functioning as a master must set the clock frequency fsck according to the number of slaves.
[0021] Furthermore, each of the microphone units 21-1 to 21-4 functioning as a slave can recognize the number of slaves, and in the case of a first-stage slave, there is a method in which the master recognizes it via I2C, or a method in which the slave itself automatically recognizes it from the fsck period and fs period. In addition, in the case of a second-stage slave, the number of slaves can be automatically recognized from the output flag period and fsck period in the setting data.
[0022] On the other hand, the microphone units 21-1 to 21-4 functioning as slaves each include a microphone 21A that converts input audio into an input audio signal (analog signal) and outputs it, an analog / digital converter (ADC) 21B that performs analog / digital conversion of the input audio signal and outputs it as audio data described below, and a controller 21C.
[0023] In this case, the MPU 11 functioning as a master and the microphone units 21-1 to 21-4 functioning as slaves form a ring network in which time-division multiplexed data is transferred sequentially from the microphone units 21-1 to 21-4 to the MPU 11.
[0024] That is, when the MPU 11 functioning as the master outputs the frame clock signal WS, the transmission data is transmitted in the order of microphone unit 21-1 → microphone unit 21-2 → microphone unit 21-3 → microphone unit 21-4 → MPU 11.
[0025] 4 is a diagram illustrating an example of a data format of time division multiplexed data according to an embodiment. Two frames of time division multiplexed data DTDM are shown in FIG. The time division multiplexed data DTDM is configured as so-called frame data, and one frame can time division multiplex data from four slaves.
[0026] The time division multiplexed data DTDM has four slots SLT1 to SLT4 in one frame, each corresponding to a slave. Therefore, the time division multiplexed data DTDM in Fig. 4 can transfer audio data from four slaves, i.e., four microphone units, per frame.
[0027] More specifically, when the frame clock signal WS rises at time t0, for example, data is sequentially transmitted from the slaves SL1 to SL4 to the MPU 11 functioning as the master after time t1 when the frame clock signal WS falls. Note that data may also be transmitted at the rising edge of the frame clock signal WS.
[0028] Fig. 5 shows an example of the data format of slot data corresponding to each slave. In this embodiment, the data length of the slot data DT is a fixed length of 32 bits, as shown in Fig. 5. However, the data length of the slot data DT is not limited to 32 bits, and can be set to any number of bits.
[0029] 6 is an explanatory diagram of the detailed data format of the slot data DT. The slot data DT comprises 24-bit audio data DTa and 8-bit control data DTc.
[0030] In this case, the data format of the audio data DTa can be set appropriately according to the specifications of the smart speaker device 10. For example, I2S, Sound-Wire, TDM, etc. can be used.
[0031] The control data DTc includes fixed value data Dfx, a format bit Dfm, and an output flag bit Dof. In the example of FIG. 6, from the most significant bit to the least significant bit, the fixed value data Dfx is 6 bits, and the format bit Dfm and output flag bit Dof are each 1 bit, for a total of 8 bits. The fixed value data Dfx is used to identify the positions of the audio data DTa, the format bit Dfm, and the output flag bit Dof, and any bit width and value can be selected. Furthermore, a subsequent slave confirms that this fixed value data Dfx has been input, and if it can then confirm the output flag bit Dof (="1"), it will output its own audio data DTa and control data DTc to the subsequent slave.
[0032] If the bit width of the fixed value data Dfx is small, it may not be possible to separate it from the audio data DTa, which could result in erroneous detection. Increasing the bit width of the fixed value data Dfx can suppress erroneous recognition, but this reduces the amount of information that can be used as the audio data DTa, which means that there is no correlation with the audio data, resulting in a trade-off between detection accuracy and the accuracy of the audio data DTa.
[0033] The least significant bit of the control data DTc is an output flag bit Dof, which functions as output enable / disable information indicating whether the slave is capable of outputting its own data.
[0034] When a slave receives slot data DT with this output flag bit Dof in an enabled state ("1" in the following explanation) from a preceding slave, it updates the audio data DTa of the slot corresponding to itself in the time division multiplexed data DTDM and outputs it to the succeeding slave or master.
[0035] In this case, each slave processes the audio data DTa corresponding to the preceding slave or the audio data DTa corresponding to itself based on the control data DTc, and outputs it to the succeeding slave or the master.
[0036] FIG. 7 is an explanatory diagram of the data transfer state. FIG. 8 is a processing flowchart of the slave data transfer process. In FIG. 7, the notation "D_init" in the data content of the audio data DTa indicates a state in which no effective data has yet been stored, for example, all 24 bits are 0 data, representing the initial state. In the following description, the time required to transfer data corresponding to one slot to the next slave will be referred to as the unit slot time.
[0037] Furthermore, the time from the latest timing at which the frame clock signal WS transitions to the “H” level until the elapse of a unit slot time is called the first slot period, the time from the timing at which the first slot period elapses until the elapse of a unit slot time is called the second slot period, the time from the timing at which the second slot period elapses until the elapse of a unit slot time is called the third slot period, and the time from the timing at which the third slot period elapses until the elapse of a unit slot time is called the fourth slot period.
[0038] FIG. 7A is an explanatory diagram of input data and output data in the microphone unit 21-1 functioning as a slave.
[0039] First, controller 21C of microphone unit 21-1 functioning as a slave determines whether or not a frame clock signal WS has been input to input terminal I_DT during the first slot period (step S11 in FIG. 8). In this case, the latest frame clock signal WS has been input as input data to input terminal I_DT from MPU 11 functioning as a master (step S11 in FIG. 8; Yes), so controller 21C of microphone unit 21-1 functioning as slave SL1 outputs its own transmission data (step S13 in FIG. 8). More specifically, controller 21C of microphone unit 21-1 first outputs 24-bit audio data DTa-1 one bit at a time at the data transmission timing corresponding to the first slot period.
[0040] Next, the controller 21C of the microphone unit 21-1 outputs the 8-bit control data DTc-1 bit by bit. Then, to indicate that the corresponding audio data DTa-1 has been output during the first slot period, the controller 21C of the microphone unit 21-1 sets the output flag bit Dof, which is the least significant bit of the control data DTc-1, to "1," thereby notifying the microphone unit 21-2 that output is now possible (step S14 in FIG. 8).
[0041] As a result of the above operation, the microphone unit 21-1 transmits the first slave data D_SL1, which is data corresponding to itself, to the downstream microphone unit 21-2.
[0042] Here, the controller 21C of the microphone unit 21-1 determines whether or not the frame clock signal WS has been input to the input terminal I_DT during the second slot period to the fourth slot period (step S11).
[0043] In this case, since the frame clock signal WS is not input to the input terminal I_DT (step S11; No), the controller 21C of the microphone unit 21-1 determines whether the output enable / disable information of the transmission data of the previous slave, whose input terminal I_DT has received the frame clock signal WS, is in an output state (step S15).
[0044] At this stage, the output flag bit Dof, which is the lowest bit (=7th bit) of the control data DTc-1 corresponding to the output enable / disable information of the transmission data of the previous slave, is 0, and the output enable / disable information is in an output disabled state (step S15; No), so the controller 21C of the microphone unit 21-1 outputs the initial data as transmission data in the second slot period to the fourth slot period and ends the processing (step S16).
[0045] FIG. 7B is an explanatory diagram of input data and output data in the microphone unit 21-2 functioning as a slave.
[0046] During the first slot period, first, controller 21C of microphone unit 21-2 functioning as a slave determines whether or not a frame clock signal WS has been input to input terminal I_DT (step S11 in FIG. 8). In the determination of step S11 in FIG. 8, since the frame clock signal WS has not been input to input terminal I_DT (step S11 in FIG. 8; No), controller 21C of microphone unit 21-2 determines whether or not the output enable / disable information of transmission data of the preceding slave whose input terminal I_DT received the frame clock signal WS is in the output state (step S15 in FIG. 8). That is, upon completion of data transmission from microphone unit 21-1 functioning as slave SL1, controller 21C of microphone unit 21-2 functioning as slave SL2 extracts output flag bit Dof, which is the least significant bit of control data DTc-1 during the first slot period, and determines whether output flag bit Dof="1" or not.
[0047] In this case, since the output flag bit Dof, which is the least significant bit of the control data DTc-1 in the first slot period, is "1" (step S15 in Figure 8; Yes), the controller 21C of the microphone unit 21-2 determines that it is itself that should update the data next, and resets the output flag bit Dof, which is the least significant bit of the control data DTc-1 in the first slot period, to "0", which indicates an output-disabled state (step S12 in Figure 8).
[0048] Next, controller 21C of microphone unit 21-2 functioning as slave SL2 outputs its own transmission data (step S13 in FIG. 8). More specifically, controller 21C of microphone unit 21-2 first outputs 24-bit audio data DTa-1 bit by bit at the data transmission timing corresponding to the first slot period.
[0049] Next, the controller 21C of the microphone unit 21-2 outputs the 8-bit control data DTc-1 bit by bit with the output flag bit Dof changed, and then outputs the 24-bit audio data DTa-2 bit by bit at the data transmission timing for the second slot period.
[0050] Then, the controller 21C of the microphone unit 21-2 sets the output flag bit Dof, which is the least significant bit of the control data DTc-2, to "1" to indicate that the corresponding audio data DTa-2 has been output during the second slot period, thereby notifying the microphone unit 21-3 that output is now possible (step S14 in Figure 8).
[0051] As a result of the above operation, the controller 21C of the microphone unit 21-2 transmits the second slave data D_SL2, which is data corresponding to itself, and the transmission data from the upstream microphone unit 21-1 to the downstream microphone unit 21-3.
[0052] FIG. 7C is an explanatory diagram of input data and output data in the microphone unit 21-3 functioning as a slave.
[0053] During the second slot period, first, the controller 21C of the microphone unit 21-3 functioning as a slave determines whether or not a frame clock signal WS has been input to the input terminal I_DT (step S11 in FIG. 8). Since the frame clock signal WS has not been input to the input terminal I_DT in the determination of step S11 in FIG. 8 (step S11; No), the controller 21C of the microphone unit 21-3 determines whether or not the output enable / disable information of the transmission data of the microphone unit 21-2 functioning as the slave SL2, which is the preceding slave, is in the output state (step S15 in FIG. 8). That is, upon completion of the data transmission of the microphone unit 21-2 functioning as the slave SL2, the controller 21C of the microphone unit 21-3 functioning as the slave SL3 extracts the output flag bit Dof, which is the least significant bit of the control data DTc-2 during the second slot period, and determines whether or not the output flag bit Dof="1".
[0054] In this case, since the output flag bit Dof, which is the least significant bit of the control data DTc-2 during the second slot period, is "1" (step S15 in Figure 8; Yes), the controller 21C of the microphone unit 21-3 determines that it is itself that should update the data next, and resets the output flag bit Dof, which is the least significant bit of the control data DTc-2 during the second slot period, to "0", which indicates an output-disabled state (step S12 in Figure 8).
[0055] Next, controller 21C of microphone unit 21-3 functioning as slave SL3 outputs its own transmission data (step S13 in FIG. 8). More specifically, controller 21C of microphone unit 21-3 first outputs 24-bit audio data DTa-1 one bit at a time at the data transmission timing corresponding to the first slot period. Next, controller 21C of microphone unit 21-3 outputs 8-bit control data DTc-1 one bit at a time. Next, controller 21C of microphone unit 21-3 outputs 24-bit audio data DTa-2 one bit at a time at the data transmission timing corresponding to the second slot period, and then outputs 8-bit control data DTc-2 one bit at a time with the output flag bit Dof changed.
[0056] Subsequently, the controller 21C of the microphone unit 21-3 outputs 24-bit audio data DTa-3 bit by bit, and further outputs 8-bit control data DTc-3 bit by bit, at the data transmission timing corresponding to the third slot period.
[0057] Then, the controller 21C of the microphone unit 21-3 sets the output flag bit Dof, which is the least significant bit of the control data DTc-3, to "1" to indicate that the corresponding audio data DTa-3 has been output during the third slot period, thereby notifying the microphone unit 21-4, which functions as the next slave, that output is now possible (step S14 in Figure 8).
[0058] As a result of the above operation, the controller 21C of the microphone unit 21-3 transmits the third slave data D_SL3, which is the data corresponding to itself, and the transmission data from the upstream microphone units 21-1 and 21-2 to the downstream microphone unit 21-4.
[0059] FIG. 7D is an explanatory diagram of input data and output data in the microphone unit 21-4 functioning as a slave.
[0060] During the third slot period, first, controller 21C of microphone unit 21-4 functioning as a slave determines whether a frame clock signal WS has been input to input terminal I_DT (step S11 in FIG. 8). Since the frame clock signal WS has not been input to input terminal I_DT in the determination of step S11 in FIG. 8 (step S11; No), controller 21C of microphone unit 21-4 determines whether the transmission data output enable / disable information of microphone unit 21-3 functioning as slave SL3, the preceding slave, is in the output state (step S15 in FIG. 8). That is, upon completion of data transmission from microphone unit 21-3 functioning as slave SL3, controller 21C of microphone unit 21-4 functioning as slave SL4 extracts output flag bit Dof, which is the least significant bit of control data DTc-3 during the third slot period, and determines whether output flag bit Dof="1".
[0061] In this case, since the output flag bit Dof, which is the least significant bit of the control data DTc-3 during the third slot period, is "1" (step S15 in Figure 8; Yes), the controller 21C of the microphone unit 21-4 determines that it is itself that should update the data next, and resets the output flag bit Dof, which is the least significant bit of the control data DTc-3 during the third slot period, to "0", which indicates an output-disabled state (step S12 in Figure 8).
[0062] Next, controller 21C of microphone unit 21-4 functioning as slave SL4 outputs its own transmission data (step S13 in FIG. 8). More specifically, controller 21C of microphone unit 21-4 first outputs 24-bit audio data DTa-1 one bit at a time at the data transmission timing corresponding to the first slot period. Next, controller 21C of microphone unit 21-4 outputs 8-bit control data DTc-1 one bit at a time.
[0063] Next, at the data transmission timing corresponding to the second slot period, controller 21C of microphone unit 21-4 outputs 24-bit audio data DTa-2 one bit at a time, followed by 8-bit control data DTc-2 one bit at a time.Furthermore, at the data transmission timing corresponding to the third slot period, controller 21C of microphone unit 21-4 outputs 24-bit audio data DTa-3 one bit at a time, followed by 8-bit control data DTc-3 one bit at a time with the output flag bit Dof changed.
[0064] Furthermore, the controller 21C of the microphone unit 21-4 outputs 24-bit audio data DTa-4 bit by bit, and also outputs 8-bit control data DTc-4 bit by bit, at the data transmission timing corresponding to the fourth slot period.
[0065] Then, the controller 21C of the microphone unit 21-4 notifies the MPU 11 functioning as the master by setting the output flag bit Dof, which is the least significant bit of the control data DTc-4, to "1" to indicate that the corresponding audio data DTa-4 has been output during the fourth slot period. This allows the MPU 11 functioning as the master to detect that the data transmission has ended.
[0066] As a result of the above operation, the microphone unit 21-4 transmits the data corresponding to itself and the transmission data from the upstream microphone units 21-1 to 21-3 to the downstream MPU 11.
[0067] That is, at the end of the fourth slot period, all of the audio data DTa from the microphone units 21-1 to 21-4 is transmitted to the MPU 11 functioning as the master.
[0068] Here, the parallel operation of the controllers 21C of the microphone units 21-1 to 21-4 will be described. During the first slot period, in parallel with the operation of the controller 21C of the microphone unit 21-1, the controllers 21C of the microphone units 21-2 to 21-4 determine whether or not a frame clock signal WS has been input to the input terminal I_DT during the first slot period (step S11 in FIG. 8).
[0069] In this case, since the frame clock signal WS is not input to the input terminal I_DT (step S11 in Figure 8; No), the controller 21C of microphone unit 21-2 to microphone unit 21-4 determines whether the output enable / disable information of the transmission data of the previous slave to which the frame clock signal WS is input to the input terminal I_DT is in an output state (step S15 in Figure 8).
[0070] At this stage, the output flag bit Dof, which is the least significant bit of control data DTc-1 corresponding to the output enable / disable information of the transmission data of the preceding slave, is 0, and the output enable / disable information is in an output disabled state (step S15 in FIG. 8; No), so controllers 21C of microphone units 21-2 to 21-4 output the initial data as transmission data in the first slot period and end the process (step S16 in FIG. 8). Also, in the second slot period to the fourth slot period, they operate in parallel in the same way as in the first slot period.
[0071] As described above, the MPU 11 processes the audio data DTa transmitted from the microphone units 21-1 to 21-4 and transmits the audio data to a smartphone or personal computer via a wireless communication interface or a wired communication interface, where it is used as audio for calls, audio for web conferences, etc.
[0072] [4] Effects of the Embodiments As described above, according to the above embodiments, it is possible to suppress an increase in power consumption without increasing the number of terminals or the circuit size.
[0073] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as set forth in the claims. For example, in the above description, a one-bit output flag bit is used as output enable / disable information indicating whether or not the device's own data is output, but it is also possible to configure it to contain multiple bits of information.
[0074] 10 Smart speaker device 11 MPU 12 Memory unit 13 Wireless communication interface unit 14 Wired communication interface unit 15 Audio processing unit 16 Operation input unit 17 Display unit 18 Audio output unit 19 Power supply unit 21-1 to 21-4 Microphone unit 21A Microphone 21B Analog / digital converter 21C Controller D_SL1 First slave data D_SL2 Second slave data D_SL3 Third slave data D_SL4 Fourth slave data DT Slot data DTDM Time division multiplexed data DTa Audio data DTc Control data Dfm Format bit Dfx Fixed value data Dof Output flag bit I_DT Data input terminal O_DT Data output terminal O_SCK System clock output terminal O_WS Frame clock output terminal SCK System clock signal SDI Data input terminal SL1 to SL4 Slave SLT1 to SLT4 Slot I_SCK Clock input terminal WS Frame clock signal
Claims
1. A time division multiplexing system having one master and a plurality of slaves, wherein the master and the plurality of slaves form a ring-shaped communication network, and when a slave transmits data including output enable information to a subsequent slave or the master, if the output enable information received from the previous slave is set to an output enable state, the slave resets the output enable information to an output disable state and sequentially outputs its own data, and sets the output enable information to an output enable state and outputs it prior to the timing at which the next slave transmits data.
2. The time division multiplexing system according to claim 1, wherein an output flag is used as the output permission information.
3. The time division multiplexing system according to claim 1, wherein said master terminates data transmission when said output enable / disable information set to said output enable state is input.
4. A time division multiplexing system as described in claim 1, wherein the slave obtains the total number of slaves constituting the time division multiplexing system by being notified by the master, or by automatically obtaining the number by counting the number of system clocks within one frame clock.
5. A time division multiplexing system according to claim 1, wherein said own data includes audio data and control data, and said slave processes said audio data based on said control data and outputs it to a subsequent slave or to said master.
6. A slave capable of forming a ring-type communication network constituting a time division multiplexing system in cooperation with a master and other slaves, which, when transmitting data including output enable / disable information to a subsequent slave or the master, resets the output enable / disable information to an output disable state if the output enable information received from the previous slave is set to an output enable state, and outputs its own data sequentially, and sets the output enable / disable information to an output enable state and outputs it prior to the timing at which the next slave transmits data.
7. A method executed by a slave capable of forming a ring-type communication network constituting a time division multiplexing system in cooperation with a master and other slaves, comprising the steps of: when transmitting data including output enable information to a subsequent slave or the master, if the output enable information received from the previous slave is set to an output enable state, resetting the output enable information to an output disable state and outputting the slave's own data sequentially; and setting the output enable information to an output enable state and outputting it prior to the timing at which the subsequent slave transmits data.
8. A program for controlling a slave by a computer that can cooperate with a master and other slaves to form a ring-type communication network that constitutes a time division multiplexing system, the program functioning as: when transmitting data including output enable information to a subsequent slave or master, if the output enable information received from the previous slave is set to an output enable state, resetting the output enable information to an output disable state and sequentially outputting its own data; and setting the output enable information to an output enable state and outputting it prior to the timing at which the next slave transmits data.