Quantum semiconductor circuit

Abstract

This quantum semiconductor circuit comprises: a single-electron device (SET) that senses the state of a silicon qubit; a first node (QDO) that is connected to a first precharge potential (VPCHA); a second node (LDO) that is connected to a second precharge potential (VPCH) being higher than the first precharge potential; a first amplification circuit that is electrically connected to the single-electron transistor (SET) via the first node (QDO) and has a first charge transfer MIS circuit for transferring the charge of the second node (LDO) to the first node (QDO); a second amplification circuit that is electrically connected to the first amplification circuit via the second node (LDO) and has a second charge transfer MIS circuit for transferring the charge of a third node (RDO) to the second node (LDO); and a third amplification circuit that outputs a potential to a data line and performs amplitude amplification in response to the third node (RDO) reaching a prescribed potential by means of the first amplification circuit and the second amplification circuit.

Description

Quantum Semiconductor Circuits

[0001] The present disclosure relates to quantum semiconductor circuits.

[0002] There is great interest in building quantum computers that can perform at high speeds and in a cost-effective manner. Quantum computers use superconducting logic-based devices, which are typically cooled to cryogenic temperatures to function in a superconducting state. Patent Document 1 (JP 2021-523572 A) discloses a system including at least two sets of superconducting logic devices, a cooling apparatus adapted to cool the logic devices to a first operating temperature, and an interconnect that couples the superconducting logic devices.

[0003] JP 2021-523572 A JP 2023-3726 A

[0004] Sushil Subramanian, “Spin Qubits: Principles, Control / Readout Architectures, and Cryoelectronic Solutions”, The IEEE International Solid-State Circuits Conference (ISSCC), 2023

[0005] Previously, quantum semiconductors have demonstrated quantum operation at 1 to 100 qubits in an absolute zero atmosphere, achieved using dilution refrigerators and other devices. However, systems with a medium number of qubits do not provide sufficient computational resources for analyzing complex phenomena. On the other hand, to secure sufficient computational resources by further increasing the number of qubits, it becomes important to highly integrate the readout circuit, which detects and amplifies the output current, or Elsermann current, that indicates the difference in the spin state of the qubits. If the circuit scale (dimensions) of this readout circuit, which reads out the information from one qubit, is large, the quantum semiconductor chip size will increase as the qubit capacity increases. As a result, the chip's current consumption increases, raising the temperature of the absolute zero atmosphere, a necessary condition for quantum operation.

[0006] Non-Patent Document 1 discloses a method in which differences in spin information within a quantum bit are converted into large and small currents using a single-electron transistor, and the large and small values ​​of the single-electron transistor current are read out externally from the chip as large and small impedances. This method requires large passive components such as inductors and capacitors, and poses the problem of increasing chip size due to increased capacity, making it unsuitable for large-scale silicon quantum bits.

[0007] Patent Document 2 (JP 2023-3726 A) discloses a method in which quantum bit information, which is a complementary signal from a quantum bit array that holds complementary information, is output from a single-electron device connected to the quantum bit, and the signal is further amplified by a differential amplifier circuit connected to the single-electron device. In this method, the drain-source voltage of the single-electron device becomes the input differential potential of the differential amplifier circuit. As a result, an input differential potential necessary for differential circuit operation is generated, which causes fluctuations in the sweep current value of the single-electron device, and may prevent the desired readout operation.

[0008] In view of the above background, an object of the present disclosure is to provide a semiconductor quantum circuit that can amplify the minute current of a single electron transistor (SET) and read out the quantum bit state with high accuracy, in order to realize large-scale silicon quantum bits.

[0009] In order to solve the above problems, the present disclosure provides a semiconductor quantum circuit comprising: a quantum bit array circuit including a plurality of quantum bit elements and a plurality of single-electron elements for detecting the spin states of the plurality of quantum bit elements; a first node that is a quantum bit readout line that outputs a readout current representing the spin state from the quantum bit element; and a quantum bit readout current amplifier circuit connected to the first node, wherein the quantum bit readout current amplifier circuit is configured to set the first node to a first pre-charge potential, and the quantum bit readout current amplifier circuit is configured to set the first node to a second pre-charge potential that is higher than the first pre-charge potential. a node, a first amplifier circuit electrically connected to the single-electron element via the first node and having a first charge transfer MIS circuit that transfers the charge stored in the second node to the first node; a second amplifier circuit electrically connected to the first amplifier circuit via the second node and electrically connected to a third amplifier circuit via a third node and having a second charge transfer MIS circuit that transfers the charge stored in the third node to the second node; and the third amplifier circuit that outputs a potential to a data line and amplifies the amplitude in response to the third node reaching a predetermined potential via the first amplifier circuit and the second amplifier circuit.

[0010] According to the present disclosure, in order to realize large-scale silicon quantum bits, it is possible to amplify the minute current of a single electron transistor (SET) and read out the quantum bit state with high accuracy. Note that the effects described here are not necessarily limited to those described herein, and any of the effects described in the present disclosure may be used.

[0011] FIG. 1 is a circuit diagram of a quantum semiconductor quantum bit section according to an embodiment. FIG. 2 is a readout circuit diagram for amplifying a quantum semiconductor quantum bit signal according to an embodiment. FIG. 3 is a diagram showing the operation sequence of a readout circuit for amplifying a quantum semiconductor quantum bit signal according to an embodiment. FIG. 4 is a block circuit diagram integrating quantum semiconductor quantum bits and a readout circuit according to an embodiment. FIG. 5 is a block circuit diagram integrating a quantum semiconductor quantum bit array according to an embodiment. FIG. 6 is a block circuit diagram of an entire quantum semiconductor chip according to an embodiment. FIG. 7 is a block diagram showing a quantum computer using a quantum semiconductor according to an embodiment. FIG. 8 is a diagram showing a method of implementing a quantum semiconductor chip according to an embodiment in a dilution refrigerator.

[0012] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, detail, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements, etc. (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the number of characteristics, unless otherwise specified or when it is clearly limited to a specific number in principle.

[0013] Furthermore, in the following embodiments, it goes without saying that the components (including element steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numerical values ​​and ranges.

[0014] When describing elements of the same type without distinguishing between them, the common portion (the portion excluding the branch number) of the reference sign including the branch number may be used, and when describing elements of the same type while distinguishing between them, the reference sign including the branch number may be used. For example, taking the quantum bit transistor shown in Figure 1 as an example, when describing individual quantum bit transistors without distinguishing between them, they may be referred to as "quantum bit transistor MQ," and when describing individual quantum bit transistors while distinguishing between them, they may be referred to as "quantum bit transistor MQ0," "quantum bit transistor MQ1," etc.

[0015] The circuit configuration of a quantum semiconductor according to this embodiment and its layout and wiring method will be described with reference to FIGS. 1 to 8. FIG. 1 is a circuit diagram SQBA of a quantum bit section of a quantum semiconductor according to this embodiment. FIG. 1 shows a reservoir RSEV that supplies electrons or holes, which are charged particles that form the quantum bit; a quantum bit transistor MQ for storing the quantum bit and drive wiring XQ0-XQ3 that drives it; a quantum control transistor MJ and control wiring XJ0-XJ4 that drives it; single-electron elements SETU0-SETU10 and SETD0-SETD10 arranged above and below the quantum bit transistor MQ and the quantum control transistor MJ, drive terminal wiring XQE0-XQE3 electrically connected to their gate electrodes; and the control wiring XJ0-XJ4. Also shown are reservoir elements MR00, MR10 and source control elements MS00, MS10, which form the potential distribution necessary to send charged particles to the quantum bit transistor MQ, as well as reservoir control lines GRE and source control lines GSR that control them. The Source in the figure is a terminal line for controlling the potential relationship with RSEV. Note that in the configuration of Figure 1, two transistor elements are shown as one unit. This is because in advanced silicon semiconductor processes, it is difficult to physically separate the gate electrodes (metal gates) of each transistor element, and the configuration shown in Figure 1 may make manufacturing easier.

[0016] While there are various methods for quantum operations (quantum computing) using quantum bits, the present example in Figure 1 will explain the use of magnetic resonance. First, charged particles (quantum bits) are stored in the quantum bit transistor MQ from the reservoir RSEV. To store the charged particles, appropriate potentials are applied to the gate electrodes of the quantum bit transistor MQ and the quantum control transistor MJ, transferring the charged particles one by one from the reservoir. After the quantum bits are stored (initialized) one by one in the quantum transistor, a standby potential (e.g., a negative potential) is applied to the gate electrode of the quantum control transistor MJ, setting the potential barriers on both ends of the quantum bit high and controlling the quantum bit to remain in its designated position in the quantum transistor MQ. Although not shown in the figure to avoid cluttering the diagram, a static magnetic field is applied to the entire quantum semiconductor using a superconducting magnet installed in the dilution refrigerator that implements the quantum semiconductor. The static magnetic field aligns the spin states of the charged particles to the ground state (e.g., all quantum bits are in the up-spin state), thereby initializing the quantum bit state. The initialized quantum bit precesses at a certain resonant frequency.

[0017] After storing the quantum bit in a predetermined position, reverse currents are passed through the quantum bit control wiring XJ0 and the quantum bit drive wiring XJ1, for example. Passing reverse currents generates a local magnetic field in the quantum bit transistors MQ00 and MQ10. The generated local magnetic field shifts the resonant frequencies of the quantum bits MQ00 and MQ10 by a certain amount. By irradiating microwaves with the same frequency as this shifted resonant frequency, the quantum bits can be selectively rotated. In the example shown in Figure 1, the quantum bits MQ00 and MQ10 all have the same resonant frequency, so both quantum bits are rotated in the same way. For example, MQ00 and MQ10 are rotated to an up-spin state. Note that the quantum bits MQ01, MQ11, MQ02, MQ12, MQ03, and MQ13, which do not generate a local magnetic field, maintain their ground state even when microwaves are irradiated for the same period of time because their resonant frequencies are different from the microwaves. By performing similar control, the example in FIG. 1 shows, using arrows, a case in which MQ01 and MQ11 are downspin, MQ02 and MQ12 are upspin, and MQ03 and MQ13 are downspin.

[0018] To read the information from the quantum-manipulated quantum bits MQ00 and MQ10, the quantum state is maintained while the quantum bit drive wire XQ and quantum bit control wire XJ are controlled to the desired potential, transferring the quantum information to the positions of MQ03 and MQ13. The quantum bits stored in MQ03 and MQ13 move to the source terminal line Source with a certain probability due to the tunneling current mechanism, and then return to the designated position of the original quantum bit element (Elsermann mechanism). This quantum bit behavior causes the gate potential of the single-electron device SU13, located opposite MQ03, to fluctuate, resulting in a predetermined current fluctuation (e.g., from 500 pA to 50 pA) on the quantum readout data line QDOU. Similarly, the gate potential of the single-electron device SD03, located opposite MQ13, fluctuates, resulting in a predetermined current fluctuation (e.g., from 500 pA to 50 pA) on the quantum readout data line QDOD. In this way, in the example of Figure 1, the same quantum bit information is output to the quantum readout data lines QDOU and QDOD. On the other hand, if down-spin information is stored in the quantum bit transistors MQ03 and MQ13, the tunneling current mechanism described above does not occur, and no current fluctuations appear in the quantum readout data lines. In this way, if the difference in output current fluctuations due to differences in quantum bit states can be read and amplified to logic levels, i.e., the power supply voltage levels VCCA (0.75V) and VSSA (0V) of the LSI circuit, the quantum operation results can be output externally to the quantum semiconductor.

[0019] 2 shows a quantum bit read current amplifier circuit according to an embodiment of the present invention. The amplifier circuit of this embodiment is composed of a first amplifier circuit that controls the gate electrode TPA, a second amplifier circuit that controls the gate electrode TRD, a local data line LDO that electrically connects the first amplifier circuit and the second amplifier circuit, and a third amplifier circuit that is composed of a so-called differential amplifier in which the gate electrodes of an NMOS pair are differential inputs and a PMOS level holder is connected.

[0020] The gate potential of one NMOS transistor in the third amplifier circuit is connected to the drain of the second amplifier circuit, forming the read data line RDO. The quantum bit read line QDO, local data line LDO, and read data line RDO are connected to precharge circuits that precharge to the array precharge voltage VPCHA, half precharge voltage VPCH, and precharge voltage VPCHS, respectively, and precharge activation signals PCH, PCH1, and PCH2 are connected to their gate electrodes. The third amplifier circuit starts amplifying by asserting the amplifier activation signal PSN high, and outputs an amplified differential potential to the data lines DT and DB. The amplified differential potential output to the data line pair is amplified to the full amplitude potential of the power supply voltages VCCA and VSSA by asserting the common source activation signals CSN and CSP of the so-called cross-coupled amplifier circuit in the subsequent stage, and the information is latched by the cross-coupled amplifier circuit. The latched signal potential is then transmitted to an information device outside the quantum semiconductor via the external data line EXRT in the subsequent buffer circuit. The data line pair DT and DB are precharged to, for example, the VCCA level using a data line precharge circuit composed of a pMOS equalizer and a level holder pMOS element.

[0021] The quantum bit readout line QDO may also be referred to as a “first node,” the local data line LDO may also be referred to as a “second node,” and the readout data line RDO may also be referred to as a “third node.” A node refers to an element (e.g., a connecting line) that enables electrical connection of elements that constitute a circuit.

[0022] The first precharge potential (array precharge voltage VPCHA) of the first node may be 0.1 mV to 20 mV, the second precharge potential (half precharge voltage VPCH) of the second node may be greater than the first precharge potential of the first node and less than the third precharge potential of the third node (for example, it may be around 1 / 2 or 1 / 2 of the high level of the power supply voltage), and the third precharge potential (precharge voltage VPCHS) of the third node may be equivalent to the high level of the power supply voltage.

[0023] The MOS transistors (Metal Oxide Semiconductor Field Effect Transistors) (NMOS transistors) 21a and 21b included in the first amplifier circuit are a type of MISFET (Metal Insulator Semiconductor Field Effect Transistor). A circuit including the MOS transistor 21b is sometimes referred to as a "first charge transfer MIS circuit."

[0024] The MOS transistor (PMOS transistor) 22a and the MOS transistor (NMOS transistor) 22b included in the second amplifier circuit are a type of MISFET, and a circuit including the MOS transistor 22b is sometimes called a "second charge transfer MIS circuit."

[0025] Next, the operational sequence of the amplifier circuit of this embodiment will be explained using Figure 3. Before operating this amplifier circuit, the spin state of the desired quantum bit is determined. During this period, each precharge circuit, which is a component of the amplifier circuit, is activated, and the quantum read data line QDO is precharged to approximately 10 mV, the local data line LDO is precharged to 0.375 V, and the read data line RDO is precharged to 0.75 V. Since the state of the quantum bit transistor MQ is determined, setting the gate electrode of the single-electron element to the desired potential causes the gate potential of the single-electron element SETU8 or SETD8 to fluctuate depending on the state of the quantum bit element, outputting a signal to the quantum read data line QDO.

[0026] In this state, the TPA potential is set to, for example, 270 mV to activate the first amplifier circuit. At this time, it is advisable to additionally connect a stabilizing capacitance CQDL to the quantum bit read data line QDO and a stabilizing capacitance CLDL to the local data line LDO. Preferably, the capacitance value of the capacitor for stable operation is femtofarads (10 -15) is preferable. Furthermore, it is preferable to ensure that these capacitance values ​​satisfy the relationship CQDL > CLDL. With this circuit connection and potential relationship of each node, when the first amplifier circuit is activated, a signal potential is output to the local data line LDO that is amplified to a certain extent from the maximum initial difference potential that can be output to the quantum read data line, that is, within the range in which the single-electron device can operate.

[0027] Specifically, under conditions where only an initial potential difference of 5 mV appears on the quantum readout data line, a potential difference of approximately 20 mV occurs on the local data line LDO. If the potential fluctuation on the quantum readout data line exceeds 5 mV, the amplification effect of the single-electron device decreases, potentially resulting in erroneous amplification of the information held by the quantum bit. Therefore, in this embodiment, the addition of a CQDL prevents the potential on the quantum readout data line from fluctuating more than necessary. Preferably, the activation signal TPA of the first amplifier circuit, once asserted, is negated. This allows the local data line LDO to maintain a potential difference corresponding to the information held in the quantum bit. By asserting the activation signal TRD of the second amplifier circuit, this maintained potential difference can be further amplified and output to the readout data line RDO.

[0028] The principle of amplification in this case is the same as that of the first amplifier circuit. Preferably, the value of the stabilizing capacitance CLDL is set larger than the parasitic capacitance of the read data line RDO. This setting allows the charge on the read data line RDO to be efficiently discharged to the local data line LDO. Also, as shown in FIG. 3, after a signal level corresponding to the information stored in the quantum bit is amplified and output to the read data line RDO, a reference voltage (e.g., 600 mV) is input to the reference potential side of the NMOS differential input of the third amplifier circuit. The activation signal PSN of the third amplifier circuit is turned on at a timing that determines whether the potential of the read data line RDO is higher (dashed line) or lower (solid line) than the reference voltage VREF. Preferably, the activation signal PSN of the third amplifier circuit is turned on at a timing when the potential difference between the reference voltage and the higher potential becomes equal to the potential difference between the reference voltage and the lower potential. This control outputs complementary signals to the data line pair DT and DB. Then, by activating the latch-type cross-coupled amplifier circuit, the data line pair is fully amplified to the power supply voltage of the LSI circuit.

[0029] FIG. 4 is a block circuit diagram showing the connection relationship between the quantum bit array SQBA and the quantum bit readout current amplifier circuit of this embodiment. The drive wiring and control wiring of the quantum bit array SQBA are connected to so-called NAND circuits located in the driver circuits DRVU and DRVD arranged above and below it. Selector circuits SELU and SELD are also arranged adjacent to the driver circuits. A low active signal line MWLB is connected to this selector circuit, and its inverted signal line SXJT is connected to the driver circuit. By connecting this inverted signal line to the NAND circuit in the driver circuit, the gate electrode potential of a desired quantum bit transistor can be selectively controlled. The block circuits shown by dashed lines in the figure are quantum bit readout current amplifier circuits ((SACKTU) and (SACTKD)), selector circuits ((SELU) and (SELD)), and quantum readout data lines ((QDOU) and (QDOD)) connected to another quantum bit array arranged adjacent to the quantum bit array SQBA. In addition, while the control wiring of the quantum bit read current amplifier circuit is shown as being arranged so as to pass over the amplifier circuit, it is also advisable to arrange the aforementioned low active signal line MWLB so as to pass over this amplifier circuit. By arranging and wiring in this manner, it is possible to repeatedly arrange the block circuit of the embodiment of Figure 4 vertically and horizontally, thereby enabling an increase in quantum bit capacity.

[0030] FIG. 5 shows a block circuit diagram, QBITARRAY, integrating a quantum semiconductor quantum bit array according to this embodiment. The symbols in the figure are the same as those described in the embodiments of FIGS. 1 to 4, and therefore will not be described here. The example in the figure shows an arrangement of quantum bit arrays SQBA in 256 rows and 256 columns. Each quantum bit array SQBA has four quantum bits, for a total of 256k quantum bits. Since some circuit blocks are unnecessary at the ends of the repeated arrangement, dummy quantum bit readout current amplifier circuits DMYSA and dummy selector circuits DMYSELU and DMYSELD are arranged to prevent manufacturing defects. This regular arrangement of circuit blocks has the advantage of improving chip yield.

[0031] 6 is a block circuit diagram QBA of the entire quantum semiconductor chip according to this embodiment. The block circuit diagram QBA includes an address buffer ADDRESS BUFFER, a column address buffer COLUMN ADDRESS BUFFER, a column address counter COLUMN ADDRESS COUNTER, a row address buffer ROW ADDRESS BUFFER, a refresh counter REFRESH COUNTER, a quantum bit bank select QBANK SELECT, a quantum mode register QMODE RESISTER, a row decoder ROW DEC, a column decoder COLUMN DEC, a main sense amplifier MAIN AMP, a quantum bit array QBIT ARRAY, a data input buffer Din BUFFER, a data output buffer Dout BUFFER, a data buffer DQS BUFFER, a delay-locked loop DLL, a control logic CONTROL LOGIC, clocks CLK and / CLK, a clock enable signal CKE, a chip select signal / CS, a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, a data strobe signal DQS, and data DQ.

[0032] The block circuit diagram of this embodiment is an application of the configuration of a general-purpose DRAM. Clocks CLK and / CLK are input from the system bus, and a clock enable signal CKE is asserted to prompt the control logic to generate commands. Various signals, such as chip select, row address strobe, column address strobe, and write enable signals, are input in the desired bit pattern, and the control logic generates various commands, such as precharging the QBITARRAY, activating the QBITARRAY (in this case, activating the quantum bit drive signal XQ), and reading (in this case, activating the quantum bit read current amplifier circuit). When the desired address information ADDRESS is input from an external control LSI chip, the data is transferred to various address buffers (ROW ADDRESS BUFFER, COLUMN ADDRESS BUFFER), and the downstream row decoder circuit, column address counter, and column decoder circuit appropriately assert the selected bit drive signal and control signal.

[0033] The quantum mode register selects modes such as test mode and error correction mode for the QBA circuit of this embodiment. It also sets quantum operation modes such as rotating a quantum bit 90 degrees or swapping it with an adjacent quantum bit. The signal latched to the power supply level by the quantum bit readout current amplifier of this embodiment is transferred to the main amplifier. The data from the main amplifier is transferred to the outside of the quantum semiconductor chip QBA as a data DQ signal via the data output buffer. Data signals can be exchanged with external devices at desired timing using timing and data strobe signals generated by the delay-locked loop circuit. Data written to the quantum semiconductor chip QBA is input from the data input buffer and written to the quantum bit array QBTARRAY via the main amplifier. As described above, for the quantum operation required for data writing, an appropriate command generation pattern is input to the quantum mode register, and the quantum bit drive signal and quantum bit control signal are set to the desired potential. As described above, even when the quantum bit array of this embodiment is increased in capacity, stable data transmission and reception can be achieved by applying the embodiment of FIG. 6.

[0034] Figure 7 shows the connection relationship between the quantum semiconductor QBA of the present invention, the analog chip CAC that inputs control signals to control the quantum semiconductor QBA, and the digital processing unit CDU that inputs control signals to control the analog chip CAC. The quantum computer is configured as a whole system by logically and electrically connecting these components. The analog chip CAC is preferably configured using a classical computer, i.e., an integrated LSI using the so-called CMOS process. Similarly, the digital processing unit CDU is preferably a processing unit that utilizes semiconductor chips using the CMOS process, just like the analog chip CAC. Simply put, the digital processing unit CDU can be a general-purpose personal computer (PC). It is also possible to incorporate a software module that generates the desired control signals into the PC.

[0035] Figure 8 shows an implementation method using a quantum semiconductor QBA, an analog chip CAC, a digital processing unit CDU, and a dilution refrigerator 10 according to the embodiment. The dilution refrigerator 10 is separated by a frame and a room temperature plate RT-PL to separate the external atmosphere from the internal vacuum atmosphere. The degree of vacuum inside the frame is controlled by using a pump device installed outside the refrigerator 10 to evacuate air through a vacuum tube VC. Temperature control inside the dilution refrigerator 10 is achieved by circulating diluted liquid helium through a pulse tube (PulseTube) shown in Figure 8. Figure 8 shows an example in which two pulse tubes are connected. The diluted liquid helium is obtained by liquefying two helium isotopes, 3He and 4He, and then injecting the 3He phase into the 4He phase to dilute it.

[0036] In the example of the dilution refrigerator 10 shown in Figure 8, multiple metal (mainly oxygen-free copper) plates (50K-PL (set to -223°C), 4K-PL (set to -269°C), PLA, PLB, and mKPL (set to approximately -273°C)) are installed and stored inside the Frame housing of the dilution refrigerator 10. The metal plates PLA and PLB are controlled at temperatures between 4K (-269°C) and mK (approximately -273°C). Temperature control is configured to control and maintain thermal equilibrium using temperature control heaters (not shown) installed on each plate (50K-PL, 4K-PL, PLA, PLB, and mKPL) and a temperature controller (not shown) installed outside the dilution refrigerator 10 that controls the power input to the temperature control heaters. In the example shown in Figure 8, diluted liquid helium is circulated from the pulse tube (PulseTube) to the heat sink (Heatsink). As a result, the metal plate 4K-PL and the metal plate mKPL, to which the heatsink Heatsink is connected, are brought to a cryogenic temperature via the heatsink through which diluted liquid helium circulates, thereby realizing a cryogenic atmosphere of 10 mK to 100 mK in the metal plate 4K-PL and the metal plate mKPL.

[0037] The heatsink Heatsink can be considered the first cryotube, and the pulse tube PulseTube can be considered the second cryotube. The metal plate mKPL can be considered the first metal plate, and the metal plate 4K-PL can be considered the second metal plate. The quantum semiconductor QBA is mounted on the first cooling plate FGNDPLT of the quantum semiconductor QBA, which is located below the metal plate mKPL. The cooling plate FGNDPLT is thermally connected to the metal plate mKPL via cooling rods C0 to C3 (even-numbered C0 and C2 are not shown). In other words, the heatsink Heatsink is a cryotube that cools the metallic cooling plate FGNDPLT using diluted liquid helium. The metallic cooling plate FGNDPLT is thermally connected to the metal plate mKPL via cooling rods C0 to C3. In this embodiment, the quantum semiconductor QBA is located below the metal plate mKPL rather than directly mounted on it, because a static magnetic field is applied to the quantum semiconductor QBA for quantum operation. Due to space limitations for placing the magnet MAGNET for generating the static magnetic field on the lowest layer of the dilution refrigerator 10, the quantum semiconductor QBA is arranged as shown in Figure 8 in the example configuration of the dilution refrigerator 10 of this embodiment. Note that the electrical signals required to cause the quantum semiconductor QBA to perform quantum operations are output from a control device (not shown) installed outside the dilution refrigerator 10, and the control signals among the electrical signals are electrically connected to the quantum semiconductor QBA via coaxial wiring CXE and CXO, while the power supply voltage and power supply current among the electrical signals are electrically connected to the quantum semiconductor QBA via DC twisted wiring TWE and TWO. By using the above implementation configuration, quantum operations and quantum computers as described in Figures 1 to 7 can be realized.

[0038] The present disclosure provides a technology for realizing a circuit that amplifies read current when increasing the capacity of quantum semiconductors using an integrated LSI, and for amplifying minute output current in a quantum bit cell circuit composed of a quantum bit element and a single-electron element while minimizing fluctuations in the drain-source voltage of the single-electron element so as not to impair the current amplification effect of the single-electron element.

[0039] The present disclosure can provide a quantum computer with high quantum fidelity because it can maintain a temperature as close to absolute zero as possible when a large-capacity quantum semiconductor is operated quantum. <<Modifications>> The invention (disclosure) made by the present inventor has been specifically described above based on the embodiments, but it goes without saying that the present disclosure is not limited to the above embodiments and can be modified in various ways without departing from the spirit and scope of the present disclosure.

[0040] The above-described embodiment has been described in detail to clearly explain the present disclosure, and is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to add, delete, or replace part of the configuration of the embodiment with other configurations.

[0041] Furthermore, for example, in the above embodiment, a case where a silicon quantum semiconductor is used has been described as an example, but the present invention is not limited to this and can also be applied to superconducting quantum semiconductors, etc.

[0042] The present disclosure may be a silicon quantum bit semiconductor integrated circuit having the following configuration.

[0043] The silicon semiconductor quantum bit integrated circuit has a plurality of MISFETs of a first conductivity type, a plurality of MISFETs of a second conductivity type, and a first amplifier circuit, a second amplifier circuit, and a third amplifier circuit section configured from these.

[0044] The plurality of MISFETs are composed of at least a first MISFET (Barrier), a second MISFET (Plunger), and a third MISFET (Barrier), and a reservoir node that shares electrons with the first MISFET is electrically connected to the drain of the first MISFET and the reservoir, the source of the first MISFET is connected to the drain of the second MISFET, the source of the second MISFET is connected to the drain of the third MISFET, and the drain of the third MISFET is connected to a ground potential (Drain).

[0045] The gate potentials of the first MISFET and the third MISFET are controlled to a desired level so that the electrons for quantum bit operation supplied from the reservoir are present at the interface between the semiconductor substrate on which the second MISFET is formed and the gate oxide film of the second MISFET, and a fourth MISFET, a fifth MISFET (SET), and a sixth MISFET are arranged to face the first MISFET, the second MISFET, and the third MISFET.

[0046] The source of the fourth MISFET is connected to the drain of the fifth MISFET, the source of the fifth MISFET is connected to the drain of the sixth MISFET, and the source of the sixth MISFET is connected to a ground potential (VSSA).

[0047] The first amplifier circuit is composed of a seventh MISFET (PCH) of a first conductivity type and an eighth MISFET (TPA) of a first conductivity type, and the drain of the fourth MISFET, the drain of the seventh MISFET, and the source of the eighth MISFET are electrically connected to form a first node (QDO), and the source of the seventh MISFET is connected to a first precharge potential (VPCHA) of the first node.

[0048] The second amplifier circuit is composed of a ninth MISFET (T_RD) of a first conductivity type and a tenth MISFET (PCH1) of a second conductivity type, the drain of the eighth MISFET, the source of the ninth MISFET and the drain of the tenth MISFET are electrically connected to form a second node (LDO), and the source of the tenth MISFET is connected to a second precharge potential (VPCH) of the second node.

[0049] The third amplifier circuit has a gate of an eleventh MISFET of a first conductivity type connected to the drain of the ninth MISFET, a drain of a fourteenth MISFET of a second conductivity type electrically connected to the gate of the eleventh MISFET, and a source of the fourteenth MISFET connected to a third precharge potential (VPCHS) of the third node, a twelfth MISFET of the first conductivity type and a thirteenth MISFET of the first conductivity type, a source of the twelfth MISFET, a source of the eleventh MISFET and a drain of the thirteenth MISFET electrically connected, the eleventh MISFET and a drain of the eleventh MISFET are connected to a first data line (DT), and the drain of the twelfth MISFET is connected to a second data line (DB), and has a first MISFET pair of first conductivity type having one gate and the other drain connected to each other and sources connected to the first source line, and a second MISFET pair of first conductivity type having one gate and the other drain connected to each other and sources connected to the two source lines.

[0050] The mutually connected nodes of the first MISFET pair are connected to the first data line (DT), the mutually connected nodes of the second MISFET pair are connected to the second data line (DB), a first stabilizing capacitance (CQDL) is connected to the first node (QDO), a second stabilizing capacitance (CLDL) is connected to the second node (LDO), a first power supply voltage (VCCA) and a second power supply voltage (VSSA) are supplied to the third amplifier circuit, the first power supply voltage and the third pre-charge potential are at the same level of potential, the second pre-charge potential is a potential approximately intermediate between the first power supply voltage and the second power supply voltage, and the first pre-charge potential is a potential lower than the second pre-charge potential, and when electrons stored and arranged in the second MISFET are in an up-spin state, an on-current (ISET on) flows to the fifth MISFET to drive the first node (QDO) to a low level side at a relatively high speed, and when electrons stored and arranged in the second MISFET are in a down-spin state, an off-current (ISET on) flows to the fifth MISFET off) flows, driving the first node to a low level at a speed relatively slower than in the up spin state, and immediately after the first node QDO becomes a potential (first difference potential) different between the up spin state and the down spin state, the gate potential of the eighth MISFET is changed from the second power supply voltage to a first drive voltage, and the charge stored in the second node LDO is transferred to the first node QDO, amplifying the first difference potential to a second difference potential, and immediately after the second difference potential of the second node LDO is sufficiently amplified, the gate potential of the eighth MISFET is changed from the first drive voltage to the second power supply voltage, and immediately thereafter, The gate potential of T is changed from the second power supply voltage to a second drive voltage, and the charge stored in the third node RDO is transferred to the second node LDO, thereby amplifying the second difference potential to a third difference potential, and after the third node RDO has reached the third difference potential, the gate potential of the thirteenth MISFET is changed from the second power supply voltage to the third drive voltage, thereby outputting a fourth difference potential to the first data line and the second data line, and then the first MISFET pair and the second MISFET pair are activated, thereby fully amplifying the first data line and the second data line to the first power supply voltage and the second power supply voltage.

[0051] The circuit including the eighth MISFET (TPA) may be referred to as a “first charge transfer MIS circuit.” The circuit including the ninth MISFET (T_RD) may be referred to as a “second charge transfer MIS circuit.”

[0052] The present disclosure may also have the following configurations.

[0053] a quantum bit array circuit including a plurality of quantum bit elements and a plurality of single-electron elements for detecting the spin states of the plurality of quantum bit elements; a first node which is a quantum bit readout line for outputting a readout current representing the spin state from the quantum bit element; and a quantum bit readout current amplifier circuit connected to the first node, wherein the quantum bit readout current amplifier circuit is configured to set the first node to a first precharge potential, and the quantum bit readout current amplifier circuit is configured to connect a second node to a second precharge potential higher than the first precharge potential; a first amplifier circuit electrically connected to the single-electron element via the first node, and having a first charge transfer MIS circuit which transfers the charge stored in the second node to the first node; and a second amplifier circuit electrically connected to the first amplifier circuit via the second node and to a third amplifier circuit via a third node, and having a second charge transfer MIS circuit which transfers the charge stored in the third node to the second node. a third amplifier circuit that outputs a potential to a data line and amplifies the amplitude in response to the third node reaching a predetermined potential by the first amplifier circuit and the second amplifier circuit.

[0054] TP1...gate electrode, TRD...gate electrode, LDO...local data line, RDO...data line, QDO...qubit readout line, LDO...local data line, RDO...readout data line, VPCHA...array precharge voltage, VPCH...half precharge voltage, VPCHS...precharge voltage, PCH, PCH1, PCH2...precharge activation signal, PSN...amplifier circuit activation signal, DT, DB...data lines, CSN, CSP...common source activation signal

Claims

1. A quantum bit array circuit including a plurality of quantum bit elements and a plurality of single electron elements for detecting the spin states of the plurality of quantum bit elements; a first node which is a quantum bit read line for outputting a read current representing the spin state from the quantum bit element; and a quantum bit read current amplifier circuit connected to the first node, wherein the quantum bit read current amplifier circuit is configured to set the first node to a first precharge potential, and the quantum bit read current amplifier circuit is configured to connect a second node to a second precharge potential higher than the first precharge potential; a first amplifier circuit electrically connected to the single electron element via the first node and having a first charge transfer MIS circuit for transferring a charge charged at the second node to the first node; and a second amplifier circuit electrically connected to the first amplifier circuit via the second node and electrically connected to a third amplifier circuit via a third node and having a second charge transfer MIS circuit for transferring a charge charged at the third node to the second node. a third amplifier circuit that outputs a potential to a data line and amplifies the amplitude in response to the third node reaching a predetermined potential by the first amplifier circuit and the second amplifier circuit.

2. A quantum semiconductor circuit as claimed in claim 1, wherein the quantum bit read current amplifier circuit comprises: a capacitor for a first stable operation connected to the first node; and a capacitor for a second stable operation connected to the second node.

3. In the quantum semiconductor circuit according to claim 2, the capacitance value of the capacitor for the first stable operation and the capacitance value of the capacitor for the second stable operation are femtofarads (10 -15 Quantum semiconductor circuits, which have values ​​on the order of 1000 times the quantum efficiency of quantum dots.

4. A quantum semiconductor circuit as claimed in claim 1, wherein the first precharge potential of the first node is 0.1 mV to 20 mV, the second precharge potential of the second node is higher than the first precharge potential and lower than the third precharge potential of the third node, and the third precharge potential of the third node is equivalent to a high level of a power supply voltage.

5. A quantum semiconductor circuit according to claim 1, wherein the control voltages of said first amplifier circuit and said second amplifier circuit during their amplifying operations are voltages between the high level and low level of the power supply voltage.

6. A quantum semiconductor circuit as claimed in claim 5, wherein the quantum bit read current amplifier circuit is configured to: apply the control voltage to the gate electrode of the first amplifier circuit, and then, after a desired difference potential is output and transferred to the second node, transition the control voltage of the gate electrode to the low level of the power supply voltage.

7. A quantum semiconductor circuit as claimed in claim 6, wherein the gate electrode of the second amplifier circuit transitions to the high level of the power supply voltage after the gate electrode of the first amplifier circuit transitions to the low level, thereby starting an amplifying operation of the second amplifier circuit.

8. A quantum semiconductor circuit as claimed in claim 1, wherein the third node reaching a predetermined potential means that a state has been reached in which it is possible to determine whether the potential of the third node is higher or lower than a predetermined reference voltage.

9. A quantum semiconductor circuit according to claim 2, wherein the capacitance value of the capacitor for the first stable operation is greater than the capacitance value of the capacitor for the second stable operation.