Mask and method for producing mask

Abstract

This mask may include: a first layer including a first surface and a second surface located on the opposite side of the first surface, in which at least one first opening penetrating the first layer is formed; a second layer including a third surface facing the first surface and a fourth surface located on the opposite side of the third surface, in which a second opening penetrating the second layer is formed at a position overlapping the first opening in a planar view; and a third layer including a fifth surface facing the second opening and / or the fourth surface and a sixth surface positioned on the opposite side of the fifth surface, in which a plurality of third openings penetrating the third layer is formed at a position overlapping the first opening and the second opening in the planar view. The second layer may include a silicon oxide, a silicon nitride, or a silicon oxynitride. The third layer may include silicon or metal.

Description

Mask and mask manufacturing method

[0001] FIELD Embodiments of the present disclosure relate to a mask and a method for manufacturing the mask.

[0002] Vapor deposition is known as a method for forming precise patterns. In vapor deposition, a mask with openings formed therein is combined with a substrate. Then, a vapor deposition material is applied to the substrate through the openings in the mask. By vapor deposition, a vapor deposition layer containing the vapor deposition material is formed on the substrate in a pattern corresponding to the pattern of the openings in the mask. Vapor deposition is used, for example, as a method for forming pixels of an organic electroluminescence (EL) display device.

[0003] For example, Patent Document 1 discloses a deposition mask including an outer frame substrate including beam portions that define a plurality of pixel areas, and a mask substrate including a plurality of openings located in the pixel areas. The mask substrate is thinner than the outer frame substrate. For example, the thickness of the mask substrate is 1 μm to 100 μm, and the thickness of the outer frame substrate is 100 μm to 775 μm.

[0004] Japanese Patent Application Laid-Open No. 2022-175723

[0005] There is a demand for highly accurate control of the shape, size, and position of the openings formed in the mask substrate.

[0006] A mask according to an embodiment of the present disclosure may include: a first layer including a first surface and a second surface opposite the first surface, the first layer having at least one first opening formed therethrough from the first surface to the second surface; a second layer including a third surface opposite the first surface and a fourth surface opposite the third surface, the second layer having at least one second opening formed therethrough from the third surface to the fourth surface at a position overlapping the first opening in a plan view; and a third layer including a fifth surface opposite the second opening and / or the fourth surface and a sixth surface opposite the fifth surface, the third layer having a plurality of third openings formed therethrough from the fifth surface to the sixth surface at positions overlapping the first opening and the second opening in a plan view. The second layer may include silicon oxide, silicon nitride, or silicon oxynitride. The third layer may include silicon or metal.

[0007] According to embodiments of the present disclosure, the shape, size or position of the openings can be controlled with high precision.

[0008] 14 is a plan view showing an example of an organic device. FIG. 15 is a diagram showing an example of a vapor deposition apparatus provided with a mask. FIG. 16 is a plan view showing an example of a mask when viewed from the incident surface side. FIG. 17 is a plan view showing an example of a mask when viewed from the exit surface side. FIG. 18 is a cross-sectional view taken along line V-V of the mask of FIG. 3. FIG. 19 is a cross-sectional view showing an example of a pattern region. FIG. 19 is a cross-sectional view showing an example of a method for manufacturing a mask according to an embodiment. FIG. 20 is a cross-sectional view showing an example of a method for manufacturing a mask according to an embodiment. FIG. 21 is a cross-sectional view showing an example of a method for manufacturing a mask according to an embodiment. FIG. 22 is a cross-sectional view showing an example of a method for manufacturing a mask according to an embodiment. FIG. 23 is a cross-sectional view showing an example of a method for manufacturing a mask according to an embodiment. FIG. 24 is a cross-sectional view showing an example of a method for manufacturing a mask according to an embodiment. FIG. 25 is a cross-sectional view showing an example of a method for manufacturing a mask according to an embodiment. FIG. 26 is a cross-sectional view showing an example of a method for manufacturing a mask according to an embodiment.

[0009] In this specification and drawings, unless otherwise specified, terms meaning the materials underlying a certain structure, such as "substrate," "sheet," and "film," are not to be distinguished from one another solely on the basis of differences in name.

[0010] In this specification and drawings, unless otherwise specified, terms that specify shapes, geometric conditions, and their degrees, such as "parallel" and "orthogonal," and values ​​of lengths and angles, are not bound by strict meanings, but are interpreted to include a range within which similar functions can be expected.

[0011] In this specification and drawings, unless otherwise specified, when a certain component, such as a certain region, is referred to as "above" or "below," "upper" or "lower," or "upward" or "below" another component, such as another region, this includes cases where the component is in direct contact with the other component. It also includes cases where another component is contained between the component and the other component, that is, cases where the components are in indirectly in contact. Furthermore, unless otherwise specified, the terms "above," "upper side," or "upper," or "under," "lower side," or "lower" may be used in the reversed up-down direction.

[0012] In this specification, when multiple upper limit value candidates and multiple lower limit value candidates are listed for a certain parameter, the numerical range of the parameter may be constructed by combining any one upper limit value candidate with any one lower limit value candidate. For example, consider a description that reads, "Parameter B is, for example, A1 or more, or may be A2 or more, or may be A3 or more. Parameter B is, for example, A4 or less, or may be A5 or less, or may be A6 or less." In this case, the numerical range of parameter B may be A1 or more and A4 or less, A1 or more and A5 or less, A1 or more and A6 or less, A2 or more and A4 or less, A2 or more and A5 or less, A2 or more and A6 or less, A3 or more and A4 or less, A3 or more and A5 or less, or A3 or more and A6 or less.

[0013] In this specification and drawings, unless otherwise specified, the state in which the surface of element A is "opposed to" the surface of element B includes not only the case in which the surface of element A is in contact with the surface of element B, but also the case in which element C is located between the surfaces of element A and element B. In other words, the term "opposed to" is a term that indicates the orientation of two surfaces.

[0014] In this specification and drawings, unless otherwise specified, the same or similar symbols are used to designate the same parts or parts having similar functions, and repeated explanations may be omitted. Furthermore, for the sake of convenience, the dimensional ratios of the drawings may differ from the actual ratios, and some components may be omitted from the drawings.

[0015] In this specification and drawings, unless otherwise specified, one embodiment of this specification may be combined with other examples to the extent that no contradiction occurs. In addition, other examples may also be combined with each other to the extent that no contradiction occurs.

[0016] Unless otherwise specified, in the present specification and drawings, when two or more steps or processes are disclosed in a method such as a manufacturing method, other steps or processes that are not disclosed may be performed between the disclosed steps or processes. In addition, the order of the disclosed steps or processes is arbitrary within the range that does not cause a contradiction.

[0017] In one embodiment of the present specification, an example will be described in which a mask is used to form an organic layer or an electrode on a substrate when manufacturing an organic electroluminescence (EL) display device. However, the use of the mask is not particularly limited, and this embodiment can be applied to masks used for various purposes. For example, the mask of this embodiment may be used to form electrodes of a device for displaying or projecting images or videos to express virtual reality (VR) or augmented reality (AR). The mask of this embodiment may also be used to form electrodes of a display device other than an organic electroluminescence (EL) display device, such as an electrode of a liquid crystal display device. The mask of this embodiment may also be used to form electrodes of an organic device other than a display device, such as an electrode of a pressure sensor.

[0018] A first aspect of the present disclosure is a mask comprising: a first layer including a first surface and a second surface located opposite the first surface, wherein at least one first opening is formed through the first layer from the first surface to the second surface; a second layer including a third surface opposite the first surface and a fourth surface located opposite the third surface, wherein at least one second opening is formed through the second layer from the third surface to the fourth surface at a position overlapping with the first opening in a planar view; and a third layer including a fifth surface opposite the second opening and / or the fourth surface and a sixth surface located opposite the fifth surface, wherein a plurality of third openings are formed through the third layer from the fifth surface to the sixth surface at positions overlapping with the first opening and the second opening in a planar view; wherein the second layer comprises silicon oxide, silicon nitride, or silicon oxynitride; and the third layer comprises silicon or a metal.

[0019] A second aspect of the present disclosure may include the following aspect in the mask according to the first aspect described above: The third layer may include a pattern region overlapping the first opening and the second opening in a plan view, and a peripheral region surrounding the pattern region in a plan view, and the second layer may be located between the peripheral region and the first layer.

[0020] A third aspect of the present disclosure may include the following aspect in the mask according to the first or second aspect described above: The third layer may include single crystal silicon.

[0021] A fourth aspect of the present disclosure may include the following aspect in the mask according to any one of the first to third aspects: The third layer may be an epitaxial layer.

[0022] A fifth aspect of the present disclosure may include the following aspect in the mask according to any one of the first to fourth aspects: The second layer may include silicon dioxide.

[0023] A sixth aspect of the present disclosure may include the following aspect in the mask according to any one of the first to fifth aspects: The first layer may include silicon or a silicon compound.

[0024] A seventh aspect of the present disclosure is a method for manufacturing a mask according to any one of the first to sixth aspects described above, comprising: a step of forming a laminate including the first layer and a first coating layer covering the second surface of the first layer; a step of forming an uneven surface on the surface of the first coating layer according to the shape of the third layer; a step of forming the third layer on the uneven surface, the third layer accommodating the convex portions of the first coating layer within the third opening; a step of removing a portion of the first layer to form the first opening; and a step of removing a portion of the first coating layer to form the second layer having the second opening from the first coating layer, wherein the first coating layer within the third opening is removed.

[0025] An eighth aspect of the present disclosure may include the following aspect in the method for manufacturing a mask according to the seventh aspect described above: The step of forming the third layer on the uneven surface may include the steps of forming a second coating layer that covers the convex portions of the uneven surface, and polishing the surface of the second coating layer until the convex portions of the first coating layer are exposed, and forming the third layer having the third openings from the second coating layer.

[0026] A ninth aspect of the present disclosure may include the following aspects in the method for manufacturing a mask according to the seventh or eighth aspect: The third layer may include single crystal silicon, and forming the third layer on the uneven surface may include epitaxially growing the single crystal silicon on the uneven surface.

[0027] A tenth aspect of the present disclosure may include the following aspects in the method for manufacturing a mask according to the seventh or eighth aspect: The third layer may include a metal, and the step of forming the third layer on the uneven surface may include the step of performing a sputtering method, a vapor deposition method, an ion plating method, and / or a plating method on the uneven surface.

[0028] An eleventh aspect of the present disclosure may include the following aspect in the method for manufacturing a mask according to any one of the seventh to tenth aspects described above. The first layer may include silicon or a silicon compound. The step of forming a laminate including the first layer and the first coating layer may include the steps of preparing a base material formed of the same material as the first layer, and forming the first coating layer from a portion of the base material by oxidizing or thermally oxidizing another portion of the base material.

[0029] A twelfth aspect of the present disclosure may include the following aspect in the method for manufacturing a mask according to any one of the seventh to tenth aspects described above: The step of forming a laminate including the first layer and the first coating layer may include the step of depositing a material that forms the first coating layer on the second surface of the first layer.

[0030] An embodiment of the present disclosure will be described in detail with reference to the drawings. Note that the embodiment described below is an example of an embodiment of the present disclosure, and the present disclosure should not be interpreted as being limited to only these embodiments.

[0031] An organic device 100 including an organic layer formed by using a mask will be described. The organic device 100 includes an organic layer or an electrode formed by using a mask. Figure 1 is a cross-sectional view showing an example of the organic device 100.

[0032] The organic device 100 includes a substrate 110 and a plurality of elements 115 arranged along an in-plane direction of the substrate 110. The substrate 110 includes a first surface 111 and a second surface 112 located on the opposite side of the first surface 111. The elements 115 are located on the first surface 111. The elements 115 are, for example, pixels. The substrate 110 may include two or more types of elements 115. For example, the substrate 110 may include a first element 115A and a second element 115B. Although not shown, the substrate 110 may also include a third element. The first element 115A, the second element 115B, and the third element are, for example, a red pixel, a blue pixel, and a green pixel.

[0033] The element 115 may include a first electrode 120 , an organic layer 130 located on the first electrode 120 , and a second electrode 140 located on the organic layer 130 .

[0034] The organic device 100 may include an insulating layer 160 located between two adjacent first electrodes 120 in a planar view. The insulating layer 160 includes, for example, polyimide. The insulating layer 160 may overlap an edge of the first electrode 120. "Planar view" means viewing an object along the normal direction to the surface of a plate-like member such as the substrate 110.

[0035] The substrate 110 may be made of an insulating material. Materials that can be used for the substrate 110 include, for example, inflexible materials such as silicon, quartz glass, Pyrex (registered trademark) glass, and synthetic quartz plates, as well as flexible materials such as resin films, optical resin plates, and thin glass. The substrate 110 may have a planar shape similar to that of silicon wafers used in semiconductor manufacturing. In this case, the substrate 110 can be processed using equipment used in semiconductor manufacturing processes. For example, the first electrode 120, the insulating layer 160, and the like can be formed on the substrate 110 using equipment used in semiconductor manufacturing processes.

[0036] The element 115 is configured to realize some function by applying a voltage between the first electrode 120 and the second electrode 140 or by causing a current to flow between the first electrode 120 and the second electrode 140. For example, if the element 115 is a pixel of an organic EL display device, the element 115 can emit light that forms an image.

[0037] The first electrode 120 includes a conductive material. For example, the first electrode 120 includes a metal, a conductive metal oxide, or another conductive inorganic material. The first electrode 120 may include a transparent and conductive metal oxide such as indium tin oxide.

[0038] The organic layer 130 includes an organic material. When the organic layer 130 is energized, the organic layer 130 can perform some function. "Electrification" means that a voltage is applied to the organic layer 130 or that a current flows through the organic layer 130. The organic layer 130 may be a light-emitting layer that emits light when energized, or a layer whose light transmittance or refractive index changes when energized. The organic layer 130 may include an organic semiconductor material.

[0039] 1 , the organic layer 130 may include a first organic layer 130A and a second organic layer 130B. The first organic layer 130A is included in the first element 115A. The second organic layer 130B is included in the second element 115B. Although not shown, the organic layer 130 may include a third organic layer included in a third element. The first organic layer 130A, the second organic layer 130B, and the third organic layer are, for example, a red light-emitting layer, a blue light-emitting layer, and a green light-emitting layer.

[0040] When a voltage is applied between the first electrode 120 and the second electrode 140, the organic layer 130 located therebetween is driven. If the organic layer 130 is an emitting layer, light is emitted from the organic layer 130 and extracted to the outside from the second electrode 140 side or the first electrode 120 side.

[0041] The organic layer 130 may further include a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, and the like.

[0042] The second electrode 140 may include a conductive material such as a metal. Examples of materials that can be used for the second electrode 140 include platinum, gold, silver, copper, iron, tin, chromium, aluminum, indium, lithium, sodium, potassium, calcium, magnesium, chromium, carbon, and alloys thereof. As shown in FIG. 1 , the second electrode 140 may extend across two adjacent organic layers 130 in a plan view.

[0043] Next, a method for forming the organic layer 130 on the substrate 110 by vapor deposition will be described. Fig. 2 is a diagram showing a vapor deposition apparatus 10. The vapor deposition apparatus 10 performs a vapor deposition process for depositing a vapor deposition material on an object.

[0044] 2 , the vapor deposition apparatus 10 may include therein a vapor deposition source 6, a heater 8, and a mask 20. The vapor deposition apparatus 10 may further include an exhaust unit for creating a vacuum atmosphere inside the vapor deposition apparatus 10. The vapor deposition source 6 is, for example, a crucible. The vapor deposition source 6 contains a vapor deposition material 7 such as an organic material or a metal material. The heater 8 heats the vapor deposition source 6 to evaporate the vapor deposition material 7 under a vacuum atmosphere.

[0045] The mask 20 includes an incident surface 201, an exit surface 202, a first opening 31, a second opening 41, and a third opening 51. The incident surface 201 faces the deposition source 6. The exit surface 202 is located on the opposite side of the incident surface 201. The exit surface 202 faces the first surface 111 of the substrate 110. The first opening 31 is located on the incident surface 201. The third opening 51 is located on the exit surface 202. The first opening 31 and the third opening 51 are connected in the thickness direction of the mask 20 via the second opening 41. One second opening 41 overlaps one first opening 31 in a plan view. Multiple third openings 51 overlap one second opening 41 and one first opening 31 in a plan view. A portion of the deposition material 7 that enters the mask 20 from the exit surface 202 passes through the first opening 31, the second opening 41, and the third opening 51 and exits from the exit surface 202. The deposition material 7 that exits from the exit surface 202 adheres to the first surface 111 of the substrate 110. The exit surface 202 of the mask 20 may be in contact with the first surface 111 of the substrate 110.

[0046] As shown in FIG. 2 , the deposition apparatus 10 may include a magnet 5 disposed on the second surface 112 side of the substrate 110. When the mask 20 includes a magnetic material, the magnet 5 can attract the mask 20 toward the substrate 110 by magnetic force. As a result, the gap between the mask 20 and the substrate 110 can be reduced or eliminated. Therefore, the occurrence of a shadow during the deposition process can be suppressed. In this application, a shadow refers to a phenomenon in which the thickness of the organic layer 130 formed near the wall surface of the third opening 51 is smaller than the thickness of the organic layer 130 formed at the center of the third opening 51. The shadow occurs due to the deposition material 7 adhering to the wall surface of the mask 20, the deposition material 7 entering the gap between the mask 20 and the substrate 110, or the like.

[0047] Next, the mask 20 will be described in detail. Fig. 3 is a plan view showing an example of the mask 20 when viewed from the incident surface 201 side. Fig. 4 is a plan view showing an example of the mask 20 when viewed from the exit surface 202 side. Fig. 5 is a cross-sectional view taken along line V-V of the mask 20 in Fig. 3.

[0048] As shown in FIG. 5, the mask 20 includes a first layer 30, a second layer 40, and a third layer 50.

[0049] The first layer 30 includes a first surface 301, a second surface 302, a first opening 31, and a first wall surface 32. The first surface 301 may form the incident surface 201. The second surface 302 is located on the opposite side of the first surface 301 in the thickness direction of the first layer 30.

[0050] The first opening 31 penetrates the first layer 30 from the first surface 301 to the second surface 302. As shown in FIG. 3 , the first layer 30 may include a plurality of first openings 31. The plurality of first openings 31 may be aligned in a first direction D1 and a second direction D2. The second direction D2 may be perpendicular to the first direction D1. The first direction D1 and the second direction D2 are directions parallel to the first surface 301.

[0051] One first opening 31 may correspond to one screen of the organic EL display device. The mask 20 including multiple first openings 31 can simultaneously form organic layer patterns corresponding to multiple screens on the substrate 110. As shown in Figure 3, the first opening 31 may have a rectangular outline in a plan view.

[0052] The first wall surface 32 is located between the first surface 301 and the second surface 302. The first wall surface 32 faces the first opening 31. In the example shown in FIG. 5 , the first wall surface 32 extends along the normal direction of the first surface 301.

[0053] As shown in Fig. 3 , the region of the first layer 30 where the first openings 31 are not formed may be divided into an outer region 35 and an inner region 36. The inner region 36 is a region located between two adjacent first openings 31 in a plan view. The outer region 35 is a region located between an outer edge 303 of the first layer 30 and the first openings 31 in a plan view. As shown in Fig. 3 , the inner region 36 may extend in a first direction D1 and a second direction D2.

[0054] 3 and 4 , the first layer 30 may include alignment marks 39. The alignment marks 39 are formed, for example, on the second surface 302. The alignment marks 39 may also be formed on the first surface 301. The alignment marks 39 are used, for example, to adjust the relative position of the substrate 110 with respect to the mask 20. If the substrate 110 has a property of transmitting visible light, the alignment marks 39 can be seen through the substrate 110.

[0055] 3 and 4, the alignment mark 39 may have a cross-shaped outline in a plan view. Although not shown, the alignment mark 39 may have an outline other than a cross, such as a rectangle or a circle. The alignment mark 39 may be located in the outer region 35 or the inner region 36.

[0056] The shape of the alignment mark 39 in the cross-sectional view is arbitrary. For example, the alignment mark 39 may include a recess located on the first surface 301 or the second surface 302. The alignment mark 39 may include a hole penetrating the first layer 30 from the first surface 301 to the second surface 302. The recess and hole may be formed by etching the first surface 301 or the second surface 302. The recess and hole may be formed by irradiating the first surface 301 or the second surface 302 with a laser. For example, the alignment mark 39 may include a layer located on the first surface 301 or the second surface 302. The layer is formed of a material different from that of the first layer 30. The alignment mark 39 may be formed in a layer other than the first layer 30.

[0057] The first layer 30 includes silicon or a silicon compound. The first layer 30 is produced, for example, by processing a silicon wafer. As shown in FIG. 3 , an outer edge 303 of the first layer 30 may include a linear portion. The linear portion is also referred to as an orientation flat. Although not shown, a notch may be formed in the outer edge 303. The notch is also referred to as a notch. The orientation flat and the notch represent the crystal orientation of the silicon wafer.

[0058] The maximum dimension S11 of the first layer 30 in a plan view is, for example, 100 mm or more, or may be 150 mm or more, or 200 mm or more. The dimension S11 is, for example, 500 mm or less, or may be 400 mm or less, or may be 300 mm or less.

[0059] The dimension S12 of the first openings 31 in the direction in which the first openings 31 are arranged is, for example, 5 mm or more, or may be 10 mm or more, or may be 20 mm or more. The dimension S12 is, for example, 100 mm or less, or may be 50 mm or less, or may be 30 mm or less.

[0060] The distance S13 between two first openings 31 in the direction in which the first openings 31 are arranged is, for example, 0.1 mm or more, or may be 0.5 mm or more, or 1.0 mm or more. The distance S13 is, for example, 20 mm or less, or may be 15 mm or less, or may be 10 mm or less.

[0061] The thickness of the first layer 30 is defined as the maximum thickness T11 of the outer region 35. The thickness T1 is, for example, 50 μm or more, or may be 100 μm or more, or may be 200 μm or more. The thickness T11 is, for example, 1000 μm or less, or may be 800 μm or less, or may be 600 μm or less.

[0062] Next, the second layer 40 will be described. As shown in Fig. 5 , the second layer 40 includes a third surface 401, a fourth surface 402, a second opening 41, and a second wall surface 42. The third surface 401 faces the second surface 302 of the first layer 30. The fourth surface 402 is located on the opposite side of the second layer 40 from the third surface 401 in the thickness direction of the second layer 40.

[0063] The second opening 41 penetrates the second layer 40 from the third surface 401 to the fourth surface 402. As shown in Fig. 3 , the second layer 40 may include a plurality of second openings 41. The plurality of second openings 41 may be aligned in the first direction D1 and the second direction D2, similar to the plurality of first openings 31. The second openings 41 overlap the first openings 31 in a plan view. One second opening 41 may overlap one first opening 31.

[0064] The second wall surface 42 is located between the third surface 401 and the fourth surface 402. The second wall surface 42 faces the second opening 41. In the example shown in FIG. 5 , the second wall surface 42 extends along the normal direction of the third surface 401.

[0065] As shown in FIG. 3 , the region of the second layer 40 where no second openings 41 are formed may be divided into an outer region 45 and an inner region 46. The inner region 46 is a region located between two adjacent second openings 41 in a planar view. The outer region 45 is a region located between an outer edge 403 of the second layer 40 and the second openings 41 in a planar view. As shown in FIG. 3 , the inner region 46 may extend in the first direction D1 and the second direction D2. The outer region 45 overlaps the outer region 35 of the first layer 30 in a planar view. The inner region 46 overlaps the inner region 36 of the first layer 30 in a planar view.

[0066] The second layer 40 may include silicon oxide (SiOx). The second layer 40 may include silicon dioxide. The second layer 40 is produced by processing a coating layer (first coating layer 65 described below) formed on the second surface 302 of the first layer 30. The coating layer 65 may be formed by partially performing an oxidation treatment or a thermal oxidation treatment on a silicon wafer, which is the substrate 60 for forming the above-mentioned first layer 30.

[0067] The maximum dimension S21 of the second layer 40 in a plan view may be the same as dimension S11. The dimension S22 of the second openings 41 in the direction in which the second openings 41 are aligned may be the same as dimension S12. The spacing S23 between two second openings 41 in the direction in which the second openings 41 are aligned may be the same as spacing S13.

[0068] The thickness of the second layer 40 is defined as a thickness T21 between the first layer 30 and the third layer 50. The thickness T21 is smaller than the thickness T11 of the first layer 30. The thickness T21 is, for example, 25.0 μm or less, may be 10.0 μm or less, or may be 5.0 μm or less. The thickness T21 is, for example, 0.5 μm or more, may be 1.0 μm or more, or may be 2.0 μm or more.

[0069] Next, the third layer 50 will be described. As shown in Fig. 5 , the third layer 50 includes a fifth surface 501 and a sixth surface 502. The fifth surface 501 faces the fourth surface 402 of the second layer 40 and / or the second opening 41. The sixth surface 502 is located on the opposite side of the fifth surface 501 in the thickness direction of the third layer 50. The sixth surface 502 may form the emission surface 202 or a part thereof.

[0070] The third layer 50 includes silicon. The third layer 50 may include single crystal silicon. The third layer 50 may be fabricated, for example, by epitaxially growing a single crystal silicon layer on the second layer 40. The single crystal silicon layer may be formed on the second layer 40 by chemical vapor deposition, metalorganic vapor phase epitaxy, or molecular beam epitaxy.

[0071] The third layer 50 includes a plurality of through-hole groups 51A. Each through-hole group 51A includes a plurality of third openings 51. The third layer 50 includes a plurality of through-hole groups 51A aligned along the fifth surface 501. For example, the plurality of through-hole groups 51A may be aligned in the first direction D1 and the second direction D2, similar to the plurality of first openings 31 and second openings 41. The through-hole groups 51A overlap the first openings 31 and the second openings 41 in a plan view. One through-hole group 51A may overlap one first opening 31 and one second opening 41.

[0072] Each through hole group 51A includes a plurality of third openings 51. In plan view, the plurality of third openings 51 in one through hole group 51A may overlap one first opening 31 and one second opening 41. As shown in FIG. 5 , each third opening 51 penetrates the third layer 50 from the fifth surface 501 to the sixth surface 502.

[0073] One third opening 51 corresponds to one vapor deposition layer. One vapor deposition layer is, for example, one organic layer 130. A group of multiple third openings 51 included in one through-hole group 51A may correspond to one screen of the organic EL display device.

[0074] As shown in FIGS. 4 and 5 , the third layer 50 may include a pattern region 54, an outer edge region 55, and a peripheral region 56 in a plan view. In other words, the third layer 50 may be partitioned into a plurality of pattern regions 54, an outer edge region 55, and a peripheral region 56 in a plan view. The pattern region 54 is a region including a plurality of third openings 51 that overlap the first openings 31 and the second openings 41 in a plan view. One pattern region 54 may correspond to one through-hole group 51A. The pattern region 54 may be a region partitioned by the second wall surface 42 of the second layer 40 in a plan view. The peripheral region 56 is a region surrounding the pattern region 54 in a plan view. One peripheral region 56 may surround a plurality of pattern regions 54. The outer edge region 55 is a region surrounding the peripheral region 56 in a plan view. The outer edge region 55 may be located at the outer edge 503 of the third layer 50. The outer edge region 55 may extend completely around the outer edge 503 of the third layer 50 .

[0075] As shown in Fig. 5 , the third layer 50 includes a third wall surface 52. The third wall surface 52 is located between a fifth surface 501 and a sixth surface 502. The third wall surface 52 faces the third opening 51 as shown in Fig. 5 .

[0076] The maximum dimension S31 of the third layer 50 in plan view may be the same as the dimension S11 and the dimension S21. The dimension S31 may be smaller than the dimension S11 and the dimension S21. In other words, the outer edge 503 of the third layer 50 may be located inside the outer edge 303 of the first layer 30 and the outer edge 403 of the second layer 40 in plan view.

[0077] The thickness of the third layer 50 is defined as the maximum thickness T31 in the pattern region 54. The thickness T31 is smaller than the thickness T31 of the first layer 30. The thickness T31 of the third layer 50 may be smaller than the thickness T21 of the second layer 40, may be the same as the thickness T21, or may be larger than the thickness T21. The thickness T31 is, for example, 25.0 μm or less, may be 10.0 μm or less, or may be 5.0 μm or less. As a result, the occurrence of shadows can be suppressed. The thickness T31 is, for example, 0.5 μm or more, may be 1.0 μm or more, or may be 2.0 μm or more. As a result, the occurrence of defects such as pinholes or deformations in the third layer 50 can be suppressed.

[0078] The pattern region 54, the outer edge region 55 and the surrounding region 56 will now be described in detail.

[0079] 6 is a cross-sectional view showing an example of the pattern region 54. Symbol R1 represents the dimension of the third opening 51 at the fifth surface 501. Symbol R2 represents the dimension of the third opening 51 at the sixth surface 502. Dimension R1 is also referred to as the first dimension. Dimension R2 is also referred to as the second dimension. The dimension of the deposition layer formed on the substrate 110 by the deposition process using the mask 20 is determined by the second dimension R2 of the third opening 51 at the sixth surface 502.

[0080] The first dimension R1 may be greater than the second dimension R2. In other words, the second dimension R2 may be smaller than the first dimension R1. As a result, it is possible to suppress the occurrence of a shadow near the third wall surface 52. The first dimension R1 and the second dimension R2 are specified in the direction in which the third openings 51 are aligned.

[0081] 6, the third wall surface 52 may include a tapered surface 52a that widens away from the center of the third opening 51 as it moves from the sixth surface 502 toward the fifth surface 501. When the third wall surface 52 includes the tapered surface 52a, the first dimension R1 can be made larger than the second dimension R2.

[0082] The second dimension R2 is, for example, 1.0 μm or more, or may be 2.0 μm or more, or 3.0 μm or more. The second dimension R2 is, for example, 25.0 μm or less, or may be 10.0 μm or less, or may be 5.0 μm or less.

[0083] 6, the reference symbol S32 denotes the width of the tapered surface 52a in the direction in which the third openings 51 are arranged. The width S32 is, for example, 0.2 μm or more, or may be 0.5 μm or more, or 1.0 μm or more. The width S32 is, for example, 25 μm or less, or may be 20 μm or less, or may be 10 μm or less.

[0084] 6, the symbol θ1 represents the angle formed between the third wall surface 52 and the sixth surface 502. The angle θ1 is, for example, 50° or more, or may be 55° or more, or 60° or more. The angle θ1 is, for example, less than 90°, or may be 85° or less, or may be 80° or less.

[0085] The distance S33 between the two third wall surfaces 52 in the direction in which the third openings 51 are aligned is, for example, 1.0 μm or more, or may be 2.0 μm or more, or 3.0 μm or more. The distance S33 is, for example, 25.0 μm or less, or may be 10.0 μm or less, or may be 5.0 μm or less.

[0086] The thickness of each layer, the dimensions of each component, the width, etc. are measured by observing an image of the cross section of the mask 20 using a scanning electron microscope.

[0087] Next, a method for manufacturing the mask 20 will be described. First, as shown in FIG. 7, a substrate preparation step is performed to prepare a substrate 60. A silicon wafer may be used as the substrate 60. One surface and the other surface of the substrate 60 may be polished to a mirror finish. The arithmetic mean roughness Ra of the one surface and the other surface of the substrate 60 may be 1.5 nm or less, or may be 1.0 nm or less. The surface orientation of the one surface and the other surface of the substrate 60 may be (100), (110), or the like.

[0088] Next, as shown in FIG. 8 , a first coating layer 65 is formed on one entire surface of the substrate 60. The first coating layer 65 may be a silicon oxide film. Alternatively, as shown in FIG. 8 , a coating layer 70 may be formed on the other surface of the substrate 60. The coating layer 70 is used as a resist layer in the first layer processing step described below, and therefore is also referred to as a resist coating layer 70 hereinafter. The resist coating layer 70 may be a silicon oxide film. The coating layers 65, 70 may be formed by oxidizing or thermally oxidizing a portion of the substrate 60. The portion of the substrate 60 on which the coating layers 65, 70 are not formed becomes the first layer 30. In this manner, a laminate 61 is produced in which the first layer 30, the first coating layer 65, and the resist coating layer 70 are integrated.

[0089] The thickness of the first coating layer 65 may be equal to or greater than the sum of the thickness T21 of the second layer 40 and the thickness T31 of the third layer 50. The thickness of the resist coating layer 70 is not particularly limited. It is preferable that the resist coating layer 70 has a sufficient thickness to function as a resist film in the first layer processing step described below.

[0090] Next, as shown in FIG. 9 , a first resist layer 75 is partially formed on the surface of the first coating layer 65. The first resist layer 75 has a plurality of first resist openings 76. The first resist layer 75 includes a seventh surface 751, an eighth surface 752, first resist openings 76, and a first resist wall surface 77. The seventh surface 751 faces the first coating layer 65. The eighth surface 752 is located on the opposite side of the seventh surface 751 from the seventh surface 751 in the thickness direction of the first resist layer 75. The first resist openings 76 penetrate the first resist layer 75 from the seventh surface 751 to the eighth surface 752. The first resist wall surface 77 is located between the seventh surface 751 and the eighth surface 752. The first resist wall surface 77 faces the first resist openings 76.

[0091] The first resist openings 76 are formed corresponding to the plurality of third openings 51 in the third layer 50. The first resist layer 75 may be formed by a known method. Specifically, a resist layer material for forming the first resist layer 75 is prepared, and the resist layer material is partially applied onto the first coating layer 65. Subsequently, the resist layer material on the first coating layer 65 is exposed to light and developed. As a result, the first resist layer 75 having the plurality of first resist openings 76 is formed.

[0092] 9 , a second resist layer 80 is partially formed on the surface of the resist coating layer 70. The second resist layer 80 has a plurality of second resist openings 81. The second resist openings 81 are formed corresponding to the plurality of first openings 31 in the first layer 30. The second resist layer 80 may be formed by the same method as the first resist layer 75.

[0093] Next, a first dry etching process is performed on the first coating layer 65. The dry etching may be reactive ion etching (RIE). Specifically, as shown in FIG. 10 , the surface of the first coating layer 65 is exposed to an etching gas PI containing a plasmatized processing gas. The etching gas PI etches the portions of the first coating layer 65 that are not covered by the first resist layer 75. The etching proceeds from the first coating layer 65 toward the first layer 30. Accordingly, recesses 66 are formed in the surface of the first coating layer 65 at positions corresponding to the first resist openings 76. As a result, the surface of the first coating layer 65 has an uneven surface including recesses 66 and protrusions 67. The recesses 66 have a bottom surface 66a. The protrusions 67 have a side surface 67a and a top surface 67b. The side surface 67a faces the recesses 66. The top surface 67b faces away from the first layer 30.

[0094] A second dry etching process is also performed on the resist coating layer 70. Specifically, as shown in FIG. 10 , the surface of the resist coating layer 70 is exposed to an etching gas PI containing a plasmatized processing gas. The etching gas PI etches the portions of the resist coating layer 70 that are not covered by the second resist layer 80. The etching proceeds from the resist coating layer 70 toward the first layer 30. Therefore, portions of the resist coating layer 70 that overlap with the second resist openings 81 in a plan view are removed. As a result, third resist openings 71 are formed in the resist coating layer 70.

[0095] The etching using the etching gas PI may be anisotropic etching. The anisotropic etching may be, for example, reactive ion etching. That is, the dry etching process may include an anisotropic etching process. In anisotropic etching, the etching reaction proceeds generally in one direction. For example, the etching proceeds generally in the thickness direction of the first coating layer 65 and the resist coating layer 70. Therefore, the uneven shape of the first coating layer 65 and the shape of the third resist opening 71 in the resist coating layer 70 can be controlled with high precision.

[0096] The etching gas PI is not particularly limited as long as it can dry etch the coating layers 65 and 70. The etching gas PI may be, for example, CF ４ , CHF ３ or C ４ F ８ The gas may be a gas containing

[0097] The uneven shape of the first coating layer 65 may correspond to the shape of the third layer 50. More specifically, the shape, dimensions, and position of the convex portion 67 of the first coating layer 65 correspond to the shape, dimensions, and position of the third opening 51. A dimension T67 of the convex portion 67 along the thickness direction of the first coating layer 65 may be equal to or greater than the thickness T31 of the third layer 50. The dimension T67 of the convex portion 67 is defined as the distance between the bottom surface 66a of the concave portion 66 and the top surface 67b of the convex portion 67. Therefore, the dimension T67 is also the dimension of the concave portion 66 along the thickness direction of the first coating layer 65.

[0098] A bottom surface 66a of the recess 66 of the first coating layer 65 defines a fifth surface 501 of the third layer 50. The distance between the bottom surface 66a of the first coating layer 65 and the surface facing the first layer 30 is equal to the thickness T21 of the second layer 40.

[0099] Next, the first resist layer 75 is removed from the first covering layer 65. Also, the second resist layer 80 is removed from the resist covering layer 70. The first resist layer 75 and the second resist layer 80 can be removed using, for example, a resist processing liquid.

[0100] Next, as shown in FIG. 11 , a second coating layer 85 is formed on the uneven surface of the first coating layer 65. The second coating layer 85 may be an epitaxial layer formed by epitaxial growth. An epitaxial layer is a layer grown on a single crystal substrate. The second coating layer 85 formed by epitaxial growth is also referred to as an epitaxial layer 85. The epitaxial layer 85 may be formed by, for example, a vapor phase growth method. Specifically, the stack 61 is placed in a reaction chamber of a vapor phase growth apparatus, and a vapor phase growth gas is introduced into the reaction chamber to grow the epitaxial layer 85 on the uneven surface of the first coating layer 65. The epitaxial layer 85 is, for example, a silicon single crystal film. The vapor phase growth gas includes a reaction gas that serves as a raw material for the silicon single crystal film and a carrier gas for diluting the reaction gas. The reaction gas is, for example, a silane-based gas such as trichlorosilane. The carrier gas is, for example, hydrogen. As the reaction progresses, the recesses 66 of the first coating layer 65 are filled with the epitaxial layer 85. The epitaxial layer 85 may be grown, for example, until the recesses 66 are completely filled with the epitaxial layer 85.

[0101] After the epitaxial layer 85 has grown to a desired thickness, the introduction of the vapor deposition gas into the reaction chamber is stopped, thereby stopping the growth of the epitaxial layer 85 .

[0102] Next, a polishing process is performed. In the polishing process, as shown in FIG. 12 , the surface of the second coating layer 85 is polished and planarized. The polishing process may be performed by chemical mechanical polishing (CMP). The polishing process may be performed until the polishing surface of the polishing tool reaches the convex portions 67 of the first coating layer 65 in the thickness direction. As a result, the convex portions 67 are exposed on the surface of the second coating layer 85. In other words, through holes that accommodate the convex portions 67 of the first coating layer 65 are formed in the second coating layer 85. As described above, the shape, size, and position of the convex portions 67 of the first coating layer 65 correspond to the shape, size, and position of the third openings 51. Therefore, the through holes in the second coating layer 85 become the third openings 51. In this manner, the third layer 50 having the third openings 51 is produced from the second coating layer 85.

[0103] Next, a first layer processing step is performed to form a first opening 31 in the first layer 30. In the first layer processing step, as shown in FIG. 12 , the first layer 30 is etched from the first surface 301 side of the first layer 30, thereby forming the first opening 31 in the first layer 30. The etching may be dry etching using an etching gas. In this case, the resist coating layer 70 on the first layer 30 may be used as a resist layer. Furthermore, the first coating layer 65 may be used as a stopper layer that prevents the etching from progressing to the third layer 50. The etching gas may be, for example, SF ６ It's gas.

[0104] 13 , a first coating layer removal step is performed to remove a portion of the first coating layer 65. The first coating layer removal step is performed by supplying an etchant for the first coating layer 65 to the first opening 31. The first coating layer removal step removes the first coating layer 65 that overlaps the first opening 31 in a plan view. As a result, the second layer 40 having the second opening 41 is formed from the first coating layer 65. By removing a portion of the first coating layer 65, the first coating layer 65 in the third opening 51 of the third layer 50 is removed. The resist coating layer 70 may also be removed simultaneously with the removal of the first coating layer 65. The coating layers 65, 70 may be removed by dry etching using a fluorine-based gas or the like, or by wet etching using an etching solution containing hydrofluoric acid. In this manner, the mask 20 is produced.

[0105] Next, a dry etching apparatus 90 for performing the first dry etching step or the second dry etching step on the coating layer 65, 70 will be described. Fig. 14 is a diagram showing an example of the overall configuration of the dry etching apparatus 90. In the example shown in Fig. 14, the dry etching apparatus 90 includes a chamber 91, a gas supply means 92, and an exhaust means 93. The gas supply means 92 supplies an etching gas into the chamber 91. The exhaust means 93 exhausts the gas from the chamber 91. The pressure inside the chamber 91 is adjusted by supplying the etching gas from the gas supply means 92 into the chamber 91 while exhausting the gas from the exhaust means 93.

[0106] The dry etching apparatus 90 further includes a dielectric window 94 and an antenna 95. The dielectric window 94 is attached to the top of the chamber 91 and seals the chamber 91. The antenna 95 is disposed outside the chamber 91, for example, above the dielectric window 94. The antenna 95 may be in the form of a loop coil. A high-frequency power supply 96 is connected to the antenna 95 via a matching circuit (not shown). The high-frequency power supply 96 functions as a power supply that supplies power to generate plasma in the chamber.

[0107] The dry etching apparatus 90 further includes a stage 97. The stage 97 is disposed within the chamber 91. When etching the stack 61, the stack 61 is disposed on the stage 97. A power supply 98 for applying a bias is connected to the stage 97 via a matching circuit (not shown). The power supply for applying a bias is also referred to as a bias power supply.

[0108] The dry etching apparatus 90 further includes a control means 99. The dry etching apparatus 90 controls the gas supply means 92, the exhaust means 93, the high-frequency power supply 96, and the bias power supply 98. The control means 99 can adjust various parameters. Parameters that can be adjusted by the control means 99 include, for example, the flow rate of the etching gas supplied from the gas supply means 92 to the chamber 91, the flow rate of the gas exhausted from the chamber 91 by the exhaust means 93, the pressure within the chamber 91, the output of the high-frequency power supply 96, the output of the bias power supply 98, the voltage applied to the antenna 95, and the voltage applied to the stage 97. The voltage applied to the antenna 95 is also referred to as the antenna voltage. The voltage applied to the stage 97 is also referred to as the bias voltage.

[0109] As described above, the recessed portions 66 and the protruding portions 67 of the first coating layer 65 are formed according to the shape of the third layer 50. The shape of the side surface 67a of the protruding portion 67 determines the shape of the third wall surface 52 of the third opening 51. Therefore, the angle θ2 between the side surface 67a and the top surface 67b of the protruding portion 67 (see FIG. 15 ) determines the angle θ1 between the third wall surface 52 and the sixth surface 502.

[0110] The angle between the side surface 67a and the top surface 671 of the convex portion 67 may be controlled, for example, by the following methods: Controlling the angle of the first resist wall surface 77 relative to the eighth surface 752 of the first resist layer 75. Controlling the above parameters of the dry etching apparatus 90. Selecting the etching gas to be supplied from the gas supply means 92 to the chamber 91. Adjusting the resist selectivity. Adjusting the thickness of the first coating layer 65. Note that the order in which the above methods are described is unrelated to the order of control. For example, the thickness of the first coating layer 65 may be adjusted prior to selecting the etching gas to be supplied from the gas supply means 92 to the chamber 91.

[0111] According to the findings of the inventors, by controlling the bias voltage applied to the stage 97 and thereby controlling the balance between ions and radicals in the plasma, it is possible to adjust the thickness of the deposition occurring on the etching side surface, thereby suppressing the progression of unintended side etching.

[0112] Furthermore, according to the findings of the inventors, increasing the flow rate of the etching gas supplied from the gas supply means 92 to the chamber 91 increases the angle θ2 between the side surface 67 a and the top surface 67 b of the convex portion 67. However, in this case, the etching rate and the resist selectivity deteriorate.

[0113] Furthermore, according to the knowledge of the inventors, lowering the antenna voltage increases the angle θ2 between the side surface 67a and the top surface 67b of the convex portion 67. In this case, the etching rate and the resist selectivity remain almost unchanged.

[0114] Furthermore, according to the findings of the inventors, lowering the bias voltage increases the angle θ2 between the side surface 67a and the top surface 67b of the convex portion 67. However, in this case, the etching rate and the resist selectivity are significantly deteriorated.

[0115] According to the method for manufacturing the mask 20 according to the embodiment described above, the first coating layer 65 is used as a mold for forming the third layer 50. Since the uneven shape of the first coating layer 65 can be controlled with high precision, the shape, size, or position of the third layer 50 can be controlled with high precision. In particular, the shape, size, or position of the third opening 51 can be controlled with high precision.

[0116] The above-described embodiment can be modified in various ways. Below, modified examples will be described with reference to the drawings as necessary. In the following description and the drawings used in the following description, parts that can be configured similarly to the above-described embodiment will be designated by the same reference numerals as those used for corresponding parts in the above-described embodiment. Duplicate descriptions will be omitted. Furthermore, if it is clear that the effects obtained in the above-described embodiment can also be obtained in modified examples, the description of those effects may be omitted.

[0117] (First Modification) The coating layers 65, 70 may be formed by depositing a material for forming the coating layers 65, 70 on the substrate 60. In this case, the substrate 60 constitutes the first layer 30. In this case, the first coating layer 65 and the resist coating layer 70 may be formed by low-pressure chemical vapor deposition (Low-Pressure CVD) or plasma-enhanced CVD. The first coating layer 65 containing silicon oxide SiOx may be formed by depositing a material such as tetraethyl orthosilicate Si(OC ２ H ５ ) ４ The silicon dioxide may be formed by low pressure chemical vapor deposition or plasma chemical vapor deposition using tetraethyl orthosilicate Si(OC) as a raw material. ２ H ５ ) ４ The first coating layer 65 containing silicon oxide SiOx is also called tetraethoxysilane (TEOS). ４ and nitrogen oxides N ２ Alternatively, the first coating layer 65 and the resist coating layer 70 may be formed by plasma enhanced chemical vapor deposition using O as a raw material. By low-pressure chemical vapor deposition, the first coating layer 65 and the resist coating layer 70 can be formed simultaneously on a plurality of substrates 60. By plasma enhanced chemical vapor deposition, the first coating layer 65 and the resist coating layer 70 can be formed on the substrate 60 at a lower temperature than by low-pressure chemical vapor deposition.

[0118] (Second Modification) The second layer 40 is made of silicon nitride Si ｘ N ｙ or silicon oxynitride SiO ｘ N ｙ In this case, the first coating layer 65 may be a silicon nitride film or a silicon oxide nitride film. The silicon nitride film or the silicon oxide nitride film may be formed by performing a low pressure chemical vapor deposition method, a plasma chemical vapor deposition method, a sputtering method, or the like on a silicon wafer as the first layer 30. The first coating layer 65 containing silicon nitride may be formed by, for example, silane SiH ４ and / or nitrogen oxides N ２ O and / or ammonia NH ３ The film may be formed by low pressure chemical vapor deposition or plasma chemical vapor deposition using the above as a raw material.

[0119] (Third Modification) The side surface 67a of the convex portion 67 of the second layer 40 may be formed in a stepped shape. In this case, the third wall surface 52 of the third opening 51 of the third layer 50 is also formed in a stepped shape, which is considered to pose no practical problem. The convex portion 67 having the stepped side surface 67a can be formed by repeating the formation of the first resist layer 75 and the etching of the first covering layer 65 multiple times. In this case, the gradient θ2 of the side surface 67a relative to the top surface 67b of the convex portion 67 can be controlled by controlling the area of ​​the first resist layer 75 and the etching depth of the first covering layer 65 each time.

[0120] (Fourth Modification) The third layer 50 may include a metal. The metal may be a magnetic material or a non-magnetic material. Examples of magnetic materials include nickel, iron, cobalt, and alloys thereof. Examples of non-magnetic materials include copper, aluminum, titanium, chromium, and alloys thereof. The third layer 50 may be composed of one layer or multiple layers.

[0121] When the third layer 50 includes a metal, the third layer 50 may be formed by a physical deposition method, a plating method, or a combination thereof. The physical deposition method may be sputtering, vapor deposition, or ion plating. The plating method may be electrolytic plating or electroless plating. The third layer 50 may include a layer formed by a physical deposition method and a layer formed by a plating method. In this case, the layer formed by the physical deposition method may form the fifth surface 501 of the third layer. In this case, the layer formed by the physical deposition method may function as a seed layer for the layer formed by the plating method. That is, after a layer formed by a physical deposition method on the uneven surface of the first coating layer 65 is formed, the layer may be used as a seed layer to form a layer by the plating method.

[0122] (Fifth Modification) Fig. 17 is a diagram showing an example of an apparatus 200 including an organic device 100. The apparatus 200 includes a substrate 110 and an organic layer 130. The organic layer 130 is a layer formed by a vapor deposition method using a mask 20. The apparatus 200 is, for example, a smartphone. The apparatus 200 may also be a tablet terminal, a wearable terminal, or the like. The wearable terminal may be smart glasses, a head-mounted display, or the like.

[0123] It is also possible to combine the multiple components disclosed in the above-described embodiments and modifications as needed, or to delete some of the components disclosed in the above-described embodiments and modifications.

Claims

1. A mask comprising: a first layer including a first surface and a second surface located opposite to the first surface, wherein at least one first opening is formed penetrating the first layer from the first surface to the second surface; a second layer including a third surface opposing the first surface and a fourth surface located opposite to the third surface, wherein at least one second opening is formed penetrating the second layer from the third surface to the fourth surface at a position overlapping with the first opening in a planar view; and a third layer including a fifth surface opposing the second opening and / or the fourth surface and a sixth surface located opposite to the fifth surface, wherein a plurality of third openings are formed penetrating the third layer from the fifth surface to the sixth surface at positions overlapping with the first opening and the second opening in a planar view; 2. The mask described in claim 1, wherein the third layer includes a pattern region that overlaps the first opening and the second opening in a planar view, and a peripheral region that surrounds the pattern region in a planar view, and the second layer is located between the peripheral region and the first layer.

3. The mask of claim 1, wherein said third layer comprises single crystal silicon.

4. The mask of claim 1, wherein said third layer is an epitaxial layer.

5. The mask of claim 1, wherein said second layer comprises silicon dioxide.

6. The mask of claim 1, wherein the first layer comprises silicon or a silicon compound.

7. A method for manufacturing a mask as described in claim 1, comprising the steps of: forming a laminate including the first layer and a first coating layer covering the second surface of the first layer; forming an uneven surface on the surface of the first coating layer according to the shape of the third layer; forming the third layer on the uneven surface, the third layer accommodating the convex portion of the first coating layer within the third opening; removing a portion of the first layer to form the first opening; and removing a portion of the first coating layer to form the second layer having the second opening from the first coating layer, wherein the first coating layer within the third opening is removed.

8. A method for manufacturing a mask as described in claim 7, wherein the step of forming the third layer on the uneven surface includes the steps of: forming a second coating layer covering the convex portions of the uneven surface; and polishing the surface of the second coating layer until the convex portions of the first coating layer are exposed, thereby forming the third layer having the third opening from the second coating layer.

9. The method of manufacturing a mask according to claim 7, wherein the third layer comprises single crystal silicon, and the step of forming the third layer on the uneven surface comprises the step of epitaxially growing the single crystal silicon on the uneven surface.

10. The method for manufacturing a mask as described in claim 7, wherein the third layer contains a metal, and the step of forming the third layer on the uneven surface includes a step of performing a sputtering method, a vapor deposition method, an ion plating method and / or a plating method on the uneven surface.

11. A method for manufacturing a mask as described in claim 7, wherein the first layer contains silicon or a silicon compound, and the step of forming a laminate including the first layer and the first coating layer includes the steps of: preparing a substrate formed of the same material as the first layer; and forming the first coating layer from a portion of the substrate by oxidizing or thermally oxidizing another portion of the substrate.

12. The method of claim 7, wherein the step of forming a laminate including the first layer and the first coating layer includes a step of depositing a material that forms the first coating layer on the second surface of the first layer.