Doherty amplifier

Abstract

In this Doherty amplifier in which a plurality of Doherty amplifier cells (11), (12) are arranged in parallel, each Doherty amplifier cell (11), (12) comprises: a carrier amplifier (111), (112) that has an input node electrically connected to a carrier input pad and an output node electrically connected to a carrier output pad; a peak amplifier (121), (122) that has an input node electrically connected to a peak input pad and an output node electrically connected to a peak output pad; an in-cell input distribution circuit (231), (232) that has a cell input terminal to which an input signal is inputted, a carrier output terminal electrically connected to the carrier input pad, and a peak output terminal electrically connected to the peak input pad, and that distributes and outputs the input signal inputted to the cell input terminal to the carrier output terminal and the peak output terminal; and an in-cell output combining circuit (241), (242) that has a carrier input terminal electrically connected to the carrier output pad, a peak input terminal electrically connected to the peak output pad, and a cell output terminal, combines a carrier amplified output signal outputted to the carrier output pad and a peak amplified output signal outputted to the peak output pad, and outputs a cell output signal to the cell output terminal.

Description

Doherty Amplifier

[0001] The present disclosure relates to a Doherty amplifier having a carrier amplifier and a peaking amplifier.

[0002] In recent years, signals with a large peak-to-average power ratio (hereinafter referred to as PAPR) have been used in wireless communication systems such as mobile phones to improve communication speeds. Doherty amplifiers are known as amplifiers that can amplify signals with a large PAPR with high efficiency. Patent Document 1 discloses a Doherty amplifier with higher power efficiency. The Doherty amplifier disclosed in Patent Document 1 comprises multiple Doherty cells, each of which is made up of a carrier sub-amplifier and a peaking sub-amplifier, arranged in parallel.

[0003] Japanese Patent Application Laid-Open No. 2021-035042

[0004] The Doherty amplifier disclosed in Patent Document 1 is configured such that the carrier input terminals for all Doherty cells are electrically coupled to a carrier input signal manifold having an elongated conductor structure to which a power splitter is electrically coupled, the peaking input terminals for all Doherty cells are electrically coupled to a peaking input signal manifold having an elongated conductor structure to which a power splitter is electrically coupled, and the carrier output terminals and peaking output terminals for all Doherty cells are electrically coupled to an output signal coupling manifold having an elongated conductor structure to which an output node is electrically coupled.

[0005] However, in the Doherty amplifier disclosed in Patent Document 1, the electrical lengths of the paths from the input node of the power splitter to the carrier input terminals for each Doherty cell are different, the electrical lengths of the paths from the input node of the power splitter to the peaking input terminals for each Doherty cell are different, and the electrical lengths of the paths from the carrier output terminals and peaking output terminals for each Doherty cell to the output node are different. As a result, there is a problem in that the differences in electrical lengths cause a decrease in performance (efficiency).

[0006] The present disclosure has been made in consideration of the above points, and has an object to provide a Doherty amplifier in which a plurality of Doherty amplifier cells, each having a carrier amplifier and a peaking amplifier, are arranged in parallel, and which is free from path differences that arise due to the positions of the carrier amplifier and the peaking amplifier in the Doherty amplifier cell, thereby achieving improved performance (efficiency).

[0007] A Doherty amplifier according to the present disclosure is a Doherty amplifier having a plurality of Doherty amplifier cells arranged in parallel, each Doherty amplifier cell comprising: a carrier amplifier having an input node electrically connected to a carrier input pad and an output node electrically connected to a carrier output pad; a peak amplifier having an input node electrically connected to a peaking input pad and an output node electrically connected to a peaking output pad; an intra-cell input distribution circuit having a cell input terminal to which an input signal is input, a carrier output terminal electrically connected to the carrier input pad, and a peaking output terminal electrically connected to the peaking input pad, and distributing the input signal input to the cell input terminal to the carrier output terminal and the peaking output terminal for output; and an intra-cell output combining circuit having a carrier input terminal electrically connected to the carrier output pad, a peaking input terminal electrically connected to the peaking output pad, and a cell output terminal, and combining a carrier amplified output signal output to the carrier output pad and a peak amplified output signal output to the peaking output pad, and outputting a cell output signal to the cell output terminal.

[0008] According to the present disclosure, each Doherty amplifier cell has an intra-cell input distribution circuit and an intra-cell output combining circuit in addition to a carrier amplifier and a peaking amplifier, so there is no difference in electrical length when dividing and combining multiple Doherty amplifier cells, and performance (efficiency) can be improved.

[0009] Fig. 1 is a diagram showing a configuration example of a Doherty amplifier according to a first embodiment. Fig. 2 is a diagram showing a configuration example of a Doherty amplifier according to a second embodiment. Fig. 3 is a plan view showing an example of a structure around a DC blocking capacitance in a Doherty amplifier according to a second embodiment. Fig. 4 is a cross-sectional view showing an example of a structure around a DC blocking capacitance in a Doherty amplifier according to a second embodiment. Fig. 5 is a plan view showing an example of a structure around a DC blocking capacitance in a Doherty amplifier according to a second embodiment.

[0010] Embodiment 1. A Doherty amplifier according to embodiment 1 will be described with reference to Figure 1. The Doherty amplifier according to embodiment 1 is a Doherty amplifier in which a plurality of Doherty amplifier cells 1, each having a carrier amplifier (carrier amp) 11 and a peak amplifier (peaking amplifier) ​​12, are arranged in parallel, and each Doherty amplifier cell 1 further has an intra-cell input distribution circuit 13 that distributes an input signal to the input sides of the carrier amplifier 11 and the peak amplifier 12, and an intra-cell output combining circuit 14 that combines a carrier amplified output signal from the carrier amplifier 11 and a peak amplified output signal from the peak amplifier 12 on the output sides of the carrier amplifier 11 and the peak amplifier 12.

[0011] 1 shows two Doherty amplifier cells 1, the first Doherty amplifier cell 1 being given the subscript 1 and the second Doherty amplifier cell 1 being given the subscript 2. １ and the second Doherty amplifier cell 1 ２ The first Doherty amplifier cell 1 has the same circuit configuration and size. １ and the second Doherty amplifier cell 1 ２ In the description of the above, in order to avoid complexity of the description, the subscripts will be omitted and the description will be given as a common configuration.

[0012] Also, there may be three or more Doherty amplifier cells 1. Even if there are three or more Doherty amplifier cells 1, each Doherty amplifier cell 1 ｎ (n≧3) have the same circuit configuration and size. The number of Doherty amplifier cells 1 is determined by the output power desired to be obtained as a Doherty amplifier.

[0013] An input signal, which is a high frequency signal to be amplified, is input to an input terminal 100. A plurality of Doherty amplifier cells 1 １ , 1 ２ The cell output signals output from the respective cells are combined to produce a Doherty amplified signal.

[0014] The input node of the carrier amplifier 11 is electrically connected to a carrier input pad 11a, and the output node is electrically connected to a carrier output pad 11b. The carrier amplifier 11 operates in class AB or class B. The carrier amplifier 11 is provided with a signal amplification element (carrier transistor), and the carrier transistor 11 is a high-voltage transistor having a source field plate of a GaN HEMT (High Electron Mobility Transistor) using gallium nitride (GaN).

[0015] The carrier transistor 11 may be a transistor such as a field effect transistor (FET), a heterojunction bipolar transistor (HBT), or a high electron mobility transistor (HEMT).

[0016] In the carrier transistor 11, a gate electrode is electrically connected to a carrier input pad 11a as an input node, a drain electrode is electrically connected to a carrier output pad 11b as an output node, and a source electrode is connected to a ground node. The carrier output pad 11b is connected to a drain voltage supply node, and a drain voltage is supplied to the drain electrode of the carrier transistor 11 from the drain voltage supply node via the carrier output pad 11b.

[0017] A carrier input pad to which the gate electrode of the carrier transistor 11 is connected is connected to a carrier gate voltage application node, and a gate voltage for causing the carrier transistor 11 to operate in class AB or class B is applied to the gate electrode of the carrier transistor 11 from the carrier gate voltage application node via the carrier input pad. The size of the carrier transistor 11 is determined in accordance with the output power desired to be obtained as a Doherty amplifier, along with the number of Doherty amplifier cells 1 set.

[0018] The peak amplifier 12 has an input node electrically connected to a peak input pad 12a and an output node electrically connected to a peak output pad 12b. The peak amplifier 12 operates in class C. The peak amplifier 12 is equipped with a signal amplification element (peak transistor), and the peak transistor 12 is a high-voltage GaN HEMT transistor. Note that the peak transistor 12 may also be a field-effect transistor, a heterojunction bipolar transistor, a high electron mobility transistor, or other transistor.

[0019] The peak transistor 12 has a gate electrode electrically connected to a peak input pad 12a as an input node, a drain electrode electrically connected to a peak output pad 12b as an output node, and a source electrode connected to a ground node. The peak output pad 12b is connected to a drain voltage supply node, and a drain voltage is supplied to the drain electrode of the peak transistor 12 from the drain voltage supply node via the peak output pad 12b.

[0020] The peak input pad to which the gate electrode of the peak transistor 12 is connected is connected to a peak gate voltage application node, and a gate voltage for causing the peak transistor 12 to operate in class C is applied to the gate electrode of the peak transistor 12 from the peak gate voltage application node via the peak input pad.

[0021] The size of the peaking transistor 12 is determined by the output power desired to be obtained as a Doherty amplifier, along with the number of Doherty amplifier cells 1. The carrier transistor 11 and the peaking transistor 12 are each mounted and integrated as GaN HEMTs in a GaN MMIC (Monolithic Microwave Integrated Circuit) and formed on the same chip.

[0022] All of the carrier transistors 11 and peaking transistors 12 in the multiple Doherty amplifier cells 1 may be formed on the same chip. When all of the carrier transistors 11 and peaking transistors 12 in the multiple Doherty amplifier cells 1 are formed on the same chip, the carrier transistors 11 and peaking transistors 12 are alternately arranged in parallel.

[0023] The intra-cell input distribution circuit 13 has a cell input terminal 13a electrically connected to the input terminal 100 to which the input signal input to the input terminal 100 is input, a carrier output terminal 13b electrically connected to the carrier input pad 11a, and a peak output terminal 13c electrically connected to the peak input pad 12a. The intra-cell input distribution circuit 13 distributes the input signal input to the cell input terminal 13a to the carrier output terminal 13b and the peak output terminal 13c and outputs them.

[0024] The intra-cell input distribution circuit 13 functions as a matching circuit and a phase adjustment line, and distributes an input signal input to the cell input terminal 13a to the carrier input pad 11a and the peak input pad 12a and outputs the signal. The intra-cell input distribution circuit 13 is implemented on the GaN MMIC.

[0025] The intra-cell input distribution circuit 13 may be formed on the same chip as the carrier transistor 11 and the peaking transistor 12. The intra-cell input distribution circuit 13, carrier transistor 11, and peaking transistor 12 of each of the multiple Doherty amplifier cells 1 may all be formed on the same chip. When formed on the same chip, the electrical connection between the carrier output terminal 13b and the carrier input pad 11a, and the electrical connection between the peaking output terminal 13c and the peaking input pad 12a are each made by conductive layers formed on the same chip.

[0026] Furthermore, when the intra-cell input distribution circuit 13, the carrier transistor 11, and the peaking transistor 12 are formed on different chips, the electrical connection between the carrier output terminal 13b and the carrier input pad 11a, and the electrical connection between the peaking output terminal 13c and the peaking input pad 12a are made by bonding wires, respectively. The electrical connection between the input terminal 100 and the cell input terminal 13a is made by a conductive layer or a bonding wire.

[0027] Since the multiple Doherty amplifier cells 1 all have the same circuit configuration and size, the electrical length from the cell input terminal 13a of the intra-cell input distribution circuit 13 in each Doherty amplifier cell 1 to the carrier input pad 11a is equal for all of the multiple Doherty amplifier cells 1. Also, the electrical length from the cell input terminal 13a of the intra-cell input distribution circuit 13 in each Doherty amplifier cell 1 to the peaking input pad 12a is equal for all of the multiple Doherty amplifier cells 1.

[0028] The intra-cell output combining circuit 14 has a carrier input terminal 14b electrically connected to the carrier output pad 11b, a peak input terminal 14c electrically connected to the peak output pad 12b, and a cell output terminal 14a electrically connected to the output terminal 200 from which the Doherty amplified signal is output. The intra-cell output combining circuit 14 combines the carrier amplified output signal output to the carrier output pad 11b and the peak amplified output signal output to the peak output pad 12b, and outputs the cell output signal to the cell output terminal 14a.

[0029] The intra-cell output combining circuit 14 has the functions of a matching circuit and a phase adjustment line, and also has the function of combining the carrier amplified output signal output to the carrier output pad 11 b and the peak amplified output signal output to the peak output pad 12 b, and outputting the cell output signal to the cell output terminal 14 a. The intra-cell output combining circuit 14 is implemented on the GaN MMIC.

[0030] The intra-cell output combiner circuit 14 may be formed on the same chip as the carrier transistors 11 and the peaking transistors 12. The intra-cell output combiner circuit 14, carrier transistors 11, peaking transistors 12, and intra-cell input distribution circuit 13 of each of the multiple Doherty amplifier cells 1 may all be formed on the same chip. When formed on the same chip, the electrical connection between the carrier input terminal 14b and the carrier output pad 11b, and the electrical connection between the peaking input terminal 14c and the peaking output pad 12b are each made by conductive layers formed on the same chip.

[0031] Furthermore, when the intra-cell output combining circuit 14, the carrier transistor 11, and the peaking transistor 12 are formed on different chips, the electrical connection between the carrier input terminal 14b and the carrier output pad 11b, and the electrical connection between the peaking input terminal 14c and the peaking output pad 12b are made by bonding wires, respectively. The electrical connection between the output terminal 200 and the cell output terminal 14a is made by a conductive layer or a bonding wire.

[0032] Since the multiple Doherty amplifier cells 1 all have the same circuit configuration and size, the electrical length from the carrier output pad 11b in each Doherty amplifier cell 1 to the cell output terminal 14a of the intra-cell output combining circuit 14 is equal for all of the multiple Doherty amplifier cells 1. Also, the electrical length from the peak output pad 12b in each Doherty amplifier cell 1 to the cell output terminal 14a of the intra-cell output combining circuit 14 is equal for all of the multiple Doherty amplifier cells 1.

[0033] Next, the operation of the Doherty amplifier according to the first embodiment will be described. The operating principle of the Doherty amplifier is well known and will not be described here. An input signal input to the input terminal 100 is input to a plurality of Doherty amplifier cells 1 １ , 1 ２ Each intra-cell input distribution circuit 13 １ , 13 ２ Cell input terminal 13a in １ , 13a ２ Each Doherty amplifier cell 1 １ , 1 ２ In the cell input terminal 13a １ , 13a ２ The input signal input to the intra-cell input distribution circuit 13 １ , 13 ２ and is distributed to the carrier output terminal 13b １ , 13b ２ and peak output terminal 13c １ , 13c ２ is output from

[0034] Each Doherty amplifier cell 1 １ , 1 ２ In the carrier output terminal 13b １ , 13b ２ The input signal output from the carrier input pad 11a １ , 11a ２ , and is input to the input node (gate electrode) of the carrier transistor 11 via the １ , 1 ２ In the peak output terminal 13c １ , 13c ２ The input signal output from the peak input pad 12a １ , 12a ２ and input to the input node (gate electrode) of the peak transistor 12 via

[0035] Doherty amplifier cell 1 １ Intra-cell input distribution circuit 13 １ Cell input terminal 13a １ to carrier input pad 11a １ and the electrical length of the Doherty amplifier cell 1２ Intra-cell input distribution circuit 13 ２ Cell input terminal 13a ２ to carrier input pad 11a ２ The electrical lengths of the Doherty amplifier cells 1 and 2 are equal. １ and Doherty amplifier cell 1 ２ As described above, the electrical length from the cell input terminal 13a of the intra-cell input distribution circuit 13 to the carrier input pad 11a is the same for all of the plurality of Doherty amplifier cells 1.

[0036] Doherty amplifier cell 1 １ Intra-cell input distribution circuit 13 １ Cell input terminal 13a １ to peak input pad 12a １ and the electrical length of the Doherty amplifier cell 1 ２ Intra-cell input distribution circuit 13 ２ Cell input terminal 13a ２ to peak input pad 12a ２ The electrical lengths of the Doherty amplifier cells 1 and 2 are equal. １ and Doherty amplifier cell 1 ２ As described above, the electrical length from the cell input terminal 13 a of the intra-cell input distribution circuit 13 to the peaking input pad 12 a is the same for all of the multiple Doherty amplifier cells 1. Therefore, on the input side of the multiple Doherty amplifier cells 1, there is no difference in the path when the input signal is distributed, and there is no degradation in the performance (efficiency) of the Doherty amplifier.

[0037] Each Doherty amplifier cell 1 １ , 1 ２ In the carrier transistor 11 １ , 11 ２ The input signal input to the input node of the carrier transistor 11 １ , 11 ２ and the carrier transistor 11 １ , 11 ２ from the output node (drain electrode) of the carrier output pad 11b １ , 11b ２ The carrier amplified output signal is input to the intra-cell output combining circuit 14 via the１ , 14 ２ Carrier input terminal 14b １ , 14b ２ is entered into

[0038] On the other hand, each Doherty amplifier cell 1 １ , 1 ２ In the peak transistor 12 １ , 12 ２ The input signal input to the input node of the peak transistor 12 １ , 12 ２ and the peak transistor 12 １ , 12 ２ output node (drain electrode) to the peak output pad 12b １ , 12b ２ The peak amplified output signal is fed to the intra-cell output combining circuit 14 via the １ , 14 ２ Peak input terminal 14c １ , 14c ２ is entered into

[0039] Each Doherty amplifier cell 1 １ , 1 ２ In the carrier input terminal 14b １ , 14b ２ and the carrier amplified output signal input to the peak input terminal 14c. １ , 14c ２ The peak amplified output signal input to the cell output combiner circuit 14 １ , 14 ２ and outputted as a cell output signal to the cell output terminal 14a. １ , 14a ２ Each Doherty amplifier cell 1 １ , 1 ２ Output terminal 14a for each cell １ , 14a ２ The cell output signals output from are synthesized and output from an output terminal 200.

[0040] Doherty amplifier cell 1 １ Carrier output pad 11b in １ to the intra-cell output synthesis circuit 14 １ Cell output terminal 14a１ and the electrical length of the Doherty amplifier cell 1 ２ Carrier output pad 11b in ２ to the intra-cell output synthesis circuit 14 ２ Cell output terminal 14a ２ The electrical lengths of the Doherty amplifier cells 1 and 2 are equal. １ and Doherty amplifier cell 1 ２ As described above, the electrical length from the carrier output pad 11b to the cell output terminal 14a of the intra-cell output combining circuit 14 is the same for all of the plurality of Doherty amplifier cells 1.

[0041] Doherty amplifier cell 1 １ Peak output pad 12b in １ to the intra-cell output synthesis circuit 14 １ Cell output terminal 14a １ and the electrical length of the Doherty amplifier cell 1 ２ Peak output pad 12b in ２ to the intra-cell output synthesis circuit 14 ２ Cell output terminal 14a ２ The electrical lengths of the Doherty amplifier cells 1 and 2 are equal. １ and Doherty amplifier cell 1 ２ As described above, the electrical length from the peak output pad 12b to the cell output terminal 14a of the intra-cell output combining circuit 14 is equal for all of the multiple Doherty amplifier cells 1. Therefore, on the output side of the multiple Doherty amplifier cells 1, there is no difference in the paths for combining the carrier amplified output signal and the peak amplified output signal, and there is no degradation in the performance (efficiency) of the Doherty amplifier.

[0042] The Doherty amplifier according to the first embodiment includes a plurality of Doherty amplifier cells 1 １ , 1 ２ are arranged in parallel, and each Doherty amplifier cell 1 １ , 1 ２ is the carrier amplifier 11 １ , 11 ２ and peak amplifier 12 １ , 12 ２ The input signal is then input to a carrier amplifier 11. １ , 11２ and peak amplifier 12 １ , 12 ２ Intra-cell input distribution circuit 13 １ , 13 ２ and carrier amplifier 11 １ , 11 ２ and the carrier amplified output signal from the peak amplifier 12 １ , 12 ２ an intra-cell output combining circuit 14 that combines the peak amplified output signals from the １ , 14 ２ , the plurality of Doherty amplifier cells 1 １ , 1 ２ Between them, Doherty amplifier cell 1 １ , 1 ２ There is no difference in electrical length between the input side and the output side, and the performance (efficiency) of the Doherty amplifier does not decrease, improving power efficiency.

[0043] The Doherty amplifier according to the first embodiment includes a plurality of Doherty amplifier cells 1 １ , 1 ２ are housed in one package and configured to have an input terminal 100 and an output terminal 200, thereby providing an easy-to-handle Doherty amplifier.

[0044] Second Embodiment A Doherty amplifier according to a second embodiment will be described with reference to FIGS.

[0045] The Doherty amplifier according to the second embodiment differs from the Doherty amplifier according to the first embodiment in that: １ , 1 ２ Each carrier amplifier 11 １ , 11 ２ and peak amplifier 12 １ , 12 ２ 2 to 5, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.

[0046] As shown in FIG. 2 , the Doherty amplifier according to the second embodiment is a Doherty amplifier in which a plurality of Doherty amplifier cells 1, each having a carrier amplifier 11 and a peak amplifier 12, are arranged in parallel, and each Doherty amplifier cell 1 further includes an intra-cell input distribution circuit 23 that distributes an input signal to the input sides of the carrier amplifier 11 and the peak amplifier 12, an intra-cell output combining circuit 24 that combines a carrier amplified output signal from the carrier amplifier 11 and a peak amplified output signal from the peak amplifier 12 on the output sides of the carrier amplifier 11 and the peak amplifier 12, an input distribution circuit 31, a carrier gate bias application circuit 32, a peak gate bias application circuit 33, and an output combining circuit 40.

[0047] 2 shows two Doherty amplifier cells 1, with the first Doherty amplifier cell 1 being given the subscript 1 and the second Doherty amplifier cell 1 being given the subscript 2. １ and the second Doherty amplifier cell 1 ２ The first Doherty amplifier cell 1 has the same circuit configuration and size. １ and the second Doherty amplifier cell 1 ２ In the description of the above, in order to avoid complexity of the description, the subscripts will be omitted and the description will be given as a common configuration.

[0048] Also, there may be three or more Doherty amplifier cells 1. Even if there are three or more Doherty amplifier cells 1, each Doherty amplifier cell 1 ｎ (n≧3) have the same circuit configuration and size. The number of Doherty amplifier cells 1 is determined by the output power desired to be obtained as a Doherty amplifier.

[0049] The first input terminal 101 receives an input signal, which is a high frequency signal to be amplified, and a gate bias voltage Vgc for the carrier transistor 11 that constitutes the carrier amplifier 11. The second input terminal 102 receives an input signal and a gate bias voltage Vgp for the peak transistor 12 that constitutes the peak amplifier 12. The output terminals 201 and 202 are connected to a plurality of Doherty amplifier cells 1. １ , 1 ２The cell output signals output from the respective cells are combined to produce a Doherty amplified signal.

[0050] The intra-cell input distribution circuit 23 has a carrier side input circuit 231, a peak side input circuit 232, and a DC blocking capacitance 233. The DC blocking capacitance 233 is electrically connected between the cell input terminal 23a and the carrier side input circuit 231 and peak side input circuit 232. For example, as shown in Figures 3 and 4, the DC blocking capacitance 233 is configured as a capacitor having one end of the carrier side input circuit 231 as one electrode, a dielectric sandwiched between one end of the carrier side input circuit 231 and one end of the peak side input circuit 232 as the other electrode. One electrode of the DC blocking capacitance 233 is electrically connected to the cell input terminal 23a.

[0051] 5, the DC blocking capacitance 233 may include a capacitor 233a connected between the cell input terminal 23a and one end of the carrier side input circuit 231, and a capacitor 233b connected between the cell input terminal 23a and one end of the peak side input circuit 232. In either case, the DC blocking capacitance 233 is short-circuited to the input signal, which is a high-frequency signal input to the cell input terminal 23a, and distributes the input signal input to the cell input terminal 23a to both the carrier side input circuit 231 and the peak side input circuit 232. On the other hand, the DC blocking capacitance 233 blocks DC between the carrier side input circuit 231 and the peak side input circuit 232. In other words, the cell input terminal 23a has the function of being open in terms of DC.

[0052] The carrier side input circuit 231 is AC connected between the cell input terminal 23a and the carrier output terminal 23b, and has a carrier gate bias terminal 23d to which a gate bias voltage Vgc for the carrier transistor 11 is applied. The peak side input circuit 232 is AC connected between the cell input terminal 23a and the peak output terminal 23c, and has a peak gate bias terminal 23e to which a gate bias voltage Vgp for the peak transistor 12 is applied.

[0053] The carrier side input circuit 231 and the peak side input circuit 232 each have the functions of a matching circuit and a phase adjustment line. The carrier side input circuit 231, the peak side input circuit 232, and the DC blocking capacitor 233 are each mounted on a GaN MMIC.

[0054] The intra-cell input distribution circuit 23 may be formed on the same chip as the carrier transistor 11 and the peaking transistor 12. The intra-cell input distribution circuit 23, carrier transistor 11, and peaking transistor 12 of each of the multiple Doherty amplifier cells 1 may all be formed on the same chip. When formed on the same chip, the electrical connection between the carrier output terminal 23b and the carrier input pad 11a, and the electrical connection between the peaking output terminal 23c and the peaking input pad 12a are each made by conductive layers formed on the same chip.

[0055] Furthermore, when the intra-cell input distribution circuit 23, the carrier transistor 11, and the peak transistor 12 are formed on different chips, the electrical connection between the carrier output terminal 23b and the carrier input pad 11a, and the electrical connection between the peak output terminal 23c and the peak input pad 12a are each made by bonding wires.

[0056] Since the multiple Doherty amplifier cells 1 all have the same circuit configuration and size, the electrical length from the cell input terminal 13a of the intra-cell input distribution circuit 13 in each Doherty amplifier cell 1 to the carrier input pad 11a is equal for all of the multiple Doherty amplifier cells 1. Also, the electrical length from the cell input terminal 13a of the intra-cell input distribution circuit 13 in each Doherty amplifier cell 1 to the peaking input pad 12a is equal for all of the multiple Doherty amplifier cells 1.

[0057] The intra-cell output combining circuit 24 is composed of a matching circuit. The intra-cell output combining circuit 24 has a carrier input terminal 24b electrically connected to the carrier output pad 11b, a peak input terminal 24c electrically connected to the peak output pad 12b, and a cell output terminal 24a. The intra-cell output combining circuit 24 combines the carrier amplified output signal output to the carrier output pad 11b and the peak amplified output signal output to the peak output pad 12b, and outputs the cell output signal to the cell output terminal 24a.

[0058] The intra-cell output combiner circuit 24 is implemented on a GaN MMIC. The intra-cell output combiner circuit 24 may be formed on the same chip as the carrier transistors 11 and the peaking transistors 12. The intra-cell output combiner circuit 24, carrier transistors 11, peaking transistors 12, and intra-cell input distribution circuit 23 of each of the multiple Doherty amplifier cells 1 may all be formed on the same chip. When formed on the same chip, the electrical connection between the carrier input terminal 24b and the carrier output pad 11b, and the electrical connection between the peaking input terminal 24c and the peaking output pad 12b are each made by conductive layers formed on the same chip.

[0059] Furthermore, when the intra-cell output synthesis circuit 24, the carrier transistor 11, and the peak transistor 12 are formed on different chips, the electrical connection between the carrier input terminal 24b and the carrier output pad 11b, and the electrical connection between the peak input terminal 24c and the peak output pad 12b are each made by bonding wires.

[0060] Since the multiple Doherty amplifier cells 1 all have the same circuit configuration and size, the electrical length from the carrier output pad 11b in each Doherty amplifier cell 1 to the cell output terminal 24a of the intra-cell output combining circuit 24 is equal for all of the multiple Doherty amplifier cells 1. Also, the electrical length from the peak output pad 12b in each Doherty amplifier cell 1 to the cell output terminal 24a of the intra-cell output combining circuit 24 is equal for all of the multiple Doherty amplifier cells 1.

[0061] The input distribution circuit 31 is connected to the first input terminal 101 and the second input terminal 102, and the cell input terminal 23a １ , 23a ２ The input distribution circuit 31 has a function of being DC-open with the first input terminal 101 and the second input terminal 102. The input distribution circuit 31 distributes the input signal input to the first input terminal 101 and the input signal input to the second input terminal 102 to the cell input terminal 23a. １ and cell input terminal 23a ２ and output.

[0062] Since the input distribution circuit 31 has a function of being DC-open with the first input terminal 101, the gate bias voltage Vgc input to the first input terminal 101 is not transmitted to the cell input terminal 23a. Also, since the input distribution circuit 31 has a function of being DC-open with the second input terminal 102, the gate bias voltage Vgp input to the second input terminal 102 is not transmitted to the cell input terminal 23a. The input distribution circuit 31 uses a Wilkinson combiner / divider or a 90° hybrid circuit.

[0063] The input distribution circuit 31 is electrically connected to the first input terminal 101 and the second input terminal 102 by bonding wires. １ and cell input terminal 23a ２ The electrical connections are made by bonding wires. The input distribution circuit 31 is mounted on the GaN MMIC. The input distribution circuit 31 includes a plurality of Doherty amplifier cells 1. １ , 1 ２ may be formed on the same chip as

[0064] The carrier gate bias application circuit 32 is connected to the first input terminal 101, and the intra-cell input distribution circuit 23 １ , 23 ２ The carrier side input circuit 231 in each １ , 231 ２ The carrier gate bias application circuit 32 is connected to the carrier amplifier 11 １ , 11 ２The gate bias voltage Vgc for the plurality of Doherty amplifier cells 1 １ , 1 ２ Intra-cell input distribution circuit 23 in each １ , 23 ２ Carrier side input circuit 231 １ , 231 ２ Apply to.

[0065] In the second embodiment, the carrier gate bias application circuit 32 is a capacitor, and one electrode of the capacitor is connected to the first input terminal 101 and the carrier side input circuit 231. １ (Carrier gate bias terminal 23d １ ), and the carrier side input circuit 231 ２ (Carrier gate bias terminal 23d ２ ) are electrically connected to each other by bonding wires, and the other electrode is grounded.

[0066] The bonding wire connecting the first input terminal 101 and the carrier gate bias application circuit 32, the capacitance in the carrier gate bias application circuit 32, and the capacitance between the carrier gate bias application circuit 32 and the carrier side input circuit 231 １ As a result, the input signal input to the first input terminal 101 is in an open state in terms of AC by the carrier gate bias application circuit 32, and therefore the carrier side input circuit 231 １ The gate bias voltage Vgc applied to the first input terminal 101 is transmitted to the carrier side input circuit 231 via the carrier gate bias application circuit 32. １ and the carrier amplifier 11 １ is applied to the gate electrode of

[0067] Similarly, the bonding wire connecting the first input terminal 101 and the carrier gate bias application circuit 32, the capacitance in the carrier gate bias application circuit 32, and the capacitance between the carrier gate bias application circuit 32 and the carrier side input circuit 231 are ２As a result, the input signal input to the first input terminal 101 is in an open state in terms of AC by the carrier gate bias application circuit 32, and therefore the carrier side input circuit 231 ２ The gate bias voltage Vgc applied to the first input terminal 101 is transmitted to the carrier side input circuit 231 via the carrier gate bias application circuit 32. ２ and the carrier amplifier 11 ２ is applied to the gate electrode of

[0068] The carrier gate bias application circuit 32 is mounted on the GaN MMIC. The carrier gate bias application circuit 32 is connected to a plurality of Doherty amplifier cells 1 １ , 1 ２ may be formed on the same chip as

[0069] The peak gate bias application circuit 33 is connected to the second input terminal 102, and the intra-cell input distribution circuit 23 １ , 23 ２ The peak side input circuit 232 in each １ , 232 ２ The peak gate bias application circuit 33 is connected to the peak amplifier 12 １ , 12 ２ The gate bias voltage Vgp for the plurality of Doherty amplifier cells 1 １ , 1 ２ Intra-cell input distribution circuit 23 in each １ , 23 ２ Peak side input circuit 232 １ , 232 ２ Apply to.

[0070] In the second embodiment, the peak gate bias application circuit 33 is a capacitor, and one electrode of the capacitor is connected to the second input terminal 102 and the peak side input circuit 232. １ (Peak gate bias terminal 23e １ ), and the peak side input circuit 232 ２ (Peak gate bias terminal 23e ２) are electrically connected to each other by bonding wires, and the other electrode is grounded.

[0071] The bonding wire connecting the second input terminal 102 and the peak gate bias application circuit 33, the capacitance in the peak gate bias application circuit 33, and the capacitance between the peak gate bias application circuit 33 and the peak side input circuit 232 １ As a result, the input signal input to the second input terminal 102 is in an open state in terms of AC by the peak gate bias application circuit 33, so that the peak side input circuit 232 １ The gate bias voltage Vgp applied to the second input terminal 102 is transmitted to the peak side input circuit 232 via the peak gate bias application circuit 33. １ and the peak amplifier 12 １ is applied to the gate electrode of

[0072] Similarly, the bonding wire connecting the second input terminal 102 and the peak gate bias application circuit 33, the capacitance in the peak gate bias application circuit 33, and the capacitance between the peak gate bias application circuit 33 and the peak side input circuit 232 ２ As a result, the input signal input to the second input terminal 102 is in an open state in terms of AC by the peak gate bias application circuit 33, so that the peak side input circuit 232 ２ The gate bias voltage Vgp applied to the second input terminal 102 is transmitted to the peak side input circuit 232 via the peak gate bias application circuit 33. ２ and the peak amplifier 12 ２ is applied to the gate electrode of

[0073] The peak gate bias application circuit 33 is mounted on the GaN MMIC. The peak gate bias application circuit 33 applies a plurality of Doherty amplifier cells 1 １ , 1 ２ may be formed on the same chip as

[0074] The output combining circuit 40 is connected to the cell output terminal 24a.１ , 24a ２ and is electrically connected to output terminals 201 and 202. The output combining circuit 40 is １ Cell output terminal 24a in １ Cell output signal from Doherty amplifier cell 1 ２ Cell output terminal 24a in ２ The output signal from the cells is combined and output as a Doherty amplified signal to output terminals 201 and 202. The output combining circuit 40 is a Wilkinson combiner / divider or a 90° hybrid circuit.

[0075] Next, the operation of the Doherty amplifier according to the second embodiment will be described. Note that the operating principle of the Doherty amplifier is known and will not be discussed. An input signal and a gate bias voltage Vgc input to the first input terminal 101 are input to the input distribution circuit 31 and the carrier gate bias application circuit 32. An input signal and a gate bias voltage Vgp input to the second input terminal 102 are input to the input distribution circuit 31 and the peak gate bias application circuit 33.

[0076] In the input distribution circuit 31, the input signal input to the first input terminal 101 and the input signal input to the second input terminal 102 are combined and output to a plurality of Doherty amplifier cells 1 １ , 1 ２ Each intra-cell input distribution circuit 13 １ , 13 ２ Cell input terminal 23a in １ , 23 ２ is entered into

[0077] Since the input distribution circuit 31 has the function of being DC-open to each of the first input terminal 101 and the second input terminal 102, the gate bias voltage Vgc input to the first input terminal 101 and the gate bias voltage Vgp input to the second input terminal 102 are not transmitted to the cell input terminal 23a.

[0078] Moreover, the cell input terminal 23a １ , 23a ２ DC blocking capacitor 233 １ , 233２ is connected to the cell input terminal 23a １ , 23a ２ has a function of being open in terms of DC, the gate bias voltage Vgc and the gate bias voltage Vgp are １ , 233 ２ is cut off by the carrier side input circuit 231 １ , 231 ２ and peak side input circuit 232 １ , 232 ２ is not transmitted to

[0079] That is, the gate bias voltage Vgc input to the first input terminal 101 is supplied to the input distribution circuit 31, the cell input terminal 23a １ , 23a ２ , and the peak side input circuit 232 １ , 232 ２ via the peak transistor 12 １ , 12 ２ The gate bias voltage Vgp input to the second input terminal 102 is not transmitted to the input node (gate electrode) of the cell 23a. １ , 23a ２ , and the carrier side input circuit 231 １ , 231 ２ via the carrier transistor 11 １ , 11 ２ The signal is not transmitted to the input node (gate electrode).

[0080] Each Doherty amplifier cell 1 １ , 1 ２ , the signals are combined by the input distribution circuit 31 and input to the cell input terminal 23a １ , 23 ２ The input signal input to the cell is sent to the intra-cell input distribution circuit 23 １ , 23 ２ and is distributed to the carrier output terminal 23b １ , 23b ２ and peak output terminal 23c １ , 23c ２ is output from

[0081] Each Doherty amplifier cell 1 １, 1 ２ In the carrier output terminal 23b １ , 23b ２ The input signal output from the carrier input pad 11a １ , 11a ２ via the carrier transistor 11 １ , 11 ２ The signal is input to the input node (gate electrode) of each Doherty amplifier cell 1 １ , 1 ２ In the peak output terminal 23c １ , 23c ２ The input signal output from the peak input pad 12a １ , 12a ２ via the peak transistor 12 １ , 12 ２ The signal is input to the input node (gate electrode).

[0082] In the carrier gate bias application circuit 32, the input signal and the gate bias voltage Vgc input to the first input terminal 101 are in an open state in terms of AC by the carrier gate bias application circuit 32, so the input signal is transmitted to the plurality of Doherty amplifier cells 1. １ , 1 ２ Each intra-cell input distribution circuit 13 １ , 13 ２ Carrier side input circuit 231 in １ , 231 ２ is not transmitted to the carrier side input circuit 231 １ , 231 ２ A gate bias voltage Vgc is transmitted to

[0083] Each Doherty amplifier cell 1 １ , 1 ２ In the carrier side input circuit 231 １ , 231 ２ The gate bias voltage Vgc transmitted to the carrier output terminal 23b １ , 23b ２ to carrier input pad 11a １ , 11a ２ via the carrier transistor 11 １ , 11 ２The gate bias voltage Vgc is applied to the input node (gate electrode) of the cell input terminal 23a. １ , 23 ２ DC blocking capacitor 233 １ , 233 ２ is connected, the DC blocking capacitor 233 １ , 233 ２ is cut off by the peak side input circuit 232 １ , 232 ２ is not transmitted to

[0084] In the peak gate bias application circuit 33, the input signal and the gate bias voltage Vgp input to the second input terminal 102 are in an AC open state by the peak gate bias application circuit 33, so the input signal is applied to the plurality of Doherty amplifier cells 1 １ , 1 ２ Each intra-cell input distribution circuit 13 １ , 13 ２ Peak side input circuit 232 in １ , 232 ２ is not transmitted to the peak side input circuit 232 １ , 232 ２ A gate bias voltage Vgp is transmitted to

[0085] Each Doherty amplifier cell 1 １ , 1 ２ In the peak side input circuit 232 １ , 232 ２ The gate bias voltage Vgp transmitted to the peak output terminal 23c １ , 23c ２ to peak input pad 12a １ , 12a ２ via the peak transistor 12 １ , 12 ２ The gate bias voltage Vgp is applied to the input node (gate electrode) of the cell input terminal 23a. １ , 23 ２ DC blocking capacitor 233 １ , 233 ２ is connected, the DC blocking capacitor 233 １ , 233 ２ is cut off by the carrier side input circuit 231１ , 231 ２ is not transmitted to

[0086] Carrier transistor 11 １ , 11 ２ The gate bias voltage Vgc is applied to the amplifier, which operates in class AB or class B to amplify the input signal and output the carrier amplified output signal to the carrier output pad 11b. １ , 11b ２ Peak transistor 12 １ , 12 ２ The gate bias voltage Vgp is applied to the amplifier, which operates in class C and amplifies the input signal, and outputs the peak amplified output signal to the peak output pad 12b. １ , 12b ２ Output to.

[0087] Doherty amplifier cell 1 １ Intra-cell input distribution circuit 23 １ Cell input terminal 23a １ to carrier input pad 11a １ and the electrical length of the Doherty amplifier cell 1 ２ Intra-cell input distribution circuit 23 ２ Cell input terminal 13a ２ to carrier input pad 11a ２ The electrical lengths of the Doherty amplifier cells 1 and 2 are equal. １ and Doherty amplifier cell 1 ２ As described above, the electrical length from the cell input terminal 23a of the intra-cell input distribution circuit 23 to the carrier input pad 11a is the same for all of the plurality of Doherty amplifier cells 1.

[0088] Doherty amplifier cell 1 １ Intra-cell input distribution circuit 23 １ Cell input terminal 23a １ to peak input pad 12a １ and the electrical length of the Doherty amplifier cell 1 ２ Intra-cell input distribution circuit 23 ２ Cell input terminal 23a ２ to peak input pad 12a ２The electrical lengths of the Doherty amplifier cells 1 and 2 are equal. １ and Doherty amplifier cell 1 ２ As described above, the electrical length from the cell input terminal 23 a of the intra-cell input distribution circuit 23 to the peaking input pad 12 a is the same for all of the multiple Doherty amplifier cells 1. Therefore, on the input side of the multiple Doherty amplifier cells 1, there is no difference in the path when the input signal is distributed, and there is no degradation in the performance (efficiency) of the Doherty amplifier.

[0089] Each Doherty amplifier cell 1 １ , 1 ２ In the carrier transistor 11 １ , 11 ２ The input signal input to the input node of the carrier transistor 11 １ , 11 ２ and the carrier transistor 11 １ , 11 ２ from the output node (drain electrode) of the carrier output pad 11b １ , 11b ２ The carrier amplified output signal is input to the intra-cell output combining circuit 24 via the １ , 24 ２ Carrier input terminal 24b １ , 24b ２ is entered into

[0090] On the other hand, each Doherty amplifier cell 1 １ , 1 ２ In the peak transistor 12 １ , 12 ２ The input signal input to the input node of the peak transistor 12 １ , 12 ２ and the peak transistor 12 １ , 12 ２ output node (drain electrode) to the peak output pad 12b １ , 12b ２ The peak amplified output signal is fed to the intra-cell output combining circuit 24 via the １ , 2 4 ２ Peak input terminal 24c １ , 24c ２ is entered into

[0091] Each Doherty amplifier cell 1 １ , 1 ２ In the carrier input terminal 24b １ , 24b ２ and the carrier amplified output signal input to the peak input terminal 24c. １ , 24c ２ The peak amplified output signal input to the cell output combiner circuit 24 １ , 24 ２ and outputted as a cell output signal to the cell output terminal 24a. １ , 24a ２ will be output.

[0092] Each Doherty amplifier cell 1 １ , 1 ２ Output terminal 24a for each cell １ , 24a ２ The cell output signals output from the output terminals 201 and 202 are combined by an output combining circuit 40 and output as Doherty amplified signals from output terminals 201 and 202. Although two output terminals are shown as the output terminals 201 and 202, a single output terminal may be used as in the first embodiment.

[0093] Doherty amplifier cell 1 １ Carrier output pad 11b in １ to the intra-cell output synthesis circuit 24 １ Cell output terminal 24a １ and the electrical length of the Doherty amplifier cell 1 ２ Carrier output pad 11b in ２ to the intra-cell output synthesis circuit 24 ２ Cell output terminal 24a ２ The electrical lengths of the Doherty amplifier cells 1 and 2 are equal. １ and Doherty amplifier cell 1 ２ As described above, the electrical length from the carrier output pad 11b to the cell output terminal 24a of the intra-cell output combining circuit 24 is the same for all of the plurality of Doherty amplifier cells 1.

[0094] Doherty amplifier cell 1 １ Peak output pad 12b in １ to the intra-cell output synthesis circuit 24 １Cell output terminal 24a １ and the electrical length of the Doherty amplifier cell 1 ２ Peak output pad 12b in ２ to the intra-cell output synthesis circuit 24 ２ Cell output terminal 24a ２ The electrical lengths of the Doherty amplifier cells 1 and 2 are equal. １ and Doherty amplifier cell 1 ２ As described above, the electrical length from the peak output pad 12b to the cell output terminal 24a of the intra-cell output combining circuit 24 is equal for all of the multiple Doherty amplifier cells 1. Therefore, on the output side of the multiple Doherty amplifier cells 1, there is no difference in the paths for combining the carrier amplified output signal and the peak amplified output signal, and there is no degradation in the performance (efficiency) of the Doherty amplifier.

[0095] The Doherty amplifier according to the second embodiment includes a plurality of Doherty amplifier cells 1 １ , 1 ２ are arranged in parallel, and each Doherty amplifier cell 1 １ , 1 ２ is the carrier amplifier 11 １ , 11 ２ and peak amplifier 12 １ , 12 ２ The input signal is then input to a carrier amplifier 11. １ , 11 ２ and peak amplifier 12 １ , 12 ２ Intra-cell input distribution circuit 23 １ , 23 ２ and carrier amplifier 11 １ , 11 ２ and the carrier amplified output signal from the peak amplifier 12 １ , 12 ２ an intra-cell output combining circuit 24 that combines the peak amplified output signals from the １ , 24 ２ , the plurality of Doherty amplifier cells 1 １ , 1 ２ Between them, Doherty amplifier cell 1 １ , 1 ２There is no difference in electrical length between the input side and the output side, and the performance (efficiency) of the Doherty amplifier does not decrease, improving power efficiency.

[0096] Furthermore, the Doherty amplifier according to the second embodiment includes an intra-cell input distribution circuit 23 １ , 23 ２ is the carrier side input circuit 231 １ , 231 ２ and the peak side input circuit 232 １ , 232 ２ and a carrier side input circuit 231 １ , 231 ２ and the peak side input circuit 232 １ , 232 ２ A DC blocking capacitor 233 is used to short-circuit the AC and open the DC between the １ , 233 ２ and an input signal and a carrier transistor 11 １ , 11 ２ and the gate bias voltage Vgc for the peak transistor 12 １ , 12 ２ The gate bias voltage Vgp for the １ , 233 ２ is connected to the cell input terminal 23a １ , 23 ２ an input distribution circuit 31 that receives an input signal and a gate bias voltage Vgc and outputs the gate bias voltage Vgc to a carrier side input circuit 231; １ , 231 ２ a carrier gate bias application circuit 32 that applies the carrier gate bias voltage Vgp to the peak side input circuit 232; １ , 232 ２ The peak gate bias application circuit 33 is provided to apply a peak gate bias to the plurality of Doherty amplifier cells 1 １ , 1 ２ Carrier amplifier 11 in １ , 11 ２ and peak amplifier 12 １ , 12 ２ Independent gate bias voltages Vgc and Vgp can be applied to the gates.

[0097] The Doherty amplifier according to the second embodiment includes a plurality of Doherty amplifier cells 1 １ , 1 ２ By housing the input distribution circuit 31, carrier gate bias application circuit 32, peak gate bias application circuit 33, and output combining circuit 40 in a single package and configuring the amplifier to have two input terminals, a first input terminal 101 and a second input terminal 102, and one output terminal, an easy-to-use Doherty amplifier can be obtained.

[0098] It should be noted that the embodiments may be freely combined, any of the components of the embodiments may be modified, or any of the components of the embodiments may be omitted.

[0099] The Doherty amplifier of the present disclosure is suitable as a communications amplifier for portable wireless terminals and base station mobiles in the mobile communications infrastructure.

[0100] 1 １ , 1 ２ Doherty amplifier cell, 11 １ , 11 ２ Carrier amplifier, 12 １ , 12 ２ Peak amplifier, 13 １ , 13 ２ , 23 １ , 23 ２ Intra-cell input distribution circuit, 14 １ , 14 ２ , 24 １ , 24 ２ Intra-cell output combining circuit, 231 １ , 231 ２ Carrier side input circuit, 232 １ , 232 ２ Peak side input circuit, 233 １ , 233 ２ DC blocking capacitance, 31 input distribution circuit, 32 carrier gate bias application circuit, 33 peak gate bias application circuit, 40 output combining circuit.

Claims

1. Multiple Doherty amplifier cells are arranged in parallel, Each Doherty amplifier cell is: A carrier amplifier in which the input node is electrically connected to a carrier input pad and the output node is electrically connected to a carrier output pad, A peak amplifier in which the input node is electrically connected to a peak input pad and the output node is electrically connected to a peak output pad, An in-cell input distribution circuit has a cell input terminal into which an input signal is input, a carrier output terminal electrically connected to the carrier input pad, and a peak output terminal electrically connected to the peak input pad, and distributes the input signal input to the cell input terminal to the carrier output terminal and the peak output terminal for output. The cell comprises an in-cell output combining circuit having a carrier input terminal electrically connected to the carrier output pad, a peak input terminal electrically connected to the peak output pad, and a cell output terminal, which combines the carrier amplified output signal output to the carrier output pad and the peak amplified output signal output to the peak output pad to output a cell output signal to the cell output terminal, The cell-internal input distribution circuit comprises: a carrier-side input circuit AC-connected between the cell input terminal and the carrier output terminal and having a carrier gate bias terminal to which a gate bias voltage to the carrier amplifier is applied; a peak-side input circuit AC-connected between the cell input terminal and the peak output terminal and having a peak gate bias terminal to which a gate bias voltage to the peak amplifier is applied; and a DC blocking capacitor connected to the cell input terminal to AC-short-circuit and DC-open-circuit between the carrier-side input circuit and the peak-side input circuit. An input distribution circuit is electrically connected to a first input terminal to which the input signal and the gate bias voltage for the carrier amplifier are input, and to a second input terminal to which the input signal and the gate bias voltage for the peak amplifier are input, and is electrically connected to the cell input terminal in each of the plurality of Doherty amplifier cells, and distributes and outputs the input signals input to the first input terminal and the second input terminal to the cell input terminal in each of the plurality of Doherty amplifier cells, A carrier gate bias application circuit is electrically connected to the first input terminal and the carrier-side input circuit of the cell-internal input distribution circuit in each of the plurality of Doherty amplifier cells, and applies the gate bias voltage applied to the carrier amplifier applied to the first input terminal to the carrier-side input circuit of the cell-internal input distribution circuit in each of the plurality of Doherty amplifier cells, A peak gate bias application circuit is electrically connected to the second input terminal and the peak-side input circuit of the cell-internal input distribution circuit in each of the plurality of Doherty amplifier cells, and applies the gate bias voltage applied to the second input terminal for the peak amplifier to the peak-side input circuit of the cell-internal input distribution circuit in each of the plurality of Doherty amplifier cells. Doherty amplifier equipped with

2. The cell-internal input distribution circuit has the functions of a matching circuit and a phase adjustment line, and the function of distributing and outputting the input signal input to the cell input terminal to the carrier input pad and the peak input pad. The cell output combining circuit has the functions of a matching circuit and a phase adjustment line, and the function of combining the carrier amplified output signal output to the carrier output pad and the peak amplified output signal output to the peak output pad to output a cell output signal to the cell output terminal. The Doherty amplifier according to claim 1.

3. The aforementioned gate bias application circuit for the carrier is a capacitance. The aforementioned peak gate bias application circuit is a capacitance. The Doherty amplifier according to claim 1.

4. The aforementioned gate bias application circuit for the carrier is a capacitance. The aforementioned peak gate bias application circuit is a capacitance. The Doherty amplifier according to claim 2.

5. The Doherty amplifier according to any one of claims 1 to 4, wherein in each Doherty amplifier cell, the carrier amplifier, the peak amplifier, the in-cell input distribution circuit, and the in-cell output combining circuit are configured on the same chip.

6. A Doherty amplifier according to any one of claims 1 to 4, wherein the plurality of Doherty amplifier cells, the input distribution circuit, the carrier gate bias application circuit, and the peak gate bias application circuit are housed in a package having the first input terminal, the second input terminal, and the output terminal.

7. The Doherty amplifier according to any one of claims 1 to 4, wherein the plurality of Doherty amplifier cells are housed in a single package and have input terminals and output terminals.

8. The Doherty amplifier according to claim 5, wherein the plurality of Doherty amplifier cells are housed in a single package and have input terminals and output terminals.

9. The Doherty amplifier according to claim 6, wherein the plurality of Doherty amplifier cells are housed in a single package and have input terminals and output terminals.