Semiconductor device and method for manufacturing the same

Abstract

The bonding layer (15) is disposed directly on the diamond substrate (16) and is made of an amorphous material. The silicon crystal layer (11) is bonded to the diamond substrate (16) at least via the bonding layer (15). The buffer layer (12) is made of a nitride containing aluminum atoms and is disposed on the bonding layer (15) at least via the silicon crystal layer (11). The nitride semiconductor layer (13) is disposed directly on the buffer layer (12) and has a composition different from that of the buffer layer (12).

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device having a semiconductor layer made of a nitride and a method for manufacturing the same. [Background technology]

[0002] According to JP 2019-036566 A (Patent Document 1), in order to improve the heat dissipation of a semiconductor device, it is effective to use diamond as a heat spreader or heat sink, because diamond has a high thermal conductivity. In addition, a method of bonding a semiconductor substrate of a semiconductor device to diamond by a surface activated bonding method is mentioned. During bonding, diamond does not deform because the rigidity of diamond is extremely high, and many voids are likely to occur between the semiconductor substrate and diamond. In particular, many voids are likely to occur when a SiC substrate is used as the semiconductor substrate. These voids cause a decrease in heat dissipation.

[0003] Taking this problem into consideration, the semiconductor device according to the invention described in the above publication includes a semiconductor chip including a substrate and an element region on the substrate, a diamond heat conductor, and a metal layer between the semiconductor chip and the heat conductor, and the substrate has an amorphous region on the back surface. The amorphous region and the metal layer are bonded to each other. The metal layer and the heat conductor are bonded to each other. The element region may include a high electron mobility transistor (HEMT). According to what is asserted in the above publication, the semiconductor device can obtain excellent heat dissipation by including a substrate including an amorphous region, a heat conductor, and a metal layer.

[0004] According to the manufacturing method of the semiconductor device described in the above publication, first, a semiconductor chip and a structure having a heat conductor are prepared separately. In the method of preparing the semiconductor chip, the back surface of the semiconductor chip having an element region formed on the front surface of a substrate is polished. This makes the substrate thinner. On the other hand, in the method of preparing the structure having a heat conductor, the front surface of the diamond heat conductor is polished. A metal layer is formed on this front surface. Next, a rare gas beam is irradiated to the back surface of the semiconductor chip and the front surface of the metal layer. As a result, an amorphous region is formed on the back surface of the semiconductor chip. In addition, the back surface of the semiconductor chip and the front surface of the metal layer are activated. Next, the back surface of the semiconductor chip and the front surface of the metal layer are bonded to each other by being in close contact with each other.

[0005] International Publication No. 2023 / 048160 (Patent Document 2) discloses a semiconductor device including a HEMT. In the semiconductor device, a bonding layer, a SiC layer, and a nitride semiconductor layer are stacked in this order on the main surface of a diamond substrate. A source electrode, a drain electrode, and a gate electrode are formed at intervals on the main surface of the nitride semiconductor layer.

[0006] In the manufacturing method of the semiconductor device described in the above International Publication, the following steps may be performed. First, a SiC layer and a nitride semiconductor layer are formed in order on a Si substrate. Next, a HEMT is formed on the nitride semiconductor layer. Next, the entire Si substrate is removed by etching. A diamond substrate is bonded to the SiC layer thus exposed. According to the above International Publication, it is preferable to use a surface activated bonding method for the bonding. In this case, first, in a reduced pressure and room temperature atmosphere, the diamond substrate and the SiC layer are irradiated with energy particles (e.g., Ar particles) to remove adsorbed substances from the diamond substrate and the SiC layer. By irradiating the energy particles, an amorphous layer mainly composed of C appears on the diamond substrate, and an amorphous layer mainly composed of C and Si appears on the SiC layer. By bringing the pair of amorphous layers into contact with each other, the diamond substrate and the SiC layer are bonded via a bonding layer including the pair of amorphous layers. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] JP 2019-036566 A [Patent Document 2] International Publication No. 2023 / 048160 Summary of the Invention [Problem to be solved by the invention]

[0008] In the semiconductor device according to the invention described in the above-mentioned JP2019-036566A, a metal layer is provided between the semiconductor chip and the heat conductor. This metal layer increases the parasitic capacitance in the semiconductor device. In addition, in the manufacturing method according to the invention, the back surface of the semiconductor chip is polished. As a result, the back surface of the portion of the semiconductor device related to the operation of the HEMT, i.e., the back surface of the nitride semiconductor layer, is likely to be damaged due to polishing. This damage to the back surface may increase the current collapse of the HEMT. In this way, the performance of the semiconductor device may be reduced due to damage to the back surface of the nitride semiconductor layer.

[0009] According to the above-mentioned WO 2023 / 048160, a nitride semiconductor layer is formed by homoepitaxial growth on a SiC layer provided directly on a Si substrate. On the other hand, unlike the invention described in the WO 2023 / 048160, a silicon crystal layer may be more desirable than a SiC layer as an underlayer for homoepitaxial growth. For example, when a high in-plane uniformity of the thickness of the underlayer is required, a silicon crystal layer is more likely to meet such a requirement than a SiC layer. Specifically, by using a silicon on insulator (SOI) substrate having a structure in which an insulating layer and a silicon crystal layer as an underlayer are stacked in order on a Si substrate, a silicon crystal layer suitable for the underlayer can be easily prepared. In addition, when a semiconductor device is manufactured using the above-mentioned SOI substrate, it is also easy to remove the Si substrate that is finally unnecessary. In contrast, according to the above-mentioned WO 2023 / 048160, when the entire Si substrate is removed by etching, the surface where the etching is stopped is made of a SiC layer, so it may be difficult to stop the etching precisely at the desired position. As a result, the rear surface of the nitride semiconductor layer is damaged, which may cause a decrease in the performance of the semiconductor device.

[0010] The present disclosure has been made to solve the above-mentioned problems, and has an object to provide a semiconductor device and a method for manufacturing a semiconductor device that can suppress degradation of the performance of the semiconductor device caused by damage to the back surface of a nitride semiconductor layer. [Means for solving the problem]

[0011] The semiconductor device according to the present disclosure comprises a diamond substrate, a bonding layer made of an amorphous material and disposed directly on the diamond substrate, a silicon crystal layer bonded to the diamond substrate at least via the bonding layer, a buffer layer made of a nitride containing aluminum atoms and disposed on the bonding layer at least via the silicon crystal layer, and a nitride semiconductor layer disposed directly on the buffer layer and having a composition different from that of the buffer layer.

[0012] A method for manufacturing a semiconductor device according to the present disclosure includes the steps of: a) directly or indirectly forming a buffer layer made of a nitride containing aluminum atoms on a silicon crystal layer, the silicon crystal layer being disposed directly on an oxide layer, the oxide layer being disposed on a support substrate; b) forming a nitride semiconductor layer having a composition different from that of the buffer layer on the buffer layer; c) forming a semiconductor element structure on the nitride semiconductor layer; d) providing a protective substrate on the semiconductor element structure via an adhesive layer; e) removing the support substrate after d); and f) bonding the silicon crystal layer and a polished surface of a diamond substrate to each other via at least a bonding layer after e), the bonding layer being disposed directly on the polished surface of the diamond substrate and on the silicon crystal layer directly or via the oxide layer; and g) removing the bonding layer and the protective substrate. Effect of the Invention

[0013] According to the semiconductor device of the present disclosure, in the semiconductor device, the buffer layer is disposed on the bonding layer via at least a silicon crystal layer. Therefore, in the manufacturing of the semiconductor device, the silicon crystal layer can continue to protect the buffer layer until the structure including the nitride semiconductor layer is bonded to the diamond substrate using the bonding layer. This allows the buffer layer to continue to protect the back surface of the nitride semiconductor layer from damage caused by any manufacturing process. Therefore, it is possible to suppress the deterioration of the performance of the semiconductor device caused by damage to the back surface of the nitride semiconductor layer.

[0014] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings. [Brief description of the drawings]

[0015] [Figure 1] 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to a first embodiment. [Diagram 2]FIG. 2 is a top view illustrating a schematic configuration of the semiconductor device of FIG. [Diagram 3] 2 is a flow chart illustrating a method for manufacturing the semiconductor device according to FIG. 1. [Figure 4] 2 is a cross-sectional view illustrating a schematic first step in a method for manufacturing the semiconductor device according to FIG. [Diagram 5] 2 is a top view illustrating a first step in the method for manufacturing the semiconductor device according to FIG. 1. [Figure 6] 1. FIG. 4 is a cross-sectional view illustrating a second step in the method for manufacturing the semiconductor device according to FIG. [Figure 7] 1. FIG. 4 is a cross-sectional view illustrating a third step in the method for manufacturing the semiconductor device according to FIG. [Figure 8] 1. FIG. 4 is a cross-sectional view illustrating a fourth step in the method for manufacturing the semiconductor device according to FIG. [Figure 9] 1. FIG. 4 is a cross-sectional view illustrating a fifth step in the method for manufacturing the semiconductor device according to FIG. [Figure 10] 1. FIG. 4 is a cross-sectional view illustrating a sixth step in the method for manufacturing the semiconductor device according to FIG. [Figure 11] 1. FIG. 4 is a cross-sectional view illustrating a seventh step in the method for manufacturing the semiconductor device according to FIG. [Figure 12] 1. FIG. 4 is a cross-sectional view illustrating an eighth step in the method for manufacturing the semiconductor device according to FIG. [Figure 13] 1. FIG. 4 is a cross-sectional view illustrating a ninth step in the method for manufacturing the semiconductor device according to FIG. [Figure 14] 1. FIG. 4 is a cross-sectional view illustrating a schematic diagram of a tenth step in the method for manufacturing the semiconductor device according to FIG. [Figure 15] 1 is a graph diagram illustrating a relationship between a drain voltage Vds and a drain current Ids in a semiconductor device. [Figure 16] 1 is a graph showing a relationship between applied power P and a temperature rise ΔT in a current-carrying region in a semiconductor device. [Figure 17] 1 is a graph showing a relationship between a thickness of a silicon crystal layer and a rate of temperature rise Rth in a semiconductor device. [Figure 18] FIG. 11 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to a second embodiment. [Figure 19] FIG. 11 is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to a third embodiment. [Figure 20] 20 is a flow chart illustrating a manufacturing method of the semiconductor device according to FIG. 19. [Figure 21] 20 is a cross-sectional view illustrating a schematic process of a method for manufacturing the semiconductor device according to FIG. 19. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and the description thereof will not be repeated. In addition, the size of each member in the drawings may differ from the actual size in order to make the drawings easier to see.

[0017] <Embodiment 1> 1 and 2 are a cross-sectional view and a top view, respectively, that illustrate a schematic configuration of a semiconductor device 100 according to the first embodiment. In the top view of Fig. 2, a dot pattern is applied to the surface electrodes 14 in order to make them easily distinguishable.

[0018] The semiconductor device 100 has a diamond substrate 16, a bonding layer 15, a silicon crystal layer 11, a buffer layer 12, and a nitride semiconductor layer 13. The diamond substrate 16, the bonding layer 15, the silicon crystal layer 11, the buffer layer 12, and the nitride semiconductor layer 13 may be stacked in this order as shown in FIG. 1. A semiconductor element structure ES is provided on the main surface FM1 of the nitride semiconductor layer 13. The semiconductor element structure ES may include a surface electrode 14. In the first embodiment, the semiconductor element structure ES is a HEMT structure, and the surface electrode 14 includes a plurality of electrode portions, namely, a gate electrode portion 14a, a source electrode portion 14b, and a drain electrode portion 14c. The semiconductor element structure ES may have an insulating film in addition to the surface electrode 14. The semiconductor element structure ES may also have a protective film that protects its surface. The material of the insulating film is, for example, SiN, Al2O3, or SiO2. The material of the protective film is, for example, polyimide.

[0019] The diamond substrate 16 is made of a single crystal diamond, a mosaic diamond, or a polycrystalline diamond. The mosaic diamond is composed of a plurality of single crystal diamonds bonded together in the in-plane direction (the lateral direction in FIG. 1). The diamond substrate 16 may have a thickness of 50 μm or more and 600 μm or less.

[0020] The bonding layer 15 is disposed directly on the diamond substrate 16 and is made of an amorphous material. The material of the bonding layer 15 may be a single layer material or a laminated material. The bonding layer 15 may include an amorphous carbon layer disposed directly on the diamond substrate 16. The amorphous carbon layer may have a thickness of 1 nm or less. The bonding layer 15 may include a silicon-containing layer. The silicon-containing layer may be laminated on the amorphous carbon layer. The silicon-containing layer is a layer containing silicon atoms. The silicon-containing layer may further contain carbon atoms and / or oxygen atoms. Thus, the material of the silicon-containing layer may be, for example, Si, SiO X (X>0), SiC, or SiC X O Y (X>0, Y>0).

[0021] The thickness of the bonding layer 15 is preferably 1 nm or more and 10 nm or less, more preferably 1 nm or more and 5 nm or less. The bonding layer 15 has a first interface IF1 in contact with the diamond substrate 16 and a second interface IF2 opposite to the first interface IF1. In the first embodiment, the second interface IF2 is an interface between the bonding layer 15 and the silicon crystal layer 11. The first interface IF1 may have an arithmetic mean roughness of 0.5 nm or less. In other words, the upper surface of the diamond substrate 16 in FIG. 1 (corresponding to the main surface FM3 in FIG. 12) may have an arithmetic mean roughness of 0.5 nm or less. The second interface IF2 may have an arithmetic mean roughness of 0.5 nm or less. In other words, the back surface FB2 of the silicon crystal layer 11 may have an arithmetic mean roughness of 0.5 nm or less.

[0022] The silicon crystal layer 11 is bonded to the diamond substrate 16 via at least a bonding layer 15. In the first embodiment, the silicon crystal layer 11 is directly bonded to the bonding layer 15. The silicon crystal layer 11 may be a single crystal Si layer. The silicon crystal layer 11 serves as a base layer for successively growing the buffer layer 12 and the nitride semiconductor layer 13, in other words, a growth substrate. The thickness of the silicon crystal layer 11 is preferably 0.5 μm or more and 20.0 μm or less, and more preferably 0.5 μm or more and 5.0 μm or less. The silicon crystal layer 11 may have a resistivity of 5000 Ω·cm or less.

[0023] The buffer layer 12 is disposed on the bonding layer 15 via at least the silicon crystal layer 11. In the first embodiment, the buffer layer 12 is disposed directly on the silicon crystal layer 11. The thickness of the buffer layer 12 is preferably 2 μm or less. The buffer layer 12 is made of a nitride containing aluminum atoms. The nitride may also contain gallium atoms. The material of the buffer layer 12 may be a single-layer material or a laminated material in which a plurality of materials with different compositions are applied. Specifically, the material of the buffer layer 12 is, for example, AlGaN or AlN. The component ratio of Al atoms in the composition of the buffer layer 12 may be different from the component ratio of Al atoms in the composition of the nitride semiconductor layer 13.

[0024] The nitride semiconductor layer 13 is disposed directly on the buffer layer 12. The thickness of the nitride semiconductor layer 13 is preferably 10 μm or less, taking into consideration the effect on heat dissipation performance. The nitride semiconductor layer 13 has a composition different from that of the buffer layer 12. The material of the nitride semiconductor layer 13 may contain aluminum atoms, but does not necessarily have to contain them. The material of the nitride semiconductor layer 13 may be a single layer material or a multilayer material. The single layer material may be SiN, GaN, AlGaN, InAlN, or AlN, and may be doped with impurities such as Fe and / or C. The multilayer material may be two or more of the above-mentioned materials.

[0025] The material of the surface electrode 14 may be a single metal element or an alloy. The single metal element may be one element selected from the group consisting of Cu, Ti, Al, Au, Ni, Nb, Pd, Pt, Cr, W, Ta, and Mo. The alloy may be AlSi, AlCu, AuGe, AuGa, or AuSn. The material of the surface electrode 14 may be a laminate using two or more materials among the above-mentioned materials. When the surface electrode 14 includes multiple electrode parts, the materials of the multiple electrode parts may be the same or different.

[0026] Fig. 3 is a flow diagram that generally shows a manufacturing method MM1 of the semiconductor device 100 (Fig. 1). Figs. 4 and 5 are a cross-sectional view and a top view, respectively, that generally show a first step in the manufacturing method of the semiconductor device 100. Figs. 6 to 14 are cross-sectional views that generally show second to tenth steps in the manufacturing method of the semiconductor device 100, respectively.

[0027] 4 and 5, first, an SOI substrate 10 is formed. The SOI substrate 10 is composed of a silicon crystal layer 11, an oxide layer 19, and a support substrate 20. The oxide layer 19 is disposed on the support substrate 20. The silicon crystal layer 11 is disposed directly on the oxide layer 19. In the SOI substrate 10, the thickness of the support substrate 20 is preferably 500 μm or more and 700 μm or less. The thickness of the oxide layer 19 is preferably 0.1 μm or more and 2.0 μm or less. The support substrate 20 is typically a Si substrate.

[0028] In the SOI substrate 10, the silicon crystal layer 11 preferably has an in-plane uniformity within 10%. Preferably, such in-plane uniformity is satisfied in an SOI substrate 10 (wafer) having a diameter of about 50 millimeters (2 inches) or more. The in-plane uniformity of the silicon crystal layer 11 may be calculated based on the thickness at, for example, nine measurement points PM (FIG. 5) shown in FIG. 5. One of the measurement points may be approximately the center point of the wafer. The other eight measurement points may be selected at approximately equiangular intervals (in other words, at intervals of about 45°) on the boundary between the ineffective region at the outer edge of the wafer and the effective region inside it. The maximum, minimum and average thickness values ​​at these measurement points are used to calculate the following equation: In-plane uniformity (%) = (maximum value - minimum value) / (average value x 2) x 100 The in-plane uniformity may be calculated by the following equation.

[0029] To obtain the SOI substrate 10, for example, the silicon crystal layer 11 is bonded to the support substrate 20 via the oxide layer 19, and then the silicon crystal layer 11 is given a desired thickness and in-plane uniformity by grinding and polishing. The silicon crystal layer 11 may be deposited on the oxide layer 19 instead of being bonded thereto, and at that time, a dopant such as boron or phosphorus may be added to adjust the resistivity. Alternatively, a technique called SIMOX (separation by implanted oxygen) method may be used. That is, the silicon crystal layer 11 and the oxide layer 19 may be formed on the surface of the support substrate 20 by implanting a high concentration of oxygen ions into the inside of a single crystal silicon substrate and then performing a heat treatment at a high temperature. In the following description of the manufacturing method, a case in which the support substrate 20 is a single crystal Si substrate and the oxide layer is a silicon oxide film will be exemplified.

[0030] 6, in step ST10 (FIG. 3), a buffer layer 12 made of nitride is formed directly or indirectly on a silicon crystal layer 11 of an SOI substrate 10. In the first embodiment, the buffer layer 12 is formed directly on the silicon crystal layer 11. Next, in step ST20 (FIG. 3), a nitride semiconductor layer 13 having a composition different from that of the buffer layer 12 is formed on the buffer layer 12. These are formed by, for example, a metal organic chemical vapor deposition (MOCVD) method or the like. Next, in step ST30 (FIG. 3), a semiconductor element structure ES is formed on a main surface FM1 of the nitride semiconductor layer 13.

[0031] 8, in step ST40 (FIG. 3), a protective substrate 18 is provided on the main surface FM1 (FIG. 7) on which the semiconductor element structure ES is provided, via an adhesive layer 17. The adhesive layer 17 may be made of an adhesive material containing a resin. The protective substrate 18 is provided temporarily to protect the semiconductor element structure ES. The thickness of the protective substrate 18 is, for example, 500 μm or more. The material of the protective substrate 18 is preferably one having high strength, and is preferably transparent when light irradiation is used to harden the adhesive layer 17. The material of the protective substrate 18 is, for example, sapphire, quartz, or SiC.

[0032] Next, in step ST50 (FIG. 3), the support substrate 20 (FIG. 8) is removed as shown in FIG. 9. This removal process is performed so as to proceed from the main surface FM4 (FIG. 8) of the support substrate 20 and stop on the oxide layer 19. This exposes the main surface FM5 of the oxide layer 19. This removal process may be performed by grinding, dry etching, or wet etching. It is easy to ensure a sufficient etching selectivity of the support substrate 20 such as a single crystal Si substrate to the oxide layer 19 such as a silicon oxide film. Therefore, it is easy to remove the support substrate 20 by etching without sacrificing the oxide layer 19 significantly. For wet etching, an alkaline solution such as KOH, NaOH, or ammonia is used.

[0033] Next, in the present embodiment 1, in step ST61 (FIG. 3), wet etching is performed with a higher etching rate for the material of the oxide layer 19 than for the material of the silicon crystal layer 11. As a result, the oxide layer 19 (FIG. 9) is removed as shown in FIG. 10 while leaving the silicon crystal layer 11. As a result, the back surface FB2 of the silicon crystal layer 11 is exposed. It is very easy to ensure the etching selectivity of the silicon crystal layer 11 with respect to the oxide layer 19 such as a silicon oxide film. Therefore, it is sufficiently easy to remove the oxide layer 19 by etching without sacrificing the silicon crystal layer 11. It is preferable to use hydrofluoric acid or buffered hydrofluoric acid for this wet etching. Since the selectivity is very easy to ensure as described above, the surface roughness of the back surface FB2 of the silicon crystal layer 11 after the oxide layer 19 is removed corresponds approximately to the surface roughness of the back surface FB2 of the silicon crystal layer 11 before the oxide layer 19 is removed (FIG. 4). It is preferable that these surface roughnesses have an arithmetic mean roughness of 0.5 nm or less.

[0034] Next, an activation process may be performed on the back surface FB2 of the silicon crystal layer 11. Specifically, an ion beam of a rare gas element (e.g., He, Ar, Xe, or Ne) is irradiated onto the back surface FB2. This removes impurities and deposits on the back surface FB2 and exposes dangling bonds on the irradiated surface.

[0035] Meanwhile, referring to Fig. 11, a diamond substrate 16 having a main surface FM3 is prepared. The diamond substrate 16 is preferably fabricated by a chemical vapor deposition (CVD) method. Further referring to Fig. 12, the main surface FM3 of the diamond substrate 16 is polished. This polishing is preferably performed so that the main surface FM3 has an arithmetic mean roughness of 0.5 nm or less.

[0036] Further referring to FIG. 13, the bonding layer 15 is formed on the main surface FM3 (FIG. 12) of the diamond substrate 16. Therefore, the bonding layer 15 is disposed directly on the main surface FM3 (FIG. 12) of the diamond substrate 16, that is, on the polished surface of the diamond substrate 16. Preferably, the main surface FM3 (FIG. 12) of the diamond substrate 16 is first activated. Specifically, the main surface FM3 of the diamond substrate 16 is irradiated with an ion beam of a rare gas element (e.g., He, Ar, Xe, or Ne). As a result, impurities and deposits on the main surface FM3 are removed, and dangling bonds are exposed on the irradiated surface. At the same time, the vicinity of the main surface FM3 of the diamond substrate 16 is amorphized, so that an amorphous carbon layer is formed on the diamond substrate 16 as at least a part of the bonding layer 15. Next, the bonding layer 15 may be further formed by deposition on the amorphous carbon layer. This deposition is performed by a sputtering method using, for example, Si, SiO2, or SiC as a target material.

[0037] 14, in step ST71 (FIG. 3), the silicon crystal layer 11 and the main surface FM3 (FIG. 12), which is the polished surface of the diamond substrate 16, are bonded to each other through at least the bonding layer 15. In the present embodiment 1, the bonding layer 15 is disposed directly on the silicon crystal layer 11. As a result, the structure including the diamond substrate 16 (FIG. 13) and the structure including the silicon crystal layer 11 (FIG. 10) are bonded to each other through the bonding layer 15. This bonding is preferably performed by room temperature pressure bonding. In the case of room temperature pressure bonding, it is preferable that the bonded surfaces have atomic level smoothness. Specifically, it is preferable that the arithmetic mean roughness of the bonded surfaces is 0.5 nm or less. In addition, in room temperature pressure bonding, there is generally a concern that partial peeling may occur, and the bonding layer 15 has a function to prevent this. In addition, in room temperature pressure bonding, since heating for bonding is not required, it is possible to avoid the occurrence of warping due to thermal stress.

[0038] Next, in step ST80 (FIG. 3), the adhesive layer 17 and the protective substrate 18 are removed (FIG. 1). Specifically, the adhesive layer 17 is peeled off, and the adhesive layer 17 and the protective substrate 18 are separated from the portion that will become the semiconductor device 100 (FIG. 1). In this way, the semiconductor device 100 is obtained.

[0039] FIG. 15 is a graph diagram showing a schematic relationship between the drain voltage Vds and the drain current Ids in the semiconductor device 100 having a HEMT structure. In the figure, the solid line shows the characteristics when no pulse is applied, and the dashed line shows the characteristics when a pulse is applied. The amount of decrease in the drain current Ids (see the arrow in the figure) is related to the current collapse caused by carrier traps on the back surface of the nitride semiconductor layer 13, in other words, back surface collapse. According to the first embodiment, the silicon crystal layer 11 is left until the semiconductor device 100 is completed, and this ensures that the back surface of the nitride semiconductor layer 13 is protected. Therefore, the back surface collapse is suppressed. This makes it possible to suppress the decrease in the drain current Ids. On the other hand, since the silicon crystal layer 11 is located between the semiconductor element structure ES and the diamond substrate 16, the heat dissipation characteristics are sacrificed to some extent.

[0040] FIG. 16 is a graph diagram showing the relationship between the applied power P (=Ids×Vds) in the semiconductor device and the temperature rise ΔT of the current-carrying region. In the figure, the dashed line corresponds to a device in which the diamond substrate 16 is omitted from the semiconductor device 100 (FIG. 1). In this device, the heat dissipation promotion by the diamond substrate 16 is not obtained, so the temperature rise ΔT is very large. On the other hand, the lower of the two solid lines in the figure corresponds to a device in which the silicon crystal layer 11 is omitted from the semiconductor device 100 (FIG. 1). In this device, the heat dissipation promotion by the diamond substrate 16 is obtained without being hindered by the silicon crystal layer 11, so the temperature rise ΔT is significantly suppressed. In the figure, the upper of the two solid lines corresponds to a semiconductor device having both the diamond substrate 16 and the silicon crystal layer 11. In this device, the larger the thickness of the silicon crystal layer 11, the larger the temperature rise ΔT. That is, the heat dissipation characteristics are deteriorated. However, since the heat dissipation promotion effect by the diamond substrate 16 is very large, the heat dissipation promotion effect can be fully enjoyed as long as the thickness of the silicon crystal layer 11 is not excessive. In addition, since the bonding layer 15 is very thin and has little effect on heat dissipation, reference to the bonding layer 15 is omitted in the above description.

[0041] FIG. 17 is a graph diagram that shows a schematic relationship between the thickness of the silicon crystal layer 11 of the semiconductor device 100 and the temperature rise rate Rth per 1 W / mm in the semiconductor device 100. As shown in this figure, if the thickness of the silicon crystal layer 11 is 20.0 μm or less, it is possible to avoid excessive sacrifice of heat dissipation characteristics due to the provision of the silicon crystal layer 11. On the other hand, in order to fully obtain the effect of suppressing current collapse by the silicon crystal layer 11, it is preferable that the thickness is 0.5 μm or more. Therefore, in order to fully obtain the effect of suppressing current collapse by the silicon crystal layer 11 while fully suppressing the influence of deterioration of heat dissipation characteristics by the silicon crystal layer 11, it is preferable that the thickness is 0.5 μm or more and 20.0 μm or less.

[0042] If the silicon crystal layer 11 is removed by etching and / or grinding the bottom of the structure shown in FIG. 10 and the removal process can be stopped at the timing when the back surface made of the buffer layer 12 is exposed, and the diamond substrate 16 is bonded to the back surface via the bonding layer 15, a semiconductor device without the silicon crystal layer 11 can be obtained. In this semiconductor device, the silicon crystal layer 11 is prevented from impeding heat dissipation. However, since the buffer layer 12 is usually very thin, it is very difficult to control the removal process to stop at the timing when the buffer layer 12 is exposed, and especially in mass production, the buffer layer 12 is easily lost and the back surface of the silicon crystal layer 11 is easily exposed. In order to bond the diamond substrate 16 to this back surface with sufficient strength via the bonding layer 15, the back surface needs to have high smoothness. To obtain such a back surface, a process such as polishing or dry etching is usually required. Such a process directly physically damages the back surface of the nitride semiconductor layer 13, and as a result, the back surface collapse worsens. Furthermore, even if the buffer layer 12 is lost and the back surface of the nitride semiconductor layer 13 is exposed, this can lead to an increase in back surface collapse.

[0043] According to the first embodiment, referring to FIG. 1, the buffer layer 12 is disposed on the bonding layer 15 via at least the silicon crystal layer 11. Therefore, in the manufacturing of the semiconductor device 100, the silicon crystal layer 11 can continue to protect the buffer layer 12 until the configuration shown in FIG. 14 is obtained in step ST71 (FIG. 3), in other words, until the structure including the nitride semiconductor layer 13 is bonded to the diamond substrate 16 using the bonding layer 15. This allows the buffer layer 12 to continue to protect the back surface of the nitride semiconductor layer 13 from damage caused by any manufacturing process. Specifically, the back surface of the nitride semiconductor layer 13 can continue to be protected from damage caused by a polishing process for smoothing or an ion beam irradiation process for activation. Therefore, it is possible to suppress the deterioration of the performance of the semiconductor device 100 caused by damage to the back surface of the nitride semiconductor layer 13.

[0044] The bonding layer 15 is made of an amorphous material. This alleviates the decrease in bonding strength caused by lattice mismatch at the bonding interface. From this perspective, it is particularly preferable that the bonding layer 15 includes an amorphous carbon layer that is in direct contact with the diamond substrate 16.

[0045] In the present embodiment 1, the silicon crystal layer 11 is directly bonded to the bonding layer 15. This makes it possible to avoid a decrease in heat dissipation caused by a certain member disposed between the silicon crystal layer 11 and the bonding layer 15.

[0046] By making the thickness of the silicon crystal layer 11 0.5 μm or more, the buffer layer 12 can be more reliably protected in the manufacture of the semiconductor device 100. Therefore, the deterioration of the performance of the semiconductor device 100, specifically, current collapse, caused by damage to the back surface of the nitride semiconductor layer 13 can be more reliably suppressed. By making the thickness of the silicon crystal layer 11 20.0 μm or less, preferably 5.0 μm or less, it is possible to prevent the silicon crystal layer 11 from having an excessively adverse effect on the heat dissipation from the nitride semiconductor layer 13 to the diamond substrate 16.

[0047] Furthermore, by making the silicon crystal layer 11 20.0 μm or less, the rigidity of the silicon crystal layer 11 can be suppressed. As a result, even if the diamond substrate 16 has a slight warp, the silicon crystal layer 11 can be easily bonded along the warp. This bonding process is usually performed by bonding the SOI substrate 10, including the portion that will become the silicon crystal layer 11 of the semiconductor device 100, to the diamond substrate 16. It is preferable that the in-plane uniformity of the thickness of the silicon crystal layer 11 in the SOI substrate 10 is within 10%.

[0048] In the present embodiment 1, the buffer layer 12 is disposed directly on the silicon crystal layer 11. This makes it possible to avoid a decrease in heat dissipation caused by any member disposed between the buffer layer 12 and the silicon crystal layer 11.

[0049] The silicon crystal layer 11 may have a resistivity of 5000 Ω·cm or less. In this case, the occurrence of current collapse in the silicon crystal layer 11 can be suppressed.

[0050] The bonding layer 15 may include an amorphous carbon layer disposed directly on the diamond substrate 16. The amorphous carbon layer may be formed incidental to activating the surface of the diamond substrate 16.

[0051] The bonding layer 15 may include a silicon-containing layer. The silicon-containing layer may be, for example, a Si layer and a SiO2 layer formed by a sputtering method using Si or SiO2, or a laminate thereof. The silicon-containing layer does not need to be a semiconductor layer to which a dopant is added, and therefore can have a high resistivity. This can suppress the leakage current of the semiconductor device 100.

[0052] By making the thickness of the bonding layer 15 1 nm or more, it is easy to ensure sufficient bonding strength by the bonding layer 15. By making the thickness of the bonding layer 15 10 nm or less, it is possible to prevent the bonding layer 15 from having an excessively adverse effect on the heat dissipation from the nitride semiconductor layer 13 to the diamond substrate 16.

[0053] The diamond substrate 16 is made of single crystal diamond, mosaic diamond, or polycrystalline diamond. Although single crystal diamond, mosaic diamond, and polycrystalline diamond have different crystal grain boundary configurations, they all have high thermal conductivity. Therefore, all of these are suitable materials for the diamond substrate 16. In particular, the thermal conductivity of single crystal diamond and mosaic diamond is the highest among natural solids.

[0054] The diamond substrate 16 may have a thickness of 50 μm or more and 600 μm or less. This thickness range is suitable for obtaining high heat dissipation by the diamond substrate 16.

[0055] The arithmetic mean roughness of each of the first interface IF1 and the second interface IF2 of the bonding layer 15 may be 0.5 nm or less. By using such an atomically smooth surface, voids or defects are unlikely to occur at the first interface IF1 and the second interface IF2. This makes it possible to make bonding defects of the bonding layer 15 less likely to occur.

[0056] The process from FIG. 9 to FIG. 10, that is, the process of removing the oxide layer 19 while leaving the silicon crystal layer 11, is performed by a wet etching method. This can suppress the occurrence of damage compared to physical methods such as polishing. In addition, the wet etching that removes the oxide layer 19 while leaving the silicon crystal layer 11 can be performed with a high selectivity. As a result, the surface roughness of the interface between the silicon crystal layer 11 and the oxide layer 19 becomes the surface roughness of the interface between the silicon crystal layer 11 and the adhesive layer 17 almost as it is. Therefore, if the former is made sufficiently small, the latter can be made sufficiently small. In this case, it is not necessary to perform a smoothing process such as polishing after the wet etching.

[0057] Furthermore, when the SOI substrate 10 (FIG. 4) is used, the in-plane thickness uniformity of the silicon crystal layer 11 included therein can be easily set to within 10%. In the semiconductor device 100 obtained using the SOI substrate 10 having such high in-plane uniformity, the variation in the effect of the silicon crystal layer 11 on the heat dissipation characteristics can be sufficiently suppressed.

[0058] <Embodiment 2> 18 is a cross-sectional view that illustrates a schematic configuration of a semiconductor device 101 according to a second embodiment. The semiconductor device 101 is different from the semiconductor device 100 (FIG. 1: first embodiment) in that the semiconductor device 101 has a silicon compound layer 21 between the silicon crystal layer 11 and the buffer layer 12. Thus, in the second embodiment, the buffer layer 12 is indirectly disposed on the silicon crystal layer 11 via the silicon compound layer 21. The silicon compound layer 21 may be any one of a silicon carbide layer, a silicon oxide layer, and a silicon nitride layer. The silicon compound layer 21 may also be a layer formed by stacking two or more of these layers.

[0059] Since the configuration other than the above is substantially the same as that of the first embodiment, the same or corresponding elements are given the same reference numerals and the description thereof will not be repeated.

[0060] According to the second embodiment, the crystal growth of the buffer layer 12 and the nitride semiconductor layer 13 can be performed on the silicon compound layer 21. By selecting the silicon compound layer 21 suitable for the crystal growth of the buffer layer 12, it is possible to further reduce lattice defects during the crystal growth.

[0061] <Embodiment 3> FIG. 19 is a cross-sectional view that shows a schematic configuration of a semiconductor device 102 according to a third embodiment. The semiconductor device 102 differs from the semiconductor device 100 (FIG. 1: first embodiment) in that the semiconductor device 102 has an oxide layer 19. The oxide layer 19 is disposed between the silicon crystal layer 11 and the bonding layer 15. The oxide layer 19 is in direct contact with the silicon crystal layer 11 and is also directly bonded to the bonding layer 15. Thus, the silicon crystal layer 11 is indirectly bonded to the bonding layer 15 via the oxide layer 19. The silicon crystal layer 11 is also bonded to the diamond substrate 16 via the oxide layer 19 and the bonding layer 15. The oxide layer 19 may be made of SiO2. The oxide layer 19 may have a thickness of 0.1 μm or more and 1.0 μm or less.

[0062] In the case of the semiconductor device 102 (FIG. 19), the second interface IF2 of the bonding layer 15 is an interface with the oxide layer 19, unlike the semiconductor device 100 (FIG. 1: embodiment 1). In the case of the semiconductor device 102, similarly to the case of the semiconductor device 100, it is preferable that the arithmetic mean roughness of the second interface IF2 is 0.5 nm or less. This can increase the bonding strength between the bonding layer 15 and the oxide layer 19.

[0063] FIG. 20 is a flow diagram that outlines a manufacturing method MM2 of the semiconductor device 102 (FIG. 19). First, similarly to the above-mentioned manufacturing method MM1 (FIG. 3: embodiment 1), the steps up to step S50 are performed to form the configuration shown in FIG. 9. Next, in step S62 (FIG. 20), the main surface FM5 of the oxide layer 19 is polished. This makes the main surface FM5 a polished surface. In other words, a polished surface is formed as the main surface FM5 of the oxide layer 19. This polishing is preferably precision polishing by chemical mechanical polishing (CMP). In addition, this polished surface preferably has an arithmetic mean roughness of 0.5 nm or less. In addition, this polishing is preferably controlled so that the thickness of the oxide layer 19 after polishing is 0.1 μm or more and 1.0 μm or less.

[0064] 21, next, in step ST72 (FIG. 20), the bonding layer 15 is disposed on the silicon crystal layer 11 with the oxide layer 19 interposed therebetween, and is disposed directly on the polished surface serving as the main surface FM5 of the oxide layer 19. Thus, the bonding layer 15 is disposed on the silicon crystal layer 11 with the oxide layer 19 interposed therebetween. Thereafter, step S80 is performed in the same manner as in the above-described manufacturing method MM1 (FIG. 3: embodiment 1), thereby forming the semiconductor device 102 (FIG. 19).

[0065] Since the configuration other than the above is substantially the same as that of the above-mentioned embodiment 1, the same or corresponding elements are denoted by the same reference numerals and the description thereof will not be repeated. As a modification of the present embodiment 3, the silicon compound layer 21 (FIG. 18) described in the above-mentioned embodiment 2 may be applied to the semiconductor device 102 (FIG. 19).

[0066] According to the semiconductor device 102 in the third embodiment, the buffer layer 12 is disposed on the bonding layer 15 via not only the silicon crystal layer 11 but also the oxide layer 19. Therefore, in the manufacture of the semiconductor device 102, until the configuration shown in FIG. 21 is obtained, in other words, until the structure including the nitride semiconductor layer 13 is bonded to the diamond substrate 16 using the bonding layer 15, not only the silicon crystal layer 11 but also the oxide layer 19 can continue to protect the buffer layer 12. This allows the buffer layer 12 to continue to protect the back surface of the nitride semiconductor layer 13 from damage caused by any manufacturing process. Therefore, it is possible to suppress the deterioration of the performance of the semiconductor device 102 caused by damage to the back surface of the nitride semiconductor layer 13. In particular, when an ion beam treatment is performed immediately before bonding to the structure including the diamond substrate 16, the damage caused by the ion beam to the nitride semiconductor layer 13 can be suppressed by not only the buffer layer 12 and the silicon crystal layer 11 but also the oxide layer 19.

[0067] In the third embodiment, the bonding layer 15 is bonded to the oxide layer 19. The bonding layer 15 made of an amorphous material is more likely to have a better lattice match with the oxide layer 19 than with the silicon crystal layer 11. Therefore, the bonding strength can be increased compared to when the bonding layer 15 is bonded to the silicon crystal layer 11.

[0068] The oxide layer 19 of the semiconductor device 102 may be a SiO2 layer having a thickness of 0.1 μm or more. Although the thermal conductivity of SiO2 is relatively low, if the thickness is not excessively large and is set to 1.0 μm or less, a large decrease in heat dissipation caused by the oxide layer 19 being interposed between the nitride semiconductor layer 13 and the diamond substrate 16 can be avoided.

[0069] According to the manufacturing method of the semiconductor device 102 according to the third embodiment, a polishing step for forming a polished surface is performed, but the step is performed on the oxide layer 19. This makes it possible to suppress damage to the nitride semiconductor layer 13 caused by the polishing step.

[0070] In addition, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted. Although the present disclosure has been described in detail, the above description is illustrative in all aspects and is not intended to be limiting. It is understood that countless modified examples not illustrated can be envisioned from the present disclosure. [Explanation of symbols]

[0071] 10 SOI substrate (silicon-on-insulator substrate), 11 silicon crystal layer, 12 buffer layer, 13 nitride semiconductor layer, 14 surface electrode, 15 bonding layer, 16 diamond substrate, 17 adhesion layer, 18 protection substrate, 19 oxide layer, 20 support substrate, 21 silicon compound layer, 100 to 102 semiconductor device, ES semiconductor element structure, IF1 first interface, IF2 second interface.

Claims

1. Diamond substrate and A bonding layer made of amorphous material is directly placed on the diamond substrate, A silicon crystal layer having a thickness of 0.5 μm to 20.0 μm is bonded to the diamond substrate at least via the bonding layer, A buffer layer comprising a nitride containing aluminum atoms, disposed on the bonding layer via at least the silicon crystal layer, A nitride semiconductor layer is directly disposed on the buffer layer and has a composition different from that of the buffer layer. A semiconductor device equipped with a semiconductor device.

2. The semiconductor device according to claim 1, wherein the silicon crystal layer is directly bonded to the bonding layer.

3. The semiconductor device according to claim 1, further comprising an oxide layer disposed between the silicon crystal layer and the bonding layer, in direct contact with the silicon crystal layer, and directly bonded to the bonding layer.

4. The oxide layer is SiO ２ The semiconductor device according to claim 3, comprising and having a thickness of 0.1 μm or more and 1.0 μm or less.

5. The semiconductor device according to any one of claims 1 to 4, wherein the buffer layer is disposed directly on the silicon crystal layer.

6. The semiconductor device according to any one of claims 1 to 4, further comprising a silicon compound layer between the silicon crystal layer and the buffer layer.

7. The semiconductor device according to any one of claims 1 to 4, wherein the silicon crystal layer has a resistivity of 5000 Ω·cm or less.

8. The semiconductor device according to any one of claims 1 to 4, wherein the bonding layer includes an amorphous carbon layer directly disposed on the diamond substrate.

9. The semiconductor device according to any one of claims 1 to 4, wherein the bonding layer includes a silicon-containing layer.

10. The semiconductor device according to any one of claims 1 to 4, wherein the bonding layer has a thickness of 1 nm or more and 10 nm or less.

11. The semiconductor device according to any one of claims 1 to 4, wherein the diamond substrate is made of single-crystal diamond, mosaic diamond, or polycrystalline diamond.

12. The semiconductor device according to any one of claims 1 to 4, wherein the diamond substrate has a thickness of 50 μm or more and 600 μm or less.

13. The semiconductor device according to any one of claims 1 to 4, wherein the bonding layer has a first interface in contact with the diamond substrate and a second interface opposite to the first interface, and each of the first interface and the second interface has an arithmetic mean roughness of 0.5 nm or less.

14. a) The process comprises a step of directly or indirectly forming a buffer layer made of a nitride containing aluminum atoms on a silicon crystal layer, wherein the silicon crystal layer is directly placed on an oxide layer, the oxide layer is placed on a support substrate, and further, b) A step of forming a nitride semiconductor layer having a composition different from that of the buffer layer on the buffer layer, c) A step of forming a semiconductor device structure on the nitride semiconductor layer, d) A step of providing a protective substrate on the semiconductor device structure via an adhesive layer, e) After d) above, a step of removing the support substrate, f) The step of joining the silicon crystal layer and the polished surface of the diamond substrate to each other after e) via at least a bonding layer, wherein the bonding layer is disposed directly on the polished surface of the diamond substrate and disposed directly on the silicon crystal layer or via the oxide layer, and further, g) A step of removing the adhesive layer and the protective substrate, A method for manufacturing a semiconductor device comprising the same equipment.

15. The process further includes removing the oxide layer while leaving the silicon crystal layer intact by wet etching having a higher etching rate for the oxide layer material than for the silicon crystal layer material, after e) and before f), In the above f), the bonding layer is directly placed on the silicon crystal layer. The method for manufacturing a semiconductor device according to claim 14.

16. The process further includes a step of forming a polished surface of the oxide layer by polishing the oxide layer after e) and before f), In the above f), the bonding layer is disposed on the silicon crystal layer via the oxide layer and is disposed directly on the polished surface of the oxide layer. The method for manufacturing a semiconductor device according to claim 14.

17. A method for manufacturing a semiconductor device according to any one of claims 14 to 16, wherein, in a) above, the silicon crystal layer, the oxide layer, and the support substrate constitute a silicon-on-insulator substrate, and the silicon crystal layer in the silicon-on-insulator substrate has an in-plane uniformity of 10% or less.

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