Matching network with switchable variable capacitance

Abstract

A matching network having a switchable variable capacitance. In one embodiment, the matching network includes a first variable capacitance, a second variable capacitance, and a third variable capacitance dynamically connectable in parallel with the first variable capacitance. The matching network also includes a controller, the controller being configured to: control at least one of the first variable capacitance and the second variable capacitance for impedance tuning for a first power pulse; arrange the third variable capacitance in parallel with the first variable capacitance in response to a second power pulse; and control at least the third variable capacitance for impedance tuning for a second power pulse.

Description

Technology Field

[0001] background

[0002] technology

[0003] The present disclosure generally relates to plasma processing systems, and more specifically to impedance matching in plasma processing systems. Background Technology

[0004] In plasma processing, matching networks optimize power transfer between a generator and a plasma load. Modern plasma processing systems increasingly use multi-pulsed power for more advanced plasma control. However, multi-pulsing generates multiple impedance states, and conventional matching network approaches are insufficient for impedance matching of these additional impedance states. means of solving the problem

[0005] According to an embodiment, the matching network comprises a first variable capacitance, a second variable capacitance, and a third variable capacitance dynamically connectable in parallel with the first variable capacitance. The matching network also comprises a controller, said controller configured to: control at least one of the first variable capacitance and the second variable capacitance for impedance tuning for a first power pulse; arrange the third variable capacitance in parallel with the first variable capacitance in response to the second power pulse; and control at least the third variable capacitance for impedance tuning for the second power pulse.

[0006] According to another aspect, a method is disclosed, wherein the method comprises the steps of: supplying power including a first power pulse and a second power pulse to a dynamic load impedance; controlling at least one of a first variable capacitance and a second variable capacitance for impedance tuning for the first power pulse; connecting a third variable capacitance in parallel with the first variable capacitance in response to the second power pulse; and controlling at least the third variable capacitance for impedance tuning for the second power pulse.

[0007] According to another aspect, a non-transient processor-readable medium is disclosed comprising instructions for execution by a processor or for configuring a field-programmable gate array, wherein the instructions include: controlling at least one of a first variable capacitance and a second variable capacitance for impedance tuning for a first power pulse; connecting a third variable capacitance in parallel with the first variable capacitance in response to the second power pulse; and controlling at least the third variable capacitance for impedance tuning for the second power pulse. Brief explanation of the drawing

[0008] FIG. 1 is a block diagram of a plasma processing system according to an embodiment of the present disclosure. FIG. 2 is a graph illustrating multiple pulsing in an exemplary embodiment. FIG. 3 illustrates a variable reactance section, which is an example of the variable reactance section of FIG. 1. Figure 4 illustrates a variable reactance section, which is another example of the variable reactance section of Figure 1. FIG. 5 is a flowchart illustrating a method of impedance tuning in an exemplary embodiment. Figure 6 is a graph illustrating examples of load impedances of multiple power states. FIG. 7a is a graph illustrating an example of adjusting the shunt capacitance for impedance tuning for multiple power states. FIG. 7b is a graph illustrating an example of adjusting the series capacitance for impedance tuning for multiple power states. FIG. 8a is a Smith chart showing examples of impedance values ​​presented to a generator for multiple power states. Figure 8b is a graph illustrating an example of the absolute value of the reflection coefficient that varies over successive tuning iterations for multiple power states. FIG. 9 is a flowchart illustrating a method of impedance tuning in an exemplary embodiment. FIG. 10 is a block diagram illustrating physical components that may be used to implement an element controller according to one embodiment of the present disclosure. Specific details for implementing the invention

[0009] The following modes, features, or aspects, given only as examples, are described to provide a more precise understanding of the subject matter of the claimed embodiments.

[0010] The word "exemplary" is used herein to mean "serving as an example, instance, or example." Any embodiment described herein as "exemplary" is not necessarily to be interpreted as being more desirable or advantageous than other embodiments.

[0011] FIG. 1 is a block diagram of a plasma processing system (100) according to an embodiment of the present disclosure. The plasma processing system (100) includes a generator (102), a matching network (104), a plasma chamber (105), and an external controller (107). When operating, the generator (102) applies power (e.g., medium frequency power, radio frequency (RF) power, or power at any frequency where impedance matching is advantageous) to the matching network (104) via a transmission line (108) (e.g., a coaxial cable), and then to the plasma chamber (105) via an electrical connection (110). In one embodiment, the generator (102) includes a frequency tuning subsystem (103) configured to adjust the frequency of the generator (102).

[0012] The matching network (104) includes an input section (112) having an electrical connector (not shown) for coupling to a generator (102) via a transmission line (108), and an output section (114) having an electrical connector (not shown) for coupling to a plasma chamber (105) via an electrical connection section (110). The matching network (104) also includes a measurement section (124), an input sensor (116) coupled to an internal controller (119) including an element controller (122), and a variable reactance section (120). Furthermore, as described in more detail below, the variable reactance section (120) includes variable capacitances (131, 132 and 133).

[0013] Generally, the matching network (104) operates to achieve complex conjugate matching between the generator (102) and the plasma load. That is, the internal controller (119) controls the variable reactance section (120) such that the impedance presented to the generator (102) (i.e., presented to the transmission line (108) at the input section (112) of the matching network (104)) is the complex conjugate of the impedance of the dynamic load Zp. By doing so, the measurement section (124) may monitor the impedance of the plasma (109), and the element controller (122) uses this measurement feedback to generate control signals to adjust the variable capacitances (131, 132, and 133) accordingly. Thus, the internal controller (119) continuously adapts the matching network (104) so ​​that impedance matching may occur under changing plasma conditions. Such impedance matching helps achieve efficient power transfer, stable plasma conditions, and controlled processing results.

[0014] A plasma processing system (100) is generally configured to use multiple pulsing as a technique for precisely controlling the plasma environment. Multiple pulsing involves applying a series of pulses having different parameters, such as different power levels, frequencies, durations, or timing between pulses. Compared to continuous wave or single pulse approaches, multiple pulsing enables increased dynamic control of the plasma environment by customizing the pulse sequence and parameters to the process being performed, material properties, and desired effects.

[0015] FIG. 2 is a graph illustrating multiple pulsing in an exemplary embodiment. In this example, the generator (102) applies dual-level pulsing to the plasma chamber (105), including a first power level (201) (e.g., a high-power state) and a second power level (202) (e.g., a low-power state), and these levels alternate with each other in a cycle that repeats over time. As mentioned, alternating between two or more states in this manner may result in several plasma processing benefits, including increased control of plasma interaction with the material. However, the use of two or more pulse states in plasma processing can make it difficult to achieve impedance matching. That is, compared to single-pulse applications, multiple pulsing increases the number of states for which impedance matching must be performed.

[0016] Current approaches for matching tuning dual-level pulsing typically involve using a matching network to tune to one pulse state (e.g., a first power level (201) or a high power state) and using generator frequency tuning to attempt to match to the remaining pulse state(s) (e.g., a second power level (202) or a low power state). This can result in reflected power during the remaining pulse states because frequency tuning can typically only compensate for the imaginary component of the plasma impedance. Reflected power can have a negative impact on the efficiency and stability of plasma processing and is often unacceptable for plasma processing applications such as semiconductor manufacturing.

[0017] Returning to FIG. 1, to address the problems described above, the matching network (104) is enhanced to perform impedance matching for multiple pulse states. In particular, in addition to the first variable capacitance (131) and the second variable capacitance (132) for tuning to the first pulse state, the variable reactance section (120) includes at least one additional variable capacitance (e.g., a third variable capacitance (133)), which is configured to be dynamically placed in parallel with at least one of the first / second variable capacitances (131 / 132) (e.g., via one or more solid-state switches (150)) for tuning to the second or additional pulse state. Advantageously, this may enable the matching network (104) to achieve true matching for each individual pulse state so that reflected power is reduced and / or to tune to the desired impedance in a finely tuned manner. Additionally, this allows the number of solid-state switches in the matching network (104) to be reduced, thereby reducing power dissipation due to switching and increasing cooling of individual switches.

[0018] FIG. 3 illustrates a variable reactance section (300) which is an example of the variable reactance section (120) of FIG. 1. In the variable reactance section (300), the first variable capacitance C1, the second variable capacitance C2, and the third variable capacitance C3 are examples of the first variable capacitance (131), the second variable capacitance (132), and the third variable capacitance (133), respectively. The variable reactance section (300) is an example of an “L” matching network topology comprising a shunt leg (310) (including C1 and inductive element L1 between the input (301) and ground (303)) and a serial leg (320) (including C2 and inductive element L2 between the input (301) and the output (302), but it will be understood that the concepts discussed herein are also applicable to other arrangements including “T” and “Pi” architectures.

[0019] In this example, C1 is a shunt element and C2 is a series element. C3 is an additional shunt element configured to be switched in parallel with C1 through one or more solid-state devices (350) (solid-state switches such as, for example, a field-effect transistor (FET), an insulated gate bipolar transistor (IGBT), etc.). In one embodiment, the variable capacitances C1, C2, and C3 each include one or more variable capacitors (e.g., variable vacuum capacitors and / or variable air capacitors). The variable capacitors may include movable parts, such as rotors and / or stators, which can be controlled electronically or manually to adjust the capacitance. In contrast, the solid-state capacitors may have a fixed, immutable capacitance value (e.g., having dielectric materials and metal plates, excluding adjustable or mechanical parts). Additionally, in some embodiments, each solid-state device (350) may include a plurality of switches in parallel or in series to accommodate voltages of the matching circuit.

[0020] Variable capacitances C1, C2, and C3 may be controlled so that the impedance shown in the input section (301) matches the load impedance in the output section (302) for a number of power states. For example, for a first power level (201) (e.g., high power state), the element controller (122) (shown in FIG. 1) may adjust the capacitive values ​​of C1 and C2 to obtain impedance matching while the solid-state device (350) is open and C3 is switched out of the circuit. To tune for a second power level (202) (e.g., low power state), the element controller (122) may close the solid-state device (350) to switch C3 in parallel with C1 and adjust C3 so that the sum of C1 and C3 obtains the best possible impedance matching for the second state. Accordingly, the element controller (122) is configured to switch the solid-state device (350) to open or close according to the pulse state, thereby adding or removing C3 (e.g., one or more variable vacuum capacitors) according to the pulse state. Additionally, when C3 is switched in or added to the circuit, the element controller (122) is configured to adjust the capacitance value of C3 to achieve the best tuning for the additional pulse state.

[0021] In some embodiments, the matching network (104) and / or the variable reactance section (120) (e.g., the variable reactance section (300) of FIG. 3) may function in conjunction with the frequency tuning subsystem (103) to convert the impedance at the output section (114) to a desired impedance value for the load ZL (presented to the transmission line (108) at the input section (112) of the matching network (104). For example, in the topology shown in FIG. 3, C1 and C3 are part of the shunt leg (310) and their adjustment may primarily affect the real part of the impedance presented to the generator (102), while C2 is part of the series leg (320) and may primarily affect the imaginary part of the impedance presented to the generator (102). Here, to complete the process of impedance tuning for a second / additional pulse state, the frequency tuning subsystem (103) may adjust the frequency of the generator (102) (i.e., perform frequency tuning) so that the imaginary part of the impedance is tuned together with the real part adjusted by C3.

[0022] FIG. 4 illustrates a variable reactance section (400), which is another example of the variable reactance section (120) of FIG. 1. The variable reactance section (400) has a configuration similar to the variable reactance section (300) described above. However, here, the variable reactance section (400) includes two switchable variable capacitances (e.g., one switchable variable capacitance for each pulse state) to tune for a number of states without frequency tuning. In particular, C3 is configured for parallel placement with C1 via a shunt switch (Ssh), and C4 is configured for parallel placement with C2 via a serial switch (Sser). The shunt switch (Ssh) and the serial switch (Sser) may include the previously discussed solid-state devices (350).

[0023] The element controller (122) is configured to control one or more of a shunt switch Ssh and a serial switch Sser to adjust the capacitance of the variable reactance section (400) and, thus, the impedance state. That is, the element controller (122) is configured to control one or more of a shunt switch (Ssh), a first variable capacitance (C1), and a third variable capacitance (C3) to tune the capacitance of the shunt leg (310). And, the element controller (122) is configured to control one or more of a serial switch (Sser), a second variable capacitance (C2), and a fourth variable capacitance (C4) to adjust the capacitance of the serial leg (320). According to tuning commands, the element controller (122) may control the switches Ssh and Sser to operate in tandem or in reverse to add or remove variable capacitance for the shunt leg (310) and the serial leg (320), respectively. Accordingly, the variable reactance section (400) is configured to be tuned for multiple pulses without frequency tuning.

[0024] Although FIGS. 3 and 4 describe a dual-pulsing example, it will be understood that the concepts are also applicable to embodiments having three or more multiple pulse states. That is, for each additional pulse state, one or two additional variable capacitances and associated switch(s) may be added. For example, for a third pulse state, the variable reactance section (400) may include a fifth variable capacitance configured to be placed in parallel with C3 and C1. The element controller (122) may close the solid-state device (350) to switch the fifth variable capacitance to a parallel arrangement with C1 and adjust it so that the sum of the capacitances obtains the best possible impedance match for the third state. The imaginary part of the impedance of the third state may be completed by frequency tuning or a sixth variable capacitance configured to be placed in parallel with C4 and C2.

[0025] Additionally, as previously mentioned, alternative arrangements of variable capacitances are considered. For example, T-network matching arrangements and Pi-network matching arrangements may be configured to adjust impedance through elements corresponding to the shunt elements and series elements described in FIGS. 3 and 4. In some arrangements, one element may be referred to as a load element (e.g., primarily tuning the real part of the impedance), and another element may be referred to as a tuning element (e.g., primarily tuning the imaginary part of the impedance).

[0026] FIG. 5 is a flowchart illustrating a method of impedance tuning in an exemplary embodiment. The steps of the method are described with reference to the plasma processing system (100) of FIG. 1, but those skilled in the art will understand that the method may be performed in other systems. The steps of the flowcharts described herein are not all comprehensive and may include other steps not illustrated and may be performed in an alternative order.

[0027] In step 502, the generator (102) provides power, including a first power pulse and a second power pulse, to the dynamic load impedance. In step 504, the element controller (122) controls at least one of the first variable capacitance (131) and the second variable capacitance (132) for impedance tuning for the first power pulse. In step 506, the element controller (122) connects the third variable capacitance (133) in parallel with the first variable capacitance (131) in response to the second power pulse. In step 508, the element controller (122) controls at least the third variable capacitance (133) for impedance tuning for the second power pulse.

[0028] yes

[0029] FIGS. 6 through 8 illustrate graphs representing examples of impedance tuning for multiple power states. For the purposes of discussion, these examples are discussed in relation to the variable reactance section (400) of FIG. 4 and the plasma processing system (100) of FIG. 1, but it will be understood that the principles may be applied to alternative variable reactance configurations, plasma processing systems, number of power states, etc. FIG. 6 is a graph illustrating an example of load impedance for multiple power states. Some RF-related electrical parameters (e.g., voltage, current, and / or impedance) may be complex numbers expressed in real and imaginary parts. For example, impedance Z may be expressed as resistance "R" (real part) and reactance "X" (imaginary part): Z = R + Xj, where j is the square root of -1.

[0030] For this example, it is assumed that in the initial time before the matching network (104) begins to tune the variable reactance section (400), the load impedance for the first power state (601) (e.g., the first pulse) is 5-j15 ohms, and the load impedance for the second power state (602) (e.g., the second pulse) is 7-j20 ohms. Additionally, for this example, it is assumed that the generator (102) is designed for optimal operation when 50 ohms is presented to the generator (102). To provide an efficient path for power delivery, the matching network (104) operates to tune the variable reactance section (400) to convert the impedance presented to the generator (102) to 50 ohms. The impedance presented to the generator (102) by the load ZL may include the plasma (109) itself, components associated with the plasma chamber (105), and the variable reactance section (400) of the matching network (104).

[0031] For example, for a first power state (601), the element controller (122) may control a shunt leg (310) (e.g., a combination of a shunt switch Ssh, a first variable capacitance (C1), or a combination of a first variable capacitance (C1) and a third variable capacitance (C3)) and a series leg (320) (e.g., a combination of a series switch Sser, a second variable capacitance (C2), or a combination of a second variable capacitance (C2) and a fourth variable capacitance (C4)), wherein the unique combination of the shunt capacitance (C1 or a combination of C1 and C3) and the series capacitance (C1 or a combination of C1 and C3) converts the load impedance for the first power state to 50 ohms as presented to the generator. Then, for the second power state (602), the element controller (122) may toggle a switch (e.g., a serial switch Sser and / or a shunt switch Ssh) to add or remove variable capacitance for the serial leg (320) and / or the shunt leg (310) depending on whether more or less capacitance is required for each leg. Additional details of the example are discussed below.

[0032] FIG. 7a is a graph illustrating an example of adjusting shunt capacitance for impedance tuning for multiple power states. In particular, the element controller (122) adjusts the shunt capacitance for a first power state (601) and a second power state (602), corresponding to load impedances of 5-j15 ohms and 7-j20 ohms, respectively. To initiate the impedance matching process by tuning the shunt leg (310), the element controller (122) decides to reduce the shunt capacitance from its initial position, which is about 50% of its maximum capacitance value, thereby partially reducing the absolute value of the reflection coefficient presented to the generator (102).

[0033] More specifically, referring to the exemplary variable reactance section (400) of FIG. 4, the element controller (122) may decide to connect the third variable capacitance C3 for impedance tuning for the first power state (601) and to disconnect the third variable capacitance C3 for impedance tuning for the second power state (602). That is, the shunt capacitance for the first power state (601) is based on the sum of the capacitances of C3 and C1, and the shunt capacitance for the second power state (602) is based on the capacitance value of C1 excluding C3.

[0034] After reducing the shunt capacitance during fifteen tuning iterations in which the first power state (601) and the second power state alternate, impedance matching of the first power state (601) is reached with a shunt capacitance at about 38% of the maximum capacitance. In subsequent tuning iterations, the element controller (122) maintains the shunt capacitance value for the first power state (601) (the capacitance sum of C1 and C3) and continues to reduce the first variable capacitance C1 for the second power state (602) up to tuning iteration 22, where impedance matching of the second power state (602) is reached with a shunt capacitance at about 28% of the maximum capacitance. After that, for the optimal load impedance presented to the generator (102), the element controller (122) can toggle the shunt switch (Ssh) according to the alternating power states so that the shunt capacitance is about 38% of the maximum capacitance for the first power state (601) and about 28% of the maximum capacitance for the second power state (602).

[0035] FIG. 7b is a graph illustrating an example of adjusting series capacitance for impedance tuning for multiple power states. Here, the element controller (122) adjusts the series capacitance for a first power state (601) and a second power state (602), corresponding to load impedances of 5-j15 ohms and 7-j20 ohms, respectively. To initiate the impedance matching process by tuning the series leg (320), the element controller (122) decides to reduce the series capacitance from its initial position of about 50% of its maximum capacitance value (e.g., to provide a more negative reactance to partially offset the imaginary part of the load impedances).

[0036] More specifically, the element controller (122) may decide to connect the fourth variable capacitance C4 for impedance tuning for the second power state (602) and disconnect the fourth variable capacitance C4 for impedance tuning for the first power state (601). That is, the series capacitance for the second power state (602) is based on the sum of the capacitances of C2 and C4, and the series capacitance for the first power state (601) is based on the capacitance value of C2 excluding C4.

[0037] After reducing the series capacitance during eleven tuning iterations in which the first power state (601) and the second power state (602) alternate, impedance matching of the second power state (602) is achieved with a series capacitance at about 40% of the maximum capacitance. In subsequent tuning iterations, the element controller (122) maintains the series capacitance value for the second power state (602) and continues to reduce the second variable capacitance C2 for the first power state (601) up to tuning iteration 26, where impedance matching of the first power state (601) is achieved with a series capacitance at about 22% of the maximum capacitance. Afterward, for the optimal load impedance presented to the generator (102), the element controller (122) may toggle the series switch (Sser) according to the alternating power states so that the series capacitance becomes about 40% of the maximum capacitance for the second power state (602) and about 22% of the maximum capacitance for the first power state (601).

[0038] FIG. 8a is a Smith chart illustrating examples of impedance values ​​presented to the generator (102) for multiple power states. In particular, each point represents a specific impedance value having both a real component and an imaginary component for each of the first power state (601) and the second power state (602). As the element controller (122) performs the variable capacitance tuning and switching described above for the shunt and series legs, the impedance values ​​for each power state tend toward 50 ohms. Although 50 ohms is the typical characteristic impedance of the generator, those skilled in the art of plasma processing systems will understand that, depending on the specific type used to realize the generator (102) (e.g., design architecture, manufacturer, and / or model), the source impedance Zg of the generator (102) may differ from 50 ohms and / or the desired impedance may differ from 50 ohms for other reasons.

[0039] FIG. 8b is a graph illustrating an example of the absolute value of the reflection coefficient changing over successive tuning iterations for multiple power states. The reflection coefficient, or gamma, quantifies the amount of power reflected during operation. As the element controller (122) performs the variable capacitance tuning and switching described above for the shunt and series legs, the absolute value of the reflection coefficient decreases over time, which indicates an improvement in matching the load impedance to the tuned state as the matching network (104) is adjusted through various iterations.

[0040] FIG. 9 is a flowchart illustrating a method of impedance tuning in an exemplary embodiment. Although the steps of the method are described with reference to the plasma processing system (100) of FIG. 1 and the variable reactance section (400) of FIG. 4, those skilled in the art will understand that the method may be performed in other systems and matching topologies. The steps of the flowcharts described herein are not all comprehensive and may include other steps not illustrated and may be performed in an alternative order.

[0041] In step 902, the matching network (104) detects a first power pulse. In step 904, the internal controller (119) determines a first target shunt capacitance value and a first target series capacitance value for tuning to the first power pulse. In step 906, the element controller (122) tunes the shunt leg (310) and the series leg (320) to the first target shunt capacitance value and the first target series capacitance value, respectively. In step 908, the matching network (104) detects a second power pulse. In step 910, the internal controller (119) determines a second target shunt capacitance value and a second target series capacitance value for tuning to the second power pulse. In step 912, the element controller (122) operates one or more switches to add or remove variable capacitance to at least one of the shunt leg (310) and the series leg (320). Then, in step 914, the element controller (122) tunes the shunt leg (310) and the series leg (320) to a second target shunt capacitance value and a second target series capacitance value, respectively.

[0042] Steps 902 through 914 may be repeated for the continuous adjustment of capacitance values ​​and the continuous adaptation of changing load conditions to efficiently deliver multiple pulsed power. The determination of target capacitance values ​​for each leg may be based on real-time measurement feedback regarding the impedance of the load. The internal controller (119) may also determine whether to add or remove a variable capacitance for each leg based at least partially on an initial or current variable capacitance position and a determined tuning direction (e.g., increase or decrease of capacitance). For example, the internal controller (119) may assign one variable capacitance to a first power pulse and assign a variable capacitance in parallel with said one variable capacitance to a second power pulse based on load impedance differences for the power pulses, initial capacitor positions, and a determined tuning direction.

[0043] Although not illustrated to keep the drawing of FIG. 1 simple and clear, those skilled in the art will readily understand that the generator (102), the matching network (104), and / or the external controller (107) may include a user interface to enable an operator of the plasma processing system (100) to control and monitor the plasma processing system (100). It should also be noted that the depiction of the external controller (107) should not be interpreted to mean that common supervisory control of the generator (102) and the matching network (104) is required.

[0044] Plasma (109) may be plasma formed in a plasma processing chamber (105) known for performing processes such as etching substrates or deposition of thin layers on substrates. Plasma (109) is typically achieved by forming plasmas in low-pressure gases. The plasma is initiated and maintained by a generator (102) (and potentially additional generators). The generator (102) may power the plasma chamber (105) by a conventional 13.56 MHz signal, but other frequencies may also be utilized.

[0045] The external controller (107) may be realized by hardware combined with hardware or software, and the external controller (107) may be coupled to various components of the plasma processing system (100), including the generator (102), the matching network (104), the equipment coupled to the plasma chamber (105), other generators, the mass flow controller, etc. The input sensor (116) may be realized by a conventional dual directional coupler (known to those skilled in the art) comprising a sensing circuit that provides outputs indicating forward and reflected power at the input of the matching network (104). The input sensor (116) may also be realized by a conventional voltage-current (V / I) sensor (known to those skilled in the art) comprising a sensing circuit that provides outputs indicating voltage, current, and the phase between voltage and current. As a non-limiting example, a directional coupler may be used to implement the input sensor (116). The input sensor (116) may also include a frequency sensor known to those skilled in the art. Additionally, the input sensor (116) may be realized by more than one distinct sensor (e.g., a distinct voltage sensor and a distinct current transducer). In other words, although a single block is shown for each input sensor (116), the block may represent one or more sensors (and potentially a processing circuit).

[0046] The measurement section (124) may include processing components for sampling, filtering, and digitizing the outputs of the input sensor (116) for use by the element controller (122). Because the impedance of the load ZL tends to change during the processing of the workpiece (e.g., substrate), the element controller (122) may continue to operate to adjust the variable reactance section (120) to change its impedance to compensate for variations in the impedance of the dynamic load.

[0047] In some variations, a communication link (126) telecommunicationally couples the generator (102) and the matching network (104) so ​​that information and / or control signals can be transmitted between the generator (102) and the matching network (104). However, it should be recognized that many implementations do not require a communication link (126), and in these implementations, the matching network (104) may operate substantially independently of the generator (102). A specific embodiment of the matching network (104) of FIG. 1 (where the element controller (122) and the measurement section (124) are located within the internal controller (119) of the matching network (104)) may be advantageous for one or more reasons. For example, the internal controller (119) of the matching network (104) may have access to internal parameters of the matching network (104) that the external controller (107) (or other external controllers) does not have access to. As another example, the internal controller (119) is closer to the input sensor (116); thus, data from the sensor (116) may be received and processed relatively quickly. Additionally, the components of the internal controller (119) may be realized on the same printed circuit board or even on the same chip (as a system-on-chip); thus, very fast bus communications may be executed between the components of some embodiments of the internal controller (119) (without the need to convert to other communication protocols, such as local area network protocols).

[0048] However, in variations of the embodiment illustrated in FIG. 1, other configurations are certainly considered, as it may be advantageous to disperse one or more of the components of the matching network (104) and / or the generator (102). For example, the input sensor (116) may be located outside the matching network (104). As another example, the input sensor (116) may reside within the generator (102), and the generator (102) may provide a signal to the measurement section (124) indicating electrical parameters at the output of the generator (102). Additionally, one or more of the components of the internal controller (119) (e.g., one or more of the element controller (122) and the measurement section (124)) may be located away from the matching network (104). For example, it is considered that one or more components of the internal controller (119) may be located remotely from the matching network (104) and may be coupled to the matching network (104), the generator (102), or the external controller (107) by a network connection. It is also considered that the frequency tuning subsystem (103) may be realized at least partially in the external controller (107). In many cases, the operator of the plasma processing system (such as the system shown in FIG. 1) may prefer to use a central controller (such as the external controller (107)) for convenience and because they prefer to have control over the logic and algorithms utilized in the generator (102) and / or the matching network (104).

[0049] As an additional example, it should also be recognized that the components of the matching network (104) are illustrated as logical components and that the illustrated components may be realized by closely integrated common structures (e.g., a common central processing unit and non-volatile memory), or that the illustrated components may be further distributed. For example, the functionality of the measurement section (124) may be distributed with the input sensor (116) so that the signals output from the input sensor (116) are processed and digitized digital signals, which allows the element controller (122) to directly receive the processed signals from the input sensor (116). Since it is certainly taken into account that various alternatives may be utilized depending on the type of hardware selected and the extent to which software (e.g., embedded software) is utilized, specific examples of the distribution of the illustrated functions are not intended to be limiting.

[0050] The element controller (122) may be configured to obtain an input impedance at the input of the matching network (104). The input impedance is also referred to herein as the impedance value of the load ZL presented to the generator (102). As will be understood by those skilled in the art, the input sensor (116) may provide essential measurements of power-related parameters, such as voltage, current, phase between voltage and current, forward power, and reflected power, which may be used to calculate the input impedance.

[0051] The methods described in connection with the embodiments disclosed herein may be directly implemented in hardware, in processor executable instructions encoded on a non-transient machine-readable medium, or as a combination of both. For example, referring to FIG. 10, a block diagram is shown illustrating physical components that may be utilized to realize one or more of a frequency tuning subsystem (103), an external controller (107), and / or an internal controller (119). As illustrated, in this embodiment, a display portion (1012) and a non-volatile memory (1020) are coupled to a bus (1022), which also includes random access memory ("RAM") (1024), a processing portion ( N (1026), field programmable gate array (FPGA) (1027), and N It is coupled to a transceiver component (1028) comprising several transceivers. Although the components illustrated in FIG. 10 represent physical components, FIG. 10 is not intended to be a detailed hardware diagram; therefore, many of the components illustrated in FIG. 10 may be realized by common structures or distributed among additional physical components. Furthermore, it is considered that other existing and yet-to-be-developed physical components and architectures may be utilized to implement the functional components described with reference to FIG. 10.

[0052] The display portion (1012) generally operates to provide a user interface for a user, and in several implementations, the display is realized by a touchscreen display. For example, the display portion (1012) may be used to control and interact with an internal controller (119) in relation to characterizing a dynamic load to generate an associated impedance trajectory. The user interface may also be used to enable an operator to select specific power levels, frequencies, and pulse parameters for the generator (102). Generally, the non-volatile memory (1020) is a non-transient memory that functions to store (e.g., continuously store) data and machine-readable (e.g., processor-readable and executable) code (including executable code associated with carrying out the methods described herein). In some embodiments, for example, the non-volatile memory (1020) includes bootloader code, operation system code, file system code, and non-transient processor executable code to facilitate the execution of the methods described herein (methods described with reference to FIG. 5 and / or FIG. 9).

[0053] In many implementations, the non-volatile memory (1020) is realized by flash memory (e.g., NAND or ONENAND memory), but it is considered that other memory types may also be utilized. Although it may be possible to execute code from the non-volatile memory (1020), the executable code in the non-volatile memory is typically loaded into RAM (1024) and within the processing part (1026). N It is executed by one or more of the processing components.

[0054] When operating, related to RAM (1024) NThe processing components may generally operate to execute instructions stored in non-volatile memory (1020) to realize the functionality of the frequency tuning subsystem (103) and the element controller (122). For example, non-transient processor-executable instructions for carrying out the methods described herein are continuously stored in non-volatile memory (1020) and related to RAM (1024). N It may be executed by several processing components. As will be understood by those skilled in the art, the processing part (1026) may include a video processor, a digital signal processor (DSP), a graphics processing unit (GPU), and other processing components.

[0055] Additionally, or alternatively, the field programmable gate array (FPGA) (1027) may be configured to implement one or more aspects of the methodologies described herein (e.g., methods described with reference to FIG. 5 and / or FIG. 9). For example, non-transient FPGA configuration commands may be continuously stored in non-volatile memory (1020) to configure the FPGA (1027) to perform the functions of the frequency tuning subsystem (103) and the element controller (122), and may be accessed by the FPGA (1027) (e.g., during boot-up).

[0056] The input component may operate to receive signals (e.g., from a sensor (116)) that represent one or more characteristics of the power output by the generator (102) and characterize the dynamic load Zp. The signals received by the input component may include, for example, voltage, current, forward power, reflected power, and dynamic load impedance. The output component generally operates to provide one or more analog or digital signals to achieve an operational mode of the matching network (104) and / or the generator (102). For example, the output portion may transmit a tuned frequency to the exciter of the generator (102) during frequency tuning. The output may also be used to control the elements described herein, including positions such as a first variable capacitance (131), a second variable capacitance (132), a third variable capacitance (133), etc.

[0057] The illustrated transceiver component (1028) may be used to communicate with external devices via wireless or wired networks, N It includes several transceiver chains. N Each of the transceiver chains may represent a transceiver associated with a specific communication method (e.g., WiFi, Ethernet, Profibus, etc.).

[0058] The prior description of the disclosed embodiments is provided to enable those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Accordingly, the invention is not intended to be limited to the embodiments shown herein but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

Claim 1 A matching network comprising: a first variable capacitance; a second variable capacitance; a third variable capacitance dynamically connectable in parallel with the first variable capacitance; and a controller, wherein the controller comprises: Controlling at least one of the first variable capacitance and the second variable capacitance for impedance tuning for the first power pulse; In response to a second power pulse, the third variable capacitance is arranged in parallel with the first variable capacitance; and A matching network configured to control at least the third variable capacitance for impedance tuning for the second power pulse. Claim 2 In claim 1, the first variable capacitance is part of a shunt leg; the second variable capacitance is part of a series leg; and the third variable capacitance is part of the shunt leg, and the matching network is switchably connected in parallel with the first variable capacitance through a first solid-state switch. Claim 3 A matching network according to claim 2, wherein the controller is configured to control the first variable capacitance and the second variable capacitance to disconnect the third variable capacitance during the first power pulse and to match the load impedance to the source impedance for the first power pulse; and the controller is configured to connect the third variable capacitance during the second power pulse and to control the sum of the first variable capacitance and the third variable capacitance for impedance tuning for the second power pulse. Claim 4 In claim 3, the impedance tuning for the second power pulse is completed through frequency tuning, in a matching network. Claim 5 A matching network according to claim 2, further comprising a fourth variable capacitance dynamically connectable in parallel with the second variable capacitance through a second solid-state switch; wherein the controller is configured to control one or more of the first solid-state switch, the first variable capacitance, and the third variable capacitance to tune the capacitance of the shunt leg; and wherein the controller is configured to control one or more of the second solid-state switch, the second variable capacitance, and the fourth variable capacitance to tune the capacitance of the series leg. Claim 6 A matching network according to claim 5, wherein the controller is configured to determine a first target shunt capacitance value and a first target series capacitance value for impedance matching for the first power pulse; the controller is configured to determine a second target shunt capacitance value and a second target series capacitance value for impedance matching for the second power pulse; the controller is configured to control the first solid-state switch to switch between the first target shunt capacitance value and the second target shunt capacitance value; and the controller is configured to control the second solid-state switch to switch between the first target series capacitance value and the second target series capacitance value. Claim 7 In claim 5, the first variable capacitance, the second variable capacitance, the third variable capacitance, and the fourth variable capacitance each comprise a variable vacuum capacitance, forming a matching network. Claim 8 A method comprising: supplying power including a first power pulse and a second power pulse to a dynamic load impedance; controlling at least one of a first variable capacitance and a second variable capacitance for impedance tuning for the first power pulse; connecting a third variable capacitance in response to the second power pulse to be in parallel with the first variable capacitance; and controlling at least the third variable capacitance for impedance tuning for the second power pulse. Claim 9 A method according to claim 8, wherein the first variable capacitance is part of a shunt leg; the second variable capacitance is part of a series leg; and the third variable capacitance is part of the shunt leg and is switchably connected in parallel with the first variable capacitance through a first solid-state switch. Claim 10 A method according to claim 9, further comprising: a step of disconnecting the third variable capacitance during the first power pulse and controlling the first variable capacitance and the second variable capacitance to match the dynamic load impedance to the source impedance for the first power pulse; and a step of connecting the third variable capacitance during the second power pulse and controlling the sum of the first variable capacitance and the third variable capacitance for impedance tuning for the second power pulse. Claim 11 A method according to claim 10, further comprising the step of performing frequency tuning during the second power pulse to complete the impedance tuning for the second power pulse. Claim 12 The method of claim 9 further comprises the step of controlling one or more of the first solid-state switch, the first variable capacitance, and the third variable capacitance to tune the capacitance of the shunt leg; and the step of controlling one or more of the second solid-state switch, the second variable capacitance, and the fourth variable capacitance to tune the capacitance of the series leg, wherein the fourth variable capacitance is part of the series leg and is switchably connected in parallel with the second variable capacitance through the second solid-state switch. Claim 13 In claim 12, the method wherein the first variable capacitance, the second variable capacitance, the third variable capacitance, and the fourth variable capacitance each comprise a variable vacuum capacitance. Claim 14 A non-transient processor-readable medium comprising instructions for execution by a processor or for configuring a field-programmable gate array, wherein the instructions are: Control at least one of a first variable capacitance and a second variable capacitance for impedance tuning for a first power pulse; In response to a second power pulse, a third variable capacitance is connected in parallel with the first variable capacitance; and A non-transient processor-readable medium comprising instructions for controlling at least the third variable capacitance for impedance tuning for the second power pulse. Claim 15 In claim 14, the first variable capacitance is part of a shunt leg; the second variable capacitance is part of a series leg; and the third variable capacitance is part of the shunt leg, and a non-transient processor-readable medium switchably connected in parallel with the first variable capacitance through a first solid-state switch. Claim 16 In Article 15, the above orders are: During the first power pulse, the third variable capacitance is disconnected, and the first variable capacitance and the second variable capacitance are controlled to match the dynamic load impedance to the source impedance for the first power pulse; and A non-transient processor-readable medium comprising instructions for connecting the third variable capacitance during the second power pulse and controlling the sum of the first variable capacitance and the third variable capacitance for impedance tuning for the second power pulse. Claim 17 In Article 16, the above orders are: A non-transient processor-readable medium comprising instructions for performing frequency tuning during the second power pulse to complete impedance tuning for the second power pulse. Claim 18 In Article 15, the above orders are: To tune the capacitance of the shunt leg, one or more of the first solid-state switch, the first variable capacitance, and the third variable capacitance are controlled; and A non-transient processor-readable medium comprising instructions for controlling one or more of a second solid-state switch, a second variable capacitance, and a fourth variable capacitance to tune the capacitance of the serial leg, wherein the fourth variable capacitance is part of the serial leg and can be switchedably connected in parallel with the second variable capacitance through the second solid-state switch. Claim 19 In Article 18, the above orders are: For impedance matching for the first power pulse, a first target shunt capacitance value and a first target series capacitance value are determined; For impedance matching for the above second power pulse, a second target shunt capacitance value and a second target series capacitance value are determined; Control the first solid-state switch to switch between the first target shunt capacitance value and the second target shunt capacitance value; and A non-transient processor-readable medium comprising instructions for controlling the second solid-state switch to switch between the first target serial capacitance value and the second target serial capacitance value. Claim 20 In claim 18, a non-transient processor-readable medium wherein each of the first variable capacitance, the second variable capacitance, the third variable capacitance, and the fourth variable capacitance comprises a variable vacuum capacitance.

Images