Glass substrate with through via having asymmetric openings and method of manufacturing the same

Abstract

The present invention relates to a glass substrate having a through-via formed by penetrating from a first surface to a second surface of the glass substrate, wherein the through-via comprises a first opening on the first surface side, a second opening on the second surface side, and a minimum diameter portion located between the two, wherein the diameter of the first opening and the diameter of the second opening are different from each other, so that the sidewall profiles on both sides are asymmetric, and the electroplating growth bonding surface of a conductive metal filled inside the through-via is formed at the minimum diameter portion. Due to the difference in diameter between the two openings, the plating growth rate on both sides is differentiated during electroplating, thereby predictably controlling the position of the plating bonding surface and achieving high-quality metal filling without voids.

Description

Technology Field

[0001] The present invention relates to a through-glass via (TGV) structure formed in a glass substrate, and more specifically, to a glass substrate having a through-glass via having an asymmetric structure in which the diameter of the first-sided opening and the diameter of the second-sided opening are different from each other, and a method for manufacturing the same. The glass substrate according to the present invention can be applied to various semiconductor packaging applications, such as an interposer for a semiconductor package, a core substrate for a flip-chip ball grid array (FC-BGA), and a glass panel for panel level packaging (PLP). Background Technology

[0003] As the integration density and computational speed of high-performance semiconductor chips, such as artificial intelligence (AI) computing processors, GPUs (Graphics Processing Units), and High Bandwidth Memory (HBM), increase rapidly, the demand for semiconductor packaging technology to interconnect these chips is rising exponentially. In particular, for next-generation AI accelerator packages, the size of a single package is expanding to more than three times the limit, and consequently, the demand for large-area interposer substrates is surging.

[0004] Glass substrates are attracting attention as next-generation interposer materials because they possess low dielectric loss compared to silicon substrates, a coefficient of thermal expansion (CTE) similar to silicon, ease of forming large-area panels, and high thermal and dimensional stability. To utilize glass substrates as interposers, it is essential to secure electrical connections by forming conductive paths, or through-vias (TGVs), that penetrate the substrate in the vertical direction and filling them with conductive metal.

[0005] In conventional TGV formation technology, a laser-damage-and-etch process combining laser modification and wet etching is mainly used. In this process, a damage track is formed in the thickness direction by irradiating a glass substrate with an ultrashort pulse laser, and then the damage track is preferentially etched by immersing it in an etching solution such as hydrofluoric acid (HF) to form through-vias.

[0006] A TGV formed by a conventional laser-damage-and-etch process typically has a symmetric hourglass shape in which the diameter of the opening on the first side and the diameter of the opening on the second side are substantially the same, because etching proceeds symmetrically on both sides of the glass substrate. In such a symmetric hourglass TGV, internal conductive metal filling is performed by an electroplating process, in which metal ions in the plating solution grow inward from the openings on both sides of the via and form a metal bridge by joining at the waist, and the remaining space is filled starting from this bridge.

[0007] However, in conventional symmetric hourglass TGVs, since the diameters of the openings on both sides are the same, the electroplating growth rates from both sides are substantially the same. In this case, the growth fronts on both sides reach the minimum diameter section simultaneously to form a bonding surface. However, at the point where bonding occurs, the smooth circulation of the plating solution is blocked, and a residual plating solution space is created near the minimum diameter section, which makes it easy for void or seam defects to form. Void or seam defects increase the electrical resistance of the through-via and act as crack initiation points during thermal cycling, thereby reducing long-term reliability.

[0008] Meanwhile, a conical TGV, that is, a TGV with a shape in which the diameter decreases monotonically from the first-sided opening to the second-sided opening, is known in the past. However, since there is no waist in such a conical TGV, there is no location for a metal bridge to be formed during electroplating, so there is a limitation in that one side must be physically sealed and then bottom-up plating performed or conformal plating must be relied upon. Bottom-up plating has an extremely long process time, and conformal plating has limitations in that unfilled space remains inside the via, resulting in degraded electrical and thermal performance.

[0009] Therefore, there is a demand for a new TGV structure that can predictably control the position of the electroplated bonding surface and enable void-free, high-quality metal filling by having a minimum diameter portion (waist) while having different diameters for the openings on both sides. The problem to be solved

[0011] The present invention aims to solve the problems of the aforementioned prior art by providing a through-via structure capable of achieving high-quality metal filling without voids by intentionally designing the opening diameters of both sides of the through-via differently, thereby differentiating the electroplating growth rate from both sides and predictively aligning the position of the plating growth bonding surface with the minimum diameter portion.

[0012] Another objective of the present invention is to provide a method for manufacturing a through-via having the asymmetric opening structure. means of solving the problem

[0014] To achieve the above objective, a glass substrate having a through-via according to one embodiment of the present invention comprises a glass substrate and a through-via formed by penetrating from a first surface to a second surface of the glass substrate. The through-via includes a first opening on the first surface side, a second opening on the second surface side, and a minimum diameter portion located between the first opening and the second opening. Since the diameter of the first opening and the diameter of the second opening are different from each other, the sidewall profile between the first opening and the minimum diameter portion and the sidewall profile between the second opening and the minimum diameter portion are asymmetric. A conductive metal is filled inside the through-via, and an electroplated growth bonding surface of the conductive metal is formed on the minimum diameter portion.

[0015] A method for manufacturing a glass substrate having a through-via according to another embodiment of the present invention comprises: a step of forming a through-via that penetrates from a first surface to a second surface of a glass substrate, wherein the diameter of a first opening on the first surface side and the diameter of a second opening on the second surface side are different from each other, and a minimum diameter portion is located between the first opening and the second opening; and a step of filling the interior of the through-via by electroplating a conductive metal, wherein plating layers growing from the first opening side and the second opening side, respectively, are joined at the minimum diameter portion to form a growth bonding surface. Effects of the invention

[0017] According to the present invention, the following effects can be achieved.

[0018] First, since the through-via of the present invention has different diameters for the openings on both sides, the plating growth rate from the large-diameter opening side and the plating growth rate from the small-diameter opening side differ during electroplating. Generally, in the electroplating of through-vias, the plating growth rate depends on the cross-sectional area of ​​the opening; the large-diameter opening has high convective accessibility of the plating solution, so the supply of metal ions is smooth, and thus the advancement speed of the plating front is fast, whereas the small-diameter opening has low convective accessibility of the plating solution, so the advancement speed of the plating front is relatively slow. This difference in plating growth rates between the two sides makes it possible for the plating fronts on both sides to arrive sequentially at a specific point inside the via, separated in time. In conventional symmetric hourglass vias, since both plating fronts reach the minimum diameter portion simultaneously, the residual plating solution space is suddenly sealed, making it easy for voids to form. In contrast, in the present invention, one plating front reaches the minimum diameter portion first and starts pinching, and the other plating front joins after a time difference, so the plating solution evacuation path is maintained for a certain period of time, thereby promoting the discharge of residual plating solution and gas. Accordingly, void and seam defects are suppressed, and an electrically and thermally superior through-via is realized.

[0019] Second, by controlling the ratio of the opening diameters on both sides of the through-via, the formation location of the electroplating growth bond surface can be predicted. Specifically, once the ratio of the opening diameters and the geometric profile of the via sidewalls are determined, the relationship between the advance distance and time of the plating fronts on both sides is geometrically determined, allowing the location of the bond surface to be predicted in advance during the design phase. This predictive control improves process reliability and contributes to the stable securing of manufacturing yield.

[0020] Third, the asymmetric structure in which the diameters of the openings on both sides differ provides the advantage of independently optimizing the degree of freedom in wiring design for the first side (chip mounting side) and the second side (substrate connection side) of the interposer. For example, on the first side where a fine-pitch semiconductor die is mounted, a small-diameter opening can be placed to maintain a dense pitch between vias, and on the second side where solder balls or bumps with a relatively wide pitch are formed, a large-diameter opening can be placed to reduce electrical resistance and minimize IR drop in the power supply path. In this way, the difference in diameter between the openings on both sides is not merely a simple structural asymmetry, but provides design flexibility that allows for independent response to the requirements of each layer in the hierarchical wiring structure of chip-interposer-substrate.

[0021] Fourth, since the location of the minimum diameter portion where the current density is maximum inside the through-via can be freely adjusted within the thickness direction of the glass substrate by the ratio of the diameters of the two openings, the location where the risk of electromigration is concentrated can be moved to a location where the heat dissipation path is optimized.

[0022] Fifth, in conventional symmetric hourglass TGVs, the symmetrical shape is secured only when the etching conditions on both sides are maintained precisely identically, which places a heavy burden on process control. On the other hand, in the asymmetric aperture TGV of the present invention, the difference in diameters on both sides is intentionally designed, so minute non-uniformity in the etching conditions on both sides does not lead to defects in the via shape, but rather is absorbed into the process margin within the allowable range of the ratio of the diameters on both sides. Accordingly, the process window is expanded, contributing to an improvement in yield in large-area panel-level manufacturing.

[0023] Sixth, if the opening diameters on both sides of the through-via are different, the sidewall profile of the via becomes asymmetric, and the residual stress distribution inside the glass substrate is asymmetrically dispersed. In a symmetrical structure, residual stress is symmetrically concentrated at the minimum diameter, whereas in an asymmetrical structure, the stress concentration points are dispersed, reducing the maximum stress applied to the minimum diameter. This lowers the probability of cracking in the glass substrate during thermal cycling, thereby improving long-term reliability.

[0024] Seventh, since the aperture diameters of the power supply vias and the signal transmission vias can be designed differently, the electrical characteristics of the power supply network (PDN) and the signal transmission path can be independently optimized within the same glass substrate. By applying large apertures to the power supply vias, low resistance and high current capacity can be secured, and by applying small apertures to the signal transmission vias, high wiring density and low parasitic capacitance can be achieved. Brief explanation of the drawing

[0026] Figure 1 is a cross-sectional view of a conventional symmetric hourglass TGV structure. Figure 2 is a cross-sectional view of a conventional conical TGV structure. FIG. 3 is a cross-sectional view of an asymmetric opening TGV structure according to one embodiment of the present invention. Figure 4 is an explanatory diagram showing the change in the position of the minimum diameter deviation according to the ratio of the first opening diameter to the second opening diameter. FIG. 5 is a cross-sectional view with dimensions of a structure in which the axial distance from the first opening to the minimum diameter portion and the axial distance from the second opening to the minimum diameter portion are different. Figure 6 is a cross-sectional view of a field via structure fully filled with copper. Figure 7 is a cross-sectional view of a conformal lining structure. Figure 8 is a flowchart of the electroplating growth process of an asymmetric opening TGV. Figure 9 is a comparison diagram of the plating growth process and void generation of a conventional symmetrical TGV. Figure 10 is an explanatory diagram of the principle of controlling the position of the bonding surface by the difference in plating growth rates on both sides. Figure 11 is a cross-sectional view of an asymmetric opening TGV structure with a resin buffer layer formed thereon. FIG. 12 is a plan view and a cross-sectional view of a plurality of asymmetric opening TGVs arranged in an array. FIG. 13 is a cross-sectional view showing the difference in opening diameter between a power supply via and a signal transmission via. Figure 14 is a cross-sectional view of an example of interposer application. Figure 15 is a cross-sectional view of an example of an AI accelerator package application. Figure 16 is a cross-sectional view of an example of FC-BGA core substrate application. Fig. 17 is a plan view of a glass panel for panel-level packaging. Figure 18 is a flowchart of the laser modification and wet etching process. Figure 19 is a graph showing the relationship between the ratio of the first opening diameter to the second opening diameter and the position of the plating joint surface. Figure 20 is a graph showing the relationship between the ratio of the minimum diameter to the small diameter opening diameter and the electrical resistance. Specific details for implementing the invention

[0028] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Embodiments of the present invention may be modified in various different forms, and the scope of the present invention is not limited to the embodiments described below.

[0030] FIG. 1 illustrates a conventional symmetric hourglass TGV structure. The conventional through-via (10') is formed by penetrating from the first surface (101') to the second surface (102') of a glass substrate (100'), and the diameters of the upper opening on the first surface (101') side and the lower opening on the second surface (102') side are substantially the same. At the center of the through-via (10'), a minimum diameter portion (waist) (30') is located at the center of the thickness direction of the glass substrate (100'). In this symmetric structure, since the plating growth rate from both openings is the same during electroplating, the plating fronts on both sides are joined simultaneously at the minimum diameter portion (30'), making it easy for void (V) or seam defects to occur.

[0032] FIG. 2 illustrates a conventional conical TGV structure. The conventional conical through-via (10'') has a tapered structure in which the diameter decreases monotonically from a large-diameter opening on the first surface (101'') to a small-diameter opening on the second surface (102''), and there is no waist portion within. Since there is no waist portion, there is no location for a metal bridge to be formed during electroplating, and there are process constraints such as sealing one side to perform bottom-up plating or performing conformal plating on the sidewall.

[0034] Referring to FIG. 3, a glass substrate (1000) having a through-via according to a first embodiment of the present invention comprises a glass substrate (100) and a through-via (10) formed by penetrating from a first surface (101) to a second surface (102) of the glass substrate (100).

[0036] The glass substrate (100) may be made of borosilicate glass, aluminosilicate glass, or fused silica. The thickness (t) of the glass substrate (100) may be selected in the range of 100 μm or more and 500 μm or less, preferably 200 μm to 400 μm. The coefficient of thermal expansion (CTE) of the glass substrate (100) may be selected in the range of 3.0 ppm / °C to 4.0 ppm / °C, similar to the CTE of silicon (about 2.6 ppm / °C), thereby minimizing warpage and thermal stress caused by CTE mismatch with the semiconductor die.

[0038] The through via (10) includes a first opening (11) formed on the first surface (101) side of the glass substrate (100), a second opening (12) formed on the second surface (102) side, and a minimum diameter portion (30) located between the first opening (11) and the second opening (12). The diameter (D1) of the first opening (11) and the diameter (D2) of the second opening (12) are different from each other. In this embodiment, the diameter (D1) of the first opening (11) is designed to be larger than the diameter (D2) of the second opening (12), but the present invention is not limited thereto and also includes a configuration in which the diameter (D2) of the second opening (12) is larger than the diameter (D1) of the first opening (11).

[0040] The diameter (D1) of the first opening (11) can be selected from a range of 20 μm or more and 100 μm or less, and the diameter (D2) of the second opening (12) can be selected from a range of 10 μm or more and 80 μm or less. It is preferable that the ratio of the diameter (D1) of the first opening (11) to the diameter (D2) of the second opening (12) be 1.1:1 or more and 3:1 or less. For example, if the diameter (D1) of the first opening (11) is 60 μm and the diameter (D2) of the second opening (12) is 40 μm, the ratio of the diameters on both sides becomes 1.5:1.

[0042] The inner wall (13) of the through via (10) includes a first side wall section (14) from the first opening (11) to the minimum diameter section (30) and a second side wall section (15) from the second opening (12) to the minimum diameter section (30). Since the diameter (D1) of the first opening (11) is larger than the diameter (D2) of the second opening (12), the tapered profile of the first side wall section (14) and the tapered profile of the second side wall section (15) are asymmetric. Specifically, the first side wall section (14) has a tapered shape in which the diameter decreases from the large diameter opening (D1) to the minimum diameter section (30), and the second side wall section (15) has a tapered shape in which the diameter decreases from the small diameter opening (D2) to the minimum diameter section (30). The angle of inclination (α1) of the first side wall section (14) may be different from the angle of inclination (α2) of the second side wall section (15).

[0044] The diameter (Dw) of the minimum diameter portion (30) is preferably 30% or more and 80% or less of the diameter of the smaller of the first opening (11) and the second opening (12), i.e., the diameter (D2) of the second opening (12). For example, if D2 is 40 μm, the diameter (Dw) of the minimum diameter portion (30) is selected from a range of 12 μm or more and 32 μm or less.

[0046] The axial distance (La) from the first opening (11) to the minimum diameter portion (30) and the axial distance (Lb) from the second opening (12) to the minimum diameter portion (30) may be different from each other. If the diameter (D1) of the first opening (11) is larger than the diameter (D2) of the second opening (12), the minimum diameter portion (30) may be formed at a position deflected toward the second surface (102) side, i.e., the small diameter opening (12) side, from the center of the thickness direction of the glass substrate (100).

[0048] The aspect ratio of the through via (10) is defined as the value obtained by dividing the thickness (t) of the glass substrate (100) by the larger diameter (D1) of the first opening (11) and the second opening (12), and is preferably 5:1 or greater and 20:1 or less.

[0050] A conductive metal (40) is filled inside the through-via (10). The conductive metal (40) is preferably copper (Cu), but other conductive metals such as silver (Ag), gold (Au), aluminum (Al), tungsten (W), and nickel (Ni) may also be used. A bonding layer (41) and a seed metal layer (42) are sequentially interposed between the inner wall (13) of the through-via (10) and the conductive metal (40). The bonding layer (41) comprises at least one of Ti, TiN, TiW, Cr, and Ta, and has a thickness of 5 nm or more and 50 nm or less. The seed metal layer (42) is made of copper (Cu) or a copper alloy, and has a thickness of 50 nm or more and 500 nm or less. The adhesion layer (41) can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), and the seed metal layer (42) can be formed by PVD or electroless plating.

[0052] The electroplated growth bonding surface (50) of the conductive metal (40) is formed at the minimum diameter portion (30). The electroplated growth bonding surface (50) is an interface where the plating layer grown from the first opening (11) side and the plating layer grown from the second opening (12) side meet and bond at the minimum diameter portion (30). It is preferable that the electroplated growth bonding surface (50) be continuously closed along the circumferential direction of the minimum diameter portion (30) so that no voids are formed.

[0054] Referring to FIGS. 8 and 10, the electroplating growth process of an asymmetric opening TGV is described. It is preferable that the electroplating be performed in a kinetic-limited regime where the Thiele modulus (μ) is 1 or less. When electroplating is initiated, copper (Cu) metal grows inward from both openings on the seed metal layer (42). Since the diameter (D1) of the first opening (11) is larger than the diameter (D2) of the second opening (12), the amount of plating solution flowing in from the first opening (11) side is large, so the plating growth rate is fast, and the plating growth rate from the second opening (12) side is relatively slow. Due to this difference in growth rate, the large-diameter plating front (F1) approaches the minimum diameter portion (30) before the small-diameter plating front (F2), and pinching is initiated preferentially at the minimum diameter portion (30). Since the plating front (F2) on the small diameter side has not yet reached the minimum diameter portion (30) while pinching is in progress, the remaining space on the small diameter opening (12) side functions as a plating solution discharge path. Accordingly, the plating solution and gas that were trapped by simultaneous bonding in the conventional symmetrical structure are discharged through the remaining space on the small diameter side, and a void-free bonding surface (50) is formed.

[0056] Referring to FIG. 6, the through-via (10) according to the second embodiment of the present invention has a filled via structure. That is, the interior of the through-via (10) is completely filled with copper (Cu), which is a conductive metal (40), so that a continuous metal path is formed across the entire cross-section of the through-via (10). Since the filled via structure has minimal electrical resistance and maximum thermal conductivity, it is suitable for a high-current power supply path.

[0058] Referring to FIG. 7, a through-via (10) according to a third embodiment of the present invention has a conformal lining structure. A conductive metal (40) is formed as a conductive lining layer (43) conformally formed along the side wall of the through-via (10), and the inner space of the conductive lining layer (43) is filled with a dielectric material (44). The dielectric material (44) may be any one of SiO₂, polyimide, benzocyclobutene (BCB), or epoxy resin. The conformal lining structure can secure electrical connection while reducing copper usage and has the effect of reducing thermal stress caused by the difference in the coefficient of thermal expansion between copper and glass.

[0060] Referring to FIG. 11, a glass substrate (1000) according to the fourth embodiment of the present invention has a structure in which a resin buffer layer (60) is formed on at least one of the first surface (101) and the second surface (102) of the glass substrate (100). The resin buffer layer (60) is made of a polymer resin such as epoxy resin, polyimide, or ABF (Ajinomoto Build-up Film), and has a thickness of 5 μm or more and 30 μm or less. The coefficient of thermal expansion (CTE) of copper (Cu) is about 17 ppm / °C, which is significantly different from the CTE of the glass substrate (100) (about 3 to 4 ppm / °C). The resin buffer layer (60) is interposed between copper, which is a conductive metal (40), and the glass substrate (100), and by elastically buffering the thermal stress generated between the two during thermal expansion / contraction, it prevents cracks from occurring in the glass substrate (100).

[0062] Referring to FIG. 12, in a glass substrate (1000) according to the fifth embodiment of the present invention, a plurality of through-vias (10) are arranged in an array form on the glass substrate (100). Each of the plurality of through-vias (10) is oriented with the same directionality, with the first opening (11) on the first surface (101) side and the second opening (12) on the second surface (102) side. That is, in all through-vias (10), the large-diameter opening (D1) is located on the same surface (e.g., the first surface (101)), and the small-diameter opening (D2) is located on the opposite surface (e.g., the second surface (102)). Due to this consistent directional orientation, the plating growth bonding surface (50) of all vias is formed at the same depth during the electroplating process, thereby ensuring process uniformity.

[0064] Referring to FIG. 13, in a glass substrate (1000) according to a sixth embodiment of the present invention, a plurality of through-vias (10) include power supply vias (10a) and signal transmission vias (10b). The diameter of the first opening (11a) of the power supply via (10a) is larger than the diameter of the first opening (11b) of the signal transmission via (10b). For example, the diameter of the first opening (11a) of the power supply via (10a) is 80 μm and the diameter of the second opening (12a) is 50 μm, whereas the diameter of the first opening (11b) of the signal transmission via (10b) is 40 μm and the diameter of the second opening (12b) is 25 μm. The power supply via (10a) is designed with a large diameter to provide low electrical resistance and high current capacity, and the signal transmission via (10b) is designed with a small diameter to achieve high wiring density and low parasitic capacitance.

[0066] Referring to FIGS. 14 and 15, a glass substrate (1000) according to the seventh embodiment of the present invention is applied as an interposer for a semiconductor package. A semiconductor die (200) is mounted on a first surface (101) of the glass substrate (100), and a solder ball (70) or bump is formed on a second surface (102) for connection with a package substrate or a printed circuit board (PCB) (300). The semiconductor die (200) may include at least one of an AI computing processor, a GPU, and an HBM memory. A through-via (10) may be placed in a power supply path that supplies a supply voltage (VDD) or a ground voltage (VSS) to the semiconductor die (200). A plurality of semiconductor dies (200) are arranged in parallel in a horizontal direction on a first surface (101) of a glass substrate (100), and a signal transmission path between the plurality of semiconductor dies (200) can be formed through a redistribution layer (RDL) (80) of the glass substrate (100).

[0068] Referring to FIG. 16, a glass substrate (1000) according to the eighth embodiment of the present invention is applied as a core substrate of a flip-chip ball grid array (FC-BGA). A build-up layer (90) is formed on both sides of the glass substrate (100), and a fine wiring pattern and a blind via are formed within the build-up layer (90) and are electrically connected to a through-via (10).

[0070] Referring to FIG. 17, the glass substrate (1000) according to the ninth embodiment of the present invention is a glass panel (100P) for panel level packaging (PLP), and the size of the glass panel (100P) is at least 300 mm on one side. Preferably, it is a large-area panel of at least 510 mm × 515 mm. A plurality of package regions are defined on the glass panel (100P), and a plurality of through-vias (10) are formed in each package region.

[0072] Referring to FIG. 18, a method for manufacturing a through-via according to the 10th embodiment of the present invention is described. First, a laser modification process is performed on a glass substrate (100) to form a damage track in the thickness direction. Laser modification can be performed using a picosecond or femtosecond pulsed laser. Subsequently, the glass substrate (100) is immersed in an etching solution to perform wet etching. The etching solution may include any one of hydrofluoric acid (HF), potassium hydroxide (KOH), sodium hydroxide (NaOH), or ammonium fluoride (NH₄F).

[0074] In this embodiment, in order to form the diameter (D1) of the first opening (11) and the diameter (D2) of the second opening (12) differently from each other, at least one of the laser irradiation conditions and etching conditions is applied differently on the first surface (101) side and the second surface (102) side. For example, if the laser beam energy on the first surface (101) side is set higher than on the second surface (102) side, the degree of deformation of the damage track on the first surface (101) side increases, the etching speed increases, and as a result, the diameter (D1) of the first opening (11) is formed to be larger than the diameter (D2) of the second opening (12). Alternatively, the laser irradiation conditions may be maintained identically on both sides, but the etching time on the first surface (101) side may be applied longer than on the second surface (102) side to achieve a difference in the diameters of the openings on both sides. As another alternative, etching can be performed simultaneously on both sides, but the etching speed of one side can be selectively controlled by applying a masking or protective layer to one side.

[0076] After the through-via (10) is formed, a conductive metal (40) is filled into the interior of the through-via (10) by an electroplating process. The electroplating is performed using a copper (Cu) electrolyte, and the electrolyte consists of copper sulfate (CuSO₄·5H₂O), sulfuric acid (H₂SO₄), and chloride ions (Cl₃). -It includes ), and organic additives (suppressor, accelerator, leveler). Electroplating is preferably performed in a kinetic-limited regime where the Thiele modulus (μ) is 1 or less, so that the conductive metal (40) is pinched first in the minimum diameter portion (30) and the remaining space is filled by conformal plating. Explanation of the symbols

[0078] 10, 10', 10'': Penetrating via 10a: Power supply via 10b: via for signal transmission 11, 11a, 11b: First opening 12, 12a, 12b: Second opening 13: Inner wall 14: First sidewall section 15: Second sidewall section 30, 30': Minimum diameter (waist) 40: Conductive metal 41: Adhesion layer 42: Seed metal layer 43: Conductive lining layer 44: Genomic materials 50: Electroplated growth bonding surface 60: Resin buffer layer 70: Solder ball 80: Redistribution Layer (RDL) 90: Build-up layer 100, 100', 100'': Glass substrate 100P: Glass panel 101, 101', 101'': Page 1 102, 102', 102'': Page 2 200: Semiconductor die 300: Package board / Printed circuit board (PCB) 1000: Glass substrate having through-vias D1: Diameter of the first opening D2: Diameter of the second opening Dw: Diameter of the minimum diameter part La: Axial distance from the first opening to the minimum diameter portion Lb: Axial distance from the second opening to the minimum diameter portion t: thickness of the glass substrate α1: Angle of inclination of the first sidewall section α2: Angle of inclination of the second sidewall section F1: Large diameter side plating front F2: Small diameter side plating front V: Void

Claims

Claim 1 A glass substrate; and a through-via formed by penetrating from a first surface to a second surface of the glass substrate, wherein the through-via comprises a first opening on the first surface side, a second opening on the second surface side, and a minimum diameter portion located between the first opening and the second opening, wherein the diameter of the first opening and the diameter of the second opening are different from each other, so that the sidewall profile between the first opening and the minimum diameter portion and the sidewall profile between the second opening and the minimum diameter portion are asymmetric, and wherein a conductive metal is filled inside the through-via, and an electroplated growth bonding surface of the conductive metal is formed at the minimum diameter portion. Claim 2 A glass substrate having a through-via according to claim 1, characterized in that the diameter of the first opening is larger than the diameter of the second opening, and the minimum diameter portion is formed at a position deflected toward the second surface side from the center of the thickness direction of the glass substrate. Claim 3 A glass substrate having through-vias, characterized in that, in claim 1, the ratio of the diameter of the first opening to the diameter of the second opening is 1.1:1 or greater and 3:1 or less. Claim 4 A glass substrate having a through-via, characterized in that, in claim 1, the diameter of the minimum diameter portion is 30% or more and 80% or less of the smaller diameter between the first opening and the second opening. Claim 5 A glass substrate having through vias, characterized in that, in claim 1, the axial distance from the first opening to the minimum diameter portion and the axial distance from the second opening to the minimum diameter portion are different from each other. Claim 6 A glass substrate having through-vias according to claim 1, characterized in that the aspect ratio of the through-vias is 5:1 or greater and 20:1 or less. Claim 7 A glass substrate having through-vias, characterized in that, in claim 1, the diameter of the first opening is 20 μm or more and 100 μm or less, and the diameter of the second opening is 10 μm or more and 80 μm or less. Claim 8 A glass substrate having through-vias, characterized in that, in claim 1, the thickness of the glass substrate is 100 μm or more and 500 μm or less. Claim 9 A glass substrate having a through-via, characterized in that, in claim 1, the conductive metal is copper (Cu), and the interior of the through-via is a filled via structure in which the copper is completely filled. Claim 10 A glass substrate having a through-via according to claim 1, wherein the conductive metal is a conductive lining layer conformally formed along the sidewall of the through-via, and the inner space of the conductive lining layer is filled with a dielectric material. Claim 11 A glass substrate having a through-via according to claim 1, wherein an adhesion layer and a seed metal layer are sequentially interposed between the sidewall of the through-via and the conductive metal, and the adhesion layer comprises at least one of Ti, TiN, TiW, Cr, and Ta. Claim 12 A glass substrate having through vias, characterized in that, in claim 1, the electroplated growth bonding surface is continuously closed along the circumferential direction of the minimum diameter portion so as not to form a void. Claim 13 A glass substrate having through vias, characterized in that, in the first paragraph, the plating growth rate from the first opening side and the plating growth rate from the second opening side are different from each other due to the difference in diameter between the first opening and the second opening, and the position of the plating growth bonding surface is determined by the difference in diameter. Claim 14 A glass substrate having through-vias, wherein, in claim 1, a resin buffer layer is formed on at least one of the first surface and the second surface of the glass substrate, and the resin buffer layer buffers thermal stress caused by the difference in the coefficient of thermal expansion between the conductive metal and the glass substrate. Claim 15 A glass substrate having through-vias according to claim 1, characterized in that the glass substrate is one of borosilicate glass, aluminosilicate glass, and fused silica. Claim 16 A glass substrate having through-vias according to claim 1, wherein a plurality of through-vias are arranged in an array form on the glass substrate, and each of the plurality of through-vias is oriented in the same directionality with the first opening on the first surface side and the second opening on the second surface side. Claim 17 A glass substrate having through-vias according to claim 16, wherein the plurality of through-vias include power supply vias and signal transmission vias, and the diameter of the first opening of the power supply via is larger than the diameter of the first opening of the signal transmission via. Claim 18 A glass substrate having through-vias, wherein, in claim 1, the glass substrate serves as an interposer for a semiconductor package, wherein a semiconductor die is mounted on the first surface and a bump or solder ball for connection with a package substrate or a printed circuit board is formed on the second surface. Claim 19 A glass substrate having through-vias, wherein, in claim 18, the semiconductor die comprises at least one of an AI computing processor, a GPU, and an HBM memory, and the through-vias are disposed in a power supply path that supplies a supply voltage or a ground voltage to the semiconductor die. Claim 20 A glass substrate having through-vias, characterized in that, in claim 18, a plurality of semiconductor dies are arranged in parallel in a horizontal direction on the first surface of the interposer, and a signal transmission path between the plurality of semiconductor dies is formed through a redistribution layer (RDL) of the glass substrate. Claim 21 A glass substrate having through-vias, characterized in that, in claim 1, the glass substrate is a core substrate of a flip-chip ball grid array (FC-BGA). Claim 22 A glass substrate having through-vias, characterized in that, in claim 1, the glass substrate is a glass panel for panel level packaging (PLP), and the size of the glass panel has a side length of 300 mm or more. Claim 23 A glass substrate having a through-via according to claim 1, wherein the through-via is formed by a combination of laser modification and wet etching, and wherein the diameter of the first opening and the diameter of the second opening are formed differently by applying at least one of the laser irradiation conditions and etching conditions differently on the first side and the second side. Claim 24 A glass substrate having through-vias, characterized in that, in claim 1, the electroplating of the conductive metal is performed in a kinetic-limited regime in which the Thiele modulus (μ) is 1 or less, and the conductive metal is preferentially pinched at the minimum diameter portion, after which the remaining space is filled by conformal plating. Claim 25 A method for manufacturing a glass substrate having a through-via, comprising: a step of forming a through-via penetrating from a first surface to a second surface of a glass substrate, wherein the diameter of a first opening on the first surface side and the diameter of a second opening on the second surface side are different from each other, and a minimum diameter portion is located between the first opening and the second opening; and a step of filling the interior of the through-via with a conductive metal by electroplating, wherein plating layers growing from the first opening side and the second opening side, respectively, are joined at the minimum diameter portion to form a growth bonding surface.

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