Display Device And Transmission Charging Deviation Compensation Method Thereof

Abstract

A display device according to the present embodiment includes a display panel having a plurality of 1-pixel lines composed of a plurality of pixels; a gate driver that applies a gate signal to the 1-pixel lines; and a source driver that applies a data signal to the 1-pixel lines. The source driver includes a plurality of amplifier circuits corresponding to a plurality of source output channels, a plurality of output switches connected between the amplifier circuits and the source output channels, a source output control circuit that applies sequentially delayed source output enable signals to the output switches to delay the output section of the data signal in units of source output channels according to the delay degree of the gate signal, and an offset control circuit that applies an offset control signal generated based on the sequentially delayed source output enable signals to the amplifier circuits to switch the offset of each of the amplifier circuits within the masking section of the data signal.

Description

Technology Field

[0001] This specification relates to a display device and a method for compensating for its charge deviation. Background Technology

[0002] The display device includes a display panel having a plurality of pixels formed therein, a gate driver that supplies a scan signal to the display panel, and a source driver that supplies a data signal to the display panel. The display panel is provided with a plurality of pixel lines, and each pixel line consists of a plurality of pixels. While a gate signal is applied to one pixel line, the pixels of that pixel line simultaneously charge a data signal.

[0003] Typically, gate signals applied in the horizontal direction are delayed due to the internal load of the display panel, and the amount of delay in the gate signal increases as it moves further away from the gate driver. For example, the amount of delay in the gate signal is greater in the center of the display panel located relatively far from the gate driver compared to the edge of the display panel located relatively close to the gate driver.

[0004] Due to the delay deviation of these gate signals, the pixel charge amount for the same data signal differs between the edge and center portions of the display panel, and as a result, a luminance imbalance occurs between the edge and center portions of the display panel. The luminance imbalance caused by the charge deviation by location on the display panel degrades image quality. The problem to be solved

[0005] Accordingly, the present embodiment provides a display device capable of compensating for a charging deviation by position of a display panel and a charging deviation compensation method. means of solving the problem

[0006] A display device according to the present embodiment includes a display panel having a plurality of 1-pixel lines composed of a plurality of pixels; a gate driver that applies a gate signal to the 1-pixel lines; and a source driver that applies a data signal to the 1-pixel lines. The source driver includes a plurality of amplifier circuits corresponding to a plurality of source output channels, a plurality of output switches connected between the amplifier circuits and the source output channels, a source output control circuit that applies sequentially delayed source output enable signals to the output switches to delay the output section of the data signal in units of source output channels according to the delay degree of the gate signal, and an offset control circuit that applies an offset control signal generated based on the sequentially delayed source output enable signals to the amplifier circuits to switch the offset of each of the amplifier circuits within the masking section of the data signal. Effects of the invention

[0007] This embodiment has the following effects.

[0008] In this embodiment, since the output section of the data signal is delayed in units of source output channels according to the delay level of the gate signal, the image quality can be improved by compensating for the charging deviation at each position of the display panel.

[0009] In this embodiment, an offset control signal generated based on sequentially delayed source output enable signals is applied to the amplifier circuits, thereby changing the offset of each amplifier circuit from (+) to (-) or vice versa, which can reduce the effect of the amplifier offset.

[0010] In this embodiment, by changing the offset of each amplifier circuit from (+) to (-) or vice versa within the masking interval of the data signal, offset switching noise can be prevented from being reflected in the source output.

[0011] The effects according to this specification are not limited to those exemplified above, and a wider variety of effects are included within this specification. Brief explanation of the drawing

[0012] FIG. 1 is a block diagram showing a display device according to the present embodiment. Figure 2 is a diagram showing that a delay deviation of the gate signal occurs between the edge portion and the center portion of the display panel. Figure 3 is a diagram showing a concept for compensating for a deviation in the charge amount of a data signal caused by a delay deviation of a gate signal. Figure 4 is a diagram showing an example of a delay deviation of the gate signal occurring in a display panel. FIGS. 5A and FIGS. 5B are drawings showing methods for compensating for the gate delay deviation of FIG. 4 by varying the source delay according to location. Figure 6 is a diagram showing another example of a delay deviation of the gate signal occurring in a display panel. FIGS. 7A and 7B are diagrams showing methods to compensate for the positional gate delay deviation of FIG. 6 by varying the source delay by position. FIG. 8 is a diagram showing the configuration of a source driving chip for implementing the source delay illustrated in FIG. 5b or FIG. 7b. Figure 9 is a block diagram showing the output buffer circuit of Figure 8. FIG. 10 is a circuit diagram showing an output buffer connected to the first source channel of FIG. 9. Figure 11 is a driving waveform of the output buffer of Figure 10. FIG. 12a is an operation state diagram of an output buffer corresponding to the first section of FIG. 10. FIG. 12b is an operation state diagram of an output buffer corresponding to the second section of FIG. 10. FIG. 12c is an operation state diagram of the output buffer corresponding to the third section of FIG. 10. FIG. 12d is an operation state diagram of the output buffer corresponding to the fourth section of FIG. 10. FIG. 13 is a diagram showing an example of the connection configuration between the offset control circuit, the source output control circuit, and the output buffer circuit of FIG. 8. Figure 14 is a driving waveform diagram for making the source delay different by position in the output buffer circuit of Figure 13. Figure 15 is a diagram showing INVC noise generated during the INVC transition timing of Figure 14. Figure 16 is another driving waveform for reducing INVC noise by varying the source delay by position in the output buffer circuit of Figure 13. Figure 17 is a diagram showing that INVC noise is reduced in the INVC transition timing of Figure 16. Figure 18 is another driving waveform diagram for reducing INVC noise by varying the source delay by position in the output buffer circuit of Figure 13. Figure 19 is a diagram showing that INVC noise is reduced in the INVC transition timing of Figure 18. FIG. 20 is a diagram showing another example of the connection configuration between the offset control circuit, the source output control circuit, and the output buffer circuit of FIG. 8. FIG. 21 is a driving waveform diagram for reducing INVC noise by varying the source delay by position in the output buffer circuit of FIG. 20. Figure 22 is a diagram showing that INVC noise is reduced in the INVC transition timings of Figure 21. FIG. 23 is a diagram showing another example of the connection configuration between the offset control circuit, the source output control circuit, and the output buffer circuit of FIG. 8. FIG. 24 is a driving waveform diagram for reducing INVC noise by varying the source delay by position in the output buffer circuit of FIG. 23. Specific details for implementing the invention

[0013] The advantages and features of this specification and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below but may be implemented in various different forms; these embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention, and this specification is defined only by the scope of the claims.

[0014] Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of this specification are exemplary and are not limited to the details illustrated in this specification. Throughout the specification, the same reference numerals refer to the same components. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it includes cases where it includes the plural unless specifically stated otherwise.

[0015] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0016] In the case of describing a positional relationship, for example, when the positional relationship between two parts is described using expressions such as 'on top of,' 'above,' 'below,' or 'next to,' one or more other parts may be located between the two parts unless 'immediately' or 'directly' is used.

[0017] "First," "second," etc., may be used to describe various components, but these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of this specification.

[0018] Hereinafter, embodiments of the present specification will be described in detail with reference to the attached drawings. In the following description, if it is determined that a detailed description of a known function or configuration related to the present specification may unnecessarily obscure the essence of the present specification, such detailed description will be omitted.

[0019] FIG. 1 is a block diagram showing a display device according to the present embodiment. FIG. 2 is a diagram showing a delay deviation of the gate signal between the edge portion and the center portion of the display panel. FIG. 3 is a diagram showing a concept for compensating for a deviation in the charge amount of a data signal caused by the delay deviation of the gate signal.

[0020] A display panel (100) includes a screen (AA) on which an input image is reproduced. The screen (AA) includes a pixel array on which pixel data (hereinafter referred to as "image data") (DATA) of the input image is displayed. The pixel array includes a plurality of data lines (DL), a plurality of gate lines (GL) intersecting the data lines (DL), and a plurality of pixels.

[0021] Pixels can be arranged on the screen (AA) in a matrix form defined by data lines (DL) and gate lines (GL). In addition to the matrix form, pixels can be arranged on the screen (AA) in various ways, such as sharing pixels that emit the same color, stripe form, diamond form, etc.

[0022] A pixel array includes pixel columns and pixel lines (L1–Ln) that intersect the pixel columns. A pixel column includes pixels arranged along the y-axis direction. A pixel line includes pixels arranged along the x-axis direction. A vertical period is the time required to write one frame's worth of image data to all pixels on the screen. A horizontal period is the time obtained by dividing one frame period by the number of pixel lines (L1–Ln). A horizontal period is the time required to write one pixel line's worth of image data that shares a gate line (GL) to the pixels of one pixel line.

[0023] Each pixel may include a red (Red, R) subpixel (101), a green (Green, G) subpixel (101), and a blue (Blue, B) subpixel (101) for color implementation. Each pixel may also include a white subpixel (101).

[0024] In the case of an organic light-emitting display device, the pixel circuit may include a light-emitting element, a driving element, one or more switching elements, and a capacitor. The light-emitting element may be implemented as an Organic Light Emitting Diode (OLED). The current of the OLED may be controlled according to the gate-source voltage of the driving element. The driving element and the switching element may be implemented as transistors. The semiconductor layer of the transistor may include amorphous silicon or polysilicon. At least some of the semiconductor layers of the transistors may include oxide. The pixel circuit is connected to data lines (DL) and gate lines (GL). In FIG. 1, "D1 to D3" indicated within the circles are data lines, and "Gn-2 to Gn" are gate lines. Each of the subpixels (101) in FIG. 1 includes the same pixel circuit.

[0025] The display panel driver includes a source driver (110) and a gate driver (120). The display panel driver writes image data (DATA) to the pixels of the display panel (100) under the control of the timing controller (130).

[0026] The source driver (110) generates a data voltage by converting image data (DATA) received from the timing controller (130) into a gamma-compensated voltage using a digital-to-analog converter (hereinafter referred to as "DAC"). The source driver (110) supplies the data voltage to the data lines (DL). The data voltage is supplied to the data lines (DL) and applied to the driving element through the switch element of each subpixel (101). The source driver (110) can be implemented with a plurality of source driving chips (SIC) mounted on a conductive film (300) as shown in FIG. 2. The conductive film (300) electrically connects the source printed circuit board (200) and the display panel (100).

[0027] A gate driver (120) may be formed in a bezel area (BZ) outside the screen where an image is not displayed on the display panel (100). The gate driver (120) sequentially supplies a gate signal synchronized with the data voltage to gate lines (GL) under the control of a timing controller (130). The gate signal simultaneously activates the pixels of the pixel line where the data voltage is charged. The gate driver (120) outputs the gate signal and shifts the gate signal using one or more shift registers. The gate signal may include one or more scan signals.

[0028] The gate signal applied to the gate line (GL) is delayed due to the internal load of the display panel, and the amount of delay of the gate signal increases as it moves further away from the gate driver (120). For example, as shown in FIG. 2, the amount of delay of the gate signal is greater in the center portion of the display panel (100) located relatively far from the gate driver (120) compared to the edge portion of the display panel (100) located relatively close to the gate driver (120).

[0029] If a delay deviation occurs in the gate signal, the pixel charge amount (CA1) of the edge portion of the display panel (100), which is targeted at a source output of the same size (i.e., data voltage), becomes larger than the pixel charge amount (CA2) of the sensor portion of the display panel (100), and as a result, a brightness imbalance may occur between the edge portion and the center portion of the display panel (100) (see Case A of FIG. 3).

[0030] To reduce the charge deviation by position of the display panel, the source driver (110) can adjust the source output timing differently for each position of the display panel (100). The source driver (110) can delay the source output timing according to the delay level of the gate signal. For example, as in case B of FIG. 3, the source driver (110) can delay the source output timing by “Td” at the center portion compared to the edge portion of the display panel (100), thereby making the pixel charge amount (CA3) at the edge portion of the display panel (100) and the pixel charge amount (CA4) at the sensor portion of the display panel (100) equal to each other.

[0031] The timing controller (130) receives video data (DATA) and a timing signal synchronized with the video data (DATA) from a host system not shown. The timing signal includes a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a clock signal (DCLK), and a data enable signal (DE). The vertical synchronization signal (Vsync) defines a vertical period. The horizontal synchronization signal (Hsync) defines a horizontal period. The data enable signal (DE) defines the time during which the video data (DATA) is transmitted during the vertical period or the horizontal period. Since the vertical period and the horizontal period can be determined by counting the data enable signal (DE), the vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) may be omitted.

[0032] The timing controller (130) generates a source timing control signal (DDC) for controlling the operation timing of the data driver (110) and a gate timing control signal (GDC) for controlling the operation timing of the gate driver (120) using timing signals (Vsync, Hsync, DE) received from the host system. The source timing control signal (DDC) may include a source sampling clock for sampling image data (DATA) and a source output enable signal for setting the output timing of the data voltage (i.e., source output timing).

[0033] The timing controller (130) can control the operation timing of the display panel driving unit (110, 120) by multiplying the input frame frequency by i (i is a natural number) to a frame frequency of input frame frequency × i Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) system and 50 Hz in the PAL (Phase-Alternating Line) system.

[0034] The host system may be any one of a TV (Television), set-top box, navigation system, personal computer (PC), home theater, automotive display system, mobile device, or wearable device. In mobile devices and wearable devices, the source driver (110), timing controller (130), level shifter (140), etc., may be integrated into a single drive integrated circuit.

[0035] The level shifter (140) converts the voltage of the gate timing control signal (GDC) output from the timing controller (130) into a gate high voltage (VGH) and a gate low voltage (VGL) and supplies them to the gate driver (120). The low level voltage of the gate timing control signal (GDC) is converted into the gate low voltage (VGL), and the high level voltage of the gate timing control signal (GDC) is converted into the gate high voltage (VGH).

[0036] The timing controller (130) can transmit image data (DATA) to source driving chips (SIC) through an internal interface circuit. The internal interface circuit can be implemented as an Embedded Clock Point to Point Interface (EPI), but is not limited thereto.

[0037] FIG. 4 is a diagram showing an example of a delay deviation of a gate signal occurring in a display panel. FIG. 5a and FIG. 5b are diagrams showing methods to compensate for the gate delay deviation of FIG. 4 by varying the source delay by position. FIG. 6 is a diagram showing another example of a delay deviation of a gate signal occurring in a display panel. FIG. 7a and FIG. 7b are diagrams showing methods to compensate for the gate delay deviation by position of FIG. 6 by varying the source delay by position.

[0038] Referring to FIGS. 4 to 7b, a plurality of source driving chips (SIC1 to SIC12) may be used to drive a large-area display panel. Each of the source driving chips (SIC1 to SIC12) may have one group of source output channels. One group of source output channels defines one tap area. Accordingly, a plurality of tap areas (TA1 to TA12) may be defined by the plurality of source driving chips (SIC1 to SIC12).

[0039] Figure 4 shows an example where the delay deviation of the gate signal by position on the display panel is small. And, Figure 6 shows an example where the delay deviation of the gate signal by position on the display panel is large.

[0040] FIGS. 5a and FIGS. 7a show the result of applying a source delay corresponding to the delay level of the gate signal at each position only between the source driving chips (SIC1 to SIC12). In FIGS. 5a and FIGS. 7a, the source driving chips (SIC1 to SIC12) are subjected to different source delays, but the source output channels within the same source driving chip are subjected to the same source delay. Therefore, the amount of source delay may be discontinuous and interrupted in adjacent tap regions (TA1 to TA12).

[0041] In contrast, FIGS. 5b and 7b show the result of applying a source delay corresponding to the delay level of the gate signal at each position between source driving chips (SIC1~SIC12) and also between the source output channels of each source driving chip. In the case of FIGS. 5b and 7b, not only the source driving chips (SIC1~SIC12) but also the source output channels within the same source driving chip are subjected to different source delays. Therefore, the amount of source delay can be continuous in adjacent tap regions (TA1~TA12).

[0042] When the delay deviation of the gate signal by position is small as in Fig. 4, there is no significant difference between the inter-chip delay adjustment result as in Fig. 5a and the inter-chip and intra-chip delay adjustment result as in Fig. 5b.

[0043] However, when the delay deviation of the gate signal by position is large as shown in Fig. 6, there is a large difference between the inter-chip delay adjustment result as shown in Fig. 7a and the inter-chip and intra-chip delay adjustment result as shown in Fig. 7b. Therefore, in this case, a source delay corresponding to the delay degree of the gate signal by position as shown in Fig. 7b must be applied not only between adjacent source driving chips but also between source output channels within the same source driving chip.

[0044] In the following description of embodiments, various examples are described in which source delays between source output channels are differentially applied in a source driving chip.

[0045] FIG. 8 is a diagram showing the configuration of a source driver chip for implementing the source delay (inter-chip and intra-chip delay) illustrated in FIG. 5b or FIG. 7b. FIG. 9 is a block diagram showing the output buffer circuit of FIG. 8.

[0046] Referring to FIGS. 8 and 9, the source driving chip (SIC) includes a shifter register (11), a first latch (12), a second latch (13), a digital-to-analog converter (14), an output buffer circuit (15), an offset control circuit (16), and a source output control circuit (17).

[0047] The shifter register (11) receives image data (DATA) through the interface wiring and samples bits of the image data (DATA) according to the source sampling clock (SSC) and provides them to the first latch (12).

[0048] The first latch (12) latches bits of sampled image data (DATA) and then provides the latched image data (DATA) to the second latch (13).

[0049] The second latch (13) temporarily stores the latched image data (DATA) and then outputs it to the digital-to-analog converter (14) according to the source output enable signal (SOE).

[0050] The digital-to-analog converter (14) maps the image data (DATA) input from the second latch (13) to gamma compensation voltages (GMA) to generate an analog data voltage (Vdata) and provides this data voltage (Vdata) to the output buffer circuit (15).

[0051] The output buffer circuit (15) includes a plurality of output buffers (BUF) corresponding to a plurality of source output channels (CH1 to CH20). The output buffers (BUF) include a plurality of amplifier circuits (CAMP) corresponding to the source output channels (CH1 to CH20) and a plurality of output switches (OSW) connected between the amplifier circuits (CAMP) and the source output channels (CH1 to CH20).

[0052] The source output control circuit (17) generates sequentially delayed source output enable signals (DSOE) by applying a preset in-chip delay to the source output enable signal (SOE). The source output control circuit (17) applies the sequentially delayed source output enable signals (DSOE) to output switches (OSW) to delay the output section of the data voltage (Vdata) in units of source output channels according to the delay level of the gate signal. Accordingly, even when the delay deviation of the gate signal by position on the display panel is large, the charge deviation for the data voltage (Vdata) can be effectively compensated.

[0053] The offset control circuit (16) generates an offset control signal (INVC) based on sequentially delayed source output enable signals (DSOE). The offset control circuit (16) applies the offset control signal (INVC) to the amplifier circuits (CAMP) and switches the offset of each amplifier circuit (CAMP) from (+) to (-) or vice versa within the masking interval of the data voltage (Vdata), thereby eliminating the effect of the amplifier offset on the source output during driving. The offset control circuit (16) switches the offset of each amplifier circuit (CAMP) in accordance with the transition timing of the offset control signal (INVC). Since offset switching noise may be reflected in the source output when the offset of the amplifier circuits (CAMP) is switched, it is desirable that the offset control signal (INVC) transition within the interval where the output switch (OSW) is turned off, that is, within the masking interval of the data voltage (Vdata). The offset of each amplifier circuit (CAMP) is changed from (+) to (-) or from (-) to (+) in synchronization with the transition timing of the offset control signal (INVC).

[0054] The masking period and output period of the data voltage (Vdata) can constitute one horizontal period for the operation of one pixel line. The offset control signal (INVC) corresponding to the same source output channel is transitioned with a period of one horizontal period, thereby allowing the amplifier offset to be changed complementarily during driving. For example, the offset of each amplifier circuit (CAMP) can be changed from (+) to (-) in the masking period within the N-1 horizontal period and from (-) to (+) in the masking period within the N horizontal period, synchronized with the transition timing of the offset control signal (INVC). Through this periodic change of the amplifier offset, source output distortion caused by the amplifier offset can be prevented.

[0055] FIG. 10 is a circuit diagram showing an output buffer connected to the first source channel of FIG. 9.

[0056] Referring to FIG. 10, the output buffer (BUF) connected to the first source channel (CH1) includes an amplifier circuit (CAMP) and an output switch (OSW).

[0057] The amplifier circuit (CAMP) may be equipped with an amplifier (AMP), an input switch (ISW), a first feedback switch (LSW1), and a second feedback switch (LSW2).

[0058] The amplifier (AMP) has a first input terminal (1), a second input terminal (2), and an output terminal (3). Either the first input terminal (1) or the second input terminal (2) may be a (-) input terminal, and the other may be a (+) input terminal. The output terminal (3) is connected to an output switch (OSW) through a first node (NA). The output switch (OSW) is connected to a first source channel (CH1) through a second node (NB) and is turned on / off according to a delayed source output enable signal (DSOE).

[0059] The input switch (ISW) selectively couples the input of the data voltage (Vdata) to the first input terminal (1) and the second input terminal (2) according to the offset control signal (INVC).

[0060] The first feedback switch (LSW1) couples or decoups the first input terminal (1) and the output terminal (3) according to the offset control signal (INVC).

[0061] The second feedback switch (LSW2) decouples or couples the second input terminal (2) and the output terminal (3) according to the offset control signal (INVC).

[0062] The first feedback switch (LSW1) and the second feedback switch (LSW2) are turned on / off in opposite directions and alternate on / off operations with a horizontal period. While the input of the data voltage (Vdata) and the first input terminal (1) are coupled, the first feedback switch (LSW1) is turned off and the second feedback switch (LSW2) is turned on. Conversely, while the input of the data voltage (Vdata) and the second input terminal (2) are coupled, the first feedback switch (LSW1) is turned on and the second feedback switch (LSW2) is turned off.

[0063] FIG. 11 is a driving waveform diagram of the output buffer of FIG. 10. FIG. 12a to 12d are operation state diagrams of the output buffer corresponding to the first to fourth sections of FIG. 10.

[0064] Referring to FIG. 11, the masking interval (MSK) and output interval (OP) of the data voltage (Vdata) can be defined by the delayed source output enable signal (DSOE). The masking interval (MSK) of the data voltage (Vdata) is the high level (H) interval of the delayed source output enable signal (DSOE), and the output interval (OP) of the data voltage (Vdata) is the low level (L) interval of the delayed source output enable signal (DSOE). Since the output switch (OSW) is turned off during the high level (H) interval of the delayed source output enable signal (DSOE), the source output is masked. The offset control signal (INVC) transitions from a low level (L) to a high level (H) within the masking interval (MSK) of the data voltage (Vdata). Since the output switch (OSW) is turned on during the low level (L) period of the delayed source output enable signal (DSOE), the source output is enabled.

[0065] Referring to FIG. 11, the driving sequence of the output buffer can be divided into first to fourth intervals (P1, P2, P3, P4) by a delayed source output enable signal (DSOE) and an offset control signal (INVC). The first interval (P1) is included in the (N-1) horizontal period, and the second, third, and fourth intervals (P2, P3, P4) can be included in the Nth horizontal period.

[0066] Referring to FIG. 12a, in the first section (P1), the input switch (ISW) couples the input of the (N-1) data voltage (Vdata) to the first input terminal (1) according to the low-level (L) offset control signal (INVC). Then, according to the low-level (L) offset control signal (INVC), the first feedback switch (LSW1) is turned off and the second feedback switch (LSW2) is turned on. The second feedback switch (LSW2) couples the second input terminal (2) and the output terminal (3). At this time, the (N-1) data voltage (Vdata) is buffered in the amplifier circuit (CAMP) and then applied to the output switch (OSW).

[0067] In the first section (P1), the output switch (OSW) is turned on according to a delayed source output enable signal (DSOE) of low level (L), and the (N-1) data voltage (Vdata) is output to the data line through the first source channel (CH1).

[0068] Referring to FIG. 12b, in the second section (P2), the input switch (ISW) and the first and second feedback switches (LSW1, LSW2) maintain the operating state of the first section (P1) according to the offset control signal (INVC) of the low level (L).

[0069] In the second section (P2), the output switch (OSW) is turned off according to a delayed source output enable signal (DSOE) of high level (H), thereby masking the source output.

[0070] Referring to FIG. 12c, in the third section (P3), the output switch (OSW) is turned off according to the delayed source output enable signal (DSOE) at a high level (H), thereby masking the source output. In this third section (P3), when the offset control signal (INVC) transitions from a low level (L) to a high level (H), the operating state of the input switch (ISW) and the first and second feedback switches (LSW1, LSW2) changes. In the third section (P3), the input switch (ISW) couples the input of the (N) data voltage (Vdata) to the second input terminal (2) according to the offset control signal (INVC) at a high level (H). Then, according to the offset control signal (INVC) at a high level (H), the first feedback switch (LSW1) is turned on and the second feedback switch (LSW2) is turned off. The first feedback switch (LSW1) couples the first input terminal (1) and the output terminal (3). At this time, the (N) data voltage (Vdata) is buffered in the amplifier circuit (CAMP) and then applied to the output switch (OSW).

[0071] Referring to FIG. 12d, in the fourth section (P4), the input switch (ISW) and the first and second feedback switches (LSW1, LSW2) maintain the operating state of the third section (P3) according to the offset control signal (INVC) of the high level (H).

[0072] In the fourth section (P4), the output switch (OSW) is turned on according to the delayed source output enable signal (DSOE) of low level (L), and the (N) data voltage (Vdata) is output to the data line through the first source channel (CH1).

[0073] FIG. 13 is a diagram showing an example of the connection configuration between the offset control circuit, the source output control circuit, and the output buffer circuit of FIG. 8.

[0074] Referring to FIG. 13, the output buffer circuit (15) may include 20 amplifier circuits (CAMP) corresponding to the first to 20 source output channels (CH1 to CH20) and 20 output switches (OSW).

[0075] The source output control circuit (17) applies 20 sequentially delayed source output enable signals (DSOE1 to DSOE20) individually to 20 output switches (OSW) to delay the source output section in units of source output channels so as to correspond to the delay level of the gate signal. The 20 source output enable signals (DSOE1 to DSOE20) may be composed of 20 sequentially delayed masking sections and 20 sequentially delayed output sections.

[0076] The offset control circuit (16) can apply an offset control signal (INVC) that transitions at common timing to 20 amplifier circuits (CAMP) to switch the offset of each amplifier circuit (CAMP) from (+) to (-) or vice versa. The common timing can be pre-designed as a specific timing within the time allocated for the operation of the first to 20 source output channels (CH1~CH20).

[0077] FIG. 14 is a driving waveform diagram for varying the source delay by position in the output buffer circuit of FIG. 13. FIG. 15 is a diagram showing INVC noise generated during the INVC transition timing of FIG. 14.

[0078] Referring to FIG. 14, the offset control circuit (16) can transition the offset control signal (INVC) at a common timing that overlaps only some of the 20 masking intervals (MSK). In this case, offset switching noise (hereinafter referred to as INVC noise) may not be masked in source output channels where the common timing overlaps with the output interval (OP) and may be mixed into the source output.

[0079] Referring to FIG. 15, INVC noise is reflected in the first node (NA in FIG. 10) of the amplifier circuit (CAMP) when the amplifier offset is changed, and in the case of source output channels where the output switches (OSW) are turned on, INVC noise may be reflected and appear in the source output of the second nodes (NB in ​​FIG. 10). The magnitude of the INVC noise reflected in the source output of the second nodes (NB in ​​FIG. 10) may be smallest in the first source output channel where the output switch (OSW) is turned off, and largest in the 20th source output channel where the output switch (OSW) is turned on.

[0080] If the INVC noise reflected in the source output is large, block dimming may be visible in the pixel column connected to the source output channel. Therefore, in the following embodiments, various methods for masking INVC noise are described.

[0081] FIG. 16 is a different driving waveform diagram for reducing INVC noise by varying the source delay by position in the output buffer circuit of FIG. 13. FIG. 17 is a diagram showing that INVC noise is reduced in the INVC transition timing of FIG. 16.

[0082] Referring to FIG. 16, the offset control circuit (16) can transition the offset control signal (INVC) at a common timing that overlaps all 20 sequentially delayed masking intervals (MSK). At this time, since the masking intervals (MSK) have the same length and are sequentially delayed, design convenience can be provided.

[0083] Referring to FIG. 17, INVC noise is reflected in the first node (NA in FIG. 10) of the amplifier circuit (CAMP) when the amplifier offset changes, but since the output switches (OSW) are all off at the common timing when the offset control signal (INVC) transitions, the INVC noise is not reflected in the source outputs of the second nodes (NB in ​​FIG. 10). As a result, INVC noise can be masked in all 20 source output channels.

[0084] FIG. 18 is another driving waveform diagram for reducing INVC noise by varying the source delay by position in the output buffer circuit of FIG. 13. FIG. 19 is a diagram showing that INVC noise is reduced in the INVC transition timing of FIG. 18.

[0085] Referring to FIG. 18, the offset control circuit (16) can transition the offset control signal (INVC) at a common timing that overlaps all 20 sequentially delayed masking intervals (MSK). At this time, the masking intervals (MSK) have the same start time and sequentially delayed end times. Thus, since the masking intervals (MSK) are sequentially delayed while having different lengths, a large margin can be provided in setting the common timing.

[0086] Referring to FIG. 19, INVC noise is reflected in the first node (NA in FIG. 10) of the amplifier circuit (CAMP) when the amplifier offset changes, but since the output switches (OSW) are all off at the common timing when the offset control signal (INVC) transitions, the INVC noise is not reflected in the source outputs of the second nodes (NB in ​​FIG. 10). As a result, INVC noise can be masked in all 20 source output channels.

[0087] FIG. 20 is a diagram showing another example of the connection configuration between the offset control circuit, the source output control circuit, and the output buffer circuit of FIG. 8. FIG. 21 is a driving waveform diagram for reducing INVC noise by varying the source delay by position in the output buffer circuit of FIG. 20. FIG. 22 is a diagram showing that INVC noise is reduced at the INVC transition timings of FIG. 21.

[0088] Referring to FIGS. 20 and 21, the output buffer circuit (15) may include 20 amplifier circuits (CAMP) corresponding to the first to 20 source output channels (CH1 to CH20) and 20 output switches (OSW).

[0089] The source output control circuit (17) applies 20 sequentially delayed source output enable signals (DSOE1 to DSOE20) individually to 20 output switches (OSW) to delay the source output section in units of source output channels so as to correspond to the delay level of the gate signal. The 20 source output enable signals (DSOE1 to DSOE20) may be composed of 20 sequentially delayed masking sections (MSK) and 20 sequentially delayed output sections (OP).

[0090] The offset control circuit (16) can individually apply 20 offset control signals (INVC1~INVC20) that transition at individual timings within 20 sequentially delayed masking intervals (MSK) to 20 amplifier circuits (CAMP), thereby switching the offset of each amplifier circuit (CAMP) from (+) to (-) or vice versa.

[0091] Referring to FIG. 22, INVC noise is reflected in the first node (NA in FIG. 10) of the amplifier circuit (CAMP) when the amplifier offset changes, but since the output switches (OSW) are all off at individual timings when the offset control signals (INVC1~INVC20) are transitioning, INVC noise is not reflected in the source output of the second nodes (NB in ​​FIG. 10). As a result, INVC noise can be masked in all 20 source output channels.

[0092] FIG. 23 is a diagram showing another example of the connection configuration between the offset control circuit, the source output control circuit, and the output buffer circuit of FIG. 8. FIG. 24 is a driving waveform diagram for reducing INVC noise by varying the source delay by position in the output buffer circuit of FIG. 23.

[0093] Referring to FIGS. 23 and 24, the output buffer circuit (15) may include 20 amplifier circuits (CAMP) corresponding to the first to 20 source output channels (CH1 to CH20) and 20 output switches (OSW). The 20 amplifier circuits (CAMP) may be grouped into groups of 10 to form a first group of amplifier circuits (GP1-CAMP) and a second group of amplifier circuits (GP2-CAMP).

[0094] The source output control circuit (17) applies 20 sequentially delayed source output enable signals (DSOE1 to DSOE20) individually to 20 output switches (OSW) to delay the source output section in units of source output channels so as to correspond to the delay level of the gate signal. The 20 source output enable signals (DSOE1 to DSOE20) may be composed of 20 sequentially delayed masking sections (MSK) and 20 sequentially delayed output sections (OP). The 20 masking sections (MSK) may be grouped into groups of 10 to form a first group of masking sections (GP1-MSK) and a second group of masking sections (GP2-MSK).

[0095] The offset control circuit (16) can apply the first offset control signal (INVC1) to the first group of amplifier circuits (GP1-CAMP) in common within the first group of masking intervals (GP1-MSK) that are sequentially delayed, thereby switching the offset of each of the first group of amplifier circuits (GP1-CAMP) from (+) to (-) or vice versa.

[0096] Additionally, the offset control circuit (16) can apply the second offset control signal (INVC2) to the second group of amplifier circuits (GP2-CAMP) in common within the second group of masking intervals (GP2-MSK) that are sequentially delayed, thereby switching the offset of each of the second group of amplifier circuits (GP2-CAMP) from (+) to (-) or vice versa.

[0097] The first offset control signal (INVC1) is transitioned at the first common timing within the first group of masking intervals (GP1-MSK), and the second offset control signal (INVC2) is transitioned at the second common timing within the second group of masking intervals (GP2-MSK). At this time, since the first common timing and the second common timing are different from each other, each of the 20 masking intervals (MSK) can be designed to be short. Since the output interval (OP) increases when the masking interval (MSK) is shortened within one horizontal period, the embodiment of FIG. 23 and FIG. 24 has the advantage of being able to provide sufficient pixel charging time within one horizontal period.

[0098] From the above description, those skilled in the art will understand that various changes and modifications are possible within the scope of the technical concept of the present invention. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be determined by the claims. Explanation of the symbols

[0099] 100 : Display panel 110 : Source driver 120: Gate driver 130: Timing controller CAMP: Amplifier circuit OSW: Output switch 16: Offset control circuit 17: Source output control circuit

Claims

Claim 1 A display device comprising: a display panel having a plurality of 1-pixel lines composed of a plurality of pixels; a gate driver for applying a gate signal to the 1-pixel lines; and a source driver for applying a data signal to the 1-pixel lines, wherein the source driver comprises a plurality of amplifier circuits corresponding to a plurality of source output channels, a plurality of output switches connected between the amplifier circuits and the source output channels, a source output control circuit that applies sequentially delayed source output enable signals to the output switches to delay the output section of the data signal in units of source output channels according to the delay degree of the gate signal, and an offset control circuit that applies an offset control signal generated based on the sequentially delayed source output enable signals to the amplifier circuits to switch the offset of each of the amplifier circuits within the masking section of the data signal. Claim 2 A display device according to claim 1, wherein the offset control signal is transitioned within the masking interval, and the offset of each of the amplifier circuits is changed from (+) to (-) or from (-) to (+) in synchronization with the transition timing of the offset control signal. Claim 3 A display device according to claim 2, wherein the masking section and the output section constitute one horizontal period for the operation of the one pixel line, the offset control signal corresponding to the same source output channel is transitioned with a period of one horizontal period, and the offset of each of the amplifier circuits is changed from (+) to (-) in the masking section within the N-1 horizontal period and from (-) to (+) in the masking section within the N horizontal period, synchronized with the transition timing of the offset control signal. Claim 4 In claim 1, each of the amplifier circuits comprises: an amplifier having a first input terminal, a second input terminal, and an output terminal connected to any one of the output switches; an input switch that selectively couples the input of the data signal to the first input terminal and the second input terminal according to the offset control signal; a first feedback switch that couples or decouples the first input terminal and the output terminal according to the offset control signal; and a second feedback switch that decouples or couples the second input terminal and the output terminal according to the offset control signal. Claim 5 A display device according to claim 4, wherein the first feedback switch is turned off and the second feedback switch is turned on while the input of the data signal and the first input terminal are coupled, and the first feedback switch is turned on and the second feedback switch is turned off while the input of the data signal and the second input terminal are coupled. Claim 6 A display device according to claim 1, wherein the source output control circuit applies sequentially delayed source output enable signals, which are composed of sequentially delayed masking intervals and sequentially delayed output intervals, to the output switches, and the offset control circuit applies an offset control signal, which transitions at a common timing within the sequentially delayed masking intervals, to the amplifier circuits in common. Claim 7 In claim 6, the sequentially delayed masking intervals are a display device having the same length as each other. Claim 8 In claim 6, the sequentially delayed masking intervals are a display device having different lengths. Claim 9 A display device according to claim 1, wherein the source output control circuit applies source output enable signals, which are composed of sequentially delayed masking intervals and sequentially delayed output intervals, to the output switches, and the offset control circuit individually applies a plurality of offset control signals, which are transitioned at individual timings within the sequentially delayed masking intervals, to the amplifier circuits. Claim 10 In claim 1, the source output control circuit applies source output enable signals, which are composed of sequentially delayed masking intervals and sequentially delayed output intervals, to the output switches, and the offset control circuit applies a first offset control signal commonly to the first group of amplifier circuits within the first group of masking intervals among the sequentially delayed masking intervals, and applies a second offset control signal commonly to the second group of amplifier circuits within the second group of masking intervals among the sequentially delayed masking intervals, wherein the first offset control signal is transitioned at a first common timing within the first group of masking intervals, and the second offset control signal is transitioned at a second common timing within the second group of masking intervals, and the first common timing and the second common timing are different from each other, a display device. Claim 11 A method for compensating charge deviation of a display device comprising a display panel having a plurality of 1-pixel lines composed of a plurality of pixels, a gate driver for applying a gate signal to the 1-pixel lines, and a source driver for applying a data signal to the 1-pixel lines, wherein the source driver has a plurality of amplifier circuits corresponding to a plurality of source output channels and a plurality of output switches connected between the amplifier circuits and the source output channels, the method comprising: a first step of applying sequentially delayed source output enable signals to the output switches to delay the output section of the data signal in units of source output channels according to the delay degree of the gate signal; and a second step of applying an offset control signal generated based on the sequentially delayed source output enable signals to the amplifier circuits to switch the offset of each of the amplifier circuits within the masking section of the data signal. Claim 12 A method for compensating for charging deviation of a display device according to claim 11, wherein the offset control signal is transitioned within the masking interval, and the offset of each of the amplifier circuits is changed from (+) to (-) or from (-) to (+) in synchronization with the transition timing of the offset control signal. Claim 13 A method for compensating charging deviation of a display device according to claim 12, wherein the masking section and the output section constitute one horizontal period for the operation of the one pixel line, the offset control signal corresponding to the same source output channel is transitioned with a period of one horizontal period, and the offset of each of the amplifier circuits is changed from (+) to (-) in the masking section within the N-1 horizontal period and from (-) to (+) in the masking section within the N horizontal period, synchronized with the transition timing of the offset control signal. Claim 14 A method for compensating charging deviation of a display device, wherein the first step is to apply sequentially delayed source output enable signals, which are composed of sequentially delayed masking intervals and sequentially delayed output intervals, to the output switches, and the second step is to apply an offset control signal, which transitions at a common timing within the sequentially delayed masking intervals, to the amplifier circuits in common. Claim 15 In claim 14, a method for compensating for charging deviation of a display device in which the sequentially delayed masking sections have the same length. Claim 16 In claim 14, the sequentially delayed masking intervals are a method for compensating for charging deviation of a display device having different lengths. Claim 17 A method for compensating charge deviation of a display device according to claim 11, wherein the first step is a step of applying source output enable signals, which are composed of sequentially delayed masking intervals and sequentially delayed output intervals, to the output switches, and the second step is a step of individually applying a plurality of offset control signals, which are transitioned at individual timings within the sequentially delayed masking intervals, to the amplifier circuits. Claim 18 In claim 11, the first step comprises applying source output enable signals, which are composed of sequentially delayed masking intervals and sequentially delayed output intervals, to the output switches; the second step comprises applying a first offset control signal commonly to the first group of amplifier circuits within the first group of masking intervals among the sequentially delayed masking intervals, and applying a second offset control signal commonly to the second group of amplifier circuits within the second group of masking intervals among the sequentially delayed masking intervals, wherein the first offset control signal is transitioned at a first common timing within the first group of masking intervals, and the second offset control signal is transitioned at a second common timing within the second group of masking intervals, and the first common timing and the second common timing are different, a method for compensating for charging deviation of a display device.

Images