Semiconductor memory device and manufacturing method thoreof

Abstract

The present disclosure relates to a semiconductor device and a method for manufacturing the same. A semiconductor device according to one embodiment may include, on a substrate, a bit line extending in a first direction; a first insulating pattern located on the bit line; a channel pattern located on the upper surface of the bit line and the side surface of the first insulating pattern and comprising an oxide semiconductor material; a gate insulating pattern located on the channel pattern; a word line located on the gate insulating pattern; a second insulating pattern located on the word line; a landing pad connected to the channel pattern; and an interlayer insulating film located between the bit line and the channel pattern.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor memory device and a method for manufacturing the same. Background Technology

[0002] To meet the superior performance and low prices demanded by consumers, it is necessary to increase the integration density of semiconductor memory devices. Since integration density is a critical factor in determining product prices for semiconductor memory devices, particularly increased integration is required.

[0003] In the case of two-dimensional or planar semiconductor memory devices, the integration density is primarily determined by the area occupied by the unit memory cell, and thus is significantly influenced by the level of fine pattern formation technology. However, since ultra-expensive equipment is required for pattern miniaturization, the integration density of two-dimensional semiconductor memory devices is increasing but remains limited. Accordingly, semiconductor memory devices including vertical channel transistors in which the channel extends in the vertical direction are being proposed. The problem to be solved

[0004] The embodiments are intended to provide a semiconductor device with improved electrical characteristics by reducing contact resistance at the interface between the channel and the electrode, and a method for manufacturing the same. means of solving the problem

[0005] A semiconductor device according to one embodiment may include: a bit line (BL) extending in a first direction (Y) on a substrate (100); a first insulating pattern (115) located on the bit line; a channel pattern (CP) located on the upper surface of the bit line and the side surface of the first insulating pattern and comprising an oxide semiconductor material; a gate insulating pattern (Gox) located on the channel pattern; word lines (WL1, WL2) located on the gate insulating pattern; a second insulating pattern (141) located on the word line; a landing pad (LP) connected to the channel pattern; and an interlayer insulating film (180) located between the bit line and the channel pattern.

[0006] The above channel pattern includes first and second vertical sections facing each other and a horizontal section connecting the first and second vertical sections, wherein the horizontal section is located on the upper surface of the bit line and the first and second vertical sections may be located on the side of the first insulation pattern.

[0007] The thickness of the above interlayer insulating film may be 1 nm or less.

[0008] The above bit line may be positioned spaced apart in a second direction that intersects the above first direction.

[0009] Specifically, the system further includes a lower insulating film located in a spaced-apart space between the bit lines, and the interlayer insulating film may be positioned to cover the upper surface of the bit line and the upper surface of the lower insulating film, as well as the lower surface of the first insulating pattern and the lower insulating film.

[0010] Meanwhile, the interlayer insulating film may also be placed in the horizontal portion of the channel pattern and in the area overlapping with the bit line.

[0011] The above interlayer insulating film may include at least one of Al2O3, ZnO, TiO2, CdO, and BaTiO3.

[0012] The oxide semiconductor material may include at least one of amorphous IGZO, amorphous ITO, and amorphous IGTO.

[0013] The above word line may include first and second word lines positioned on the horizontal section facing each other between the first and second vertical sections.

[0014] The gate insulation pattern above may be placed between the first vertical portion and the first word line, and between the second vertical portion and the second word line.

[0015] A semiconductor device according to another embodiment may include: a peripheral circuit structure (PS) comprising a peripheral circuit element located on a substrate and an inter-wire insulating film (210) covering the peripheral circuit element (PT); a bit line located on the peripheral circuit structure; a first insulating pattern located on the bit line; a channel pattern located on the upper surface of the bit line and the side of the first insulating pattern, comprising first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions; a gate insulating pattern arranged to cover the first and second vertical portions and the horizontal portion; first and second word lines arranged on the gate insulating pattern covering the horizontal portion while facing each other between the first and second vertical portions; a second insulating pattern located on the first and second word lines; a landing pad connected to the channel pattern; and an inter-layer insulating film located between the bit line and the horizontal portion of the channel pattern.

[0016] In this embodiment, the thickness of the interlayer insulating film may be 1 nm or less.

[0017] The above interlayer insulating film may include at least one of Al2O3, ZnO, TiO2, CdO, and BaTiO3.

[0018] The above channel pattern may include an oxide semiconductor material.

[0019] At this time, the oxide semiconductor material may include at least one of amorphous IGZO, amorphous ITO, and amorphous IGTO.

[0020] A method for manufacturing a semiconductor device according to one embodiment may include the steps of: forming a bit line extending in a first direction on a substrate; forming an interlayer insulating film on the bit line; forming a first insulating pattern on the interlayer insulating film; forming a channel pattern on the interlayer insulating film and the first insulating pattern; forming a gate insulating pattern on the channel pattern; forming a word line on the gate insulating pattern; exposing at least a portion of the channel pattern; forming a second insulating pattern on the word line; and forming a landing pad connected to the exposed channel pattern.

[0021] The step of forming an interlayer insulating film on the bit line can be performed using at least one of atomic layer deposition and chemical vapor deposition.

[0022] In addition, in the step of forming an interlayer insulating film on the bit line, the interlayer insulating film may be formed with a thickness of 1 nm or less.

[0023] In the step of forming an interlayer insulating film on the bit line, the interlayer insulating film may be formed using a material comprising at least one of Al2O3, ZnO, TiO2, CdO, and BaTiO3. Effects of the invention

[0024] According to the embodiments, since an interlayer insulating film is located between the bit line and the channel pattern, it is possible to block the diffusion of oxygen into the bit line and simultaneously block the diffusion of hydrogen into the channel, thereby preventing degradation of device characteristics and improving the reliability of the semiconductor device.

[0025] In addition, by utilizing tunneling and eliminating Fermi-level pinning, the interfacial resistance and dispersion between bit lines and channel patterns can be reduced, thereby significantly improving the electrical characteristics of the semiconductor device.

[0026] In addition, since the semiconductor device of the present embodiment utilizes a tunneling phenomenon with low temperature dependence, it can improve the reliability of the semiconductor device by significantly reducing errors caused by temperature changes.

[0027] In addition, since an interlayer insulating film is located between the bit line and the channel pattern, leakage current in the static state can also be reduced, which is very advantageous.

[0028] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0029] FIG. 1 is a plan view of a semiconductor device according to one embodiment. Figure 2 is a cross-sectional view taken along the lines AA' and BB' of Figure 1. Figure 3 is a magnified view of the P1 portion in Figure 2. Figure 4 is illustrated as an example to explain device driving through tunneling in this embodiment. FIG. 5 is a plan view of a semiconductor device according to another embodiment. Figure 6 is a cross-sectional view taken along the lines AA' and BB' of Figure 5. Figure 7 is a cross-sectional view taken along the CC' and DD' lines of Figure 5. FIGS. 8, FIGS. 10, FIGS. 12, FIGS. 14, FIGS. 16, and FIGS. 19 are plan views illustrating a method for manufacturing a semiconductor device according to embodiments. FIGS. 9, FIGS. 11, FIGS. 13, FIGS. 15, FIGS. 17, FIGS. 18, and FIGS. 20 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to embodiments. Specific details for implementing the invention

[0030] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0031] To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are used for identical or similar components throughout the specification.

[0032] Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thicknesses have been enlarged in the drawings to clearly represent various layers and regions. Additionally, for convenience of explanation, the thickness of some layers and regions has been exaggerated in the drawings.

[0033] Furthermore, when it is said that a part, such as a layer, membrane, region, or plate, is "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when it is said that a part is "directly above" another part, it means that there is no other part in between. Also, saying that a part is "on" or "on" a reference part means that it is located above or below the reference part, and does not necessarily mean that it is located "on" or "on" in the direction opposite to gravity.

[0034] Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0035] Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side.

[0037] A semiconductor device according to one embodiment will be described below with reference to FIGS. 1 to 3. Specifically, FIG. 1 is a plan view of a semiconductor device according to one embodiment, FIG. 2 is a cross-sectional view taken along lines AA' and BB' of FIG. 1, and FIG. 3 is a magnified view of the P1 portion in FIG. 2.

[0038] Referring to FIGS. 1 to 3, a semiconductor device according to one embodiment includes a substrate (100), a bit line (BL), a first insulation pattern (115), a channel pattern (CP), a gate insulation pattern (Gox), word lines (WL1, WL2), a second insulation pattern (141), and a landing pad (LP), and includes an interlayer insulating film (180) located between the bit line and the channel pattern.

[0039] First, the substrate (100) may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, or an SOI (Semiconductor On Insulator) substrate. Hereinafter, the substrate (100) is described as being a silicon substrate.

[0040] Bit lines (BL) can be formed on a substrate (100). For example, a lower insulating film (110) can be formed on the substrate (100), and bit lines (BL) can be placed on the lower insulating film (110). Bit lines (BL) can be extended in a first direction (Y). A plurality of bit lines (BL) can each extend in the first direction (Y) and be spaced apart at equal intervals in a second direction (X) that intersects the first direction (Y). The lower insulating film (110) can be formed to fill the space between the bit lines (BL). In one embodiment, the upper surface of the portion of the lower insulating film (110) located between the bit lines (BL) can be placed at the same level as the upper surface of the bit lines (BL).

[0041] The bit line (BL) may comprise, for example, doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. The bit lines (BL) may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but are not limited thereto. The bit line (BL) may comprise a single layer or a multilayer of the materials described above. In another embodiment, the bit line (BL) may comprise a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may comprise graphene, a carbon nanotube, or a combination thereof.

[0042] A first insulating pattern (115) may be formed on a lower insulating film (110). In one embodiment, the first insulating pattern (115) is located on the upper surface of a bit line (BL), and the first insulating pattern (115) may be arranged spaced apart from each other in a first direction (Y) and extend across the bit line (BL) in a second direction (X).

[0043] The first insulation pattern (115) can extend across the bit lines (BL) in the second direction (X) and form channel trenches (TRC) that are spaced apart from each other in the first direction (Y).

[0044] The first insulating pattern (115) may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-dielectric constant (low-k) material having a dielectric constant smaller than that of silicon oxide, but is not limited thereto.

[0045] Low dielectric constant materials may include, for example, at least one of FOX (Flowable Oxide), TOSZ (Torene SilaZene), USG (Undoped Silicate Glass), BSG (Borosilicate Glass), PSG (PhosphoSilicate Glass), BPSG (BoroPhosphoSilicate Glass), PETEOS (Plasma Enhanced Tetra Ethyl Ortho Silicate), FSG (Fluoride Silicate Glass), CDO (Carbon Doped Silicon Oxide), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OSG (Organo Silicate Glass), Parylene, BCB (bis-benzocyclobutenes), SiLK, polyimide, porous polymeric material, and combinations thereof, but are not limited thereto.

[0046] Channel patterns (CPs) can be placed on bit lines (BLs). More specifically, channel patterns (CPs) can be located on the upper surface of the bit line (BL) and on the side of the first insulation pattern (115). Channel patterns (CPs) can be spaced apart from each other in a first direction (Y) on each bit line (BL). That is, channel patterns (CPs) can be arranged in a matrix form spaced apart from each other along the first direction (Y) and the second direction (X) that intersect each other.

[0047] A channel pattern (CP) may include a first source / drain region and a second source / drain region. For example, the lower part of the channel pattern (CP) may be connected to a bit line (BL) to function as a first source / drain region, and the upper part of the channel pattern (CP) may be connected to a landing pad (LP) to function as a second source / drain region, and a portion of the channel pattern (CP) between the first source / drain region and the second source / drain region may function as a channel region.

[0048] Specifically, channel patterns (CPs) can be spaced apart from each other in a first direction (Y) within each channel trench (TRC). In other words, a first insulation pattern (115) can be placed between channel patterns (CPs) adjacent in the first direction (Y). The channel patterns (CPs) can be located within the first insulation pattern (115) spaced apart in the first direction (Y). That is, the channel patterns (CPs) can extend along the profile of the channel trench (TRC). Accordingly, in cross-section, the channel patterns (CPs) can be in the shape of a "U".

[0049] Each of the channel patterns (CP) may include a horizontal portion (CP1) that extends along the first direction (Y) and is disposed on the interlayer insulating film (180), and first and second vertical portions (CP2) that extend along the third direction (Z direction) and are opposite each other in the first direction (Y).

[0050] In the semiconductor device of the present embodiment, an interlayer insulating film (180) is located between the bit line (BL) and the channel pattern (CP).

[0051] Here, the interlayer insulating film (180) can be positioned to cover the entire upper surface of the bit line (BL) and the upper surface of the lower insulating film (110).

[0052] Alternatively, the interlayer insulating film (180) may be placed only in the area overlapping with the horizontal portion (CP1) and the bit line (BL). Specifically, the upper surface of the interlayer insulating film (180) may be placed in contact with the lower surface of the horizontal portion (CP1) of the channel pattern, and the lower surface of the interlayer insulating film (180) may be placed in contact with the upper surface of the bit line (BL).

[0053] In this embodiment, since an interlayer insulating film (180) is positioned between the channel pattern (CP) and the bit line (BL) as described above, the bit line can be protected by blocking the diffusion of oxygen (D1) during the oxygen annealing process of the channel, as shown in FIG. 3. Additionally, the amorphous oxide semiconductor channel can be protected by blocking the diffusion of hydrogen (D2) into the channel during the silicon and hydrogen passivation processes. Accordingly, the reliability of the semiconductor device can be improved because the degradation of device characteristics can be prevented.

[0054] The interlayer insulating film (180) may use a material capable of inducing FN tunneling (Fowler Nordheim tunneling). Additionally, it may be used by doping a material capable of preventing oxygen from diffusing into the bit line during oxygen annealing of the channel pattern. Specifically, the interlayer insulating film (180) may include, for example, at least one of Al2O3, ZnO, TiO2, CdO, and BaTiO3.

[0055] The thickness of the interlayer insulating film (180) may be about 1 nm or less, more specifically in the range of about 0.01 nm to about 1 nm. Since the semiconductor device of the present embodiment includes an interlayer insulating film having a thin thickness of about 1 nm or less, it has a low tunneling barrier and can improve the performance of the semiconductor device by reducing the contact resistance and dispersion of the bit line and channel pattern by eliminating Fermi-level pinning.

[0056] Figure 4 is shown as an example to explain device driving through tunneling in a structure in which an interlayer insulating film is inserted between the bit line and channel pattern as in the present embodiment.

[0057] Referring to Fig. 4, the very thin interlayer insulating film of less than 1 nm is tunneled by the voltage applied to the bit line and word line, so that the device can be driven normally.

[0058] The horizontal portion (CP1) of the channel patterns (CP) can be in contact with the interlayer insulating film (180). At this time, the horizontal portion (CP1) of the channel patterns (CP) can be in contact with the upper surface of the interlayer insulating film (180).

[0059] The first and second vertical sections (CP2) of the channel patterns (CP) extend toward the third direction (Z direction) from the upper surface of the interlayer insulating film (180), the upper surface of the first and second vertical sections (CP2) contacts the landing pad (LP) to be described later, and the lower surface of the first and second vertical sections (CP2) can contact the interlayer insulating film (180).

[0060] The upper surface of the first and second vertical sections (CP2) may be located at a lower level than the upper surface of the gate insulation pattern (Gox) and word lines (WL1, WL2) to be described later. However, this is not limited thereto, and in other embodiments, the upper surface of the first and second vertical sections (CP2) of the channel patterns (CP) may be located at the same level as or at a higher level than the upper surface of the gate insulation pattern (Gox) and / or word lines (WL1, WL2).

[0061] Additionally, the first and second vertical sections (CP2) of the channel patterns (CP) may be positioned facing each other. One side of the first and second vertical sections (CP2) is connected to the horizontal section (CP1) and may come into contact with the gate insulation pattern (Gox) to be described later. That is, some of the sides of the first and second vertical sections (CP2) are connected to the side of the horizontal section (CP1), and the remaining part may come into contact with the gate insulation pattern (Gox). Accordingly, the horizontal section (CP1) of the channel pattern (CP) may be spaced apart from the first insulation pattern (115) and the first and second vertical sections (CP2) so that they do not come into contact with each other.

[0062] In one embodiment, the channel pattern (CP) may include an oxide semiconductor material. Oxide semiconductor materials include, for example, indium gallium zinc oxide (IGZO), InxGayZnzO (IGZO), indium gallium silicon oxide (IGSO), InxGaySizO (IGZO), indium tin zinc oxide (ITZO), InxSnyZnzO (ITZO), indium gallium tin oxide (IGTO), InxGaySnzO (IGTO), indium zinc oxide (IZO), and ZnO (zinc oxide, ZnxO), ZTO (zinc tin oxide, ZnxSnyO), ZnON (zinc oxynitride, ZnxOyN), ZZTO (zirconium zinc tin oxide, ZrxZnySnzO), SnO (tin oxide, SnxO), HIZO (hafnium indium zinc oxide, HfxInyZnzO), GZTO (gallium zinc tin oxide, GaxZnySnzO), AZTO(aluminium zinc tin oxide, AlxZnySnzO), It may include YGZO (ytterbium gallium zinc oxide, YbxGayZnzO), IGO (indium gallium oxide, InxGayO), or a combination thereof. More specifically, in this embodiment, the oxide semiconductor material may include at least one of amorphous IGZO, amorphous ITO, and amorphous IGTO.

[0063] Word lines (WL1, WL2) can be extended across bit lines (BL) in a second direction (X direction) and can be spaced apart along a first direction (Y direction). A pair of word lines (WL1, WL2) can be located on a horizontal portion (CP1) between the first and second vertical portions (CP2) of each channel pattern (CP).

[0064] Specifically, each of the word lines (WL1, WL2) may include one side and the other side opposite to the one side, and the one side of the word lines (WL1, WL2) may be arranged to face each other on the horizontal portion (CP1) of the channel pattern (CP). The other sides of the word lines (WL1, WL2) may each be adjacent to the first or second vertical portion (CP2) of the channel pattern (CP) and may come into contact with the gate insulation pattern (Gox) to be described later.

[0065] Although the upper surface of the word lines (WL1, WL2) is depicted as being located at a higher level than the upper surface of the channel patterns (CP), in other embodiments, the upper surface of the word lines (WL1, WL2) may be located at the same or lower level as the upper surface of the channel patterns (CP).

[0066] The word lines (WL1, WL2) may include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0067] In addition, the word lines (WL1, WL2) may be made of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but are not limited thereto.

[0068] The word lines (WL1, WL2) may comprise a single layer or a multilayer of the aforementioned materials. In another embodiment, the word lines (WL1, WL2) may comprise a two-dimensional semiconductor material, for example, the two-dimensional semiconductor material may comprise graphene, carbon nanotubes, or a combination thereof.

[0069] A gate insulation pattern (Gox) can be placed between channel patterns (CP) and word lines (WL1, WL2). The gate insulation pattern (Gox) can cover the sides of the channel patterns (CP) and landing pads (LP) with a uniform thickness.

[0070] A gate insulation pattern (Gox) may be placed between the lower surface of the word lines (WL1, WL2) and the horizontal portion (CP1) of the channel patterns (CP), and between the other surface of the word lines (WL1, WL2) and the first or second vertical portion (CP2) of the channel pattern (CP). The gate insulation pattern (Gox) may be in the shape of a "U" in cross-section.

[0071] The gate insulation pattern (Gox) may be composed of a silicon oxide film, a silicon oxynitride film, a high dielectric film having a dielectric constant higher than that of a silicon oxide film, or a combination thereof. The high dielectric film may be composed of a metal oxide or a metal oxynitride. For example, a high dielectric film usable as a gate insulation layer may be composed of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0072] A second insulation pattern (141) can be formed within a channel trench (TRC). The second insulation pattern (141) can fill the remaining channel trench (TRC) after the channel pattern (CP), gate insulation pattern (Gox), and word lines (WL1, WL2) are formed.

[0073] The second insulating pattern (141) may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-dielectric constant (low-k) material having a dielectric constant smaller than that of silicon oxide, but is not limited thereto.

[0074] Landing pads (LPs) may each be positioned to overlap at least a portion of the channel pattern (CP) in a vertical direction (e.g., the third direction (Z direction)). Landing pads (LPs) may be arranged in a matrix form spaced apart from each other in the second direction (X) and the first direction (Y). However, this is merely illustrative, and it goes without saying that multiple landing pads (LPs) may be arranged in various other forms, such as a honeycomb shape, as long as they are connected to the channel pattern (CP).

[0075] In addition, landing pads (LPs) can have various shapes on a flat surface, such as circular, elliptical, rectangular, square, rhombus, and hexagonal. However, the flat shape of these landing pads (LPs) is not limited to these.

[0076] Landing pads (LPs) can be placed on the first insulation pattern (115) and the second insulation pattern (141). The landing pads (LPs) can be in contact with the channel pattern (CP). The landing pads (LPs) can penetrate the upper insulation layer (150) and be in contact with the upper part of the channel pattern (CP).

[0077] Specifically, the landing pads (LP) may include a first portion (LP1) extended in a first direction (Y direction) and a second portion (LP2) extended from the first portion (LP1) in a third direction (Z direction).

[0078] The first part (LP1) may come into contact with the upper surface of the gate insulation pattern (Gox) and a portion of the upper surface of the second insulation pattern (141). In FIG. 3, the lower surface of the first part (LP1) of the landing pad (LP) is shown as being at the same level as the upper surface of the first insulation pattern (115) and the upper surface of the second insulation pattern (141), but is not limited thereto. In other embodiments, the lower surface of the first part (LP1) of the landing pad (LP) may be at a lower level than the upper surfaces of the first insulation pattern (115) and the second insulation pattern (141).

[0079] The second part (LP2) overlaps with the first part (LP1) in the third direction (Z direction) and extends from the lower surface of the first part (LP1) toward the third direction (Z direction), so as to be in contact with the upper surface of the first and second vertical parts (CP2) of the channel pattern (CP).

[0080] Additionally, the second part (LP2) of the landing pad (LP) contacts a part of the side of the first insulation pattern (115) and a part of the side of the gate insulation pattern (Gox), and the lower surface of the second part (LP2) may be located at a lower level than the upper surface of the word lines (WL1, WL2). However, it is not limited thereto.

[0081] Accordingly, the landing pad (LP) can be electrically connected to the horizontal portion (CP1) of the channel pattern (CP) through the first and second vertical portions (CP2) of the channel pattern (CP). However, since this is merely illustrative, the arrangement of the landing pads (LP) can vary as long as they are connected to the channel pattern (CP).

[0082] Each landing pad (LP) may comprise doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, each landing pad (LP) may comprise doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto.

[0083] The upper insulating layer (150) can fill the space between landing pads (LPs) spaced apart in the first direction (Y direction) on the first insulating pattern (115) and the second insulating pattern (141). For example, the lower surface of the upper insulating layer (150) may be located at the same level as the lower surface of the first part (LP1) of the landing pads (LPs). However, it is not limited thereto, and in other embodiments, the lower surface of the upper insulating layer (150) may be located at a different level from the lower surface of the first part (LP1) of the landing pads (LPs).

[0084] Data storage patterns (DSPs) can be placed on landing pads (LPs). Data storage patterns (DSPs) can be electrically connected to channel patterns (CPs) through the landing pads (LPs). Data storage patterns (DSPs) can be arranged in a matrix form along a second direction (X direction) and a first direction (Y direction), as shown in FIG. 1.

[0085] In one embodiment, the data storage patterns (DSPs) may be capacitors and may include a capacitor dielectric film interposed between the lower and upper electrodes. When the data storage patterns (DSPs) have such a structure, the lower electrode may come into contact with the landing pad (LP), and the lower electrode may have various shapes such as circular, elliptical, rectangular, square, rhombus, or hexagonal on a plane.

[0086] In contrast, data storage patterns (DSPs) may be variable resistance patterns that can be switched between two resistance states by an electrical pulse applied to a memory element. For example, data storage patterns (DSPs) may include phase-change materials, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials whose crystal state changes depending on the amount of current.

[0087] FIG. 5 is a plan view of a semiconductor device according to another embodiment, FIG. 6 is a cross-sectional view cut along lines AA' and BB' of FIG. 5, and FIG. 7 is a cross-sectional view cut along lines CC' and DD' of FIG. 5.

[0088] Referring to FIGS. 5 to 7, the semiconductor device of the present embodiment may include a peripheral circuit structure (PS) on a substrate (100) and a cell array structure (CS) on the peripheral circuit structure (PS).

[0089] The peripheral circuit structure (PS) may include a peripheral circuit element (PT) located on the substrate (100) and an insulating film (210) between the wiring.

[0090] Peripheral circuit elements (PT) include control elements and dummy elements and can control the functions of semiconductor memory elements formed on the substrate (100). An insulating film (210) between wirings can cover the peripheral circuit elements (PT).

[0091] In one embodiment, the peripheral circuit element (PT) may include a first conductive pattern (220) and a second conductive pattern (230) formed sequentially on the upper surface of the substrate (100). The first conductive pattern (220) and the second conductive pattern (230) may constitute various circuit elements for controlling the functions of semiconductor memory elements. The peripheral circuit element (PT) may include various active elements, such as transistors, as well as various passive elements, such as capacitors, resistors, and inductors.

[0092] In one embodiment, the insulating film (210) between the peripheral circuit element (PT) and the wiring may be placed below the interlayer insulating film (180).

[0093] For example, the lower insulating film (110) may be laminated on the upper surface of the inter-wire insulating film (210). The inter-layer insulating film (180) may be laminated on the upper surface of the lower insulating film (110). That is, the semiconductor device according to the present embodiment may have a COP (cell on peri) structure.

[0094] In one embodiment, a peripheral circuit element (PT) can be connected to a bit line (BL). For example, a wiring pattern (240) connected to the peripheral circuit element (PT) can be formed within the inter-wiring insulating film (210). Additionally, a connection via (250) connecting the bit line (BL) and the wiring pattern (240) can be formed through the lower insulating film (110) with the inter-layer insulating film (180) in between. Accordingly, the bit line (BL) can be controlled by the peripheral circuit element (PT).

[0095] The cell array structure (CS) may include memory cells including a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which the channel length extends in a direction perpendicular to the upper surface of the substrate (100).

[0096] In this embodiment, the cell array structure (CS) may include a lower insulating film (110), a bit line (BL), a first insulating pattern (115), a channel pattern (CP), word lines (WL1, WL2), a second insulating pattern (141), a landing pad (LP), an upper insulating layer (150), and data storage patterns (DSP). A detailed description thereof is the same as that described above using FIGS. 1 to 4 and is therefore omitted here.

[0098] Next, with reference to FIGS. 8 to 20, a method for manufacturing a semiconductor device according to one embodiment will be described. Specifically, FIGS. 8, 10, 12, 14, 16, and 19 are plan views for illustrating a method for manufacturing a semiconductor device according to embodiments. FIGS. 9, 11, 13, 15, 17, 18, and 20 are cross-sectional views for illustrating a method for manufacturing a semiconductor device according to embodiments.

[0099] For the convenience of explanation, parts that overlap with those described above using FIGS. 1 to 7 are briefly explained or omitted.

[0100] Referring to FIGS. 8 and 9, a bit line (BL), an interlayer insulating film (180), and a first insulating pattern (115) are formed on a substrate (100).

[0101] For example, a lower insulating film (110) may be formed on a substrate (100). The lower insulating film (110) may include insulating films stacked in multiple layers. For example, the lower insulating film (110) may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low dielectric film.

[0102] Bit lines (BL) can be formed on the lower insulating film (110). Bit lines (BL) can be extended in a first direction (Y). A plurality of bit lines (BL) each extend in the first direction (Y) and can be spaced apart at equal intervals in a second direction (X) that intersects the first direction (Y). An insulating material can be filled between the bit lines (BL). Bit lines (BL) can be formed by depositing a conductive film on the lower insulating film (110) and then patterning the conductive film.

[0103] Next, an interlayer insulating film (180) may be formed on the bit line (BL). The interlayer insulating film (180) may cover the upper surface of the bit line (BL) and the upper surface of the lower insulating film (110).

[0104] The above interlayer insulating film (180) can be formed, for example, by at least one of an atomic layer deposition (ALD) process and a chemical vapor deposition (CVD) process.

[0105] Although not shown, the above-mentioned interlayer insulating film (180) may be formed to cover only the bit line (BL).

[0106] Subsequently, a first insulating pattern (115) may be formed on the interlayer insulating film (180) to define a first trench (TRC1) that extends in a second direction (X) and is spaced apart from each other in a first direction (y direction). The first trench (TRC1) may be formed across the bit lines (BL). The first insulating pattern (115) may be formed, for example, from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low dielectric film.

[0107] Referring to FIGS. 10 and FIGS. 11, preliminary channel patterns (121) may each be formed within the first trench (TRC1). The preliminary channel patterns (121) may extend in a second direction (X).

[0108] Forming preliminary channel patterns (121) may include conformally depositing a channel film on a lower insulating film on which first insulating patterns (115) are formed, forming a sacrificial film that fills a first trench (TRC1) on the channel film, and flattening the sacrificial film and the channel film so that the upper surfaces of the first insulating patterns (115) are exposed. Accordingly, preliminary channel patterns (121) and sacrificial patterns (123) on the preliminary channel patterns (121) may be formed within each of the first trenches (TRC1).

[0109] The channel film may be formed using at least one of physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced chemical vapor deposition (PE-CVD), or atomic layer deposition (ALD) techniques. The channel film may cover the bottom surfaces and inner walls of the first trench (TRC1) with a substantially uniform thickness. The thickness of the channel film may be less than half the width of the trench. The channel film may be deposited with a thickness of, for example, several to tens of nanometers, e.g., 1 nm to 30 nm, e.g., 1 nm to 10 nm. In the present embodiment, the channel film may comprise an oxide semiconductor material, as described above.

[0110] The sacrificial patterns (123) may be formed of an insulating material having etch selectivity for the first insulating patterns (115). For example, the sacrificial patterns (123) may be one of insulating materials and silicon oxide films formed using SOG (Spin On Glass) technology.

[0111] Referring to FIGS. 12 and 13, channel patterns (CP) that are spaced apart from each other in a second direction (X) within a first trench (TRC1) can be formed by patterning preliminary channel patterns (121) and sacrifice patterns (123).

[0112] Forming channel patterns (CP) may include forming a mask pattern (MP) on pre-channel patterns (121) and sacrifice patterns (123), and using the mask pattern (MP) as an etching mask to etch the sacrifice patterns (123) and pre-channel patterns (121) in sequence to form openings (OP) that expose an interlayer insulating film (180).

[0113] For example, the openings (OP) may have a bar shape with a major axis parallel to the first direction (Y) and may be spaced apart from each other in the first direction (Y) and the second direction (X). The openings (OP) may be spaced apart from the bit lines (BL) in a planar view. In another example, the openings (OP) may have a line shape extending in the first direction (Y) parallel to the bit lines and may be formed across the first insulation pattern (115).

[0114] Each of the channel patterns (CP) formed in this way may include a horizontal portion (CP1) in contact with the bit line (BL) and first and second vertical portions (CP2) connected to the first horizontal portion and covering both side walls of the trench.

[0115] After forming a channel pattern (CP), an etching process can be performed to remove the mask pattern (MP), and sacrificial patterns (123) can be removed using an etching solution having etch selectivity for the first insulating pattern (115) and the channel pattern (CP).

[0116] Referring to FIGS. 14 and 15, a gate insulating film (131) and a gate conductive film (133) that conformally cover the channel patterns (CP) can be deposited in sequence. The gate insulating film (131) and the gate conductive film (133) can be formed using at least one of physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low-pressure chemical vapor deposition (LP-CVD), plasma-enhanced chemical vapor deposition (PE-CVD), or atomic layer deposition (ALD) techniques.

[0117] The gate insulating film (131) and the gate conductive film (133) can cover the horizontal portion (CP1) and the first and second vertical portions (CP2) of the channel pattern (CP) with substantially uniform thickness.

[0118] The gate insulating film (131) can be in direct contact with the first and second vertical portions (CP2), the horizontal portion (CP1), and the upper surface of the first insulating pattern (115) of the channel pattern (CP).

[0120] Referring to FIGS. 16 and 17, an anisotropic etching process can be performed on the gate conductive film (133) to form a pair of first and second word lines (WL1, WL2) separated from each other within the first trench (TRC1). During the anisotropic etching process on the gate conductive film (133), the upper surfaces of the first and second word lines (WL1, WL2) may be lower than the upper surface of the channel pattern (CP). Alternatively, an additional etching process may be performed to recess the upper surfaces of the first and second word lines (WL1, WL2).

[0121] In another example, during an anisotropic etching process for the gate conductive film (133), the gate insulating pattern (Gox) may be etched together, and a portion of the horizontal portion (CP1) of the channel pattern (CP) may be exposed. Accordingly, as shown in FIG. 17, a pair of opposing first and second gate insulating patterns (Gox) may be formed.

[0122] Although not illustrated, as another example, during an anisotropic etching process for the gate conductive film, the horizontal portions (CP1) of the gate insulating pattern (Gox) and the channel pattern (CP) may be etched in sequence to expose the interlayer insulating film (180). Accordingly, the channel pattern (CP) may be formed in a form that includes only a pair of first and second vertical portions (CP2) that are separated from each other and face each other within the first trench (TRC1).

[0123] Next, referring to FIG. 18, a second trench (TRC2) can be formed through an etching process that recesses parts of the first and second vertical sections (CP2) of the channel pattern (CP).

[0124] That is, by wet etching the first and second vertical portions (CP2) of the channel pattern (CP) in a vertical direction from the top surface, a second trench (TRC2) extended in a third direction (Z direction) can be formed. However, the etching process for recessing the first and second vertical portions (CP2) of the channel pattern (CP) is not limited to this and can be changed in various ways.

[0125] Accordingly, the upper surface of the first and second vertical sections (CP2) of the channel pattern (CP) may be located at a lower level than the upper surface of the word lines (WL1, WL2).

[0126] Next, referring to FIGS. 19 and 20, a second insulating pattern (141) that fills the first trench (TRC1) may be formed. The second insulating pattern (141) may be formed, for example, from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low dielectric film.

[0127] Next, landing pads (LP) can be formed on the first insulation pattern (115), the second insulation pattern (141), the gate insulation pattern (Gox), and the channel pattern (CP). In this process, the landing pads (LP) can fill the second trench (TRC2) and come into contact with the first and second vertical sections (CP2) of the channel pattern (CP).

[0128] Next, landing pads (LP) can be patterned to form holes that expose the upper surfaces of the first insulation pattern (115) and the second insulation pattern (141), and then an upper insulation layer (150) can be embedded within the holes, followed by a flattening process. However, the order of forming the landing pads (LP) and the upper insulation layer (150) is not limited thereto, and in other embodiments, the upper insulation layer (150) can be formed and patterned on the first insulation pattern (115), the second insulation pattern (141), the gate insulation pattern (Gox), and the channel pattern (CP), and then landing pads (LP) penetrating the upper insulation layer (150) can be formed.

[0129] Subsequently, data storage patterns (DSPs) may be formed on each of the landing pads (LPs). In one embodiment, if the data storage patterns (DSPs) include capacitors, lower electrodes, a capacitor dielectric film, and an upper electrode may be formed in sequence.

[0131] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention. Explanation of the symbols

[0133] 100: Substrate 110: Lower insulation layer 115: First insulation pattern 121: Reserve channel pattern 123: Sacrifice Pattern 131: Preliminary gate insulation pattern 133: Preliminary word line 141: Second insulation pattern 150: Interlayer insulation layer PS: Peripheral circuit structure CS: Seol array structure SA: Peripheral circuits BL: Beat Line Gox: Gate insulation pattern CP: Channel Pattern WL: Word Line LP: Landing pad DSP: Data Storage Pattern

Claims

Claim 1 A semiconductor device comprising: a bit line (BL) extending in a first direction (Y) on a substrate (100); a first insulating pattern (115) located on the bit line; a channel pattern (CP) located on the upper surface of the bit line and the side surface of the first insulating pattern and comprising an oxide semiconductor material; a gate insulating pattern (Gox) located on the channel pattern; word lines (WL1, WL2) located on the gate insulating pattern; a second insulating pattern (141) located on the word line; a landing pad (LP) connected to the channel pattern; and an interlayer insulating film (180) located between the bit line and the channel pattern. Claim 2 A semiconductor device according to claim 1, wherein the channel pattern comprises first and second vertical sections facing each other and a horizontal section connecting the first and second vertical sections, wherein the horizontal section is located on the upper surface of the bit line and the first and second vertical sections are located on the side of the first insulation pattern. Claim 3 A semiconductor device according to claim 1, wherein the thickness of the interlayer insulating film is 1 nm or less. Claim 4 A semiconductor device according to claim 1, wherein the bit line is spaced apart in a second direction intersecting the first direction. Claim 5 A semiconductor device according to claim 4, further comprising a lower insulating film located in a spaced-apart space between the bit lines, wherein the interlayer insulating film is arranged to cover the upper surface of the bit line and the upper surface of the lower insulating film, and the lower surface of the first insulating pattern and the lower insulating film. Claim 6 A semiconductor device in which, in paragraph 2, the interlayer insulating film is disposed in a region overlapping the horizontal portion of the channel pattern and the bit line. Claim 7 In claim 1, the interlayer insulating film comprises at least one of Al2O3, ZnO, TiO2, CdO, and BaTiO3, Semiconductor device. Claim 8 A semiconductor device according to claim 1, wherein the oxide semiconductor material comprises at least one of amorphous IGZO, amorphous ITO, and amorphous IGTO. Claim 9 A semiconductor device comprising: a peripheral circuit structure (PS) including a peripheral circuit element located on a substrate and an inter-wire insulating film (210) covering the peripheral circuit element (PT); a bit line located on the peripheral circuit structure; a first insulating pattern located on the bit line; a channel pattern located on the upper surface of the bit line and the side of the first insulating pattern, comprising first and second vertical portions facing each other and a horizontal portion connecting the first and second vertical portions; a gate insulating pattern arranged to cover the first and second vertical portions and the horizontal portion; first and second word lines arranged on the gate insulating pattern covering the horizontal portion while facing each other between the first and second vertical portions; a second insulating pattern located on the first and second word lines; a landing pad connected to the channel pattern; and an inter-layer insulating film located between the bit line and the horizontal portion of the channel pattern. Claim 10 A semiconductor device according to claim 9, wherein the thickness of the interlayer insulating film is 1 nm or less.

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