Oscillation circuit
The oscillation circuit addresses the challenge of large size and high current consumption by employing NMOS transistors and switch circuits to maintain a constant frequency output, despite power supply fluctuations, achieving a compact and efficient design.
Patent Information
- Authority / Receiving Office
- KR · KR
- Patent Type
- Patents
- Current Assignee / Owner
- ABLIC INC
- Filing Date
- 2022-07-12
- Publication Date
- 2026-07-21
AI Technical Summary
Existing oscillation circuits face issues with large circuit size and high current consumption due to the inclusion of a band gap constant voltage circuit and constant current bias generation circuit, which affect their performance in maintaining a constant frequency despite fluctuations in power supply voltage or temperature.
An oscillation circuit design utilizing an NMOS transistor and switch circuits to control voltage and current, allowing for a compact size and low current consumption while maintaining a constant frequency output, unaffected by power supply fluctuations or temperature.
The circuit achieves a small size and low current consumption while maintaining a constant frequency output, unaffected by power supply voltage or temperature fluctuations, through the use of NMOS transistors and switch circuits that manage capacitor charging and discharging with controlled voltages and currents.
Smart Images
Figure 112022072313138-PAT00001_ABST
Abstract
Description
Technology Field
[0001] The present invention relates to an oscillation circuit. Background Technology
[0002] Oscillation circuits are required to output a constant frequency without being affected by fluctuations in power supply voltage or temperature.
[0003] Figure 4 is a circuit diagram showing a conventional oscillation circuit.
[0004] The oscillation circuit (400) of FIG. 4 is equipped with a capacitor (C1), an inverter (41, 42, 44), a band gap constant voltage circuit (43) (hereinafter referred to as the BGR circuit), a constant current source circuit (45), a constant current bias generation circuit (46), a PMOS transistor (M1), and an NMOS transistor (M2).
[0005] The BGR circuit (43) supplies a voltage (VBGR) that is not affected by fluctuations in power supply voltage and temperature. The constant current source circuit (45), which is bias-controlled by the constant current bias generation circuit (46), generates a constant current that is not affected by fluctuations in power supply voltage and temperature. Since the voltage (VBGR) and the constant current control the voltage of the capacitor (C1) in the oscillation circuit of FIG. 4, a constant frequency can be output from the inverter (42) without being affected by fluctuations in power supply voltage or temperature (e.g., see Patent Document 1).
[0006] (Patent Document 1) Japanese Patent Publication No. 2005-217762 The problem to be solved
[0007] However, since the above-described oscillation circuit is equipped with a BGR circuit (43) and a constant current bias generation circuit (46), there was a problem that the circuit size of such a circuit was large and the current consumption was large.
[0008] With the above problem in mind, the present invention aims to provide an oscillation circuit capable of outputting a constant frequency without being affected by fluctuations in power supply voltage or temperature, even if the circuit size is small and the current consumption is low. means of solving the problem
[0009] An oscillation circuit of one embodiment of the present invention comprises: a capacitor; a first constant current circuit connected between a first power terminal and one terminal of the capacitor; a first switch circuit connected between the other terminal of the capacitor and a second power terminal; a second constant current circuit having one terminal connected to the first power terminal; a first MOS transistor having a gate and a drain connected to the other terminal of the second constant current circuit and a source connected to the other terminal of the capacitor; a second MOS transistor having a gate connected to the gate of the first MOS transistor and a drain connected to one terminal of the capacitor; a second switch circuit connected between the source of the second MOS transistor and the second power terminal; and an output terminal that outputs a signal based on the voltage of one terminal of the capacitor; wherein the first switch circuit and the second switch circuit are controlled to be on or off by the signal of the output terminal and the inverted signal of the signal. Effects of the invention
[0010] According to the oscillation circuit of the present invention, since it is equipped with an NMOS transistor and a switch circuit that raise and lower the voltage of a capacitor to a constant voltage and a constant current circuit that charges and discharges the capacitor with a constant current, it is possible to provide an oscillation circuit that has a small circuit size and low current consumption, and can output a constant frequency without being affected by fluctuations in power supply voltage or temperature. Brief explanation of the drawing
[0011] FIG. 1 is a block diagram showing an oscillation circuit of the present embodiment. FIG. 2 is a circuit diagram showing an example of an oscillation circuit of the present embodiment. FIG. 3 is a timing chart showing the operation of the oscillation circuit of the present embodiment. Figure 4 is a block diagram showing a conventional oscillation circuit. Specific details for implementing the invention
[0012] Hereinafter, the oscillation circuit of the present invention will be described with reference to the drawings.
[0013] FIG. 1 is a block diagram showing an oscillation circuit (100) of the present embodiment.
[0014] The oscillation circuit (100) of FIG. 1 is equipped with a constant current circuit (10, 11, 12), an NMOS transistor (13, 14, 15), a switch circuit (16, 17), a capacitor (18), and an inverter (30, 31). The constant current circuit (12) and the NMOS transistor (15) constitute a constant current inverter.
[0015] One end of the constant current circuit (10, 11, 12) is connected to the power terminal. The drain and gate of the NMOS transistor (13) are connected to the other end of the constant current circuit (10), and the source is connected to one end of the switch circuit (16). The other end of the switch circuit (16) is connected to the ground terminal, and the control terminal is connected to the output terminal of the inverter (31). The drain of the NMOS transistor (14) is connected to the other end of the constant current circuit (11), the gate is connected to the gate of the NMOS transistor (13), and the source is connected to one end of the switch circuit (17). The other end of the switch circuit (17) is connected to the ground terminal, and the control terminal is connected to the output terminal of the inverter (30). One end of the capacitor (18) is connected to the source of the NMOS transistor (13), and the other end is connected to the drain of the NMOS transistor (14). The drain of the NMOS transistor (15) is connected to the other end of the constant current circuit (12), the gate is connected to the drain of the NMOS transistor (14), and the source is connected to the ground terminal. The input terminal of the inverter (30) is connected to the drain of the NMOS transistor (15). The input terminal of the inverter (31) is connected to the output terminal of the inverter (30), and the output terminal is connected to the output terminal of the oscillation circuit (100).
[0016] The oscillation circuit (100) of FIG. 1 controls the on / off of the switch circuits (16, 17) with signals (CLK, CLKB) and the constant current (I) of the constant current circuits (10, 11). 10 , I 11 By charging and discharging the capacitor (18) with ), a signal (CLK) is output.
[0017] Here, the oscillation circuit (100) of FIG. 1 is designed under the following conditions.
[0018] If the duty cycle of the signal (CLK) is set to 50%, the constant current (I10) and the constant current (I 11) shall be the same. However, this constant current may be appropriately set by the desired duty cycle of the signal (CLK). Also, the voltage (V1) of node (N1) when the switch circuit (17) is turned on, i.e., ΔVgs=Vgs 14 -Vgs 13 will be a defined value.
[0019] The oscillation circuit (100) configured as described above operates as follows.
[0020] Figure 3 is a timing chart showing the operation of the oscillation circuit (100).
[0021] First, the interval from the initial state to time (t1) is described.
[0022] In the initial state, the capacitor (18) is not charged. When power is applied, the signal (CLK) becomes H level and the signal (CLKB) becomes L level, so the switch circuit (16) is turned on and the switch circuit (17) is turned off. Therefore, the voltage (V1) of the node (N1) becomes the voltage of the ground terminal, i.e., L level.
[0023] The capacitor (18) is charged by a constant current (I11) flowing from node (N2) to node (N1). Then, the voltage (V2) of node (N2), which is the voltage of the capacitor (18), gradually rises. At time (t1), the voltage (V2) is the threshold value (Vth) of the NMOS transistor (15). 15 When this happens, the NMOS transistor (15) turns on. Therefore, the signal (CLK) becomes L level and the signal (CLKB) becomes H level.
[0024] Next, the interval from time t1 to t2 is explained.
[0025] At time (t1), when the signal (CLK) becomes L level and the signal (CLKB) becomes H level, the switch circuit (16) is turned off and the switch circuit (17) is turned on. The NMOS transistor (13) is constant current (I 10 As ) flows, voltage (Vgs) between the gate and source 13) occurs. The NMOS transistor (14) has a constant current (I 11 A constant current (I) through the capacitor (18) and ) 10) As V flows, the voltage (Vgs) between the gate and source is generated. 14 ) occurs. Therefore, the voltage (V1) of node (N1) is ΔVgs=Vgs 14 -Vgs 13 This is the case. Here, the NMOS transistor (13) and the NMOS transistor (14) can be designed so that the voltage (ΔVgs) at this time becomes a defined value.
[0026] Since the voltage (V2) of node (N2) becomes the voltage (ΔVgs) of voltage (V1), it rises by the voltage (ΔVgs) due to the capacitor (18) so that Vth 15 +ΔVgs. Then, as the switch circuit (17) is turned on, the voltage charged in the capacitor (18) is discharged to the ground terminal through the NMOS transistor (14). At this time, the discharge current is a current corresponding to the constant current (I10) of the constant current circuit (10).
[0027] That is, voltage Vth at time (t1) 15 The voltage (V2), which is the voltage of the capacitor (18) that was +ΔVgs, is discharged from the constant current (I10) and gradually decreases. Then, at time (t2), the voltage (V2) reaches the threshold value (Vth) of the NMOS transistor (15). 15 When it falls below ), the NMOS transistor (15) is turned off. Therefore, the signal (CLK) becomes an H level and the signal (CLKB) becomes an L level.
[0028] Next, the interval from time t2 to t3 is explained.
[0029] At time (t2), when the signal (CLK) becomes H level and the signal (CLKB) becomes L level, the switch circuit (16) is turned on and the switch circuit (17) is turned off. When the switch circuit (16) is turned on, the voltage (V1) of node (N1) becomes the voltage of the ground terminal from ΔVgs. The voltage (V2) of node (N2) is lowered by the voltage (ΔVgs) by the capacitor (18) to Vth 15 It becomes -ΔVgs.
[0030] And, by repeating the same operation after time t4, the oscillation circuit (100) outputs a signal (CLK) with a duty cycle of 50% to the output terminal.
[0031] FIG. 2 is a circuit diagram showing an example of an oscillation circuit (100) of the present embodiment.
[0032] The constant current circuit (10, 11, 12) is composed of a bias circuit (20) and PMOS transistors (10, 11, 12). The PMOS transistors (10, 11) are designed to carry the same current and are of the same size. The switch circuit (16, 17) is composed of NMOS transistors (16, 17).
[0033] The bias circuit (20) is equipped with NMOS transistors (21, 22), a resistor (23), and PMOS transistors (24, 25). The source of the NMOS transistor (21) is connected to the ground terminal through the resistor (23). The source of the NMOS transistor (22) is connected to the ground terminal, and its drain and gate are connected to the gate of the NMOS transistor (21). The source of the PMOS transistor (24) is connected to the power terminal, and its drain is connected to the drain of the NMOS transistor (22). The source of the PMOS transistor (25) is connected to the power terminal, and its drain and gate are connected to the gate of the PMOS transistor (24) and the drain of the NMOS transistor (21).
[0034] The bias circuit (20) configured as described above controls the current flowing through the PMOS transistor (25) I 25 If you do it this way, I 25 =ΔVgs ＿B It is indicated as / R. ΔVgs_B is the difference in Vgs of the NMOS transistors (21, 22), and R is the resistance value of the resistor (23).
[0035] The frequency (f) of the signal (CLK) of the oscillation circuit (100) is shown as follows.
[0036] f=( I / I 25 )(ΔVgs ＿B / ΔVgs) / 2CR
[0037] I is the current flowing through the constant current circuit (10, 11), and C is the capacitance value of the capacitor (18). Here, current I and I 25 Keeping it the same, the voltage difference ΔVgs ＿B If ΔVgs is designed to be the same, the frequency (f) is determined by the capacitance value of the capacitor (18) and the resistance value of the resistor (23).
[0038] That is, the frequency (f) of the signal (CLK) of the oscillation circuit (100) can be output at a constant frequency (f) without being affected by the imbalance of the characteristics of each MOS transistor, and without being affected by fluctuations such as power supply voltage or temperature. Furthermore, as can be seen from the equation, it is obvious that the frequency (f) improves by using a resistor with good temperature characteristics.
[0039] As described above, the oscillation circuit (100) of the present embodiment is configured to include an NMOS transistor (13-14) and a switch circuit (16-17) that raise and lower the voltage of the capacitor (18) to a constant voltage (ΔVgs), and a constant current circuit (10-11) that charges and discharges the capacitor (18) with a constant current. Therefore, even if the circuit size is small and the current consumption is small, it can output a constant frequency without being affected by fluctuations in power supply voltage or temperature.
[0040] Although embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications are possible within the scope of the spirit of the present invention. For example, the entire circuit can be configured in an inverted state with respect to the power terminal and the ground terminal, and the same effect can be obtained. In this case, the circuit configuration is made such that the PMOS transistor and the NMOS transistor are swapped. Explanation of the symbols
[0041] 10, 11, 12 Constant current circuit (PMOS transistor) 13, 14, 15 NMOS transistors 16, 17 Switch circuit (NMOS transistor) 18 capacitors 20 bias circuit 21, 22 NMOS transistor 23 resistors 24, 25 PMOS transistor 30, 31 inverter 100 oscillator circuit
Claims
Claim 1 An oscillation circuit comprising: a capacitor; a first constant current circuit connected between a first power terminal and one terminal of the capacitor; a first switch circuit connected between the other terminal of the capacitor and a second power terminal; a second constant current circuit having one terminal connected to the first power terminal; a first MOS transistor having its gate and drain connected to the other terminal of the second constant current circuit and its source connected to the other terminal of the capacitor; a second MOS transistor having its gate connected to the gate of the first MOS transistor and its drain connected to one terminal of the capacitor; a second switch circuit connected between the source of the second MOS transistor and the second power terminal; and an output terminal that outputs a signal based on the voltage of one terminal of the capacitor; wherein the first switch circuit and the second switch circuit are controlled to be on or off by the signal of the output terminal and the inverted signal of the signal. Claim 2 An oscillation circuit according to claim 1, wherein the first constant current circuit and the second constant current circuit are composed of a bias circuit and a third MOS transistor and a fourth MOS transistor that flow a current based on the current flowing through the bias circuit. Claim 3 An oscillation circuit according to claim 2, wherein the bias circuit comprises: a fifth MOS transistor having a gate and a drain connected and a source connected to the second power terminal; a sixth MOS transistor having a gate connected to the gate of the fifth MOS transistor and a source connected to the second power terminal through a resistor; a seventh MOS transistor having a drain connected to the drain of the fifth MOS transistor and a source connected to the first power terminal; and an eighth MOS transistor having a gate and a drain connected to the drain of the sixth MOS transistor, the gate of the seventh MOS transistor, and the gates of the third MOS transistor and the fourth MOS transistor, and a source connected to the first power terminal.