Complementary field-effect transistor using graphene gate and its manufacturing method

Abstract

A complementary transistor is provided. The complementary transistor comprises a first transistor including a first channel sheet and a first gate electrode surrounding the first channel sheet, and a second transistor disposed on the first transistor and including a second channel sheet and a second gate electrode surrounding the second channel sheet, wherein the first transistor and the second transistor are sequentially disposed on a substrate along the normal direction of the upper surface of the substrate, and the first gate electrode and the second gate electrode may comprise graphene.

Description

Technology Field

[0001] The present invention relates to a complementary field-effect transistor using a graphene gate and a method for manufacturing the same. Background Technology

[0002] With the recent miniaturization of semiconductor devices, Gate-All-Around (GAA) structures, in which the gate surrounds all sides of the channel, are being actively researched. Silicon (Si) and next-generation 2D material (TMDC)-based GAAFETs are generally fabricated based on a channel release step in which a dummy gate is sacrificed to expose the channel, followed by a Replacement Metal Gate (RMG) process in which a High-K insulating film and a metal gate are deposited.

[0003] However, the aforementioned conventional technology has the following limitations. First, when fabricating 2D channel-based GAAFETs, an insulating protection layer is essential to protect the channel during the channel release process; however, the addition of this protection layer increases the overall height of the device, worsening the aspect ratio and increasing the difficulty of subsequent processes such as via formation, while simultaneously causing unnecessary parasitic capacitance. Second, the existing RMG process has limitations in reducing the physical thickness of the gate stack located between channels, and has structural problems in which high dielectric constant insulating films are deposited even on unnecessary side-wall regions, further increasing parasitic capacitance, thereby degrading the switching speed and power consumption performance of the device.

[0004] In conclusion, if the existing silicon (Si)-based GAA process is applied directly to 2D materials, it is difficult to improve power consumption and switching speed due to these structural limitations, which acts as a fundamental obstacle to improving device performance and integration density. Meanwhile, Korean Patent Publication No. 10-2025-0110736 (July 21, 2025) discloses a semiconductor structure having a gate isolation layer and a method for manufacturing the same. Prior art literature

[65535] Republic of Korea Published Patent Application No. 10-2025-0110736 (July 21, 2025) The problem to be solved

[0005] The technical problem that the present invention aims to solve is to provide a complementary field-effect transistor using a graphene gate and a method for manufacturing the same.

[0006] Another technical problem that the present invention aims to solve is to provide a complementary field-effect transistor and a method for manufacturing the same, which can apply the existing silicon (Si)-based GAA process directly to two-dimensional materials.

[0007] Another technical problem that the present invention aims to solve is to provide a complementary field-effect transistor with an improved aspect ratio and a method for manufacturing the same.

[0008] Another technical problem that the present invention aims to solve is to provide a complementary field-effect transistor with reduced process difficulty and wiring resistance, and a method for manufacturing the same.

[0009] Another technical problem that the present invention aims to solve is to provide a complementary field-effect transistor with improved speed and power efficiency due to reduced parasitic capacitance, and a method for manufacturing the same.

[0010] Another technical problem that the present invention aims to solve is to provide a complementary field-effect transistor with an improved self-heating effect based on excellent heat dissipation characteristics, and a method for manufacturing the same.

[0011] The technical problems that the present invention aims to solve are not limited to those described above. means of solving the problem

[0012] To solve the technical problems described above, the present invention provides a complementary transistor.

[0013] According to one embodiment, the complementary transistor comprises a first transistor including a first channel sheet and a first gate electrode surrounding the first channel sheet, and a second transistor disposed on the first transistor and including a second channel sheet and a second gate electrode surrounding the second channel sheet, wherein the first transistor and the second transistor are sequentially disposed on a substrate along the normal direction of the upper surface of the substrate, and the first gate electrode and the second gate electrode may comprise graphene.

[0014] According to one embodiment, the first gate electrode includes a first upper gate region surrounding the upper part of the first channel sheet, a first lower gate region surrounding the lower part, and a first side gate region surrounding the side part, and the second gate electrode includes a second upper gate region surrounding the upper part of the second channel sheet, a second lower gate region surrounding the lower part, and a second side gate region surrounding the side part, wherein at least one of the first upper gate region and the first lower gate region includes a material different from the first side gate region, and at least one of the second upper gate region and the second lower gate region includes a material different from the second side gate region.

[0015] According to one embodiment, at least one of the first upper gate region and the first lower gate region comprises graphene, and at least one of the second upper gate region and the second lower gate region comprises graphene, and the first side gate region and the second side gate region may comprise a metal.

[0016] According to one embodiment, the first transistor may include a first upper protective sheet disposed above the first channel sheet, a first lower protective sheet disposed below the first channel sheet, and a first gate insulating film surrounding the first channel sheet, the first upper protective sheet, and the first lower protective sheet, and the second transistor may include a second upper protective sheet disposed above the second channel sheet, a second lower protective sheet disposed below the second channel sheet, and a second gate insulating film surrounding the second channel sheet, the first upper protective sheet, and the second lower protective sheet.

[0017] According to one embodiment, the first gate electrode may be arranged to surround the first gate insulating film, and the second gate electrode may be arranged to surround the second gate insulating film.

[0018] According to one embodiment, the first transistor is an n-type or p-type metal oxide field effect transistor (MOS FET), and the second transistor may be a metal oxide field effect transistor (MOS FET) of a different type from the first transistor.

[0019] According to one embodiment, the first channel sheet and the second channel sheet may include a two-dimensional semiconductor material.

[0020] According to one embodiment, the first channel sheet may include tungsten diselenide (WSe2), and the second channel sheet may include molybdenum disulfide (MoS2).

[0022] To solve the technical problems described above, the present invention provides a method for manufacturing a complementary transistor.

[0023] According to one embodiment, the method for manufacturing the complementary transistor comprises the steps of: preparing a stacked structure comprising a first sheet structure in which a first channel sheet is disposed between a first lower graphene layer and a first upper graphene layer that are spaced apart from each other in a second direction which is perpendicular to a first direction parallel to the upper surface of a substrate; a second sheet structure in which a second channel sheet is disposed between a second lower graphene layer and a second upper graphene layer that are spaced apart from each other on the upper surface of the first sheet structure along the second direction; etching the stacked structure to form a fin structure so as to expose a first region on the upper surface of the substrate and a second region spaced apart from the first region in the first direction; forming a gate structure surrounding the fin structure on the substrate; forming a first source electrode to be connected to one side of the first channel sheet and forming a first drain electrode to be connected to the other side to form a first transistor; and forming a second source electrode to be connected to one side of the second channel sheet and forming a second drain electrode to be connected to the other side It may include the step of forming an electrode to form a second transistor.

[0024] According to one embodiment, the step of preparing the laminated structure comprises: forming a first sheet structure on a substrate comprising the first channel sheet, a first upper protective sheet disposed on top of the first channel sheet, a first lower protective sheet disposed on bottom of the first channel sheet, the first channel sheet, the first upper protective sheet, and a first high dielectric film surrounding the first lower protective sheet, the first lower graphene layer disposed on bottom of the first high dielectric film, and a first upper graphene layer disposed on top of the first high dielectric film; forming an oxide layer on the first sheet structure; and forming a second channel sheet, a second upper protective sheet disposed on top of the second channel sheet, a second lower protective sheet disposed on bottom of the second channel sheet, the second channel sheet, the second upper protective sheet, and a second high dielectric film surrounding the second lower protective sheet, the second lower graphene layer disposed on bottom of the second high dielectric film, and the second upper The method may include the step of forming the second sheet structure, which includes a graphene layer, on the oxide layer.

[0025] According to one embodiment, the step of forming the first sheet structure may include: forming the first lower graphene layer on the substrate; forming the first high-dielectric layer on the first lower graphene layer; sequentially forming the first lower protective sheet, the first channel sheet, and the first upper protective sheet on the first high-dielectric layer; etching the first lower protective sheet, the first channel sheet, and the first upper protective sheet so that a first region of the first high-dielectric layer and a second region spaced apart from the first region in the first direction are exposed; providing a material identical to the first high-dielectric layer on the exposed first high-dielectric layer to form the first high-dielectric film surrounding the first lower protective sheet, the first channel sheet, and the first upper protective sheet; and forming the first upper graphene layer on the first high-dielectric film.

[0026] According to one embodiment, the step of forming the second sheet structure may include: forming the second lower graphene layer on the oxide layer; forming the second high-dielectric layer on the second lower graphene layer; sequentially forming the second lower protective sheet, the second channel sheet, and the second upper protective sheet on the second high-dielectric layer; etching the second lower protective sheet, the second channel sheet, and the second upper protective sheet so that a first region of the second high-dielectric layer and a second region spaced apart from the first region in the first direction are exposed; providing a material identical to the second high-dielectric layer on the exposed second high-dielectric layer to form the second high-dielectric film surrounding the second lower protective sheet, the second channel sheet, and the second upper protective sheet; and forming the second upper graphene layer on the second high-dielectric film.

[0027] According to one embodiment, the step of forming the first sheet structure further includes a step of flattening the upper portion of the first high dielectric film after the step of forming the first high dielectric film and before the step of forming the first upper graphene layer, and the step of forming the second sheet structure may further include a step of flattening the upper portion of the second high dielectric film after the step of forming the second high dielectric film and before the step of forming the second upper graphene layer.

[0028] According to one embodiment, the first lower graphene layer, the first upper graphene layer, and the gate structure form a first gate electrode of the first transistor, and the second lower graphene layer, the second upper graphene layer, and the gate structure form a second gate electrode of the second transistor, wherein the first gate electrode is formed to surround the first channel sheet and the second gate electrode is formed to surround the second channel sheet.

[0030] To solve the technical problems described above, the present invention provides a semiconductor device.

[0031] According to one embodiment, the semiconductor device comprises a first gate structure including a first channel sheet of n-type or p-type and a first gate electrode surrounding the first channel sheet, and a second gate structure including a second channel sheet of a different type from the first channel sheet and a second gate electrode surrounding the second channel sheet, wherein the first channel sheet and the second channel sheet are located at different levels along the normal direction of the upper surface of the substrate, and the first gate electrode and the second gate electrode may include graphene. Effects of the invention

[0032] A complementary transistor according to an embodiment of the present invention comprises a first transistor including a first channel sheet and a first gate electrode surrounding the first channel sheet, and a second transistor disposed on the first transistor including a second channel sheet and a second gate electrode surrounding the second channel sheet, wherein the first gate electrode and the second gate electrode may comprise graphene. Accordingly, process difficulty may be alleviated and wiring resistance reduced due to improved aspect ratio, the speed and power efficiency of the device may be improved due to reduced parasitic capacitance, and the self-heating effect based on excellent heat dissipation characteristics may be improved.

[0033] More specifically, in the case of conventional 2D channel-based GAA-CFETs, the device height increases due to the protection layer and metal gate, which increases the aspect ratio of the wiring from the buried power line (BPR) to the upper NMOS, thereby increasing the difficulty of the process. In contrast, the complementary transistor (GAA-CFET) according to an embodiment of the present invention can reduce the overall height through a graphene gate, thereby shortening the wiring length between the buried power line (BPR) and the NMOS, improving the aspect ratio and ensuring ease of process. Additionally, since the total length of the intermediate wiring (MOL) can be reduced by about 30%, an improvement in wiring resistance can also be expected.

[0034] In addition, the complementary transistor (GAA-CFET) according to an embodiment of the present invention may have a significantly lower total capacitance compared to a conventional 2D channel-based GAA-CFET. In particular, the parasitic capacitance at a gate voltage of 0 V may show an improvement of 32%, which is similar to the reduction in device height (30%). This reduction in parasitic capacitance can serve as a key factor in improving the switching speed of the device and reducing dynamic power consumption.

[0035] In addition, graphene used as a gate has superior thermal conductivity compared to conventional metals, and the reduced device height can shorten the path for heat to be released externally, thereby improving the self-heating effect. Brief explanation of the drawing

[0036] FIGS. 1 and FIGS. 2 are drawings for illustrating a complementary transistor according to an embodiment of the present invention. Figure 3 is a cross-sectional view of XX' of Figure 1. FIG. 4 is a diagram illustrating the first transistor and the second transistor of a complementary transistor according to an embodiment of the present invention. FIG. 5 is a flowchart illustrating a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIG. 6 is a flowchart for specifically explaining step S100 of the method for manufacturing a complementary transistor according to an embodiment of the present invention. FIG. 7 is a flowchart for specifically explaining step S110 of the method for manufacturing a complementary transistor according to an embodiment of the present invention. FIGS. 8 and 9 are drawings for explaining step S111 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIGS. 10 and FIGS. 11 are drawings for explaining step S112 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIGS. 12 and FIGS. 13 are drawings for explaining step S113 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIGS. 14 and FIGS. 15 are drawings for explaining step S114 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIGS. 16 and 17 are drawings for explaining step S115 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIGS. 18 and 19 are drawings for explaining step S116 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIGS. 20 and 21 are drawings for explaining step S117 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIG. 22 is a drawing for explaining a first sheet structure formed through step S110 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIG. 23 is a diagram illustrating an oxide layer formed through step S120 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIG. 24 is a flowchart for specifically explaining step S130 of the method for manufacturing a complementary transistor according to an embodiment of the present invention. FIG. 25 is a drawing for explaining a stacked structure formed through step S100 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIG. 26 is a diagram illustrating step S200 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIG. 27 is a diagram illustrating step S300 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIG. 28 is a diagram illustrating step S400 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIG. 29 is a diagram illustrating step S500 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIG. 30 is a diagram illustrating step S600 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIG. 31 is a diagram illustrating step S700 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIGS. 32 and FIGS. 33 are drawings for explaining step S800 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIGS. 34 and FIGS. 35 are drawings for explaining step S900 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIG. 36 is a diagram illustrating step S1000 of a method for manufacturing a complementary transistor according to an embodiment of the present invention. FIGS. 37 to 39 are drawings for explaining a complementary transistor according to an experimental example of the present invention and a complementary transistor according to a comparative example. FIG. 40 is a diagram illustrating the gate capacitance of a complementary transistor according to an experimental example and a comparative example of the present invention. FIG. 41 is a diagram illustrating the self-heating effect of a complementary transistor according to an experimental example and a comparative example of the present invention. FIG. 42 is a diagram illustrating the TCAD simulation of a complementary transistor and the calibration results of an actually measured IV curve according to an experimental example of the present invention. FIGS. 43 and FIGS. 44 are drawings illustrating the results of resistance and capacitance analysis of complementary transistors according to experimental and comparative examples of the present invention. FIGS. 45 and 46 are drawings illustrating the results of the analysis of the gate control capability of a complementary transistor according to an experimental example and a comparative example of the present invention. FIG. 47 is a diagram illustrating the transfer curve characteristics of a complementary transistor according to an experimental example and a comparative example of the present invention. FIG. 48 is a diagram illustrating the speed-power characteristics of an inverter according to experimental and comparative examples of the present invention. Specific details for implementing the invention

[0037] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. However, the technical concept of the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed content is thorough and complete and to ensure that the concept of the present invention is sufficiently conveyed to those skilled in the art.

[0038] In this specification, when a component is described as being on another component, it means that it may be formed directly on the other component or that a third component may be interposed between them. Additionally, in the drawings, the thicknesses of the films and regions are exaggerated for the effective description of the technical content.

[0039] Additionally, although terms such as first, second, third, etc., have been used to describe various components in the various embodiments of this specification, these components should not be limited by such terms. These terms are used merely to distinguish one component from another. Accordingly, what is referred to as the first component in one embodiment may be referred to as the second component in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiment. Furthermore, in this specification, "and / or" is used to mean including at least one of the components listed before and after it.

[0040] In the specification, singular expressions include plural expressions unless the context clearly indicates otherwise. Furthermore, terms such as "include" or "have" are intended to specify the existence of the features, numbers, steps, components, or combinations thereof described in the specification, and should not be understood as excluding the existence or addition of one or more other features, numbers, steps, components, or combinations thereof. Additionally, in this specification, "connection" is used to include both indirectly connecting multiple components and directly connecting them.

[0041] Furthermore, in describing the present invention below, if it is determined that a detailed description of related known functions or configurations could unnecessarily obscure the essence of the invention, such detailed description will be omitted.

[0043] FIGS. 1 and 2 are drawings for explaining a complementary transistor according to an embodiment of the present invention, FIG. 3 is a cross-sectional view of FIG. 1', and FIG. 4 is a drawing for explaining a first transistor and a second transistor of a complementary transistor according to an embodiment of the present invention. More specifically, FIG. 1 shows a state in which the source electrode and the drain electrode are omitted, and FIG. 2 shows a state in which the source electrode and the drain electrode are indicated.

[0044] Referring to FIGS. 1 to 4, a complementary transistor according to an embodiment of the present invention comprises a substrate (S), a first transistor (TR1) disposed on the substrate (S), and a second transistor (TR2) disposed on the first transistor (TR2), wherein the first transistor (TR1) and the second transistor (TR2) may be sequentially disposed on the substrate (S) along the normal direction of the upper surface of the substrate (S). According to one embodiment, a direction parallel to the upper surface of the substrate (S) is defined as a first direction (X-axis direction), a normal direction of the upper surface of the substrate (S) is defined as a second direction (Y-axis direction), and a direction perpendicular to both the first direction and the second direction may be defined as a third direction (Z-axis direction).

[0045] The first transistor (TR1) is a Metal Oxide Semiconductor Field Effect Transistor (MOS FET) and may include a first channel sheet (C1), a first upper protection sheet (TP1), a first lower protection sheet (BP1), a first gate insulating film (GIL1), a first gate electrode (GE1), a first source electrode (S1), and a first drain electrode (D1). According to one embodiment, the first transistor (TR1) may have a Gate-All-Around (GAA) structure in which the first channel sheet (C1) is surrounded by the first gate electrode (GE1). Additionally, according to one embodiment, the first transistor (TR1) may also be defined as a first gate structure.

[0046] The first channel sheet (C1) is for forming a channel of the first transistor (TR1) and may include a two-dimensional semiconductor material. More specifically, the first channel sheet (C1) may include a p-type two-dimensional semiconductor material. For example, the first channel sheet (C1) may include tungsten diselenide (WSe2).

[0047] The first upper protective sheet (TP1) may be placed on the upper side of the first channel sheet (C1), and the first lower protective sheet (BP1) may be placed on the lower side of the first channel sheet (C1). The first upper protective sheet (TP1) and the first lower protective sheet (BP1) are intended to protect the first channel sheet (C1) during the process of manufacturing a complementary transistor according to the embodiment, and may include an insulating material. For example, the first upper protective sheet (TP1) and the first lower protective sheet (BP1) may include any one of aluminum oxide (Al2O3), silicon oxide (SiO2), hafnium oxide (HfO2), and silicon nitride (Si3N4).

[0048] The first gate insulating film (GIL1) may be arranged to surround the first channel sheet (C1), the first upper protective sheet (TP1), and the first lower protective sheet (BP1). For example, the first gate insulating film (GIL1) may comprise any one of aluminum oxide (Al2O3), silicon oxide (SiO2), hafnium oxide (HfO2), and silicon nitride (Si3N4).

[0049] The first gate electrode (GE1) may be positioned to surround the first gate insulating film (GIL1). According to one embodiment, the first gate electrode (GE1) comprises a first upper gate region (TGA1) surrounding the upper portion of the first channel sheet (C1), a first lower gate region (BGA1) surrounding the lower portion of the first channel sheet (C1), and a first side gate region (SGA1) surrounding the side portion, wherein at least one of the first upper gate region (TGA1) and the first lower gate region (BGA1) may comprise a material different from that of the first side gate region (SGA1). For example, at least one of the first upper gate region (TGA1) and the first lower gate region (BGA1) may comprise graphene, while the first side gate region (SGA1) may comprise a metal.

[0050] The first source electrode (S1) may be positioned to be in contact with one side of the first channel sheet (C1) and connected to one side of the first channel sheet (C1), and the first drain electrode (D1) may be positioned to be in contact with the other side of the first channel sheet (C1) and connected to the other side of the first channel sheet (C1). For example, the first source electrode (S1) and the first drain electrode (D1) may include at least one of gold (Au), nickel (Ni), titanium nitride (TiN), antimony (Sb), bismuth (Bi), silver (Ag), tin (Sn), titanium (Ti), palladium (Pd), platinum (Pt), and ruthenium (Ru).

[0051] According to one embodiment, the first transistor (TR1) may include a plurality of first channel sheets (C1) spaced apart and arranged parallel in the second direction (Y-axis direction), and each first channel sheet (C1) may have a first upper protection sheet (TP1) and a first lower protection sheet (BP1) disposed on its upper and lower sides, and may be surrounded by the first gate insulating film (GIL1) and the first gate electrode (GE1). That is, when the first transistor (TR1) includes a plurality of first channel sheets (C1), at least one of the upper and lower sides of each first channel sheet (C1) may be surrounded by a graphene gate electrode, while the side may be surrounded by a metal gate electrode.

[0052] The second transistor (TR2) is a Metal Oxide Semiconductor Field Effect Transistor (MOS FET) and may include a second channel sheet (C2), a second upper protection sheet (TP2), a second lower protection sheet (BP2), a second gate insulating film (GIL2), a second gate electrode (GE2), a second source electrode (S2), and a second drain electrode (D2). According to one embodiment, the second transistor (TR2) may have a Gate-All-Around (GAA) structure in which the second channel sheet (C2) is surrounded by the second gate electrode (GE2). Additionally, according to one embodiment, the second transistor (TR2) may also be defined as a second gate structure.

[0053] The second channel sheet (C2) may be placed on the substrate (S) along the second direction (Y-axis direction) above the first channel sheet (C1). That is, the first channel sheet (C1) and the second channel sheet (C2) may be located at different levels along the normal direction (Y-axis direction) of the upper surface of the substrate (S), such that the second channel sheet (C2) is located at a relatively higher level and the first channel sheet (C1) is located at a relatively lower level. The second channel sheet (C2) is for forming a channel of the second transistor (TR2) and may include a two-dimensional semiconductor material. More specifically, the second channel sheet (C2) may include an n-type two-dimensional semiconductor material. For example, the second channel sheet (C2) may include molybdenum disulfide (MoS2).

[0054] The second upper protective sheet (TP2) may be positioned above the second channel sheet (C2), and the second lower protective sheet (BP2) may be positioned below the second channel sheet (C2). The second upper protective sheet (TP2) and the second lower protective sheet (BP2) are intended to protect the second channel sheet (C2) during the process of manufacturing a complementary transistor according to the embodiment, and may include an insulating material. For example, the second upper protective sheet (TP2) and the second lower protective sheet (BP2) may include any one of aluminum oxide (Al2O3), silicon oxide (SiO2), hafnium oxide (HfO2), and silicon nitride (Si3N4).

[0055] The second gate insulating film (GIL2) may be arranged to surround the second channel sheet (C2), the second upper protective sheet (TP2), and the second lower protective sheet (BP2). For example, the second gate insulating film (GIL2) may comprise any one of aluminum oxide (Al2O3), silicon oxide (SiO2), hafnium oxide (HfO2), and silicon nitride (Si3N4).

[0056] The second gate electrode (GE2) may be positioned to surround the second gate insulating film (GIL2). According to one embodiment, the second gate electrode (GE2) comprises a second upper gate region (TGA2) surrounding the upper portion of the second channel sheet (C2), a second lower gate region (BGA2) surrounding the lower portion of the second channel sheet (C2), and a second side gate region (SGA2) surrounding the side portion, wherein at least one of the second upper gate region (TGA2) and the second lower gate region (BGA2) may comprise a material different from that of the second side gate region (SGA2). For example, at least one of the second upper gate region (TGA2) and the second lower gate region (BGA2) may comprise graphene, while the second side gate region (SGA2) may comprise a metal.

[0057] The second source electrode (S2) may be arranged to surround one side of the second channel sheet (C2) and connected to one side of the second channel sheet (C2), and the second drain electrode (D2) may be arranged to surround the other side of the second channel sheet (C2) and connected to the other side of the second channel sheet (C2). For example, the second source electrode (S2) and the second drain electrode (D2) may include at least one of gold (Au), nickel (Ni), titanium nitride (TiN), antimony (Sb), bismuth (Bi), silver (Ag), tin (Sn), titanium (Ti), palladium (Pd), platinum (Pt), and ruthenium (Ru).

[0058] According to one embodiment, the second transistor (TR2) may include a plurality of second channel sheets (C2) spaced apart and arranged parallel in the second direction (Y-axis direction), and each second channel sheet (C2) may have a second upper protection sheet (TP2) and a second lower protection sheet (BP2) disposed on its upper and lower sides, and may be surrounded by the second gate insulating film (GIL2) and the second gate electrode (GE2). That is, when the second transistor (TR2) includes a plurality of second channel sheets (C2), at least one of the upper and lower sides of each second channel sheet (C2) may be surrounded by a graphene gate electrode, while the side may be surrounded by a metal gate electrode.

[0059] Consequently, a complementary transistor according to an embodiment of the present invention comprises a first transistor (TR1) including a first channel sheet (C1) and a first gate electrode (GE1) surrounding the first channel sheet (C1), and a second transistor (TR2) disposed on the first transistor (TR1) and including a second channel sheet (C2) and a second gate electrode (GE2) surrounding the second channel sheet (C2), wherein the first gate electrode and the second gate electrode may comprise graphene. Accordingly, process difficulty may be alleviated and wiring resistance reduced due to improved aspect ratio, the speed and power efficiency of the device may be improved due to reduced parasitic capacitance, and the self-heating effect based on excellent heat dissipation characteristics may be improved.

[0060] More specifically, in the case of conventional 2D channel-based GAA-CFETs, the device height increases due to the protection layer and metal gate, which increases the aspect ratio of the wiring from the buried power line (BPR) to the upper NMOS, thereby increasing the difficulty of the process. In contrast, the complementary transistor (GAA-CFET) according to an embodiment of the present invention can reduce the overall height through a graphene gate, thereby shortening the wiring length between the buried power line (BPR) and the NMOS, improving the aspect ratio and ensuring ease of process. Additionally, since the total length of the intermediate wiring (MOL) can be reduced by about 30%, an improvement in wiring resistance can also be expected.

[0061] In addition, the complementary transistor (GAA-CFET) according to an embodiment of the present invention may have a significantly lower total capacitance compared to a conventional 2D channel-based GAA-CFET. In particular, the parasitic capacitance at a gate voltage of 0 V may show an improvement of 32%, which is similar to the reduction in device height (30%). This reduction in parasitic capacitance can serve as a key factor in improving the switching speed of the device and reducing dynamic power consumption.

[0062] In addition, graphene used as a gate has superior thermal conductivity compared to conventional metals, and the reduced device height can shorten the path for heat to be released externally, thereby improving the self-heating effect.

[0064] The complementary transistor according to an embodiment of the present invention has been described above. Below, a method for manufacturing the complementary transistor according to an embodiment of the present invention is described.

[0065] FIG. 5 is a flowchart for explaining a method for manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 6 is a flowchart for specifically explaining step S100 of a method for manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 7 is a flowchart for specifically explaining step S110 of a method for manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 8 and FIG. 9 are diagrams for explaining step S111 of a method for manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 10 and FIG. 11 are diagrams for explaining step S112 of a method for manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 12 and FIG. 13 are diagrams for explaining step S113 of a method for manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 14 and FIG. 15 are diagrams for explaining step S114 of a method for manufacturing a complementary transistor according to an embodiment of the present invention, and FIG. 16 and FIG. 17 are diagrams for step S115 of a method for manufacturing a complementary transistor according to an embodiment of the present invention FIGS. 18 and 19 are drawings for explaining the method of manufacturing a complementary transistor according to an embodiment of the present invention, FIGS. 20 and 21 are drawings for explaining the method of manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 22 is a drawing for explaining a first sheet structure formed through step S110 of the method of manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 23 is a drawing for explaining an oxide layer formed through step S120 of the method of manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 24 is a flowchart for specifically explaining step S130 of the method of manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 25 is a drawing for explaining a stacked structure formed through step S100 of the method of manufacturing a complementary transistor according to an embodiment of the present invention.FIG. 26 is a diagram illustrating step S200 of a method for manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 27 is a diagram illustrating step S300 of a method for manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 28 is a diagram illustrating step S400 of a method for manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 29 is a diagram illustrating step S500 of a method for manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 30 is a diagram illustrating step S600 of a method for manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 31 is a diagram illustrating step S700 of a method for manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 32 and FIG. 33 are diagrams illustrating step S800 of a method for manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 34 and FIG. 35 are diagrams illustrating step S900 of a method for manufacturing a complementary transistor according to an embodiment of the present invention, FIG. 36 is a drawing illustrating step S1000 of a method for manufacturing a complementary transistor according to an embodiment of the present invention.

[0066] Referring to FIG. 5, a method for manufacturing a complementary transistor according to an embodiment of the present invention may include a stacked structure preparation step (S100), a fin structure formation step (S200), a buried power rail formation step (S300), a gate structure formation step (S400), a fin structure etching step (S500), an optional etching step (S600), an internal spacer formation step (S700), a first transistor formation step (S800), a second transistor formation step (S900), and a BEOL formation step (S1000).

[0067] Referring to FIG. 6, the laminated structure preparation step (S100) may include a first sheet structure forming step (S110), an oxide layer forming step (S120), and a second sheet structure forming step (S120). According to one embodiment, as shown in FIG. 7, the step S110 may include steps S111 to S117, and as shown in FIG. 24, the step S130 may include steps S131 to S132.

[0068] More specifically, referring to FIGS. 7 to 9, a first lower graphene layer (BGP1) may be formed on a substrate (S) (S111). According to one embodiment, the first lower graphene layer (BGP1) may be formed by a direct growth method. According to one embodiment, the first lower graphene layer (BGP1) may be identical to the first lower gate region (BGA1) of the first gate electrode (GE1) of the complementary transistor described with reference to FIGS. 1 to 4.

[0069] Referring to FIGS. 7, 10, and 11, a first high-dielectric layer (HK1) may be formed on the first lower graphene layer (BGP1) (S112). According to one embodiment, the first high-dielectric layer (HK1) may include a high-dielectric (High-K) material. For example, the first high-dielectric layer (HK1) may include any one of hafnium oxide (HfO2), zirconium oxide (ZrO2), and tantalum oxide (Ta2O5). According to one embodiment, the first high-dielectric layer (HK1) may be formed by either Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).

[0070] Referring to FIGS. 7, 12, and 13, a first lower protective sheet (BP1), a first channel sheet (C1), and a first upper protective sheet (TP1) may be sequentially formed on the first high dielectric layer (HK1) (S113). According to one embodiment, the first channel sheet (C1) may comprise tungsten diselenide (WSe2) and may be formed by either chemical vapor deposition (CVD) or atomic layer deposition (ALD). According to one embodiment, the first lower protective sheet (BP1) and the first upper protective sheet (TP1) may comprise any one of aluminum oxide (Al2O3), silicon oxide (SiO2), hafnium oxide (HfO2), and silicon nitride (Si3N4) and may be formed by either chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0071] Referring to FIGS. 7, 14, and 15, the first lower protective sheet (BP1), the first channel sheet (C1), and the first upper protective sheet (TP1) can be etched so that the first region (A1) and the second region (A2) of the first high dielectric layer (HK1) are exposed (S114). According to one embodiment, the first region (A1) and the second region (A2) may be defined as regions spaced apart from each other along the first direction (X-axis direction). Accordingly, in step S114, the first region (A1) and the second region (A2) of the first high dielectric layer (HK1) are exposed, while the region between the first region (A1) and the second region (A2) may not be exposed by the first lower protective sheet (BP1), the first channel sheet (C1), and the first upper protective sheet (TP1).

[0072] Referring to FIGS. 7, 16 and 17, a high-dielectric material can be provided to the exposed first high-dielectric layer (HK1), the first lower protection sheet (BP1), the first channel sheet (C1), and the first upper protection sheet (TP1) to form a first high-dielectric film (HKL1) surrounding the exposed first high-dielectric layer (HK1), the first lower protection sheet (BP1), the first channel sheet (C1), and the first upper protection sheet (TP1) (S115). According to one embodiment, the high-dielectric material for forming the first high-dielectric film (HKL1) may be the same as the high-dielectric material for forming the first high-dielectric layer (HK1), and the first high-dielectric film (HKL1) may be the same as the first gate insulating film (GIL1) of the complementary transistor described with reference to FIGS. 1 to 4.

[0073] Referring to FIGS. 7, 18, and 19, the upper surface of the first high dielectric film (HK1) can be flattened (S116). According to one embodiment, the upper surface of the first high dielectric film (HK1) can be flattened by a Chemical Mechanical Polishing (CMP) process.

[0074] Referring to FIGS. 7, 20, and 21, a first upper graphene layer (TGP1) may be formed on the first high dielectric film (HK1) (S117). According to one embodiment, the first upper graphene layer (TGP1) may be formed by a direct growth method. According to one embodiment, the first upper graphene layer (TGP1) may be identical to the first upper gate region (TGA1) of the first gate electrode (GE1) of the complementary transistor described with reference to FIGS. 1 to 4.

[0075] Referring to FIG. 22, steps S111 through S117 may be repeated multiple times, thereby forming a first sheet structure (SHS1) in which a plurality of first channel sheets (C1) are spaced apart and arranged side by side along the second direction (Y-axis direction) (S110). According to one embodiment, the first sheet structure (SHS1) may be defined as a structure in which a first channel sheet (C1) is arranged between the first lower graphene layer (BGP1) and the first upper graphene layer (TGP1) which are spaced apart from each other in the second direction (Y-axis direction).

[0076] Referring to FIG. 6 and FIG. 23, an oxide layer (OL) may be formed on the first sheet structure (SHS1) (S120). According to one embodiment, the oxide layer (OL) may include any one of aluminum oxide (Al2O3), silicon oxide (SiO2), and hafnium oxide (HfO2), and may be formed by either chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0077] Referring to FIGS. 24 and 25, after the oxide layer (OL) is formed, a second lower graphene layer (BGP2) is formed on the oxide layer (OL) (S131); a second high-dielectric layer (HK2) is formed on the second lower graphene layer (BGP2) (S132); a first lower protective sheet (BP2), a second channel sheet (C2), and a second upper protective sheet (TP2) are sequentially formed on the second high-dielectric layer (HK2) (S133); the second lower protective sheet (BP2), the second channel sheet (C2), and the second upper protective sheet (TP2) are etched so that the first region and the second region of the second high-dielectric layer (HK2) are exposed (S134); and a high-dielectric material is provided to the exposed second high-dielectric layer (HK2), the second lower protective sheet (BP2), the second channel sheet (C2), and the second upper protective sheet (TP2). The steps of forming a second high-dielectric film (HKL2) surrounding the exposed second high-dielectric layer (HK2), the second lower protective sheet (BP2), the second channel sheet (C2), and the first upper protective sheet (TP2) (S135), flattening the upper surface of the second high-dielectric film (HKL2) (S136), and forming a second upper graphene layer (TGP2) on the second high-dielectric film (HKL2) (S137) may be performed sequentially, and steps S131 through S137 may be repeated multiple times. As a result, a second sheet structure (SHS2) may be formed in which a plurality of the second channel sheets (C2) are spaced apart and arranged side by side along the second direction (Y-axis direction) (S130). According to one embodiment, the second sheet structure (SHS2) may be defined as a structure in which a second channel sheet (C2) is disposed between the second lower graphene layer (BGP2) and the second upper graphene layer (TGP2), which are spaced apart from each other in the second direction (Y-axis direction).According to one embodiment, the second lower graphene layer (BGP2) may be identical to the second lower gate region (BGA2) of the second gate electrode (GE2) of the complementary transistor described with reference to FIGS. 1 to 4, the second high dielectric film (HKL2) may be identical to the second gate insulating film (GIL2), and the second upper graphene layer (TGP2) may be identical to the second upper gate region (TGA2).

[0078] As a result, through the above S100 step, a laminated structure (STS) in which the first sheet structure (SHS1), the oxide layer (OL), and the second sheet structure (SHS2) are sequentially laminated on the substrate (S) can be prepared (S100).

[0079] Referring to FIGS. 5 and 26, a fin structure (FS) can be formed by etching the stacked structure (STS) so that a first region (B1) and a second region (B2) on the upper surface of the substrate (S) are exposed (S200). According to one embodiment, the first region (B1) and the second region (B2) may be defined as regions spaced apart from each other along the first direction (X-axis direction). Accordingly, in step S200, the first region (B1) and the second region (B2) of the first substrate (S) are exposed, while the region between the first region (B1) and the second region (B2) may not be exposed by the fin structure (FS).

[0080] Referring to FIG. 5 and FIG. 27, a buried power rail (BPR) can be formed on the substrate (S) (S300). The above-described buried power rail (BPR) is intended to provide a path for effectively supplying power to the lower part of the device, and according to one embodiment, it can be formed through the steps of: etching the substrate (S) along the shape of the fin structure (FS) to form a trench (S310); forming a barrier to prevent metal penetration on the exposed outer surface of the substrate (S) and the fin structure (FS) (S320); depositing a titanium nitride (TiN) liner and tungsten (W) on the barrier to fill the trench (S330); etching the titanium nitride (TiN) liner and tungsten (W) to etch the fin structure (FS) (S340); filling the etched area with silicon oxide (S350); and etching the silicon oxide to expose the fin structure (FS) (S360).

[0081] Referring to FIGS. 5 and FIGS. 28, a gate structure (GS) surrounding the pin structure (FS) can be formed on the substrate (S) (S400). According to one embodiment, the gate structure (GS) can be formed to surround the central part of the side wall and the central part of the top surface of the pin structure (FS). Accordingly, the central part of the pin structure (FS) is not exposed by the gate structure (GS), while one end and the other end of the pin structure (FS) are not surrounded by the gate structure (GS) and can be exposed to the outside.

[0082] According to one embodiment, the gate structure (GS) may include a metal and may be identical to the first side gate region (SGA1) and the second side gate region (SGA2) of the complementary transistor described with reference to FIGS. 1 to 4. That is, the first lower graphene layer (BGP1), the first upper graphene layer (TGP1), and the gate structure (GS) may form the first gate electrode (GE1) of the first transistor (TR1), and the second lower graphene layer (BGP2), the second upper graphene layer (TGP2), and the gate structure (GS) may form the second gate electrode (GE2) of the second transistor (TR2).

[0083] According to one embodiment, a first sidewall spacer (GSP1) may be formed on one side of the gate structure (GS), and a second sidewall spacer (GSP2) may be further formed on the other side. The first sidewall spacer (GSP1) and the second sidewall spacer (GSP2) may also be formed to surround the central part of the sidewall and the central part of the top surface of the pin structure (FS), just like the gate structure (GS), and the physical shape and insulation characteristics of the gate electrode may be determined as the first sidewall spacer (GSP1) and the second sidewall spacer (GSP2) are formed. According to one embodiment, dual workfunction engineering may be applied in step S400 to set a threshold voltage suitable for PMOS and NMOS.

[0084] Referring to FIGS. 5 and FIGS. 29, the fin structure (FS) that is exposed to the outside and not surrounded by the gate structure (GS) can be etched (S500). More specifically, the fin structure (FS) can be etched so that regions excluding the region surrounded by the gate structure (GS), the first sidewall spacer (GSP1), and the second sidewall spacer (GSP2) are removed.

[0085] Referring to FIG. 5 and FIG. 30, a region of the first high dielectric film (HKL1), the first lower graphene layer (BGP1), the first upper graphene layer (TGP1), the second high dielectric film (HKL2), the second lower graphene layer (BGP2), and the second upper graphene layer (TGP2) among the remaining fin structure (FS) can be selectively etched (S600). That is, among the fin structure (FS), the first channel sheet (C1), the first upper protection sheet (TP1), the first lower protection sheet (BP1), the second channel sheet (C2), the second upper protection sheet (TP2), and the second lower protection sheet (BP2) remain, while a region of the first high dielectric film (HKL1), the first lower graphene layer (BGP1), the first upper graphene layer (TGP1), the second high dielectric film (HKL2), the second lower graphene layer (BGP2), and the second upper graphene layer (TGP2) can be etched. More specifically, the first high dielectric film (HKL1), the first lower graphene layer (BGP1), the first upper graphene layer (TGP1), the second high dielectric film (HKL2), the second lower graphene layer (BGP2), and the second upper graphene layer (TGP2) can each be etched in the direction of the gate structure (GS) from the first sidewall spacer (GSP1) and the second sidewall spacer (GSP2).

[0086] According to one embodiment, the first upper graphene layer (TGP1), the first lower graphene layer (BGP1), the second upper graphene layer (TGP2), and the second lower graphene layer (BGP2) are first etched using hydrogen plasma (H2 plasma), and then the first high dielectric film (HKL1) and the second high dielectric film (HKL2) can be etched by a thermal atomic layer etching method using titanium tetrachloride (TiCl4) and hydrogen fluoride (HF).

[0087] Referring to FIGS. 5 and FIGS. 31, an internal spacer covering the first high dielectric film (HKL1), the first lower graphene layer (BGP1), the first upper graphene layer (TGP1), the second high dielectric film (HKL2), the second lower graphene layer (BGP2), and the second upper graphene layer (TGP2) remaining after etching can be formed (S700). According to one embodiment, the internal spacer can be formed of the same material as the first and second sidewall spacers (GSP1, GSP2). As the above internal spacer is formed, the remaining first high dielectric film (HKL1), the first lower graphene layer (BGP1), the first upper graphene layer (TGP1), the second high dielectric film (HKL2), the second lower graphene layer (BGP2), and the second upper graphene layer (TGP2) are not exposed, whereas the first channel sheet (C1), the first upper protective sheet (TP1), the first lower protective sheet (BP1), the second channel sheet (C2), the second upper protective sheet (TP2), and the second lower protective sheet (BP2) may be exposed to the outside.

[0088] Referring to FIG. 5 and FIG. 32, a first source electrode (S1) can be formed to be connected to one side of the first channel sheet (C1) and a first drain electrode (D1) can be formed to be connected to the other side to form a first transistor (TR1) (S800). According to one embodiment, as shown in FIG. 33, a first oxide film (OL1) for insulation and a first contact (CT1) for connection to a buried power rail (BPR) can be further formed around the first source electrode (S1) and the first drain electrode (D1).

[0089] Referring to FIG. 5 and FIG. 34, a second source electrode (S2) can be formed to be connected to one side of the second channel sheet (C2) and a second drain electrode (D2) can be formed to be connected to the other side to form a second transistor (TR2) (S900). According to one embodiment, as shown in FIG. 35, a second oxide film (OL2) for insulation and a second contact (CT2) for connection to a buried power rail (BPR) can be further formed around the second source electrode (S2) and the second drain electrode (D2).

[0090] Referring to FIGS. 5 and FIGS. 36, a BEOL (Back End Of Line) may be formed to connect the first source electrode (S1), the first drain electrode (D1), the second source electrode (S2), and the second drain electrode (D2) to a metal wiring layer (S1000). According to one embodiment, as shown in FIG. 36, a third oxide film (OL3) may be further formed to surround the exposed area of ​​the second contact (CT2), the first sidewall spacer (GSP1), the second sidewall spacer (GSP2), and the gate structure (GS).

[0092] The above describes a method for manufacturing a complementary transistor according to an embodiment of the present invention. Specific experimental examples are described below.

[0093] FIGS. 37 to 39 are drawings for explaining a complementary transistor according to an experimental example of the present invention and a complementary transistor according to a comparative example.

[0094] Referring to FIGS. 37 to 39, a complementary transistor (Ex-CFET) according to an experimental example and a complementary transistor (Cx-CFET) according to a comparative example are shown. More specifically, FIG. 37 shows a perspective view, FIG. 38 (a) and (b) show the YY' and XX' cross-sectional views of FIG. 37, and FIG. 39 shows the low aspect ratio of the complementary transistor (Ex-CFET) according to the experimental example compared to the complementary transistor (Cx-CFET) according to the comparative example. In addition, the gate electrode of the complementary transistor (Cx-CFET) according to the comparative example is formed entirely of metal as in the conventional method, whereas in the complementary transistor (Ex-CFET) according to the experimental example, at least one of the upper gate region and the lower gate region of the gate electrode is formed of graphene.

[0095] As can be seen in Fig. 39 (a), the complementary transistor (Cx-CFET) according to the comparative example has increased device height due to the protection layer and metal gate, resulting in a relatively high aspect ratio of the wiring from the buried power wiring (BPR) to the upper NMOS, which increases the difficulty of the process. On the other hand, as can be seen in Fig. 39 (b), the complementary transistor (Ex-CFET) according to the experimental example has reduced the overall height through the graphene gate, thereby shortening the wiring length between the BPR and NMOS, improving the aspect ratio, ensuring ease of process, and reducing the total length of the intermediate wiring (MOL) by about 30%, which can be expected to improve wiring resistance.

[0096] FIG. 40 is a diagram illustrating the gate capacitance of a complementary transistor according to an experimental example and a comparative example of the present invention.

[0097] Referring to FIG. 40, the results of capacitance analysis according to gate voltage are shown for the complementary transistor (Proposal) according to the experimental example and the complementary transistor (Conventional) according to the comparative example, respectively. As can be seen in FIG. 40, the total capacitance of the complementary transistor (Proposal) according to the experimental example is significantly lower than that of the complementary transistor (Conventional) according to the comparative example. In particular, the parasitic capacitance at a gate voltage of 0 V shows an improvement of 32%, which is similar to the reduction in device height (30%). This reduction in parasitic capacitance can serve as a key factor in improving the switching speed of the device and reducing dynamic power consumption.

[0098] FIG. 41 is a diagram illustrating the self-heating effect of a complementary transistor according to an experimental example and a comparative example of the present invention.

[0099] Referring to Figure 41, the self-heating effect using numerical analysis simulation is shown for the complementary transistor (Ex-CFET) according to the experimental example and the complementary transistor (Cx-CFET) according to the comparative example, respectively. As can be seen in Figure 41, the complementary transistor (Ex-CFET) according to the experimental example has a lower maximum device temperature and an efficient heat dissipation path compared to the complementary transistor (Cx-CFET) according to the comparative example.

[0100] FIG. 42 is a diagram illustrating the TCAD simulation of a complementary transistor and the calibration results of an actually measured IV curve according to an experimental example of the present invention.

[0101] To quantitatively verify the electrical characteristics and performance improvement effects of the complementary transistor (Ex-CFET) according to the experimental example, industry-standard 3D TCAD simulation was utilized, and the following precise model was constructed.

[0102] First, as shown in below, we developed a library that accurately reflects key electrical properties such as the intrinsic energy band structure, mobility, and permittivity of 2D materials. The reliability of this library was ensured by cross-correcting results from atomic-level simulations (such as DFT) with experimental data from actual devices.

[0103] Parameter MoS2 WSe2 Dielectric constant of in-plane (ε II ) 15.5 15.6 Dielectric constant of out-of-plane (ε ⊥ ) 6.2 7.4 Energy band gap (E g ) [eV] 1.58 1.21 Electron affinity (X) [eV] Effective mass of electron (m e * / m0) 0.506 0.345 Effective mass of hole (m h * / m0) 0.578 0.341 Low-field Mobility [cm 2 / Vs] 217 126

[0104] Second, the shape and insulating film characteristics of the proposed ultra-low height gate electrode were precisely implemented in a three-dimensional structure to accurately reproduce the effect of the electric field on the channel and contact regions. As shown in Fig. 42, calibration was performed to adjust the parameters of the interface characteristics and mobility model so that the current-voltage characteristics obtained from the simulation matched the measured values ​​of the actual device.

[0105] Third, the van der Waals gap (vdW gap) formed between a metal and a two-dimensional material and the major factors of contact resistance resulting from it (tunneling, Schottky barrier, etc.) were incorporated into the physical model. Key variables such as the tunneling coefficient and metal-induced gap state (MIGS) were defined in the TCAD environment and precisely adjusted to match experimental results.

[0106] FIGS. 43 and FIGS. 44 are drawings illustrating the results of resistance and capacitance analysis of complementary transistors according to experimental and comparative examples of the present invention.

[0107] Referring to Figures 43 and 44, the resistance and capacitance notations and component segmentation of the complementary transistor (Prop.) according to the experimental example and the complementary transistor (Conv.) according to the comparative example are shown. As can be seen in Figures 43 and 44, the complementary transistor (Prop.) according to the experimental example exhibits a trade-off characteristic in which the capacitance decreases and the resistance increases compared to the complementary transistor (Conv.) according to the comparative example. As confirmed in Figure 40, the decrease in capacitance is attributed to a significant reduction in components due to the reduction in the physical height of the structure, whereas in the case of resistance, although the MOL parasitic component resistance was improved in the proposed structure, the channel resistance increased significantly, resulting in an increase in the total resistance.

[0108] FIGS. 45 and 46 are drawings illustrating the results of the analysis of the gate control capability of a complementary transistor according to an experimental example and a comparative example of the present invention.

[0109] Referring to FIGS. 45 and 46, the potential distribution at the gate cross-section of a complementary transistor (Proposal) according to an experimental example and a complementary transistor (Conventional) according to a comparative example are shown. More specifically, FIG. 45 shows the results for an NMOS and FIG. 46 shows the results for a PMOS.

[0110] As can be seen in Figures 45 and 46, the gate control capability of the complementary transistor (Proposal) according to the experimental example is reduced compared to the complementary transistor (Conventional) according to the comparative example through the constant potential distribution in the ON state. This is because the effective electric field applied to the channel is weakened due to the voltage drop occurring in the atomic-layer-thick graphene gate. This is in contrast to conventional metal gates, which form a uniform potential across the entire gate, enabling strong channel control.

[0111] FIG. 47 is a diagram illustrating the transfer curve characteristics of a complementary transistor according to an experimental example and a comparative example of the present invention.

[0112] Referring to Figure 47, the transfer curve characteristics of the complementary transistor (Proposal) according to the experimental example and the complementary transistor (Conventional) according to the comparative example are compared. Due to the influence of the reduction in gate control capability analyzed earlier, it can be seen that the ON-state current (On-current) of the complementary transistor (Proposal) according to the experimental example is slightly reduced compared to the complementary transistor (Conventional) according to the comparative example.

[0113] FIG. 48 is a diagram illustrating the speed-power characteristics of an inverter according to experimental and comparative examples of the present invention.

[0114] Referring to Figure 48, the frequency-power curves of the inverter according to the experimental example (Proposal) and the inverter according to the comparative example (Conventional) are shown. As can be seen in Figure 48, it can be observed that a higher operating speed is achieved at the same power consumption due to significantly improved capacitance characteristics, even though the ON current of individual transistors has decreased slightly. This demonstrates that the complementary transistor according to the experimental example has a superior power-performance trade-off at the circuit level.

[0116] Although the present invention has been described in detail using preferred embodiments, the scope of the invention is not limited to specific embodiments and should be interpreted by the appended claims. Furthermore, those skilled in the art will understand that many modifications and variations are possible without departing from the scope of the invention. Explanation of the symbols

[0117] S: Substrate TR1, TR2: 1st transistor, 2nd transistor C1, C2: 1st channel sheet, 2nd channel sheet TP1, TP2: First upper protective sheet, second upper protective sheet BP1, BP2: First lower protection sheet, second lower protection sheet GIL1, GIL2: 1st gate insulating layer, 2nd gate insulating layer GE1, GE2: 1st gate electrode, 2nd gate electrode TGA1, TGA2: First upper gate region, second upper gate region BGA1, BGA2: First lower gate region, second lower gate region SGA1, SGA2: First side gate region, second side gate region S1, S2: First source electrode, second source electrode D1, D2: First drain electrode, second drain electrode BPR: Embedded power rail BGP1, BGP2: First lower graphene layer, second lower graphene layer TGP1, TGP2: First upper graphene layer, second upper graphene layer HK1, HK2: 1st high-dielectric layer, 2nd high-dielectric layer HKL1, HKL2: 1st high dielectric film, 2nd high dielectric film SHS1, SHS2: First sheet structure, second sheet structure STS: Laminated structure

Claims

Claim 1 A first transistor comprising a first channel sheet and a first gate electrode surrounding the first channel sheet; A complementary transistor comprising a first transistor and a second transistor including a second channel sheet and a second gate electrode surrounding the second channel sheet, wherein the first transistor and the second transistor are sequentially arranged on a substrate along the normal direction of the upper surface of the substrate, and the first gate electrode and the second gate electrode comprise graphene, and the first gate electrode includes a first upper gate region surrounding the upper part of the first channel sheet, a first lower gate region surrounding the lower part, and a first side gate region surrounding the side part, and the second gate electrode includes a second upper gate region surrounding the upper part of the second channel sheet, a second lower gate region surrounding the lower part, and a second side gate region surrounding the side part, wherein at least one of the first upper gate region and the first lower gate region comprises a material different from the first side gate region, and at least one of the second upper gate region and the second lower gate region comprises a material different from the second side gate region. Claim 2 delete Claim 3 A complementary transistor according to claim 1, wherein at least one of the first upper gate region and the first lower gate region comprises graphene, at least one of the second upper gate region and the second lower gate region comprises graphene, and the first side gate region and the second side gate region comprise metal. Claim 4 In claim 1, the first transistor comprises a first upper protection sheet disposed above the first channel sheet, a first lower protection sheet disposed below the first channel sheet, and a first gate insulating film surrounding the first channel sheet, the first upper protection sheet, and the first lower protection sheet, and the second transistor comprises a second upper protection sheet disposed above the second channel sheet, a second lower protection sheet disposed below the second channel sheet, and a second gate insulating film surrounding the second channel sheet, the first upper protection sheet, and the second lower protection sheet. Claim 5 A complementary transistor according to claim 4, wherein the first gate electrode is arranged to surround the first gate insulating film, and the second gate electrode is arranged to surround the second gate insulating film. Claim 6 In claim 1, the first transistor is an n-type or p-type metal oxide field effect transistor (MOS FET), and the second transistor is a metal oxide field effect transistor (MOS FET) of a different type from the first transistor, forming a complementary transistor. Claim 7 In claim 1, the first channel sheet and the second channel sheet are complementary transistors comprising a two-dimensional semiconductor material. Claim 8 In claim 7, the first channel sheet comprises tungsten diselenide (WSe2) and the second channel sheet comprises molybdenum disulfide (MoS2), forming a complementary transistor. Claim 9 A step of preparing a stacked structure comprising: a first sheet structure in which a first channel sheet is disposed between a first lower graphene layer and a first upper graphene layer spaced apart from each other in a second direction perpendicular to a first direction parallel to the upper surface of the substrate; and a second sheet structure in which a second channel sheet is disposed between a second lower graphene layer and a second upper graphene layer spaced apart from each other on the upper surface of the first sheet structure along the second direction; a step of etching the stacked structure to form a fin structure so as to expose a first region on the upper surface of the substrate and a second region spaced apart from the first region in the first direction; a step of forming a gate structure surrounding the fin structure on the substrate; and a step of forming a first transistor by forming a first source electrode connected to one side of the first channel sheet and forming a first drain electrode connected to the other side. A method for manufacturing a complementary transistor comprising the step of forming a second source electrode connected to one side of the second channel sheet and forming a second drain electrode connected to the other side to form a second transistor. Claim 10 In claim 9, the step of preparing the laminated structure comprises: forming a first sheet structure on the substrate comprising the first channel sheet, a first upper protective sheet disposed above the first channel sheet, a first lower protective sheet disposed below the first channel sheet, the first channel sheet, the first upper protective sheet, and a first high dielectric film surrounding the first lower protective sheet, the first lower graphene layer disposed below the first high dielectric film, and a first upper graphene layer disposed above the first high dielectric film; and forming an oxide layer on the first sheet structure. A method for manufacturing a complementary transistor comprising the step of forming a second sheet structure on an oxide layer, the second channel sheet, a second upper protective sheet disposed above the second channel sheet, a second lower protective sheet disposed below the second channel sheet, a second high dielectric film surrounding the second channel sheet, the second upper protective sheet, and the second lower protective sheet, the second lower graphene layer disposed below the second high dielectric film, and the second upper graphene layer disposed above the second high dielectric film. Claim 11 A method for manufacturing a complementary transistor according to claim 10, wherein the step of forming the first sheet structure comprises: forming the first lower graphene layer on the substrate; forming the first high-dielectric layer on the first lower graphene layer; sequentially forming the first lower protective sheet, the first channel sheet, and the first upper protective sheet on the first high-dielectric layer; etching the first lower protective sheet, the first channel sheet, and the first upper protective sheet so as to expose a first region of the first high-dielectric layer and a second region spaced apart from the first region in the first direction; providing the same material as the first high-dielectric layer on the exposed first high-dielectric layer to form the first high-dielectric film surrounding the first lower protective sheet, the first channel sheet, and the first upper protective sheet; and forming the first upper graphene layer on the first high-dielectric film. Claim 12 A method for manufacturing a complementary transistor according to claim 11, wherein the step of forming the second sheet structure comprises: forming the second lower graphene layer on the oxide layer; forming the second high-dielectric layer on the second lower graphene layer; sequentially forming the second lower protective sheet, the second channel sheet, and the second upper protective sheet on the second high-dielectric layer; etching the second lower protective sheet, the second channel sheet, and the second upper protective sheet so as to expose a first region of the second high-dielectric layer and a second region spaced apart from the first region in the first direction; providing the same material as the second high-dielectric layer on the exposed second high-dielectric layer to form the second high-dielectric film surrounding the second lower protective sheet, the second channel sheet, and the second upper protective sheet; and forming the second upper graphene layer on the second high-dielectric film. Claim 13 A method for manufacturing a complementary transistor according to claim 12, wherein the step of forming the first sheet structure further comprises a step of flattening the upper portion of the first high dielectric film after the step of forming the first high dielectric film and before the step of forming the first upper graphene layer, and the step of forming the second sheet structure further comprises a step of flattening the upper portion of the second high dielectric film after the step of forming the second high dielectric film and before the step of forming the second upper graphene layer. Claim 14 A method for manufacturing a complementary transistor according to claim 12, wherein the first lower graphene layer, the first upper graphene layer, and the gate structure form a first gate electrode of the first transistor, and the second lower graphene layer, the second upper graphene layer, and the gate structure form a second gate electrode of the second transistor, wherein the first gate electrode is formed to surround the first channel sheet and the second gate electrode is formed to surround the second channel sheet. Claim 15 delete

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