Multi-chip structure including a memory die stacked on a die having a programmable integrated circuit

Abstract

Some examples described herein provide a multi-chip structure comprising one or more memory dies stacked on a die having a programmable integrated circuit (IC). In one example, the multi-chip structure comprises a package substrate, a first die, and a second die. The first die comprises a programmable IC, and the programmable IC comprises a memory controller. The first die is on the package substrate and is attached thereto. The second die comprises memory. The second die is stacked on the first die. The memory is communicably coupled to the memory controller.

Description

Technology Field

[0001] The present disclosure relates to a multi-chip structure and methods for forming such a structure, and in particular to a multi-chip structure comprising one or more memory dies stacked on a die having a programmable integrated circuit and methods for forming such a structure. Background Technology

[0002] A programmable integrated circuit (IC) refers to a type of IC that includes programmable circuits. An example of a programmable IC is a field programmable gate array (FPGA). An FPGA is characterized by the inclusion of programmable circuit blocks. Circuit designs can be physically implemented within the programmable circuits of a programmable IC by loading configuration data, often referred to as configuration bitstreams, into the device. Configuration data can be loaded into the device's internal configuration memory cells. The collective states of individual configuration memory cells determine the function of the programmable IC. For example, specific operations performed by various programmable circuit blocks and the connections between the programmable circuit blocks of the programmable IC are defined by the collective states of the configuration memory cells once the configuration data is loaded. The technology forming the background of the present invention is disclosed in the following published patent applications. [Reference 1] US 7701251 B2 (Arifur Rahman et al.) April 20, 2010. [Reference 2] US 8356138 B1 (Chidamber R. Kulkarni et al.) January 15, 2013.

[0003] Some examples described herein provide a multi-chip structure comprising one or more memory dies stacked on a die having a programmable integrated circuit (IC). Some examples described herein may exclude the use of interposers and / or physical layer (PHY) interfaces, which can reduce processing costs, power consumption, and / or die area usage.

[0004] One example is a multi-chip structure. The multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable integrated circuit, and the programmable integrated circuit includes a memory controller. The first die is on the package substrate and is attached thereto. The second die includes memory. The second die is stacked on the first die. The memory is communically coupled to the memory controller.

[0005] Another example is a method of forming a multi-chip structure. A first die is stacked on a second die. The first die includes memory. The second die includes a programmable integrated circuit, and the programmable integrated circuit includes a memory controller. The memory controller is communically coupled to the memory by the first die being stacked on the second die. The first die is attached to a package substrate.

[0006] An additional example is a multi-chip structure. The multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a field programmable gate array (FPGA) and a memory controller. The first die is on the package substrate and is attached thereto. The second die includes memory. The second die is stacked on the side of the first die opposite the package substrate. The memory is communically coupled to the memory controller. An additional example is a multi-chip structure. The multi-chip structure includes a package substrate; a first die directly mounted on the package substrate—the first die includes one or more processor cores—; a second die including a memory controller—the second die is stacked on the first die, and the memory controller is communically coupled to the package substrate through the first die—; A third die including memory is included, said third die is stacked on said second die, and said memory is sequentially coupled to said package substrate through said memory controller and said first die. An additional example is a method for forming a multi-chip structure. A method for forming a multi-chip structure includes the step of stacking a first die directly on a package substrate without an intervening interposer — said first die includes one or more processor cores —; the step of stacking a second die on said first die — said second die includes a memory controller, said memory controller is sequentially coupled to said package substrate through said first die —; and the step of stacking a third die on said second die, said third die includes memory, said memory is sequentially coupled to said package substrate through said memory controller and said first die. An additional example is a multi-chip structure.A multi-chip structure comprises: a package substrate; a first die including one or more processor cores — said first die is on said package substrate and is directly attached to said package substrate without an interposer —; a second die including a memory controller — said second die is stacked on said first die and said memory controller is communicably coupled to said package substrate through said first die —; and a plurality of memory dies stacked on said second die, said memory dies are communicably coupled to said package substrate sequentially through said memory controller and said first die.

[0007] These and other aspects can be understood by referring to the following detailed description. Brief explanation of the drawing

[0008] In order to make the features cited above understandable in detail, a more specific description of the briefly summarized above may be made by referring to exemplary embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings merely illustrate ordinary exemplary embodiments and should not be construed as limiting the scope of the invention. FIG. 1 is a block diagram illustrating a programmable IC (integrated circuit) connected to external memory according to some examples. Figure 2 illustrates a field programmable gate array (FPGA) of a programmable IC according to some examples. FIGS. 3, FIGS. 4, and FIGS. 5 are schematic circuit diagrams of individual multi-chip structures according to some examples. FIGS. 6, FIGS. 7, and FIGS. 8 are configurations of multi-chip structures on a printed circuit board (PCB) according to some examples. FIG. 9 is a flowchart of a method for forming a multi-chip structure according to some examples. For ease of understanding, identical reference numbers have been used, where possible, to designate identical elements common to the drawings. Elements in one example are considered to be advantageously integrated in other examples. Specific details for implementing the invention

[0009] Some examples described herein provide a multi-chip structure comprising one or more memory dies stacked on a die having a programmable integrated circuit (IC). In some examples, the memory dies may implement memory for high bandwidth memory (HBM). In some examples, the programmable IC includes programmable logic regions such as the fabric of a field programmable gate array (FPGA). The programmable IC allows user-configurable front-end processing of data read from or written to the memory of any of the memory dies.

[0010] Some examples described herein exclude the use of an interposer. By stacking memory dies onto a base die containing a programmable IC, an interposer will not be implemented (otherwise, the stack of base dies and memory dies would have been attached to the interposer separately). By excluding the interposer, the costs associated with including and processing the interposer in a multi-chip stack can also be avoided. Additionally, without an interposer, less processing can be implemented to form the multi-chip stack, which can reduce processing cycle times in addition to reduced costs. Excluding the interposer and stacking memory dies onto the base die can also result in a package with a smaller footprint and a smaller vertical profile.

[0011] Some of the examples described herein may exclude the use of physical layer (PHY) interfaces, such as HBM interfaces, in multi-chip structures. Physical layer interfaces can consume power and die area. By avoiding the use of physical layer interfaces, such as HBM interfaces, physical layer interfaces on two dies (e.g., one on each side of the HBM physical layer connections) can be avoided, which can reduce power consumption and reduce the use of the two dies' area. Additionally, reducing the use of the dies' area can reduce the costs associated with processing for forming the dies.

[0012] Some examples can achieve additional advantages. For instance, a composite device formed by a multi-chip structure can be tested more easily and deployed more easily in a multi-chip module, for instance, along with other packages and / or dies. Additionally, a multi-chip structure having a programmable IC as described herein can allow for the customization of logic and functions adjacent to one or more memory dies (e.g., adjacent to one or more HBM dies). Such a multi-chip structure can allow a user to create deployable custom devices in a single package, for instance, with high memory bandwidth and lower power consumption. Furthermore, such a multi-chip structure can preserve the programmability and flexibility of programmability of programmable logic zones and boundary circuits, such as input / output circuits, transceiver circuits, and / or other circuits.

[0013] Various features are described below with reference to the drawings. It should be noted that the drawings may or may not be drawn to actual scale, and that elements of similar structures or functions are represented by similar reference numbers throughout the drawings. It should be noted that the drawings are intended only to facilitate the description of features. They are not intended as a thorough description of the claimed invention or as a limitation on the scope of the claimed invention. Furthermore, the exemplified examples are not required to have all the aspects or advantages illustrated. An aspect or advantage described in relation to a particular example is not necessarily limited to that example and may be practiced in any other examples even if not so exemplified or if not explicitly described. Additionally, while the methods described herein may be described in a specific order of operation, other methods according to other examples may be implemented in various different orders with more or fewer operations (e.g., including different serial or parallel execution of various operations).

[0014] FIG. 1 is a block diagram illustrating a programmable integrated circuit (102) connected to external memory according to some examples. The programmable IC (102) may be a System-on-Chip (SoC), may include an IC that is a programmable logic device such as a field programmable gate array (FPGA), or may be an IC. The programmable IC (102) includes a processing system (104), a network-on-chip (NoC) (106), a configuration interconnect (108), one or more programmable logic regions (110a to 110n) (generally, individually or collectively, "programmable logic region(s) (110)"), a memory controller (112), multi-gigabit transceivers (MGT) (114), input / output blocks (IO) (116), and other IP circuits (118). NoC (106) includes a routing network (120) and an NPI (NoC peripheral interconnect) (122).

[0015] Generally, the processing system (104) is connected to the programmable logic zone(s) (110) via a configuration interconnect (108). The processing system (104), the programmable logic zone(s) (110), the memory controller (112), the MGTs (114), the IOs (116), and other IP circuits (118) are also connected to the NoC (106) (e.g., the routing network (120)) and thus can be coupled to communicate with each other via the NoC (106) (e.g., the routing network (120)). The processing system (104), the memory controller (112), the MGTs (114), the IOs (116), and other IP circuits (118) are also connected to individual subsets of the programmable logic zone(s) (110). For example, each of the processing system (104), IOs (116), and other IP circuits (118) is connected to the programmable logic zone (110a), and each of the memory controller (112) and MGTs (114) is connected to the programmable logic zone (110n). Various circuits may be connected to any subset of the programmable logic zone(s) (110), and circuits may be connected to a given subset of the programmable logic zone(s) (110) in any combination with any other circuits. Additionally, in some examples, the memory controller (112) may be connected to at least one of the IOs (116).

[0016] The processing system (104) may include one or more processor cores. For example, the processing system (104) may include multiple ARM-based embedded processor cores.

[0017] The programmable logic section(s) (110) may include any number of configurable logic blocks, look-up tables (LUTs), digital signal processing blocks, random access memory blocks, etc., and programmable interconnect elements, such as those described below. The programmable logic section(s) (110) may be programmed or configured using the processing system (104) via the configuration interconnect (108). For example, the configuration interconnect (108) may enable frame-based programming of the fabric of the programmable logic section(s) (110) by a processor core of the processing system (104), such as a platform management controller (PMC).

[0018] The routing network (120) of the NoC (106) provides routing of NoC packets between different systems or circuits. The routing network (120) includes NoC packet switches interconnected by line segments between NMUs (NoC master units) and NSUs (NoC slave units). Each NMU is an intress circuit connecting the master circuit to the NoC (106). Each NSU is an exit circuit connecting the NoC (106) to the slave endpoint circuit. Each NoC packet switch performs switching of NoC packets. Thus, the NMUs, NoC packet switches, and NSUs can be configured to provide channels for communication between the master endpoint circuit and the slave endpoint circuit through the NMUs, the NoC packet switches interconnected by line segments, and the NSUs. The NMUs, NoC packet switches, and NSUs also include register blocks written to configure the individual NMUs, NoC packet switches, and NSUs. Register blocks can be written via NPI (122). For example, the PMC of the processing system (104) can send memory mapping write requests to NMUs, NoC packet switches, and NSUs via NPI (122) to write to register blocks in order to configure NMUs, NoC packet switches, and NSUs. NPI (122) may include interconnected NPI switches capable of routing memory mapping write requests to appropriate register blocks.

[0019] The IOs (116) may be any input / output circuits for coupling the programmable IC (102) to communicate with other circuits and / or systems. In some examples, the IOs (116) may include HBM (high bandwidth memory) interface circuits, HDIO (high density input / output) circuits, PCIe (peripheral component interconnect express) circuits, XPIO (eXtreme Performance Input / Output) circuits, etc. Other IP circuits (118) may be, for example, digital clock managers, analog-to-digital converters, system monitoring logic, and / or any circuits for a given implementation. In some examples, at least some of the memory controller (112), MGTs (114), IOs (116), and / or other IP circuits (118) are configurable. For example, the memory controller (112), MGTs (114), IOs (116), and / or other IP circuits (118) may be configured via the NPI (122) of the NoC (106).

[0020] In some examples, the programmable IC (102) includes an interface and control logic circuit (124). In other examples, the interface and control logic circuit (124) is on a separate IC from the programmable IC (102) (e.g., as indicated by the dotted line). The interface and control logic circuit (124) is connected to an external memory (126). The external memory (126) may be, for example, a memory of a single or multiple dies. In some examples, the external memory (126) is a random access memory (RAM), such as dynamic RAM (DRAM), which can be implemented as high bandwidth memory (HBM).

[0021] In some examples, the interface and control logic circuit (124) is directly connected to the memory controller (112), whereas in other examples, the interface and control logic circuit (124) is communicably coupled to the memory controller (112) through the IO (116) of the programmable IC (102) and the IO (128) of another IC (e.g., as illustrated by the dashed arrows in FIG. 1). In some examples where the programmable IC (102) includes the interface and control logic circuit (124), the memory controller (112) is directly connected to the interface and control logic circuit (124) (e.g., without interposed physical layer (PHY) interfaces), and this interface and control logic circuit is, in turn, connected to the external memory (126). In some examples where the interface and control logic circuit (124) is in an IC separate from the programmable IC (102), the memory controller (112) is directly connected to the interface and control logic circuit (124) (e.g., without interposed physical layer (PHY) interfaces), and this interface and control logic circuit is, in turn, connected to external memory (126). In some examples where the interface and control logic circuit (124) is in an IC separate from the programmable IC (102), the memory controller (112) is directly connected to an IO (116) (e.g., HBM interface), and the IO (116) is connected to an IO (128) (e.g., HBM interface) of the separate IC, and this IO of the separate IC is connected to the interface and control logic circuit (124). The interface and control logic circuit (124) is, in turn, connected to external memory (126). Accordingly, in these examples, the memory controller (112) is coupled to the external memory (126) so as to be communicable.

[0022] In some examples, and as described in detail below, a programmable IC (102), an interface and control logic circuit (124) (if on a separate IC), and an external memory (126) may be included on dies that are stacked to form a multi-chip structure. Such a multi-chip structure may have a smaller package size and may be manufactured using reduced processing, which may increase yield and reduce the time required to manufacture the multi-chip structure.

[0023] FIG. 2 illustrates a field programmable gate array (FPGA) of a programmable IC (200) that can be implemented as the programmable IC (102) of FIG. 1 according to some examples. The programmable IC (200) includes a very large number of different programmable tiles including configurable logic blocks (CLBs) (202), random access memory blocks (BRAMs) (204), signal processing blocks (DSPs) (206), input / output blocks (IOBs) (208), configurable and clocking logic (CONFIG / CLOCK) (210), special input / output blocks (I / O) (212) (e.g., configurable ports and clock ports), and other programmable logic (214), such as digital clock managers, system monitoring logic, etc. The programmable IC (200) may also include boundary circuits such as MGTs (216), memory controllers (MCs) (218), interface and control logic circuits (INT / CNTL) (220), and other IP circuits (222), such as PCIe interfaces, analog-to-digital converters (ADCs), etc. The boundary circuits may also be programmable.

[0024] In some FPGAs, each programmable tile may include at least one programmable interconnect element (INT) (230) having connections to input and output terminals (232) of a programmable logic element within the same tile, as illustrated by the examples included in FIG. 5. Each programmable interconnect element (230) may also include connections to interconnect segments (234) of adjacent programmable interconnect element(s) of the same tile or other tile(s). Each programmable interconnect element (230) may also include connections to interconnect segments (236) of general routing resources between logic blocks (not shown). General routing resources may include routing channels between logic blocks (not shown) containing tracks of interconnect segments (e.g., interconnect segments (236)) and switch blocks (not shown) for connecting the interconnect segments. The interconnect segments of general routing resources (e.g., interconnect segments (236)) may span one or more logic blocks. The programmable interconnect elements (230) taken together with the general routing resources implement a programmable interconnect structure for the illustrated FPGA.

[0025] In an exemplary implementation, the CLB (202) may include a configurable logic element (CLE) (240) that can be programmed to implement user logic in addition to a single programmable interconnect element (230). The BRAM (204) may include a BRAM logic element (BRL) (242) in addition to one or more programmable interconnect elements (230). Typically, the number of programmable interconnect elements (230) included in a tile depends on the height of the tile. In the illustrated example, the BRAM (204) has the same height as five CLBs (202), but other numbers (e.g., four) may also be used. The signal processing block (206) may include a DSP logic element (DSPL) (244) in addition to an appropriate number of programmable interconnect elements (230). The IOB (208) may include, for example, two instances of an input / output logic element (IOL) (246) in addition to one instance of a programmable interconnect element (230). As will be obvious to those skilled in the art, for example, the actual I / O pads connected to the input / output logic element (246) are not typically limited to the area of ​​the input / output logic element (246).

[0026] In the illustrated example, a horizontal area near the center of the die is used for configuration and clocking logic (CONFIG / CLOCKS) (210) and, if possible, other control logic. Vertical columns (248) extending from this horizontal area or column are used to distribute clocks and configuration signals across the width of the FPGA.

[0027] Some FPGAs utilizing the architecture exemplified in FIG. 2 may include additional logic blocks that interfere with the regular columnar structure that makes up a large part of the FPGA. The additional logic blocks may be programmable blocks and / or dedicated logic.

[0028] Note that FIG. 2 is intended merely to illustrate an exemplary FPGA architecture. For example, the number of logic blocks in a row, the relative width of the rows, the number and order of the rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect / logic implementations included at the top of FIG. 2 are purely illustrative. For example, in an actual FPGA, two or more adjacent rows of CLBs are typically included wherever CLBs appear to facilitate the efficient implementation of user logic, but the number of adjacent rows of CLBs varies depending on the overall size of the FPGA.

[0029] FIG. 3 is a schematic circuit diagram of a multi-chip structure according to some examples. The multi-chip structure of FIG. 3 includes a programmable IC (102) and memory (302), wherein the memory (302) may be on a plurality of dies stacked on a die containing the programmable IC (102). As simplified in FIG. 3, the programmable IC (102) includes a programmable logic area (110), a bus (304), memory controllers (112), and an interface and control logic circuit (124). The programmable logic area (110) (or other subsystems, such as a processing system (104) and / or a NoC (106)) is connected to the memory controllers (112) via buses (304), which may be, for example, AXI (Advanced eXtensible Interface) buses. The memory controllers (112) are connected to the interface and control logic circuit (124).

[0030] Each memory (302) includes a plurality of memory slices (306). In some examples, each memory slice (306) may be 2 Gb (Gigabytes) of memory or other sizes. Each memory (302) may implement DRAM and may additionally implement HBM. In some examples, each memory (302) may implement 32 Gb of HBM DRAM. An interface and control logic circuit (124) is connected to the memory slices (306) of the memory (302). The interface and control logic circuit (124) may decode read and write requests from memory controllers (112) and, in response, transmit native signals to the memory (302) to read from or write to the memory (302). There is no standardized physical layer interface circuit between the memory controllers (112) and the memory slices (306) of the memory (302) for packaging read and write requests into a standardized form and unpackaging read and write requests from the standardized form. For example, if the memory (302) implements HBM, there is no HBM interface between the memory controllers (112) and the memory slices (306).

[0031] FIG. 4 is a schematic circuit diagram of another multi-chip structure according to some examples. The multi-chip structure of FIG. 4 is similar to the multi-chip structure of FIG. 3 except that two stacks of dies containing memory (302) are stacked on a die containing a programmable IC (102). The programmable IC (102) further includes additional buses (304), memory controllers (112), interface and control logic circuits (124) to accommodate an additional stack of dies containing memory (302).

[0032] In the examples of FIGS. 3 and 4, the interface and control logic circuits (124) are included in individual dies containing the programmable IC (102). In other examples, another control die (separate from the die containing the programmable IC (102)) may contain the interface and control logic circuit(s) (124) and may be interposed between the stack(s) of dies containing the programmable IC (102) and the memory (302). The schematic circuit diagram of such examples will be the same as FIGS. 3 and 4, except that it shows a separate control die.

[0033] FIG. 5 is a schematic circuit diagram of an additional multi-chip structure according to some examples. The multi-chip structure of FIG. 5 implements HBM interfaces (e.g., as PHY interfaces) between memory controllers (112) and memory slices (306). The multi-chip structure of FIG. 5 includes a programmable IC (102), a control IC (502), and a memory (302), wherein the control IC (502) is on a die stacked on a die containing the programmable IC (102) and is on a die separated therefrom, and the memory (302) may be on a plurality of dies stacked on a die containing the control IC (502). As simplified in FIG. 5, the programmable IC (102) includes a programmable logic region (110), a bus (304), memory controllers (112), and HBM interfaces (HBM PHY) (504). A programmable logic section (110) (or other subsystems, such as a processing system (104) and / or a NoC (106)) is connected to memory controllers (112) via buses (304), and the memory controllers (112) are connected to HBM interfaces (504). The HBM interfaces (504) are configured to package read and write requests from the memory controllers (112), for example, into a standardized HBM format, and to unpack responses from the memory (302) from the standardized HBM format into a format usable by the memory controllers (112).

[0034] The control IC (502) includes HBM interfaces (HBM PHY) (506) and interface and control logic circuits (124). The HBM interfaces (506) of the control IC (502) are connected to the HBM interfaces (504) of the programmable IC (102). The HBM interfaces (506) are configured to package responses from memory (302) into a standardized HBM format to unpack read and write requests from the HBM interfaces (504), for example, from a standardized HBM format into a native format available to the interface and control logic circuit (124), and to transmit them to the HBM interfaces (504) of the programmable IC (102). The interface and control logic circuit (124) can decode the read and write requests from the HBM interfaces (506) and, in response, transmit native signals to the memory (302) to read from or write to the memory (302) on various memory dies. The schematic circuit diagram of Fig. 5 can be modified to implement a single stack of memory dies similar to the differences between Fig. 3 and Fig. 4.

[0035] FIG. 6 is a configuration of a multi-chip structure on a printed circuit board (PCB) (602) according to some examples. The multi-chip structure includes a package substrate (604), a base die (606) on the package substrate (604), and memory dies (608) stacked on the base die (606). The base die (606) includes a programmable IC (102) as in FIG. 3 and / or FIG. 4, and the memory die (608) each includes a memory (302) as in FIG. 3 and / or FIG. 4.

[0036] The multi-chip structure includes a stack of four stacked memory dies (608), but other examples may implement any number of memory dies (608) in any number of stacks. Each memory die (608) has external connectors (610), such as microbumps, attached to the active side of the memory die (608) and attached to the rear side of the lower die. Each memory die (608) may include through substrate vias (TSVs) through a semiconductor substrate on which the memory (302) of the individual memory die (608) is formed. The TSVs may be implemented to electrically connect the memory (302) of the upper memory die (608) to the individual memory die (608) and / or the lower die.

[0037] The programmable IC (102) of the base die (606) includes an interface and control logic circuit (124) as illustrated in FIG. 3 and / or FIG. 4. The bottom memory die (608) of the stack of memory dies (608) has external connectors (610) attached to the active side of the bottom memory die (608) and the rear side of the base die (606). The base die (606) may include, for example, TSVs through a semiconductor substrate on which the programmable IC (102) is formed. The TSVs may be implemented to electrically connect the memory (302) of the upper memory dies (608) to the programmable IC (102). The base die (606) additionally has external connectors (612), such as controlled collapse chip connections (C4) bumps, attached to the active side of the base die (606) and to the first side of the package substrate (604). External connectors (614), such as BGA (ball grid array) balls, are attached to the second side opposite the first side of the package substrate (604), and are additionally attached to the PCB (602).

[0038] FIG. 7 is another configuration of a multi-chip structure on a PCB (602) according to some examples. The multi-chip structure includes a package substrate (604), a base die (606) on the package substrate (604), a control die (702) on the base die (606), and memory dies (608) stacked on the control die (702). The base die (606) includes a programmable IC (102) as in FIG. 3 and / or FIG. 4 without an interface and control logic circuit (124). The control die (702) includes a control IC including an interface and control logic circuit (124) as in FIG. 3 and / or FIG. 4. Each of the memory dies (608) includes a memory (302) as in FIG. 3 and / or FIG. 4.

[0039] As in FIG. 6, the multi-chip structure of FIG. 7 includes a stack of four stacked memory dies (608), but other examples may implement any number of memory dies (608) in any number of stacks. The bottom memory die (608) of the stack of memory dies (608) has external connectors (610) attached to the active side of the bottom memory die (608) and the rear side of the control die (702). The control die (702) may include TSVs through a semiconductor substrate on which logic structures (e.g., transistors) of the control die (702) are formed. The TSVs may be implemented to electrically connect the memory (302) of the upper memory dies (608) to the control IC (e.g., interface and control logic circuit (124)) of the control die (702) and / or the programmable IC (102). The active side of the control die (702) is attached to the rear side of the base die (606). For example, the active side of the control die (702) may be bonded to the rear side of the base die (606) via oxide-oxide and / or metal-metal bonding by wafer bonding or other bonding techniques. The base die (606) has external connectors (612) attached to the active side of the base die (606) and attached to the first side of the package substrate (604). External connectors (614) are attached to the second side opposite the first side of the package substrate (604), which are additionally attached to the PCB (602).

[0040] FIG. 8 shows another configuration of a multi-chip structure on a PCB (602) according to some examples. The multi-chip structure includes a package substrate (604), a base die (606) on the package substrate (604), a control die (802) on the base die (606), and memory dies (608) stacked on the control die (802). The base die (606) includes a programmable IC (102) as in FIG. 5. More specifically, the programmable IC (102) also includes HBM interfaces (504) as shown in FIG. 5. The control die (802) includes a control IC (502) as in FIG. 5. More specifically, the control IC (502) of the control die (802) includes an interface and control logic circuit (124) and HBM interfaces (506) as shown in FIG. 5. Each of the memory dies (608) includes a memory (302) as in FIG. 5.

[0041] As in FIG. 6, the multi-chip structure of FIG. 8 includes a stack of four stacked memory dies (608), but other examples may implement any number of memory dies (608) in any number of stacks. The bottom memory die (608) of the stack of memory dies (608) has external connectors (610) attached to the active side of the bottom memory die (608) and the rear side of the control die (802). The control die (802) may include TSVs through a semiconductor substrate on which logic structures (e.g., transistors) of the control IC (502) are formed, for example. The TSVs may be implemented to electrically connect the memory (302) of the upper memory dies (608) to the control die (802) and / or the control IC (502) of the programmable IC (102). The control die (802) has external connectors (804), such as microbumps, attached to the active side of the control die (802) and to the rear side of the base die (606). The base die (606) has external connectors (612) attached to the active side of the base die (606) and to the first side of the package substrate (604). External connectors (614) are attached to the second side opposite the first side of the package substrate (604), which are additionally attached to the PCB (602).

[0042] Although the various multi-chip structures described in connection with FIGS. 6 through 8 have been described as various dies having a specific orientation (e.g., specific active sides of the dies are attached to the rear sides of other dies), such orientations are provided as examples. Any die (e.g., any base die (606), memory die (608), control die (702), and / or control die (802)) may be inverted with respect to the description provided above, for example, or may have any other orientation.

[0043] The multi-chip structures described above can be programmably accessible high-density memory devices. Programmable devices with high-density memory utilizing HBM logic and stacking technology can be implemented by the structures described above. The performance advantages associated with programmable ICs (e.g., FPGAs) can be maintained while resulting in faster and simpler manufacturing, lower manufacturing costs, and lower power consumption.

[0044] Some examples may be implemented with any various programmable ICs. For example, the programmable IC may be an application-specific standard parts (ASSP) IC having configurable input / output circuits and interfaces. Some examples may be implemented with multi-port memory having host interfaces such as nx PCIe Genx, nx 100GE, nx 40G, nx 10GE, 112G PAM4, etc.

[0045] FIG. 9 is a flowchart of a method (900) for forming a multi-chip structure according to some examples. In block (902), a base die is formed. The base die may be, for example, the base die (606) of FIG. 6 through 8, and may be formed by forward and backward semiconductor processing to implement programmable ICs and TSVs on the base die.

[0046] Optionally, in block (904), a control die is formed. The control die may be, for example, the control dies (702 and / or 802) of FIG. 7 and / or FIG. 8, and likewise may be formed by forward and backward semiconductor processing to implement control ICs and TSVs in the control die. Optionally, in block (906), the control die is attached to the base die. For example, the control die may be bonded to the base die by wafer-wafer bonding during the processing of the control die and the base die (e.g., before singulating the dies). As another example, the control die may be attached to the base die using external connectors, such as microbumps—which may include reflowing the external connectors to attach the control die to the base die. In some examples, the control die is not implemented to form, for instance, the multi-chip structure of FIG. 6, and thus forming the control die in block (904) and attaching the control die to the base die in block (906) may be omitted.

[0047] In block (908), a stack of memory dies is formed. The stack of memory dies may be, for example, the memory dies (608) of FIGS. 6 through 8, and each memory die may be formed by front-side and back-side semiconductor processing to implement TSVs and memory on the memory die, except that the top memory die may omit back-side semiconductor processing and TSVs. The memory dies may be attached to each other in the stack by using, for example, external connectors, such as microbumps—which may include reflowing the external connectors to attach the memory dies together.

[0048] In block (910), a stack of memory dies is attached to a base die or, if implemented, a control die. The stack of memory dies may be attached to the base die (e.g., as in FIG. 6) or to the control die (e.g., as in FIG. 7 and FIG. 8) using external connectors, such as microbumps—which may include reflowing the external connectors to attach the stack of memory dies to the base die or the control die. As indicated above, the order of operations may vary. For example, when the control die is implemented as in FIG. 8, the stack of memory dies may be attached to the control die before the control die is attached to the base die.

[0049] In block (912), the base die is attached to the package substrate. The package substrate may be, for example, the package substrate (604) of FIGS. 6 to 8, and may be attached to the base die using external connectors, such as C4 bumps—which may include reflowing the external connectors to attach the base die to the package substrate.

[0050] In block (914), the package substrate is attached to the PCB. The PCB substrate may be, for example, the PCB (602) of FIGS. 6 to 8, and may be attached to the package substrate using external connectors, such as BGA balls—which may include reflowing the external connectors to attach the package substrate to the PCB.

[0051] According to some examples, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a programmable integrated circuit. The programmable integrated circuit includes a memory controller. The first die is on the package substrate and is attached thereto. The second die includes memory. The second die is stacked on the first die. The memory is communically coupled to the memory controller.

[0052] In some examples of the multi-chip structures above, the first die may include a semiconductor substrate. Through substrate vias (TSVs) may penetrate the semiconductor substrate. A memory controller may be coupled to the memory via the TSVs for communication.

[0053] In some examples of the multi-chip structure above, the second die can be attached to the side of the first die opposite the package substrate by external electrical connectors.

[0054] In some of the above examples of multi-chip structures, no physical layer interface may be electrically positioned to enable communication between the memory controller and the memory.

[0055] In some examples of the above multi-chip structures, the first die may include a control logic circuit, and the control logic circuit may be arranged to communicate between the memory controller and the memory.

[0056] In some examples, the above multi-chip structure may further include a third die comprising a control logic circuit. The third die may be stacked on the side of the first die opposite the package substrate and attached thereto. A second die may be stacked on the side of the third die opposite the first die and attached thereto. The control logic circuit may be arranged to communicate between the memory controller and the memory. The third die may be bonded to the first die. The third die may be attached to the side of the first die opposite the package substrate by external electrical connectors. The second die may be attached to the side of the third die opposite the first die by external electrical connectors. No physical layer interface may be arranged to communicate and electrically between the memory controller and the memory. The first die may include a first physical layer interface communicateably coupled to the memory controller. The third die may include a second physical layer interface communicateably coupled between the first physical layer interface and the control logic circuit, and between the first physical layer interface and the control logic circuit.

[0057] In some of the examples of the multi-chip structures above, the programmable integrated circuit includes a field programmable gate array (FPGA).

[0058] According to some examples, a method for forming a multi-chip structure includes the steps of stacking a first die on a second die and attaching the first die to a package substrate. The first die includes memory. The second die includes a programmable integrated circuit. The programmable integrated circuit includes a memory controller. The memory controller is communically coupled to the memory by stacking the first die on the second die.

[0059] In some examples of the above method, the step of stacking the first die on the second die may include the step of attaching the first die to the second die by means of external electrical connectors; the second die includes a control logic circuit, and the control logic circuit may be positioned to communicate between the memory controller and the memory; and no physical layer interface may be positioned to communicate and electrically between the memory controller and the memory.

[0060] In some examples, the above method may further include the step of attaching a third die to a second die. The first die may be attached to the third die. The third die may include a control logic circuit. The control logic circuit may be positioned to enable communication between a memory controller and a memory.

[0061] According to some examples, a multi-chip structure includes a package substrate, a first die, and a second die. The first die includes a field programmable gate array (FPGA) and a memory controller. The first die is on the package substrate and is attached thereto. The second die includes memory. The second die is stacked on the side of the first die opposite the package substrate. The memory is communically coupled to the memory controller.

[0062] In some of the above examples of multi-chip structures, no physical layer interface may be electrically positioned to enable communication between the memory controller and the memory.

[0063] In some of the examples of the multi-chip structure above, the first die may include a control logic circuit. The control logic circuit may be positioned to communicate between the memory controller and the memory.

[0064] In some examples, the above multi-chip structure may further include a third die comprising a control logic circuit. The third die may be stacked on the side of the first die opposite the package substrate and attached thereto. A second die may be stacked on the side of the third die opposite the first die and attached thereto. The control logic circuit may be arranged to communicate between a memory controller and a memory. The first die may include a first physical layer interface communicateably coupled to the memory controller. The third die may include a second physical layer interface communicateably coupled between the first physical layer interface and the control logic circuit, and between the first physical layer interface and the control logic circuit.

[0065] The above describes specific examples, but other and additional examples may be devised without departing from the basic scope of the invention, and the scope of the invention is determined by the following claims.

Claims

Claim 1 A multi-chip structure comprising: a package substrate; a first die directly mounted on the package substrate ― said first die comprises one or more processor cores ―; a second die comprising a memory controller ― said second die is stacked on said first die, said memory controller is communically coupled to the package substrate through said first die ―; and a third die comprising a memory, said third die is stacked on said second die, said memory is communically coupled to the package substrate sequentially through said memory controller and said first die. Claim 2 A multi-chip structure according to claim 1, wherein the first die comprises a semiconductor substrate, through substrate vias penetrate the semiconductor substrate, and the memory controller is coupled to the memory via the TSVs for communication. Claim 3 A multi-chip structure according to claim 1, wherein a fourth die is attached to the side of the third die opposite the package substrate by external electrical connectors. Claim 4 In claim 1, a multi-chip structure in which no physical layer interface is electrically arranged to enable communication between the memory controller and the memory. Claim 5 In claim 1, the first die is a multi-chip structure comprising a field programmable gate array (FPGA). Claim 6 A method for forming a multi-chip structure, comprising the steps of: stacking a first die directly on a package substrate without an intervening interposer — said first die comprises one or more processor cores —; stacking a second die on the first die — said second die comprises a memory controller, said memory controller is communicably coupled to the package substrate through the first die —; and stacking a third die on the second die, said third die comprises a memory, said memory is communicably coupled to the package substrate sequentially through the memory controller and the first die. Claim 7 In claim 6, the step of stacking the second die on the first die includes the step of attaching the first die to the second die by means of external electrical connectors; the first die includes a control logic circuit, the control logic circuit is disposed to be communicable between the memory controller and the memory; and a method of forming a multi-chip structure in which no physical layer interface is disposed to be communicable and electrically disposed between the memory controller and the memory. Claim 8 A method of forming a multi-chip structure, wherein, in claim 6, the first die includes a control logic circuit, and the control logic circuit is coupled to communicate between the memory controller and the memory. Claim 9 A multi-chip structure comprising: a package substrate; a first die including one or more processor cores ― said first die is on said package substrate and is directly attached to said package substrate without an interposing interposer ―; a second die including a memory controller ― said second die is stacked on said first die and said memory controller is communicably coupled to said package substrate through said first die ―; and a plurality of memory dies stacked on said second die, said memory dies are communicably coupled to said package substrate sequentially through said memory controller and said first die. Claim 10 In claim 9, a multi-chip structure in which no physical layer interface is electrically arranged to enable communication between the memory controller and the plurality of memory dies. Claim 11 In claim 9, the multi-chip structure further comprises a control logic circuit disposed to be communicable between the memory controller and the plurality of memory dies. Claim 12 In claim 9, the second die is bonded to the first die, forming a multi-chip structure. Claim 13 In claim 9, the second die is attached to the side of the first die opposite the package substrate by external electrical connectors, in a multi-chip structure. Claim 14 In claim 9, the second die is attached to one of the plurality of memory dies by external electrical connectors, in a multi-chip structure. Claim 15 In claim 14, a multi-chip structure in which no physical layer interface is electrically arranged to enable communication between the memory controller and the memory dies. Claim 16 In claim 14, the first die comprises a first physical layer interface communically coupled to the memory controller; and one of the plurality of memory dies comprises a second physical layer interface communically coupled to the first physical layer interface and the control logic circuit and to the first physical layer interface and the control logic circuit, a multi-chip structure. Claim 17 A method for forming a multi-chip structure comprising the step of stacking a first die on a second die ― wherein the first die comprises a memory, the second die comprises a programmable integrated circuit, the programmable integrated circuit comprises a memory controller, the memory controller is communably coupled to the memory by the first die being stacked on the second die, the second die comprises a control logic circuit communably disposed between the memory controller and the memory, and the control logic circuit is configured to decode read and write requests from the memory controller and, in response, transmit native signals to the memory to read from or write to the memory ―; and the step of attaching the first die directly to a package substrate without an interposing interposer, wherein the memory controller is communably coupled to the package substrate through the programmable integrated circuit. Claim 18 In claim 9, the first die comprises a field programmable gate array (FPGA) having a programmable integrated circuit, the memory controller is communically coupled to the package substrate through the programmable integrated circuit of the first die, and the memory dies are sequentially communically coupled to the package substrate through the memory controller and the programmable integrated circuit of the first die, a multi-chip structure.

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