Oscillation period detection circuit and method, and semiconductor memory

Abstract

Provided in the embodiments of the present application are an oscillation period measurement circuit and method, and a semiconductor memory. The oscillation period measurement circuit comprises: an oscillator module, which comprises a target oscillator and is configured to receive an enable signal and control, according to the enable signal, the target oscillator to output an oscillation clock signal; a control module, which is configured to receive the enable signal and the oscillation clock signal, and rearrange effective time according to the oscillation clock signal and the enable signal, so as to determine a target time; and a counting module, which is configured to receive the enable signal and the oscillation clock signal, and count periods according to the enable signal and the oscillation clock signal, so as to determine the number of target periods, wherein an oscillation period of the target oscillator is obtained by means of calculation according to the target time and the number of target periods.

Description

Oscillation period detection circuit, method and semiconductor memory

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202110993836.6, application date August 27, 2021, and invention name “An oscillation period detection circuit, method and semiconductor memory”, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present application relates to the field of electronic measurement technology, and in particular to an oscillation period detection circuit, method and semiconductor memory. Background Art

[0004] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, consisting of numerous repetitive memory cells. In DRAM, an oscillator is required to generate a regular timing signal, which is used to control the multiple memory cells. Therefore, oscillator cycle detection is a key component of chip quality testing.

[0005] However, in the related art, the detection method of the oscillation period duration still has shortcomings, resulting in low detection accuracy and efficiency.

[0006] Summary of the Invention

[0007] The present application provides an oscillation period detection circuit, method and semiconductor memory, which can improve the detection accuracy and efficiency of the oscillation period.

[0008] The technical solution of this application is achieved as follows:

[0009] In a first aspect, an embodiment of the present application provides an oscillation period detection circuit, comprising:

[0010] an oscillator module, comprising a target oscillator, configured to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal;

[0011] A control module is configured to receive an enable signal and an oscillation clock signal, and perform effective time resetting processing according to the oscillation clock signal and the enable signal to determine a target time;

[0012] a counting module configured to receive an enable signal and an oscillation clock signal, and perform cycle counting processing according to the enable signal and the oscillation clock signal to determine a target number of cycles;

[0013] The oscillation period of the target oscillator is calculated based on the target time and the target number of periods.

[0014] In a second aspect, an embodiment of the present application provides an oscillation period detection method, which is applied to an oscillation period detection circuit including a target oscillator. The method includes:

[0015] According to the enable signal, the target oscillator is controlled to output an oscillation clock signal;

[0016] Perform effective time resetting processing according to the oscillation clock signal and the enable signal to determine the target time;

[0017] Perform cycle counting processing according to the enable signal and the oscillation clock signal to determine the target cycle number;

[0018] The target time and the target number of cycles are calculated to determine the oscillation period of the target oscillator.

[0019] In a third aspect, an embodiment of the present application provides a semiconductor memory, which at least includes the oscillation period detection circuit as described in the first aspect.

[0020] The embodiment of the present application provides an oscillation period detection circuit, method and semiconductor memory, the oscillation period detection circuit comprising: an oscillator module, including a target oscillator, configured to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal; a control module, configured to receive the enable signal and the oscillation clock signal, and perform effective time reshaping processing according to the oscillation clock signal and the enable signal to determine the target time; a counting module, configured to receive the enable signal and the oscillation clock signal, and perform cycle counting processing according to the enable signal and the oscillation clock signal to determine the target number of cycles; wherein the oscillation period of the target oscillator is calculated based on the target time and the target number of cycles. In this way, the enable signal and the oscillation clock signal undergo effective time reshaping processing to determine the target time, and the enable signal and the oscillation clock signal undergo cycle counting to determine the target number of cycles. Subsequently, the oscillation period can be calculated based on the target time and the target number of cycles, thereby improving the detection accuracy and efficiency of the oscillation period. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG1 is a schematic structural diagram of an oscillation period circuit provided in an embodiment of the present application;

[0022] FIG2 is a schematic structural diagram of another oscillation period circuit provided in an embodiment of the present application;

[0023] FIG3 is a schematic diagram of signal waveforms of an oscillation period circuit provided in an embodiment of the present application;

[0024] FIG4 is a schematic diagram of a simulation test of an oscillation period circuit provided in an embodiment of the present application;

[0025] FIG5 is a flow chart of an oscillation period detection method provided in an embodiment of the present application;

[0026] FIG6 is a schematic diagram of the structure of a semiconductor memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the related applications and are not intended to limit the applications. It should also be noted that for ease of description, only the parts relevant to the related applications are shown in the drawings.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0029] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0030] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0031] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers, consisting of numerous repetitive memory cells. In DRAM, an oscillator is required to generate a regular timing signal, which is used to control the multiple memory cells. Therefore, oscillator cycle detection is a key component of memory chip quality testing.

[0032] There are many ways to test the oscillator inside a memory chip, which can be roughly divided into two categories. One is direct testing, which leads the oscillator's output clock to a test machine. This test method is suitable for low-speed clocks. The second type is to output the internal clock cycle number through control logic and calculate the oscillator period based on the oscillator's operating time.

[0033] However, in the related art, the detection method of the oscillation period duration still has shortcomings, resulting in low detection accuracy and efficiency.

[0034] Based on this, an embodiment of the present application provides an oscillation period detection circuit, the basic idea of ​​which is that the oscillation period detection circuit includes: an oscillator module, including a target oscillator, configured to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal; a control module, configured to receive the enable signal and the oscillation clock signal, and perform effective time reshaping processing according to the oscillation clock signal and the enable signal to determine the target time; a counting module, configured to receive the enable signal and the oscillation clock signal, and perform cycle counting processing according to the enable signal and the oscillation clock signal to determine the target number of cycles; wherein the oscillation period of the target oscillator is calculated based on the target time and the target number of cycles. In this way, the enable signal and the oscillation clock signal are subjected to effective time reshaping processing to determine the target time, and the enable signal and the oscillation clock signal are subjected to cycle counting to determine the target number of cycles. Subsequently, the oscillation period can be calculated based on the target time and the target number of cycles, thereby improving the detection accuracy and efficiency of the oscillation period.

[0035] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0036] In one embodiment of the present application, referring to FIG1 , a schematic diagram of the structure of an oscillation period detection circuit 10 provided in an embodiment of the present application is shown. As shown in FIG1 , the oscillation period detection circuit 10 includes:

[0037] The oscillator module 101 includes a target oscillator 1011 and is configured to receive an enable signal and control the target oscillator 1011 to output an oscillation clock signal according to the enable signal;

[0038] The control module 102 is configured to receive an enable signal and an oscillation clock signal, and perform effective time resetting processing according to the oscillation clock signal and the enable signal to determine a target time;

[0039] The counting module 103 is configured to receive an enable signal and an oscillation clock signal, and perform cycle counting processing according to the enable signal and the oscillation clock signal to determine a target number of cycles;

[0040] The oscillation period of the target oscillator 1011 is calculated based on the target time and the target number of periods.

[0041] It should be noted that the oscillation period detection circuit provided in the embodiments of the present application can be applied to any electronic device involving an oscillator, such as a dynamic random access memory, a static random access memory, etc.

[0042] In the embodiment of the present application, the basic principle of the oscillation period detection circuit 10 is: outputting the internal clock period number through the control logic, and calculating the period of the oscillator according to the oscillator working time.

[0043] Specifically, the oscillation period detection circuit includes an oscillator module 101, a control module 102, and a counting module 103. A target oscillator 1011 in the oscillator module 101 outputs an oscillation clock signal based on an enable signal. The control module 102 recalibrates the effective time of the enable signal based on the oscillation clock signal and outputs a target time. The counting module 103 counts the cycles of the oscillation clock signal based on the enable signal to determine the target number of cycles. Thus, the oscillation period of the target oscillator 1011 can be calculated based on the target time and the target number of cycles.

[0044] Furthermore, in some embodiments, referring to FIG2 , a schematic diagram of the structure of another oscillation period detection circuit 10 provided in an embodiment of the present application is shown. As shown in FIG2 , the control module 102 includes a first trigger 1021, a second trigger 1022, and a third trigger 1023. The input terminal (D) of the first trigger 1021 is used to receive an enable signal, the input terminal (D) of the second trigger 1022 is connected to the output terminal (Q) of the first trigger 1021, the input terminal (D) of the third trigger 1023 is connected to the output terminal (Q) of the second trigger 1022, and the clock terminal (CK) of the first trigger 1021, the clock terminal (CK) of the second trigger 1022, and the clock terminal (CK) of the third trigger 1023 are all used to receive an oscillation clock signal; wherein,

[0045] The first trigger 1021 is specifically configured to sample the enable signal according to the oscillation clock signal and output a first control signal;

[0046] The second trigger 1022 is used to sample the first control signal according to the oscillation clock signal and output a second control signal;

[0047] The third trigger 1023 is configured to sample the second control signal according to the oscillation clock signal and output a third control signal.

[0048] Here, the duration of time that the first control signal is in the first level state is used to determine the target time, which is an integer multiple of the oscillation period of the target oscillator; the second control signal is used to latch the target number of cycles when the first level state is flipped to the second level state, and the third control signal is used to clear the counting module 103 when the first level state is flipped to the second level state.

[0049] It should be noted that the control module 102 is composed of a first flip-flop 1021, a second flip-flop 1022, and a third flip-flop 1023, and their specific connection relationship is shown in Figure 2. A flip-flop is an electronic device that often appears in logic circuits. The flip-flop includes a clock terminal and an input terminal. The flip-flop receives an oscillating clock signal through the clock terminal and samples the signal at the input terminal based on the oscillating clock signal.

[0050] The first trigger 1021, the second trigger 1022, and the third trigger 1023 can be triggers based on various principles, and those skilled in the art can select a trigger based on the actual application scenario. For example, the first trigger 1021, the second trigger 1022, and the third trigger 1023 can all be D-type triggers. D-type triggers can sample the signal at the input terminal on the rising edge of the oscillation clock signal.

[0051] For the first trigger 1021, the enable signal is sampled at the rising edge of the oscillation clock signal, thereby outputting the first control signal. Referring to Figure 3, it shows a signal waveform schematic diagram of an oscillation period circuit provided by an embodiment of the present application. As shown in Figure 3, since the first trigger 1021 is sampled only at the rising edge of the oscillation clock signal, the first control signal is only likely to change its level state at the rising edge of the oscillation clock signal, so the duration of the first control signal being in the first level state must be an integer multiple of the oscillation period of the target oscillator 1011. In other words, the first trigger 1021 is mainly used to reorganize the effective time of the enable signal to an integer multiple of the oscillation period (of the target oscillator), thereby determining the target time.

[0052] The second flip-flop 1022 samples the first control signal at the rising edge of the oscillation clock signal, outputting it as a second control signal. As shown in FIG3 , the effective duration of the second control signal (the duration it remains at the first level) is delayed by one oscillation cycle (of the target oscillator) relative to the first control signal. The second control signal is primarily used to latch the target number of cycles.

[0053] The third flip-flop 1023 samples the second control signal at the rising edge of the oscillation clock signal, and outputs the third control signal. As shown in FIG3 , the effective duration of the third control signal (the duration of the first level state) is delayed by one oscillation cycle (of the target oscillator) relative to the second control signal, and is primarily used to reset the counter module 103.

[0054] Furthermore, in some embodiments, the oscillator module 101 is specifically configured to receive an enable signal and a third control signal, and to control the target oscillator 1011 to output an oscillation clock signal when the enable signal is at a first level or the third control signal is at a first level; and to control the target oscillator 1011 to stop outputting the oscillation clock signal when both the enable signal and the third control signal are at a second level. In this way, the target oscillator is controlled simultaneously using the enable signal and the third control signal, thereby preventing the target oscillator from prematurely ceasing oscillation and causing errors during the measurement process.

[0055] Therefore, in some embodiments, as shown in FIG2 , the oscillator module 101 further includes a NOR gate 1012 and a NOT gate 1013 ; wherein,

[0056] A NOR gate 1012 is configured to perform a NOR operation on the third control signal and the enable signal to obtain a calculated signal;

[0057] NOT gate 1013, used for performing a NOT operation on the calculated signal to obtain an enable control signal;

[0058] The target oscillator 1011 is configured to receive an enable control signal and output an oscillation clock signal according to the enable control signal.

[0059] It should be noted that the third control signal and the enable signal are sequentially subjected to a NOR operation and a NOT operation to obtain an enable control signal, which is used to control the target oscillator 1011 to output a target oscillation signal.

[0060] Furthermore, in some embodiments, as shown in FIG2 , the counting module 103 includes a counter 1031 , wherein the input terminal, the clock terminal, and the reset terminal of the counter 1031 are connected to the enable signal, the oscillation clock signal, and the third control signal, respectively;

[0061] Counter 1031 is used to perform cycle counting processing on the oscillation clock signal when the enable signal is in the first level state, output a cycle counting signal, and the cycle counting signal is used to indicate the target number of cycles; and perform zero clearing processing when the third control signal flips from the first level state to the second level state.

[0062] It should be noted that the counting module 103 mainly includes a counter 1031. For the counter 1031, the enable signal plays a gating role. When the enable signal is valid (in the first level state), the counter 1031 counts the cycles of the oscillation clock signal, thereby outputting a cycle counting signal; in addition, for the counter 1031, the third control signal is a reset signal. When the third control signal flips from the first level state to the second level state, the count value of the counter 1031 is cleared.

[0063] Furthermore, in some embodiments, the oscillation period detection circuit 10 further includes a latch 104, and two input terminals of the latch are connected to the period counting signal and the second control signal respectively; wherein,

[0064] The latch 104 is configured to latch the cycle counting signal when the second control signal is flipped from the first level state to the second level state, so as to achieve latching of the target number of cycles.

[0065] It should be noted that the input end of the latch 104 receives the cycle counting signal output by the counter 1031 and also receives the second control signal, and latches the cycle counting signal at the falling edge of the second control signal.

[0066] From the above, it can be seen that when the enable signal is in the first level state, the counter 1031 counts the period of the oscillation clock signal; at the falling edge of the second control signal, the latch 104 latches the period counting signal output by the counter 1031, thereby obtaining the target number of periods; at the falling edge of the third control signal, the count value of the counter 1031 is cleared.

[0067] It should also be noted that the first level state is a high level state and the second level state is a low level state, but this does not constitute a limitation of the embodiments of the present application.

[0068] Please refer to Figure 4, which shows a simulation test schematic diagram of an oscillation period circuit provided by an embodiment of the present application. As shown in Figure 4, the embodiment of the present application adopted two simulation experiments. In the first simulation experiment, the target time was 1000 nanoseconds, and the number of cycles was the simulation result: 592 (binary is 0000 0010 0101 0000), so that the oscillation period can be calculated to be 1.69 nanoseconds; in the second simulation experiment, the oscillation period was the simulation result: 1.687 nanoseconds, and the number of cycles was calculated to be 593 (binary is 0000 0010 0101 0001). As can be seen from the above, the results of the oscillation period circuit provided by the embodiment of the present application are more accurate.

[0069] Table 1

[0070]

[0071] An embodiment of the present application provides an oscillation period detection circuit, which includes an oscillator module, including a target oscillator, configured to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal; a control module, configured to receive the enable signal and the oscillation clock signal, and perform effective time reshaping processing according to the oscillation clock signal and the enable signal to determine a target time; a counting module, configured to receive the enable signal and the oscillation clock signal, and perform period counting processing according to the enable signal and the oscillation clock signal to determine a target number of periods; wherein the oscillation period of the target oscillator is calculated based on the target time and the target number of periods. In this way, the embodiment of the present application provides a new circuit control structure, which is mainly used to detect the period of the internal oscillator of the chip, and can also be used as an auxiliary circuit in the propagation delay time (Tpd) test in the wafer level test (WAT); specifically, the enable signal and the oscillation clock signal are processed by effective time reorganization to determine the target time, and the enable signal and the oscillation clock signal are processed by cycle counting to determine the target number of cycles. Subsequently, the oscillation period can be calculated by the target time and the target number of cycles, thereby improving the detection accuracy and detection efficiency of the oscillation period; in addition, the oscillation period detection circuit provided in the embodiment of the present application is suitable for high-speed clocks and low-speed clocks, and has a wide range of application scenarios.

[0072] In another embodiment of the present application, referring to FIG5 , which shows a flow chart of an oscillation period detection method provided by an embodiment of the present application. As shown in FIG5 , the method may include:

[0073] S201: According to the enable signal, control the target oscillator to output an oscillation clock signal.

[0074] It should be noted that the oscillation period detection method in the embodiments of the present application is applied to the aforementioned oscillation period detection circuit, and the oscillation period detection circuit includes a target oscillator. Here, the target oscillator is capable of outputting an oscillation clock signal in response to an enable signal. In other words, the purpose of the oscillation period detection method provided in the embodiments of the present application is to detect the period of the oscillation clock signal.

[0075] S202: Perform effective time resetting processing according to the oscillation clock signal and the enable signal to determine the target time.

[0076] S203: Perform cycle counting processing according to the enable signal and the oscillation clock signal to determine the target number of cycles.

[0077] It should be noted that the oscillation clock signal is used to perform effective clock reshaping on the enable signal, and the effective time of the enable signal is reshaped into an integer multiple of the oscillation period, thereby obtaining the target time; and the enable signal is used to perform cycle counting on the oscillation clock signal to obtain the target number of cycles.

[0078] Specifically, in some embodiments, the oscillation period detection circuit may include a first trigger, a second trigger, and a third trigger. Accordingly, the method may further include:

[0079] receiving an enable signal and an oscillation clock signal through a first trigger, performing sampling processing according to the oscillation clock signal and the enable signal, and outputting a first control signal;

[0080] receiving the first control signal and the oscillation clock signal through the second trigger, sampling the first control signal according to the oscillation clock signal, and outputting a second control signal;

[0081] The second control signal and the oscillation clock signal are received through the third trigger, and the second control signal is sampled and processed according to the oscillation clock signal to output a third control signal.

[0082] It should be noted that the first trigger samples the enable signal primarily on the rising edge of the oscillation clock signal to generate the first control signal, thereby resetting the effective duration of the enable signal to an integer multiple of the oscillation period of the target oscillator, facilitating subsequent calculations. In other words, the duration that the first control signal remains at the first level is used to determine the target time, which is an integer multiple of the oscillation period of the target oscillator.

[0083] The second flip-flop primarily samples the first control signal at the rising edge of the oscillation clock signal to generate a second control signal. The effective duration of the second control signal is delayed by one oscillation cycle (of the target oscillator) compared to the first control signal, thereby latching the target number of cycles. In other words, the second control signal is configured to latch the target number of cycles when the first level state flips to the second level state.

[0084] The third flip-flop primarily samples the second control signal at the rising edge of the oscillation clock signal to generate a third control signal. The effective duration of the third control signal is delayed by one oscillation cycle (of the target oscillator) compared to the second control signal. The third control signal is used to clear the counting module. In other words, the third control signal is used to clear the counting module when the first level state flips to the second level state.

[0085] In the above description, the valid time of a signal refers to the time during which the signal is in the first level state.

[0086] Furthermore, in some embodiments, controlling the target oscillator to output the oscillation clock signal according to the enable signal may include:

[0087] When the enable signal is in the first level state or the third control signal is in the first level state, controlling the target oscillator to output an oscillation clock signal;

[0088] When the enable signal and the third control signal are both in the second level state, the target oscillator is controlled to stop outputting the oscillation clock signal.

[0089] It should be noted that the target oscillator is controlled simultaneously by using the enable signal and the third control signal to prevent the target oscillator from stopping oscillation prematurely, thereby causing errors in the measurement process.

[0090] In a specific embodiment, the oscillation period detection circuit further includes a counter and a latch. Accordingly, the cycle counting process of the oscillation clock signal according to the enable signal to determine the target number of cycles may include:

[0091] When the enable signal is in a first level state, the oscillation clock signal is cycle counted by the counter, and a cycle count signal is output, where the cycle count signal is used to indicate a target cycle number;

[0092] When the second control signal is flipped from the first level state to the second level state, the latch performs a latching process on the cycle counting signal to achieve a latching process of the target number of cycles.

[0093] It should be noted that when the enable signal is valid, the counter counts the cycles of the oscillation clock signal and outputs a cycle count signal. Simultaneously, at the falling edge of the second control signal, the latch latches the cycle count signal to obtain the target number of cycles.

[0094] It should be noted that the reset terminal of the counter is connected to the third control signal. Therefore, in some embodiments, the method may further include:

[0095] When the third control signal is flipped from the first level state to the second level state, the control counter is cleared.

[0096] In this way, after each test is completed, the count value of the counter will be reset to zero and wait for the next test.

[0097] Furthermore, in some embodiments, controlling the target oscillator to output the oscillation clock signal according to the enable signal may include:

[0098] Performing a NOR operation on the third control signal and the enable signal to obtain a calculated signal;

[0099] Perform a negation operation on the operated signal to obtain an enable control signal;

[0100] According to the enable control signal, the target oscillator is controlled to output an oscillation clock signal.

[0101] It should be noted that the third control signal and the enable signal, after undergoing an OR operation and a NOT operation, are used to control the oscillation clock signal. Thus, when both the third control signal and the enable signal are at the second level, the enable control signal is at the second level, and the target oscillator stops outputting the target oscillation signal. When the third control signal is at the first level or the enable signal is at the first level, the enable control signal is at the first level, and the target oscillator outputs the target oscillation signal.

[0102] In this way, after the above processing, the target number of cycles of the oscillation clock signal within the target time can be obtained.

[0103] S204: Calculate the target time and the target number of cycles to determine the oscillation period of the target oscillator.

[0104] It should be noted that after the target time and the target number of cycles are obtained, the oscillation period of the target oscillator can be determined through simple calculations.

[0105] Specifically, calculating the target time and the target number of cycles to determine the oscillation period of the target oscillator may include:

[0106] The target oscillator period is obtained by dividing the target time by the target number of periods.

[0107] It should be noted that the oscillation period of the target oscillator=target time / target number of periods.

[0108] In another embodiment, since the first count value of the counter is 0, the exact number of cycles of the oscillation period signal is actually (target number of cycles + 1). In other words, the exact oscillation period = target time / (target number of cycles + 1). However, in a test, the number of oscillation cycles is generally larger, so the target number of cycles can be used instead of (target number of cycles + 1) for calculation, and the error is within an acceptable range.

[0109] It should also be noted that the first level state is a high level state, and the second level state is a low level state.

[0110] An embodiment of the present application provides an oscillation period detection method, which controls the target oscillator to output an oscillation clock signal according to an enable signal; performs effective time resetting processing based on the oscillation clock signal and the enable signal to determine the target time; performs cycle counting processing based on the enable signal and the oscillation clock signal to determine the target number of cycles; and calculates the target time and the target number of cycles to determine the oscillation period of the target oscillator. In this way, the enable signal and the oscillation clock signal undergo effective time resetting processing to determine the target time, and the enable signal and the oscillation clock signal undergo cycle counting to determine the target number of cycles. Subsequently, the oscillation period can be calculated based on the target time and the target number of cycles, thereby improving the detection accuracy and efficiency of the oscillation period.

[0111] In yet another embodiment of the present application, referring to FIG. 6 , a semiconductor memory 30 provided in an embodiment of the present application is shown. The semiconductor memory 30 at least includes the aforementioned oscillation period detection circuit 10 .

[0112] For the semiconductor memory 30, since it includes an oscillation period detection circuit 10, during the oscillation period detection process, the enable signal and the oscillation clock signal are used to perform effective time reorganization processing to determine the target time, and the enable signal and the oscillation clock signal are counted through cycles to determine the target number of cycles. Subsequently, the oscillation period can be calculated based on the target time and the target number of cycles, thereby improving the detection accuracy and efficiency of the oscillation period.

[0113] In yet another embodiment of the present application, an electronic device is provided. The electronic device includes at least the aforementioned semiconductor memory 30 .

[0114] For the electronic device, since it includes a semiconductor memory 30, during the oscillation period detection process, the enable signal and the oscillation clock signal are used to perform effective time reorganization processing to determine the target time, and the enable signal and the oscillation clock signal are counted through cycles to determine the target number of cycles. Subsequently, the oscillation period can be calculated based on the target time and the target number of cycles, thereby improving the detection accuracy and efficiency of the oscillation period.

[0115] The above description is merely a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application.

[0116] It should be noted that, in this application, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0117] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0118] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0119] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0120] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0121] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims. Industrial Applicability

[0122] The embodiment of the present application provides an oscillation period detection circuit, method and semiconductor memory, the oscillation period detection circuit comprising: an oscillator module, comprising a target oscillator, for receiving an enable signal and controlling the target oscillator to output an oscillation clock signal according to the enable signal; a control module, configured to receive the enable signal and the oscillation clock signal, and perform effective time reshaping processing according to the oscillation clock signal and the enable signal to determine the target time; a counting module, configured to receive the enable signal and the oscillation clock signal, and perform cycle counting processing according to the enable signal and the oscillation clock signal to determine the target number of cycles; wherein the oscillation period of the target oscillator is calculated based on the target time and the target number of cycles. In this way, the enable signal and the oscillation clock signal undergo effective time reshaping processing to determine the target time, and the enable signal and the oscillation clock signal undergo cycle counting to determine the target number of cycles. Subsequently, the oscillation period can be calculated based on the target time and the target number of cycles, thereby improving the detection accuracy and efficiency of the oscillation period.

Claims

1. An oscillation period detection circuit, comprising: an oscillator module including a target oscillator configured to receive an enable signal and control the target oscillator to output an oscillation clock signal according to the enable signal; a control module configured to receive the enable signal and the oscillation clock signal, and perform effective time reorganization processing according to the oscillation clock signal and the enable signal to determine a target time; a counting module configured to receive the enable signal and the oscillation clock signal, and perform period counting processing according to the enable signal and the oscillation clock signal to determine a target period number; wherein the oscillation period of the target oscillator is calculated based on the target time and the target period number.

2. The oscillation period detection circuit according to claim 1, wherein, the control module includes a first flip-flop, a second flip-flop and a third flip-flop. The input terminal (D) of the first flip-flop is used to receive the enable signal. The input terminal (D) of the second flip-flop is connected to the output terminal (Q) of the first flip-flop. The input terminal (D) of the third flip-flop is connected to the output terminal (Q) of the second flip-flop. And the clock terminals (CK) of the first flip-flop, the second flip-flop and the third flip-flop are all used to receive the oscillation clock signal; wherein, the first flip-flop is specifically configured to sample the enable signal according to the oscillation clock signal and output a first control signal; the second flip-flop is configured to sample the first control signal according to the oscillation clock signal and output a second control signal; the third flip-flop is configured to sample the second control signal according to the oscillation clock signal and output a third control signal; wherein the duration of the first control signal in the first level state is used to determine the target time, and the target time is an integral multiple of the oscillation period of the target oscillator; the second control signal is used to latch the target period number when flipping from the first level state to the second level state, and the third control signal is used to clear the counting module when flipping from the first level state to the second level state.

3. The oscillation period detection circuit according to claim 2, wherein, the oscillator module is specifically configured to receive the enable signal and the third control signal, and control the target oscillator to output the oscillation clock signal when the enable signal is in the first level state or the third control signal is in the first level state; and control the target oscillator to stop outputting the oscillation clock signal when both the enable signal and the third control signal are in the second level state.

4. The oscillation period detection circuit according to claim 3, wherein, the counting module includes a counter, and the input terminal, clock terminal and reset terminal of the counter are respectively connected to the enable signal, the oscillation clock signal and the third control signal; wherein, The counter is used to perform a cycle counting process on the oscillating clock signal when the enable signal is in the first level state, output a cycle counting signal, and the cycle counting signal is used to indicate the target cycle number; and perform a clearing process when the third control signal flips from the first level state to the second level state.

5. The oscillating period detection circuit according to claim 4, wherein, the oscillating period detection circuit further includes a latch, and two input terminals of the latch are respectively connected to the cycle counting signal and the second control signal; wherein, the latch is used to latch the cycle counting signal when the second control signal flips from the first level state to the second level state, so as to implement the latching process of the target cycle number.

6. The oscillating period detection circuit according to claim 3, wherein, the oscillator module further includes a NOR gate and a NOT gate; the NOR gate is used to perform a NOR operation on the third control signal and the enable signal to obtain an operation result signal; the NOT gate is used to perform a NOT operation on the operation result signal to obtain an enable control signal; the target oscillator is used to receive the enable control signal and output the oscillating clock signal according to the enable control signal.

7. The oscillating period detection circuit according to claim 2, wherein, the first flip-flop, the second flip-flop, and the third flip-flop are all D-type flip-flops.

8. The oscillating period detection circuit according to any one of claims 2-7, wherein, the first level state is a high level state, and the second level state is a low level state.

9. An oscillating period detection method, applied to an oscillating period detection circuit including a target oscillator, the method includes: Controlling the target oscillator to output an oscillating clock signal according to an enable signal; Performing an effective time reorganization process according to the oscillating clock signal and the enable signal to determine a target time; Performing a cycle counting process according to the enable signal and the oscillating clock signal to determine a target cycle number; Calculating the target time and the target cycle number to determine the oscillating period of the target oscillator.

10. The oscillating period detection method according to claim 9, wherein, the oscillating period detection circuit includes a first flip-flop, a second flip-flop, and a third flip-flop; the method further includes: Receiving the enable signal and the oscillating clock signal through the first flip-flop, and performing a sampling process according to the oscillating clock signal and the enable signal to output a first control signal; Receiving the first control signal and the oscillating clock signal through the second flip-flop, and performing a sampling process on the first control signal according to the oscillating clock signal to output a second control signal; Receiving the second control signal and the oscillating clock signal through the third flip-flop, and performing a sampling process on the second control signal according to the oscillating clock signal to output a third control signal; Wherein, the duration for which the first control signal is in the first level state is used to determine the target time, and the target time is an integer multiple of the oscillation period of the target oscillator; the second control signal is used to latch the target period number when flipping from the first level state to the second level state, and the third control signal is used to clear when flipping from the first level state to the second level state.

11. The oscillation period detection method according to claim 10, wherein, the controlling the target oscillator to output an oscillation clock signal according to the enable signal includes: when the enable signal is in the first level state or the third control signal is in the first level state, controlling the target oscillator to output the oscillation clock signal; when both the enable signal and the third control signal are in the second level state, controlling the target oscillator to stop outputting the oscillation clock signal.

12. The oscillation period detection method according to claim 11, wherein, the oscillation period detection circuit includes a counter and a latch, and the determining the target period number by performing a period counting process on the oscillation clock signal according to the enable signal includes: when the enable signal is in the first level state, performing a period counting process on the oscillation clock signal through the counter to output a period counting signal, and the period counting signal is used to indicate the target period number; when the second control signal flips from the first level state to the second level state, latching the period counting signal through the latch to implement the latching process of the target period number.

13. The oscillation period detection method according to claim 12, wherein, the method further includes: when the third control signal flips from the first level state to the second level state, controlling the counter to perform a clearing process.

14. The oscillation period detection method according to claim 12, wherein, the controlling the target oscillator to output an oscillation clock signal according to the enable signal includes: performing a NOR operation on the third control signal and the enable signal to obtain an operation result signal; performing a NOT operation on the operation result signal to obtain the enable control signal; controlling the target oscillator to output the oscillation clock signal according to the enable control signal.

15. The oscillation period detection method according to any one of claims 11-14, wherein, the calculating the target time and the target period number to determine the oscillation period of the target oscillator includes: dividing the target time by the target period number to obtain the oscillation period of the target oscillator.

16. The oscillation period detection method according to any one of claims 10-15, wherein, the first level state is a high level state, and the second level state is a low level state.

17. A semiconductor memory, the semiconductor memory at least includes the oscillation period detection circuit according to any one of claims 1-8.