Semiconductor device and method of fabricating thereof

Abstract

A semiconductor device includes: a first capacitor; a first channel structure located above the first capacitor; a first gate dielectric along a sidewall of the first channel structure; a first word line along a sidewall of the first gate dielectric; a bit line located above the first channel structure; a second channel structure located on the bit line; a second gate dielectric along a sidewall of the second channel structure; a second word line along a sidewall of the second gate dielectric; and a second capacitor located above the second channel structure.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. Prior Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of random access semiconductor memory that stores each bit of data in a storage cell. DRAM is known for its high speed, high density, and scalability. However, as DRAM production scales up, DRAM manufacturing becomes more challenging and more prone to defects. For example, certain designs may limit the pace of wafer size reduction. Therefore, there is a need for an efficient semiconductor device and its manufacturing method. Summary of the Invention

[0003] The embodiments disclosed herein provide a semiconductor device, including: a first capacitor; a first channel structure located above the first capacitor; a first gate dielectric along a sidewall of the first channel structure; a first word line along a sidewall of the first gate dielectric; a bit line located above the first channel structure; a second channel structure located on the bit line; a second gate dielectric along a sidewall of the second channel structure; a second word line along a sidewall of the second gate dielectric; and a second capacitor located above the second channel structure.

[0004] In some embodiments, the second capacitor at least partially overlaps with the first capacitor.

[0005] In some embodiments, the second channel structure at least partially overlaps with the first channel structure.

[0006] In some embodiments, the device further includes: a first contact located between the first channel structure and the bit line, and electrically connected to the first channel structure and the bit line; and a second contact located between the bit line and the second channel structure, and electrically connected to the bit line and the second channel structure.

[0007] In some embodiments, the system further includes: a first isolation layer adjacent to the first channel structure; and a second isolation layer adjacent to the second channel structure.

[0008] In some embodiments, the first gate dielectric is in contact with a sidewall of the first isolation layer, and the second gate dielectric is in contact with a sidewall of the second isolation layer.

[0009] In some embodiments, it further includes: a first dielectric layer surrounding the first channel structure, wherein the first word line is located between the first dielectric layer and the first isolation layer; and a second dielectric layer surrounding the first channel structure, wherein the second word line is located between the second dielectric layer and the second isolation layer.

[0010] In some embodiments, in a top view, the first character line and the second character line extend along a first direction, and the bit line extends along a second direction different from the first direction.

[0011] In some embodiments, the first channel structure and the second channel structure are made of oxide semiconductor material.

[0012] In some embodiments, both the first channel structure and the second channel structure are made of indium gallium zinc oxide (IGZO).

[0013] The embodiments disclosed herein provide a method for manufacturing a semiconductor device, comprising: forming a first capacitor; forming a first dielectric layer having a first opening above the first capacitor; forming a first word line along a sidewall of the first opening; forming a first gate dielectric layer along the first word line; forming a first channel structure along the first gate dielectric layer and above the first capacitor; forming a bit line above the first channel structure; forming a second dielectric layer having a second opening above the first channel structure; forming a second word line along a sidewall of the second opening; forming a second gate dielectric layer along the second word line; forming a second channel structure along the second gate dielectric layer and above the first channel structure; and forming a second capacitor above the second channel structure.

[0014] In some embodiments, forming the first channel structure includes: forming a channel material in a first opening above a first dielectric layer; and removing a portion of the channel material, leaving a remaining portion of the channel material as the first channel structure.

[0015] In some embodiments, the method further includes: forming an isolation layer adjacent to the first channel structure.

[0016] In some embodiments, an isolation layer is formed along the first gate dielectric.

[0017] In some embodiments, the first character line is located between the first dielectric layer and the isolation layer.

[0018] In some embodiments, the method further includes: forming a first contact above the first channel structure before forming the bit line, wherein the first contact is electrically connected to the first channel structure and the bit line; and forming a second contact on the bit line before forming the second channel structure, wherein the second contact is electrically connected to the bit line and the second channel structure.

[0019] In some embodiments, forming the second capacitor includes: forming a dielectric layer on the second channel structure; forming an opening in the dielectric layer, wherein the opening exposes a top surface of the second channel structure; forming the second capacitor in the opening; and etching back the dielectric layer, wherein a top surface of the dielectric layer is lower than a top surface of the second capacitor.

[0020] In some embodiments, the second capacitor is formed to at least partially overlap with the first capacitor.

[0021] In some embodiments, the second channel structure is formed by at least partially overlapping the first channel structure.

[0022] In some embodiments, in a top view, the first character line and the second character line extend along a first direction, and the bit line extends along a second direction different from the first direction. Simple Explanation of the Diagram

[0023] When read with reference to the accompanying drawings, the following detailed description is the best way to understand the nature of this disclosure. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 is a schematic diagram of a semiconductor device according to a partial embodiment of the present disclosure. Figure 2 is a schematic diagram of a memory cell according to a partial embodiment of this disclosure. Figure 3 is a flowchart of a method for manufacturing a semiconductor device according to some embodiments of this disclosure. Figures 4A to 22B illustrate a method for manufacturing a semiconductor device according to some embodiments of this disclosure. Implementation

[0024] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, some of which illustrate exemplary embodiments. However, this disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. It is worth noting that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0025] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another region, layer, or part. Therefore, the first element, component, region, layer, or part discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this disclosure.

[0026] Additionally, for ease of description, spatial relative terms such as "beneath," "below," "lower," "above," and "upper," and similar terms, are used to describe the relationship of one element or feature to another, as shown in the figure. It should be understood that spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. For example, if the device in the figure is flipped, an element described as "below" or "below" other elements or features would be positioned "above" other elements or features. Thus, the exemplary term "below" can encompass both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0027] As used herein, "approximately," "about," "roughly," or "substantially" can generally mean within 20%, 10%, or 5% of a given value or range. The values ​​given herein are approximate, meaning that unless explicitly stated otherwise, the terms "approximately," "about," "roughly," or "substantially" can be inferred. However, those skilled in the art will recognize that the values ​​or ranges listed throughout the description are merely examples and can decrease or vary as integrated circuits shrink in size.

[0028] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit this disclosure. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including," when used in this specification, designate the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence of said features, integrals, steps, operations, elements, and / or components.

[0029] This document describes exemplary embodiments with reference to cross-sectional views, which are schematic diagrams of idealized exemplary embodiments (and intermediate structures). Therefore, variations in the illustrated shapes are expected due to, for example, manufacturing techniques and / or tolerances. Thus, the exemplary embodiments should not be construed as limited to the specific shapes of the areas shown herein, but rather include, for example, shape deviations due to manufacturing processes. For example, an injection area illustrated as rectangular will typically have circular or curved features and / or an injection concentration gradient at its edges, rather than a binary variation from the injection area to the non-injection area. Similarly, a buried area formed through injection can result in some injection in the area between the buried area and the surface through which injection is carried out. Therefore, the areas shown in the figures are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device and are not intended to limit the scope of this disclosure.

[0030] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having the meaning consistent with their meaning in the context of the relevant field and should not be interpreted in an idealized or overly formal sense, unless explicitly defined herein.

[0031] The exemplary embodiments will now be explained in detail with reference to the accompanying drawings.

[0032] Figure 1 is a schematic diagram of a semiconductor device according to a partial embodiment of this disclosure. The figure shows a semiconductor device 10. The semiconductor device 10 includes a plurality of memory cells 11 arranged in a rectangular matrix. Figure 1 shows a simple example of a four-by-four cell matrix. Other memory matrices may have a height and width of thousands of cells. In some embodiments, the semiconductor device 10 may be dynamic random access memory (dynamic RAM or DRAM).

[0033] Each row of memory cells 11 is connected via word lines 20, and each column of memory cells 11 is connected via bit lines 30. Multiple word lines 20 can extend horizontally. The word lines 20 are parallel to each other. Furthermore, the word lines 20 can be separated from each other at substantially equal intervals. On the other side, multiple bit lines 30 can extend vertically. Similar to the word lines 20, the bit lines 30 are parallel to each other and can be separated from each other at substantially equal intervals.

[0034] Figure 2 is a schematic diagram of a memory cell according to a partial embodiment of the present disclosure. Specifically, Figure 2 is a close-up of Figure 1. In some embodiments, the memory cell 11 includes a transistor 11T and a storage capacitor 11C electrically connected to the transistor 11T.

[0035] In some embodiments, the access transistor 11T is an NMOS transistor and is configured to control the channel to the memory cell 11 by turning the gate of the access transistor 11T on or off. In some embodiments, the storage capacitor 11C is configured to store information according to the state of the charge stored therein. The storage capacitor 11C in an empty state (i.e., no charge) is represented by a logic value 0. The storage capacitor 11C in a fully charged state is represented by a logic value 1. The memory cell 11 uses the two extreme charge states stored in the storage capacitor 11C to store one bit of data.

[0036] In some embodiments, word lines 20 connected to the access transistor 11T are used to control the gate of the access transistor 11T by applying a voltage to the gate of the access transistor 11T. In some embodiments, bit lines 30 are arranged perpendicular to word lines 20 and are also connected to the access transistor 11T. When the gate of the access transistor 11T is turned on, the access transistor 11T connects a storage capacitor 11C to the bit line 30, such that the logic value stored in the storage capacitor 11C is read onto the bit line 30.

[0037] Figure 3 is a flowchart of a method for manufacturing a semiconductor device according to a partial embodiment of the present disclosure. Figures 4A to 22B are methods for manufacturing a semiconductor device according to a partial embodiment of the present disclosure. Specifically, Figures 4A to 22A are top-view cross-sectional views along line A-A' of Figures 4B to 22B.

[0038] The semiconductor device and its manufacturing method M50 will be discussed in conjunction with Figures 4A to 22A. As shown in Figure 3, the manufacturing method M50 may include the following operations: operation S100, operation S200, operation S300, operation S400, operation S500, operation S600, operation S700, operation S800, operation S900, operation S1000, operation S1100, operation S1200, operation S1300, operation S1400, operation S1500, operation S1600, operation S1700, operation S1800, and operation S1900.

[0039] This document provides various operations for the embodiments. The order in which some or all of the operations are described should not be construed as implying that these operations necessarily depend on the order. The benefits of alternative ordering can be understood through this description. Furthermore, it should be understood that not all operations must exist in every embodiment provided herein. Moreover, it should be understood that not all operations are necessary in some embodiments.

[0040] Method M50 begins with operation S100, forming a capacitor in a first dielectric layer and depositing a second dielectric layer on the capacitor. Referring to Figures 4A and 4B, a first dielectric layer 1100 is deposited on a substrate (not shown), a capacitor 1200 is formed in the first dielectric layer 1100, and a second dielectric layer 1300 is deposited and covered on the capacitor 1200.

[0041] In some embodiments, a first dielectric layer 1100 is deposited on a substrate (not shown). In some embodiments, the first dielectric layer 1100 is configured to provide electrical isolation between capacitors 1200 formed in subsequent steps. The first dielectric layer 1100 is made of a dielectric material. In some embodiments, the first dielectric layer 1100 is made of an oxide (e.g., silicon dioxide (SiO2)).

[0042] The first dielectric layer 1100 can be deposited using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flow chemical vapor deposition (FCVD) or other suitable deposition processes.

[0043] In some embodiments, the first dielectric layer 1100 may be patterned to form openings. A mask pattern (not shown) may be formed on the first dielectric layer 1100. Subsequently, the first dielectric layer 1100 is etched through this mask pattern to form openings. In some embodiments, after etching, portions of the first dielectric layer 1100 may be separated from each other by openings, wherein each opening may extend vertically from an underlying structure (not shown) in the substrate and be parallel to each other. In some embodiments, the openings may be horizontally arranged at substantially equal spacing.

[0044] Next, capacitors 1200 can be formed in the openings. In other words, each opening corresponds to one capacitor 1200. In some embodiments, the capacitors 1200 are parallel to each other and can be arranged with a generally equal spacing.

[0045] Capacitor 1200 may include a bottom electrode, a capacitor dielectric layer above the bottom electrode, and a top electrode above the capacitor dielectric layer. In some embodiments, the bottom electrode and top electrode of capacitor 1200 may include a conductive material. In some embodiments, the bottom electrode and top electrode may include a metal. In some embodiments, the bottom electrode and top electrode may include titanium nitride (TiN). In some embodiments, the capacitor dielectric layer of capacitor 1200 may include a dielectric material. The bottom electrode, capacitor dielectric layer, and top electrode of capacitor 1200 may be deposited sequentially using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0046] The capacitor 1200 can be planarized to make it flush with the first dielectric layer 1100. Therefore, the planarized capacitor 1200 and the first dielectric layer 1100 are coplanar and share the same top surface. That is, the top surface of the planarized capacitor 1200 and the top surface of the first dielectric layer 1100 can be adjacent to each other. The planarization process can be performed using a chemical mechanical polishing (CMP) process. The CMP process can be stopped when the first dielectric layer 1100 is exposed.

[0047] Next, a second dielectric layer 1300 may be deposited on the capacitor 1200 and the first dielectric layer 1100. In some embodiments, the second dielectric layer 1300 covers the capacitor 1200. The second dielectric layer 1300 is used to provide electrical isolation between some conductive structures (e.g., bit line structures) formed in subsequent steps.

[0048] The second dielectric layer 1300 is made of a dielectric material. In some embodiments, the second dielectric layer 1300 and the first dielectric layer 1100 may be made of the same material. In some embodiments, the second dielectric layer 1300 is made of an oxide, such as silicon dioxide (SiO2). The second dielectric layer 1300 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. In some embodiments, the vertical thickness of the second dielectric layer 1300 may be slightly less than the vertical thickness of the first dielectric layer 1100.

[0049] In method M50, operation S200 is performed to pattern the second dielectric layer to expose the capacitor. Referring to Figures 5A and 5B, the second dielectric layer 1300 can be patterned to form an opening 1400 exposing the capacitor 1200. A mask pattern (not shown) can be formed on the second dielectric layer 1300. Subsequently, the second dielectric layer 1300 is etched through the mask pattern.

[0050] In some embodiments, operation S200 may include a photolithography process. In some embodiments, the location of the opening 1400 may be defined by a mask pattern. For example, a mask pattern is formed on a vertical portion of a second dielectric layer 1300 on a first dielectric layer 1100, which does not cover the capacitor 1200. Therefore, the portion of the second dielectric layer 1300 on the first dielectric layer 1100 that does not cover the capacitor 1200 is not etched during the etching process, and the opening 1400 is defined after the etching process. In some embodiments, the width of the opening 1400 is greater than the width of the capacitor 1200. In some embodiments, each opening 1400 may extend along a first direction (e.g., the Y direction), and the openings 1400 are arranged along a second direction (e.g., the X direction) that is different from the first direction and substantially perpendicular to the first direction.

[0051] Method M50 continues to operation S300, forming word lines and gate dielectrics along the sidewall of the opening. Referring to Figures 6A and 6B, word lines 1500 and gate dielectrics 1600 are sequentially formed along the sidewall of the opening 1400.

[0052] In some embodiments, word line material (not shown) may be formed over an underlying structure (e.g., a first dielectric layer 1100, a capacitor 1200, and a second dielectric layer 1300). The word line material may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. Then, an anisotropic etching process is performed on the word line material to remove the horizontal portions, leaving only the vertical portions. The remaining vertical portions are referred to as word lines 1500.

[0053] In some embodiments, the character line 1500 may extend upward from the first dielectric layer 1100 and along the sidewall of the opening 1400. In some embodiments, the character line 1500 is made of a conductive material. In some embodiments, the character line 1500 may include a metal. In some embodiments, the character line 1500 may include tungsten (W). In some embodiments, the character line 1500 may serve as a gate electrode to control the channel structure 1700 in FIG. 7A. In some embodiments, the character line 1500 has a strip-shaped top profile.

[0054] Subsequently, a gate dielectric 1600 is formed on the sidewall of the opening 1400. Specifically, the gate dielectric 1600 is formed extending upward from the first dielectric layer 1100 and along the sidewall of the opening 1400.

[0055] In some embodiments, a gate dielectric material blanket (not shown) may be formed over an underlying structure (e.g., a first dielectric layer 1100, a second dielectric layer 1300, a capacitor 1200, and a word line 1500). The gate dielectric material blanket may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0056] Then, an anisotropic etching process is performed on the gate dielectric material blanket to remove the horizontal portion of the gate dielectric material blanket, leaving only the vertical portion of the gate dielectric material along the sidewall of opening 1400. The remaining vertical portion is called gate dielectric 1600.

[0057] In some embodiments, the gate dielectric 1600 is made of a dielectric material. In some embodiments, the gate dielectric 1600 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), etc. In some embodiments, the gate dielectric 1600 is configured to electrically isolate the word line 1500 from conductive structures (e.g., channel structures) formed in subsequent steps. In some embodiments, the width of the gate dielectric 1600 is substantially the same as the width of the word line 1500. In some embodiments, the gate dielectric 1600 has a striped top profile.

[0058] In some embodiments, the top of the gate dielectric 1600 may be substantially flush with the top surface of the second dielectric layer 1300 and the word line 1500. In some embodiments, the word line 1500 and the gate dielectric 1600 do not cover the top of the capacitor 1200. In other words, the capacitor 1200 remains exposed in the opening 1400.

[0059] Method M50 continues to operation S400, where a channel structure material is formed in the opening. Referring to Figures 7A and 7B, a channel structure material 1700M is formed in the opening 1400. Specifically, the channel structure material 1700M is formed on the capacitor 1200 and surrounded by the gate dielectric 1600. In some embodiments, the channel structure material 1700M is formed on a first dielectric layer 1100 and surrounded by the gate dielectric 1600.

[0060] In some embodiments, a channel layer (not shown) may be formed to cover the opening 1400. The channel layer may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. The channel layer may then be planarized (e.g., using a CMP process) to remove excess channel layer portions on top of the second dielectric layer 1300 and flush the channel layer with the second dielectric layer 1300. In some embodiments, planarization may be stopped when the second dielectric layer 1300 is exposed. The remaining portion of the channel layer is referred to as the channel structure material 1700M.

[0061] Method M50 continues to operation S500, where a portion of the channel structure material is removed to re-expose the opening. Referring to Figures 8A and 8B, the portion of the channel structure material 1700M that does not cover the capacitor 1200 is removed, re-exposing the opening 1400.

[0062] First, a masking pattern (not shown) can be formed on the second dielectric layer 1300, the word line 1500, the gate dielectric 1600, and the channel structure material 1700M covering the capacitor 1200. Subsequently, the portions of the channel structure material 1700M not covered by the masking pattern are etched, and the opening 1400 is re-exposed.

[0063] The remaining portion of the channel structure material 1700M is referred to as channel structure 1700. In some embodiments, each channel structure 1700 extends vertically from a corresponding capacitor 1200. In some embodiments, the vertical length of the channel structure 1700 is substantially the same as that of the word line 1500 and / or the gate dielectric 1600. In some embodiments, the channel structure 1700 may be electrically connected to the capacitor 1200 below. In some embodiments, the channel structure 1700 has a square top profile.

[0064] In some embodiments, channel structure 1700 may include an oxide semiconductor (OS) material. In some embodiments, channel structure 1700 may include indium gallium zinc oxide (IGZO). Vertical channel structure 1700 may increase the storage cell density in semiconductor device 10.

[0065] In some embodiments, the channel structure 1700 may be covered by the word line 1500 through the gate dielectric 1600. In other words, the word line 1500 (which can be used as a gate electrode), the gate dielectric 1600, and the channel structure 1700 may form a transistor (e.g., access transistor 11T in FIG. 2), wherein the gate dielectric 1600 covers opposite sides of the channel structure 1700. With this configuration, the channel structure 1700 has a larger contact surface, thereby increasing the current through the gate dielectric 1600 and the word line 1500. Therefore, compared to a planar channel structure, the word line 1500 can have a higher switching speed and the channel structure 1700 can be better controlled.

[0066] Method M50 continues to operation S600, where the isolation layer is refilled into the re-exposed opening. Referring to Figures 9A and 9B, the isolation layer 1800 is deposited and refilled into the re-exposed opening 1400.

[0067] In some embodiments, the isolation layer 1800 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. The isolation layer 1800 may then undergo a planarization process (e.g., CMP) to remove excess portions of the isolation layer 1800 on top of the second dielectric layer 1300, thereby making the isolation layer 1800 flush with the second dielectric layer 1300. In some embodiments, the planarization process may be stopped when the second dielectric layer 1300 is exposed.

[0068] In some embodiments, the isolation layer 1800 is made of a dielectric material. In some embodiments, the isolation layer 1800 is made of a dielectric material having a low dielectric constant (low-k), such as silicon oxide (SiO2). In some embodiments, the isolation layer 1800 is configured to provide electrical isolation between the channel structures 1700.

[0069] Method M50 continues to operation S700, where a third dielectric layer and contacts are formed on the channel structure. Referring to Figures 10A and 10B, a third dielectric layer 1900 is deposited on the second dielectric layer 1300, and contacts 1910 are formed in the third dielectric layer 1900, which are electrically connected to the corresponding channel structure 1700.

[0070] First, a third dielectric layer 1900 is deposited on the second dielectric layer 1300, the word line 1500, the gate dielectric 1600, and the isolation layer 1800. In some embodiments, the third dielectric layer 1900 is used to provide electrical isolation between the word line 1500 and the bit line structure formed in subsequent steps.

[0071] The third dielectric layer 1900 is made of a dielectric material. In some embodiments, the third dielectric layer 1900 may be made of the same dielectric material as the first dielectric layer 1100 and / or the second dielectric layer 1300. In some embodiments, the third dielectric layer 1900 is made of an oxide, such as silicon dioxide (SiO2). The third dielectric layer 1900 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. In some embodiments, the vertical thickness of the third dielectric layer 1900 is less than the vertical thickness of the second dielectric layer 1300.

[0072] In some embodiments, the third dielectric layer 1900 may be patterned to form an opening. A mask pattern (not shown) may be formed on the third dielectric layer 1900. Subsequently, the third dielectric layer 1900 is etched through the mask pattern to form an opening (not shown). In some embodiments, the opening exposes the channel structure 1700.

[0073] Next, a contact 1910 can be formed in the opening. In other words, each opening is replaced by a contact 1910. In some embodiments, the contact 1910 may be located at the top of the channel structure 1700.

[0074] The contact 1910 can be planarized to make it flush with the third dielectric layer 1900. Therefore, the planarized contact 1910 can be coplanar with the third dielectric layer 1900, thus having the same top surface. That is, the top surface of the planarized contact 1910 and the top surface of the third dielectric layer 1900 can be adjacent to each other. The planarization process can be performed using a chemical mechanical polishing (CMP) process. The CMP process can be stopped when the third dielectric layer 1900 is exposed.

[0075] In some embodiments, contact 1910 is configured to provide an electrical connection between channel structure 1700 and bitline structure formed in subsequent steps. Contact 1910 is made of a conductive material. Contact 1910 may contact channel structure 1700. In some embodiments, the widths of contact 1910, channel structure 1700, and capacitor 1200 are substantially the same. In some embodiments, contact 1910, channel structure 1700, and capacitor 1200 are substantially vertically aligned. In some embodiments, contact 1910 has a square top profile.

[0076] Method M50 continues to operation S800, forming bit line structures on the third dielectric layer and the contacts. Referring to Figures 11A and 11B, bit line structures 1950 are formed on the third dielectric layer 1900 and the contacts 1910. In some embodiments, each bit line structure 1950 may extend along a second direction (e.g., the X direction), which is different from the first direction and substantially perpendicular to the extension direction of the word line 1500.

[0077] The bit line structure 1950 may be deposited on the third dielectric layer 1900 and the contact 1910. The bit line structure 1950 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD or other suitable deposition processes. In some embodiments, the bit line structure 1950 covers the contact 1910.

[0078] In some embodiments, the bit line structure 1950 is made of a conductive material. In some embodiments, the bit line structure 1950 is made of a metal. In some embodiments, the bit line structure 1950 may include metal nitrides, metal silicides, doped polycrystalline silicon, tungsten, tungsten nitride, titanium nitride, and / or combinations thereof.

[0079] Method M50 continues to operation S900, where a fourth dielectric layer and contacts are formed on the bit line structure. Referring to Figures 12A and 12B, a fourth dielectric layer 2900 and contacts 2910 are formed on the bit line structure 1950. Operation S900 is similar to operation S700, therefore similar components will use similar numbering.

[0080] First, a fourth dielectric layer 2900 is deposited on the bit line structure 1950. In some embodiments, the fourth dielectric layer 2900 provides electrical isolation between the bit line structure 1950 and the conductive material formed in subsequent steps. The fourth dielectric layer 2900 is made of a dielectric material. In some embodiments, the fourth dielectric layer 2900 and the third dielectric layer 1900 contain the same material. In some embodiments, the fourth dielectric layer 2900 is made of an oxide (e.g., silicon dioxide (SiO2)). The fourth dielectric layer 2900 can be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0081] In some embodiments, the fourth dielectric layer 2900 may be patterned to form an opening. A mask pattern (not shown) may be formed on the fourth dielectric layer 2900. Subsequently, the fourth dielectric layer 2900 is etched through the mask pattern to form the opening (not shown). In some embodiments, the opening is located above the channel structure 1700 and the contact 1910.

[0082] Next, a contact 2910 can be formed in the opening. In other words, each opening corresponds to one contact 2910. In some embodiments, the contact 2910 is located above the channel structure 1700 and the contact 1910.

[0083] The contact 2910 can be planarized to make it flush with the fourth dielectric layer 2900. Therefore, the planarized contact 2910 can be coplanar with the fourth dielectric layer 2900, thus sharing the same top surface. In other words, the top surface of the planarized contact 2910 and the top surface of the fourth dielectric layer 2900 can be adjacent to each other. The planarization process can employ a chemical mechanical polishing (CMP) process. The CMP process can be stopped when the fourth dielectric layer 2900 is exposed.

[0084] In some embodiments, contact 2910 has a square top profile. In some embodiments, contact 2910 is configured to provide an electrical connection between the underlying bitline structure 1950 and the channel structure formed in a subsequent step. Contact 2910 is made of a conductive material. Contact 2910 may contain the same material as contact 1910.

[0085] Method M50 continues to operation S1000, where a fifth dielectric layer is formed on the fourth dielectric layer and the contact. Referring to Figures 13A and 13B, a fifth dielectric layer 2300 is formed on the fourth dielectric layer 2900 and the contact 2910. Operation S1000 is similar to the formation of the second dielectric layer 1300 in operation S100, therefore similar components will be numbered similarly.

[0086] First, a fifth dielectric layer 2300 is deposited on the fourth dielectric layer 2900 and the contact 2910. The fifth dielectric layer 2300 can be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. In some embodiments, the fifth dielectric layer 2300 covers the contact 2910. The fifth dielectric layer 2300 serves to provide electrical isolation between the contact 2910 and conductive structures (e.g., channel structures) formed in subsequent steps.

[0087] The fifth dielectric layer 2300 is made of a dielectric material. In some embodiments, the fifth dielectric layer 2300 and the second dielectric layer 1300 may be made of the same material. In some embodiments, the fifth dielectric layer 2300 is made of an oxide, such as silicon dioxide (SiO2). In some embodiments, the vertical thicknesses of the second dielectric layer 1300 and the fifth dielectric layer 2300 may be substantially the same. In some embodiments, the vertical thickness of the fifth dielectric layer 2300 is greater than the vertical thickness of the fourth dielectric layer 2900.

[0088] Method M50 continues to operation S1100, where the fifth dielectric layer is patterned to expose the contacts. Referring to Figures 14A and 14B, the fifth dielectric layer 2300 can be patterned to form openings 2400 that expose the contacts 2910. Operation S1100 is similar to operation S200, therefore similar components will be numbered similarly.

[0089] First, a mask pattern (not shown) can be formed on the fifth dielectric layer 2300. Then, the fifth dielectric layer 2300 is etched through the mask pattern.

[0090] In some embodiments, operation S1100 may include a photolithography process. In some embodiments, the location of the opening 2400 may be defined by a mask pattern. For example, a mask pattern is formed in the fifth dielectric layer 2300 on a portion that does not cover or surround the contact 2910. Therefore, the portion of the fifth dielectric layer 2300 that does not cover or surround the contact 2910 is not etched during the etching process and defines the opening 2400 after the etching process. In some embodiments, the width of the opening 2400 is greater than the width of the contact 2910.

[0091] Method M50 continues to operation S1200, forming word lines and gate dielectrics along the sidewall of the opening. Referring to Figures 15A and 15B, word lines 2500 and gate dielectrics 2600 are sequentially formed along the sidewall of opening 2400. Operation S1200 is similar to operation S300, therefore similar components will use similar numbering.

[0092] In some embodiments, word line material (not shown) may be formed over an underlying structure (e.g., a fifth dielectric layer 2300, contact 2910, and a fourth dielectric layer 2900). The word line material may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. Then, an anisotropic etching process is performed on the word line material to remove the horizontal portions, leaving only the vertical portions. The remaining vertical portions are referred to as word lines 2500.

[0093] In some embodiments, the character line 2500 may extend upward from the fourth dielectric layer 2900 and along the sidewall of the opening 2400. In some embodiments, the character line 2500 is made of a conductive material. In some embodiments, the character line 2500 may include a metal. In some embodiments, the character line 2500 is made of the same material as the character line 1500. In some embodiments, the character line 2500 may include tungsten (W). In some embodiments, the character line 2500 may be used as a gate electrode to control the channel structure formed in subsequent steps. In some embodiments, the character line 2500 has a strip-shaped top profile.

[0094] In some embodiments, word line 1500 and word line 2500 above it can be used to receive the same control voltage during a write operation.

[0095] Subsequently, a gate dielectric 2600 is formed on the sidewall of the opening 2400. Specifically, a gate dielectric 2600 is formed that extends upward from the fourth dielectric layer 2900 and along the sidewall of the opening 2400.

[0096] In some embodiments, a gate dielectric material blanket (not shown) may be formed over an underlying structure (e.g., a fifth dielectric layer 2300, a contact 2910, a fourth dielectric layer 2900, and a word line 1500). The gate dielectric material blanket may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0097] Then, an anisotropic etching process is performed on the gate dielectric material blanket to remove the horizontal portion of the gate dielectric material blanket, leaving only the vertical portion of the gate dielectric material along the sidewall of opening 2400. The remaining vertical portion is called gate dielectric 2600.

[0098] In some embodiments, gate dielectric 2600 is made of a dielectric material. In some embodiments, gate dielectric 2600 is made of the same material as gate dielectric 1600. In some embodiments, gate dielectric 2600 may include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), etc. In some embodiments, gate dielectric 2600 is configured to electrically isolate word line 2500 from conductive structures (e.g., channel structures) formed in subsequent steps. In some embodiments, the width of gate dielectric 2600 is substantially the same as the width of word line 2500. In some embodiments, gate dielectric 2600 has a striped top profile.

[0099] In some embodiments, the top of the gate dielectric 2600 may be substantially flush with the top surface of the fifth dielectric layer 2300 and the word line 2500. In some embodiments, the word line 2500 and the gate dielectric 2600 do not cover the top of the contact 2910. In other words, the contact 2910 remains exposed in the opening 2400.

[0100] Method M50 continues to operation S1300, where a channel structure material is formed in the opening. Referring to Figures 16A and 16B, channel structure material 2700M is formed in opening 1400. Specifically, channel structure material 2700M is formed on contact 2910 and surrounded by gate dielectric 2600. In some embodiments, channel structure material 2700M is formed on a fifth dielectric layer 2300 and surrounded by gate dielectric 1600. Operation S1300 is similar to operation S400, therefore similar elements will use similar designations.

[0101] In some embodiments, a channel layer (not shown) may be formed to cover the opening 2400. The channel layer may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. The channel layer may then be planarized (e.g., using a CMP process) to remove excess channel layer portions on top of the fifth dielectric layer 2300 and flush the channel layer with the fifth dielectric layer 2300. In some embodiments, planarization may be stopped when the fifth dielectric layer 2300 is exposed. The remaining portion of the channel layer is referred to as channel structure material 2700M.

[0102] Method M50 continues with operation S1400, removing a portion of the channel structure material to re-expose the opening. Referring to Figures 17A and 17B, the portion of the channel structure material 2700M that does not cover the contact 2910 is removed, and the opening 2400 is re-exposed. Operation S1400 is similar to operation S500, therefore similar components will be numbered similarly.

[0103] First, a masking pattern (not shown) is formed on the fifth dielectric layer 2300, the character line 2500, the gate dielectric 2600, and the channel structure material 1700M covering the contact 2910. Subsequently, the portion of the channel structure material 2700M not covered by the masking pattern is etched, and the opening 2400 is re-exposed.

[0104] The remaining portion of the channel structure material 2700M is referred to as channel structure 2700. In some embodiments, each channel structure 2700 extends vertically from the corresponding contact 2910. In some embodiments, the vertical length of the channel structure 2700 is substantially the same as that of the character line 2500 and / or the gate dielectric 2600. In some embodiments, the channel structure 2700 may be electrically connected to the contact 2910 below. In some embodiments, the channel structure 2700 has a square top profile.

[0105] In some embodiments, channel structure 2700 may be made of the same material as channel structure 1700. In some embodiments, channel structure 2700 may comprise an oxide semiconductor (OS) material. In some embodiments, channel structure 2700 may comprise indium gallium zinc oxide (IGZO). The vertical channel structure 2700 can increase the storage cell density in semiconductor device 10.

[0106] In some embodiments, the channel structure 2700 may be wrapped by the word line 2500 through the gate dielectric 2600. In other words, the word line 2500 (which can be used as a gate electrode), the gate dielectric 2600, and the channel structure 2700 may form a transistor (e.g., access transistor 11T in FIG. 2), wherein the gate dielectric 2600 covers opposite sides of the channel structure 2700. With this configuration, the channel structure 2700 has a larger contact surface, thereby increasing the current through the gate dielectric 2600 and the word line 2500. Therefore, compared to a planar channel structure, the word line 2500 can have a higher switching speed and the channel structure 2700 can be better controlled.

[0107] Method M50 continues with operation S1500, refilling the isolation layer into the re-exposed opening. Referring to Figures 18A and 18B, the isolation layer 2800 is deposited and refilled into the re-exposed opening 2400. Operation S1500 is similar to operation S600, therefore similar components will be numbered similarly.

[0108] In some embodiments, the isolation layer 2800 may be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes. The isolation layer 2800 may then undergo a planarization process (e.g., CMP) to remove excess portions of the isolation layer 2800 on top of the fifth dielectric layer 2300, thereby making the isolation layer 2800 flush with the fifth dielectric layer 2300. In some embodiments, the planarization process may be stopped when the fifth dielectric layer 2300 is exposed.

[0109] In some embodiments, the isolation layer 2800 is made of a dielectric material. In some embodiments, the isolation layer 2800 is made of the same material as the isolation layer 1800. In some embodiments, the isolation layer 2800 is made of a dielectric material having a low dielectric constant (low-k), such as silicon oxide (SiO2). In some embodiments, the isolation layer 2800 is configured to provide electrical isolation between the channel structures 1700.

[0110] Method M50 continues to operation S1600, forming a sixth dielectric layer on the channel structure. Referring to Figures 19A and 19B, a sixth dielectric layer 2100 is deposited on the channel structure 2700.

[0111] Specifically, the sixth dielectric layer 2100 is deposited on the channel structure 2700, the fifth dielectric layer 2300, the word line 2500, the gate dielectric 2600, and the isolation layer 2800. The sixth dielectric layer 2100 can be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0112] The sixth dielectric layer 2100 is made of a dielectric material. The sixth dielectric layer 2100 may be made of a different dielectric material than the fourth dielectric layer 2900 or the fifth dielectric layer 2300. In some embodiments, the sixth dielectric layer 2100 is made of a nitride, such as silicon nitride (SiN).

[0113] In some embodiments, the sixth dielectric layer 2100 is configured to provide electrical isolation between the character line 2500 and the conductive structure to be formed in subsequent steps.

[0114] Method M50 continues to operation S1700, where the sixth dielectric layer is patterned to expose the channel structure. Referring to Figures 20A and 20B, the sixth dielectric layer 2100 is patterned to form an opening that exposes the channel structure 2700.

[0115] First, a mask pattern (not shown) is formed on the sixth dielectric layer 2100. Then, the sixth dielectric layer 2100 is etched through the mask pattern to form an opening 2150. In some embodiments, the opening 2150 exposes the top surface of the channel structure 2700.

[0116] Method M50 continues to operation S1800, where a capacitor is formed on the channel structure. Referring to Figures 21A and 21B, capacitor 2200 is formed on channel structure 2700.

[0117] Specifically, capacitors 2200 may be formed in openings 2150. In other words, each opening 2150 corresponds to one capacitor 2200. In some embodiments, capacitors 2200 are parallel to each other and may be arranged with a substantially equal spacing rule.

[0118] Capacitor 2200 may be substantially the same as capacitor 1200. That is, capacitor 2200 may include a bottom electrode, a capacitor dielectric layer above the bottom electrode, and a top electrode above the capacitor dielectric layer. In some embodiments, the bottom electrode and top electrode of capacitor 2200 may contain conductive material.

[0119] Capacitor 2200 may contain substantially the same materials as capacitor 1200. In some embodiments, the bottom electrode and top electrode may contain metals. In some embodiments, the bottom electrode and top electrode may contain titanium nitride (TiN). In some embodiments, the capacitor dielectric layer of capacitor 2200 may contain a dielectric material. The bottom electrode, capacitor dielectric layer, and top electrode of capacitor 2200 may be deposited sequentially using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0120] Method M50 continues to operation S1900, etching back the sixth dielectric layer. Referring to Figures 22A and 22B, the sixth dielectric layer is etched back 2100.

[0121] First, the sixth dielectric layer 2100 is etched back so that the top surface of the sixth dielectric layer 2100 is lower than the top surface of the capacitor 2200. Therefore, the capacitor 2200 can protrude from the top of the etched sixth dielectric layer 2100.

[0122] In some embodiments, the vertical thickness of capacitor 2200 is greater than the vertical thickness of sixth dielectric layer 2100. In some embodiments, the vertical thickness of sixth dielectric layer 2100 is less than the vertical thickness of fourth dielectric layer 2900 and / or fifth dielectric layer 2300.

[0123] In summary, this disclosure provides a method for manufacturing a structure having dual capacitors, a dual-channel structure, dual-gate dielectrics, dual word lines, and dual contacts, wherein each dual group is separated by a bit line structure. In some embodiments, each dual group (e.g., capacitors 1200 and 2200, channel structures 1700 and 2700, gate dielectrics 1600 and 2600, word lines 1500 and 2500, contacts 1910 and 2910) at least partially overlaps and has substantially the same dimensions and materials.

[0124] This dual-arrangement design helps to increase the unit capacitance (which can be increased by 2 times) and enhance signal margin.

[0125] Although this disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are also possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0126] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of this disclosure without departing from the scope or spirit of this disclosure. In view of the foregoing, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the following claims.

[0127] 10: Semiconductor devices 11: Memory Unit 11C: Storage capacitor 11T: Access Transistor 20: Character Line 30: Bit line 1100: First dielectric layer 1200: Capacitor 1300: Second dielectric layer 1400: Opening 1500: Character Line 1600: Gate Dielectric 1700: Channel Structure 1700M: Channel structural material 1800: Isolation layer 1900: Third dielectric layer 1910: Contact element 1950: Bitline Structure 2150: Opening 2100: Sixth dielectric layer 2200: Capacitor 2300: Fifth dielectric layer 2400: Opening 2500: Character Line 2600: Gate Dielectric 2700: Channel Structure 2700M: Channel structural material 2800: Isolation layer 2900: Fourth dielectric layer 2910: Contact element A-A': line M50: Method S100: Operation S200: Operation S300: Operation S400: Operation S500: Operation S600: Operation S700: Operation S800: Operation S900: Operation S1000: Operation S1100: Operation S1200: Operation S1300: Operation S1400: Operation S1500: Operation S1600: Operation S1700: Operation S1800: Operation S1900: Operation

[0128] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device, comprising: A first capacitor; A first channel structure located above the first capacitor; A first gate dielectric along one sidewall of the first channel structure; A first word line along one sidewall of the first gate dielectric; a first isolation layer adjacent to the first channel structure, wherein the first gate dielectric is in contact with one sidewall of the first isolation layer; a bit line located above the first channel structure; a second channel structure located on the bit line; a second gate dielectric along one sidewall of the second channel structure; a second word line along one sidewall of the second gate dielectric; a second isolation layer adjacent to the second channel structure, wherein the second gate dielectric is in contact with one sidewall of the second isolation layer; and a second capacitor located above the second channel structure.

2. The apparatus as claimed in claim 1, wherein the second capacitor at least partially overlaps with the first capacitor.

3. The apparatus as claimed in claim 1, wherein the second channel structure at least partially overlaps with the first channel structure.

4. The apparatus as described in claim 1, further comprising: A first contact is located between the first channel structure and the bit line, and is electrically connected to the first channel structure and the bit line; And a second contact, located between the bit line and the second channel structure, and electrically connected to the bit line and the second channel structure.

5. The apparatus as described in claim 1, further comprising: A first dielectric layer surrounds the first channel structure, wherein the first character line is located between the first dielectric layer and the first isolation layer; And a second dielectric layer surrounding the first channel structure, wherein the second character line is located between the second dielectric layer and the second isolation layer.

6. The apparatus as described in claim 1, wherein, In a top view, the first character line and the second character line extend along a first direction, and the character line extends along a second direction different from the first direction.

7. The apparatus as described in claim 1, wherein, The first channel structure and the second channel structure are made of oxide semiconductor material.

8. The apparatus as described in claim 7, wherein, Both the first channel structure and the second channel structure are made of indium gallium zinc oxide (IGZO).

9. A method for manufacturing a semiconductor device, comprising: Form a first capacitor; A first dielectric layer having a first opening is formed above the first capacitor; A first character line is formed along one side wall of the first opening; A first gate dielectric layer is formed along the first character line; a first channel structure is formed along the first gate dielectric layer and above the first capacitor; a first isolation layer is formed adjacent to the first channel structure, wherein the first isolation layer is formed along the first gate dielectric layer; a character line is formed above the first channel structure; a second dielectric layer having a second opening is formed above the first channel structure; a second character line is formed along one sidewall of the second opening; a second gate dielectric layer is formed along the second character line; a second channel structure is formed along the second gate dielectric layer and above the first channel structure; a second isolation layer is formed adjacent to the second channel structure, wherein the second isolation layer is formed along the second gate dielectric layer; and a second capacitor is formed above the second channel structure.

10. The method as described in claim 9, wherein, Forming the first channel structure includes: forming a channel material in the first opening above the first dielectric layer; and removing a portion of the channel material, leaving a remaining portion of the channel material as the first channel structure.

11. The method as described in claim 9, wherein the first character line is located between the first dielectric layer and the first isolation layer.

12. The method as described in claim 9, further comprising: Before forming the bit line, a first contact is formed above the first channel structure, wherein the first contact is electrically connected to the first channel structure and the bit line; and before forming the second channel structure, a second contact is formed on the bit line, wherein the second contact is electrically connected to the bit line and the second channel structure.

13. The method as described in claim 9, wherein, Forming the second capacitor includes: forming a dielectric layer on the second channel structure; forming an opening in the dielectric layer, wherein the opening exposes a top surface of the second channel structure; forming the second capacitor in the opening; and etching back the dielectric layer, wherein a top surface of the dielectric layer is lower than a top surface of the second capacitor.

14. The method as described in claim 9, wherein, The second capacitor is formed by at least partially overlapping the first capacitor.

15. The method as described in claim 9, wherein, The second channel structure is formed by at least partial overlap with the first channel structure.

16. The method as described in claim 9, wherein, In a top view, the first character line and the second character line extend along a first direction, and the bit line extends along a second direction different from the first direction.

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