Semiconductor device comprising spacer structure

Abstract

This application discloses a spacer structure, a semiconductor device having the spacer, and a method for manufacturing the semiconductor device having the spacer. The spacer structure includes: an inner spacer located on one side of the bit line structure, wherein the material of the inner spacer includes silicon carbide; an intermediate spacer located on the inner spacer; and an outer spacer located on the intermediate spacer.

Description

Technical Field

[0001] This disclosure relates to a spacer structure, a semiconductor device including the spacer structure, and a method for manufacturing the semiconductor device. More specifically, it relates to an isolation structure including silicon oxide, a semiconductor device having the isolation structure, and a method for manufacturing the semiconductor device including the isolation structure.

[0002] This invention application claims priority to U.S. Application No. 19 / 174,181, filed on April 9, 2025, the entire contents of which are incorporated herein by reference. Prior Technology

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demands for computing power. However, this shrinkage process also introduces many problems, and these problems are constantly increasing. Therefore, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The discussion in the preceding technical paragraphs is for background information only. The statements in the discussion in the preceding technical paragraphs are not an admission that the content disclosed in these paragraphs constitutes the prior art of this disclosure, and nothing in the discussion in the preceding technical paragraphs shall be construed as an admission that any part of this application, including the parts in the discussion in the preceding technical paragraphs, constitutes the prior art of this disclosure. Summary of the Invention

[0005] One aspect of this disclosure provides a spacer structure, comprising: an inner spacer located on one side of a bit line structure, wherein the inner spacer comprises silicon carbide; an intermediate spacer located on the inner spacer; and an outer spacer located on the intermediate spacer.

[0006] Another aspect of this disclosure provides a semiconductor device, comprising: a substrate; a bit line structure disposed on the substrate; and a spacer structure including an inner spacer compliantly disposed on one side of the bit line structure, an intermediate spacer compliantly disposed on the inner spacer, and an outer spacer compliantly disposed on the intermediate spacer. The inner spacer comprises silicon carbide.

[0007] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming a plurality of bit line contact structures in the substrate; forming a plurality of bit line structures on the plurality of bit line contact structures, wherein the plurality of bit line structures are separated by a plurality of trenches and a plurality of recesses extending downward from the plurality of trenches and adjacent to the bit line contact structures; conformally forming a first spacer material covering the plurality of bit line structures, the plurality of bit line contact structures, the plurality of trenches and the plurality of recesses; forming a plurality of fill layers to fill the plurality of recesses; conformally forming a second spacer material covering the first spacer material and the plurality of fill layers; performing a first spacer etching process to transform the first spacer material into a plurality of internal spacers and the second spacer material into a plurality of intermediate spacers; and conformally forming a plurality of external spacers on the plurality of intermediate spacers to constitute a plurality of spacer structures. The first spacer material includes silicon carbide.

[0008] Due to the semiconductor device design disclosed herein, the internal spacers formed of silicon carbide effectively protect the bit line structure during subsequent etching processes. Their strong chemical resistance helps reduce defects such as bit line leakage current, thereby improving the yield of the semiconductor device. Furthermore, the low dielectric constant of the silicon carbide internal spacers reduces parasitic capacitance between adjacent bit line structures, thereby enhancing the overall performance of the semiconductor device.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, so as to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to modify or design other structures or processes to achieve the same purpose as this disclosure. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined in the appended claims. Simple Explanation of the Diagram

[0010] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the drawings that combine the embodiments with the scope of the patent application. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased.

[0011] Figure 1 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure;

[0012] Figure 2 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of this disclosure;

[0013] Figures 3 and 4 are cross-sectional views illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 2.

[0014] Figure 5 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of this disclosure;

[0015] Figures 6 to 8 are cross-sectional views illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along cross-sections A-A' and B-B' in Figure 5.

[0016] Figure 9 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of this disclosure;

[0017] Figures 10 and 11 are cross-sectional views illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 9.

[0018] Figure 12 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of this disclosure;

[0019] Figure 13 is a cross-sectional view taken along sections A-A' and B-B' in Figure 12;

[0020] Figure 14 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of this disclosure;

[0021] Figures 15 and 16 are cross-sectional views illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 14.

[0022] Figure 17 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of this disclosure;

[0023] Figure 18 is a cross-sectional view taken along sections A-A' and B-B' in Figure 17;

[0024] Figure 19 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of this disclosure;

[0025] Figure 20 is a cross-sectional view taken along sections A-A' and B-B' in Figure 19;

[0026] Figure 21 is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of this disclosure; and

[0027] Figures 22 to 29 are cross-sectional views illustrating a portion of the manufacturing process of a semiconductor device according to an embodiment of the present disclosure, taken along cross-sections A-A' and B-B' in Figure 21. Implementation

[0028] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations described below are provided to simplify this disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature can include embodiments in which the first and second features are formed in direct contact, or embodiments in which an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and is not in itself a limitation on the relationship between the various embodiments and / or configurations discussed.

[0029] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," "upper part," or other similar terms may be used in this document to describe the relative relationship between one element or feature depicted in the diagram and another. In addition to the orientations shown in the diagram, spatially related terms are intended to cover different orientations of the element during use or operation. The element may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein can be interpreted accordingly.

[0030] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it may be directly connected to or coupled to the other component or layer, or there may be intermediate components or intermediate layers.

[0031] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one component from another. Thus, for example, the first component, first member, or first part discussed below may be referred to as the second component, second member, or second part without departing from the teachings of this disclosure.

[0032] Unless the context otherwise indicates, terms such as “identical,” “equal,” “plane,” or “coplanar” as used herein do not necessarily mean exactly the same orientation, layout, location, shape, size, quantity, or other measure when referring to orientation, layout, location, shape, size, quantity, or other measure, but are intended to cover substantially identical orientations, layouts, locations, shapes, sizes, quantities, or other measures within an acceptable range of possible variations (e.g., due to manufacturing processes). The term “substantially” may be used herein to reflect this meaning. For example, articles described as “substantially identical,” “substantially equal,” or “substantially coplanar” may be exactly the same, equal, or coplanar, or may be substantially identical, equal, or coplanar within an acceptable range of possible variations (e.g., due to manufacturing processes).

[0033] In this disclosure, semiconductor devices generally refer to devices that can operate using semiconductor properties, and electro-optic devices, light-emitting display devices, semiconductor circuits and electronic devices are all included in the category of semiconductor devices.

[0034] It should be noted that in the description disclosed herein, "above" (or "up") corresponds to the direction of the arrow in the Z direction, and "below" (or "down") corresponds to the opposite direction of the arrow in the Z direction.

[0035] Figure 1 is a flowchart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figure 2 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figures 3 and 4 are cross-sectional views illustrating a portion of the manufacturing process of the semiconductor device 1A according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 2. Figure 5 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figures 6 to 8 are cross-sectional views illustrating a portion of the manufacturing process of the semiconductor device 1A according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 5.

[0036] Referring to Figures 1 to 8, in step S11, a substrate 101 can be provided, an isolation layer 103 can be formed in the substrate 101 to define a plurality of active regions AA, a plurality of impurity regions 105 can be formed in the plurality of active regions AA, and a plurality of character line structures 510 can be formed in the substrate 101 and intersect with the plurality of active regions AA, thereby transforming the plurality of impurity regions 105 into a plurality of common source regions 105a and a plurality of drain regions 105b.

[0037] Referring to Figures 2 and 3, substrate 101 may include a main semiconductor substrate. The main semiconductor substrate may be formed of materials such as: elemental semiconductors, such as silicon or germanium; compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, other group III-V compound semiconductors or group II-VI compound semiconductors; or combinations thereof.

[0038] In some embodiments, substrate 101 may include a semiconductor-on-insulator structure comprising, from bottom to top, a handle substrate, an insulating layer, and a top semiconductor material layer. The handle substrate and the top semiconductor material layer may be formed of the same material as the aforementioned main semiconductor substrate. The insulating layer may be a crystalline or amorphous dielectric material, such as oxides and / or nitrides. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. Another example is that the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer may comprise a stack of dielectric oxides and dielectric nitrides, such as silicon oxide stacked with silicon nitride or boron nitride in any order. The insulating layer may have a thickness between about 10 nm and 200 nm. The insulating layer can eliminate leakage current between adjacent elements in substrate 101 and reduce parasitic capacitances associated with the source / drain.

[0039] It should be noted that the term "about," used to modify the amount of ingredients, components, or reactants disclosed herein, refers, for example, to numerical variations that may occur through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to unintentional errors in the measurement procedures, differences in the manufacture, source, or purity of the ingredients used to prepare the composition or to carry out the method, etc. On one hand, the term "about" means within 10% of the reported value. On another hand, the term "about" means within 5% of the reported value. And yet another hand, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0040] Referring to Figures 2 and 3, an isolation layer 103 can be formed in substrate 101. A series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on substrate 101. Photolithography processes and subsequent etching processes, such as anisotropic dry etching processes, can be performed to form trenches that penetrate the pad oxide layer, the pad nitride layer, and extend into substrate 101. An insulating material can be deposited into these trenches, followed by planarization processes, such as chemical mechanical polishing, until the top surface of substrate 101 is exposed to remove excess filler material and provide a substantially flat surface for subsequent process steps, while simultaneously forming isolation layer 103. The insulating material can be, for example, silicon oxide or other suitable insulating materials. Isolation layer 103 can define a plurality of active regions AA in substrate 101.

[0041] It should be noted that, in the description of this disclosure, the surface of the element (or feature) at its highest vertical height along the Z-axis is referred to as the top surface of this element (or feature). The surface of the element (or feature) at its lowest vertical height along the Z-axis is referred to as the bottom surface of this element (or feature).

[0042] It should be noted that each of the plurality of active regions AA may include a portion of substrate 101 and the space above that portion of substrate 101. When describing a component as being disposed on an active region AA, it means that the component is disposed on the top surface of that portion of substrate 101. When describing a component as being disposed within an active region AA, it means that the component is disposed within that portion of substrate 101; however, the top surface of the component may be flush with the top surface of that portion of substrate 101. When describing a component as being disposed above an active region AA, it means that the component is disposed above the top surface of that portion of substrate 101.

[0043] Referring to Figures 2 and 3, a plurality of impurity regions 105 can be formed in a plurality of active regions AA, respectively and correspondingly. In some embodiments, the plurality of impurity regions 105 can be formed by a placement process. That is, the plurality of impurity regions 105 can be partially transformed from the plurality of active regions AA. The dopants in the placement process can include p-type impurities (dopants) or n-type impurities (dopants). P-type impurities can be added to the intrinsic semiconductor to generate defects of valence electrons. Examples of p-type dopants (i.e., impurities) in silicon-containing substrates include, but are not limited to, boron, aluminum, gallium, and indium. N-type impurities can be added to the intrinsic semiconductor to contribute free electrons to the intrinsic semiconductor. Examples of n-type dopants (i.e., impurities) in silicon-containing substrates include, but are not limited to, antimony, arsenic, and phosphorus. In some embodiments, the dopant concentration of the plurality of impurity regions 105 can be between about 1E19 atoms / cm3 and about 1E21 atoms / cm3. After the implantation process, the plurality of impurity regions 105 can have conductivity types such as n-type or p-type.

[0044] Referring to FIG4, a bottom insulating layer 107 may be formed on the substrate 101 and the isolation layer 103. In some embodiments, the bottom insulating layer 107 may be formed of a material that is etch-selective to the substrate 101 and the isolation layer 103. In some embodiments, the bottom insulating layer 107 may be formed of materials such as silicon nitride, boron nitride, boron silicon nitride, boron phosphorus nitride, silicon boron carbide, or combinations thereof. In some embodiments, the bottom insulating layer 107 may be formed of, for example, silicon nitride. In some embodiments, the bottom insulating layer 107 may be formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0045] Referring to Figure 4, a first masking layer 711 may be formed on the bottom insulating layer 107. In some embodiments, the first masking layer 711 may be a photoresist layer and may include a pattern of a plurality of character line structures 510.

[0046] It should be noted that, for clarity, the bottom insulating layer 107 is not shown in Figure 5.

[0047] Referring to Figures 5 and 6, a first mask layer 711 can be used as a mask for etching to form a plurality of character line trenches TR in the substrate 101. In some embodiments, the plurality of character line trenches TR may have a linear cross-sectional profile and extend along the Y direction and pass through (or intersect) a plurality of impurity regions 105 in a top perspective view. For example, each impurity region 105 may intersect with two character line trenches TR. The plurality of character line trenches TR can divide the plurality of impurity regions 105 into a plurality of common source regions 105a and a plurality of drain regions 105b. For one impurity region 105, a common source region 105a can be formed between two character line trenches TR, and two drain regions 105b can be formed respectively and correspondingly between the isolation layer 103 and the two character line trenches TR.

[0048] Referring to Figure 7, a word line dielectric layer 511 can be compliantly formed on the inner surface of the word line trench TR and on the top surface of the bottom insulating layer 107. The word line dielectric layer 511 may have a U-shaped cross-sectional profile in the word line trench TR. In some embodiments, the word line dielectric layer 511 can be formed by a thermal oxidation process. For example, the word line dielectric layer 511 can be formed by oxidizing the inner surface of the word line trench TR. In some embodiments, the word line dielectric layer 511 can be formed by a deposition process, such as chemical vapor deposition or atomic layer deposition. The word line dielectric layer 511 may include a high-k material, oxide, nitride, oxynitride, or a combination thereof. In some embodiments, the word line dielectric layer 511 can be formed by radical oxidation of the pad polycrystalline silicon layer (not shown for clarity) after deposition. In some embodiments, after forming the pad silicon nitride layer (not shown for clarity), the word line dielectric layer 511 can be formed by free radical oxidation of the pad silicon nitride layer.

[0049] In some embodiments, the high dielectric constant material may include a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, the high dielectric constant material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0050] Referring to Figure 7, a plurality of bottom conductive layers 513 for character lines can be formed respectively and correspondingly on the character line dielectric layer 511 and within the plurality of character line trenches TR. In some embodiments, to form the plurality of bottom conductive layers 513 for character lines, a conductive layer (not shown for clarity) can be formed to fill the plurality of character line trenches TR, and a recessing process can be subsequently performed. The recessing process can be an etch-back process, or a planarization process and an etch-back process performed sequentially. The plurality of bottom conductive layers 513 for character lines can have a recessed shape that partially fills the plurality of character line trenches TR. That is, the top surface of the plurality of bottom conductive layers 513 for character lines can be lower than the top surface of the substrate 101.

[0051] In some embodiments, the bottom conductive layer 513 of the plurality of character lines may include a metal, a metal nitride, or a combination thereof. For example, the bottom conductive layer 513 of the plurality of character lines may be formed of titanium nitride, tungsten, or titanium nitride / tungsten. After conformally forming titanium nitride, the titanium nitride / tungsten may have a structure in which the trenches TR of the plurality of character lines are partially filled with tungsten. Titanium nitride or tungsten may be used alone in the bottom conductive layer 513 of the plurality of character lines. In some embodiments, the bottom conductive layer 513 of the plurality of character lines may be formed of conductive materials such as doped polycrystalline silicon, doped polycrystalline silicon germanium, or a combination thereof. In some embodiments, the bottom conductive layer 513 of the plurality of character lines may be formed of materials such as tungsten, aluminum, titanium, copper, similar materials, or a combination thereof.

[0052] Referring to Figure 7, a plurality of top conductive layers 515 for multiple character lines can be formed correspondingly on the bottom conductive layer 513 of multiple character lines and within the trenches TR of multiple character lines. In some embodiments, to form the top conductive layer 515 for multiple character lines, a conductive layer (not shown for clarity) can be formed to fill the trenches TR of multiple character lines, and a recessing process can be subsequently performed. The recessing process can be an etch-back process, or a planarization process and an etch-back process performed sequentially. The top conductive layer 515 for multiple character lines can have a recessed shape that partially fills the trenches TR of multiple character lines. That is, the top surface of the top conductive layer 515 for multiple character lines can be lower than the top surface of the substrate 101.

[0053] In some embodiments, the top conductive layer 515 of the plurality of character lines may include materials such as polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or combinations thereof. In some embodiments, the top conductive layer 515 of the plurality of character lines may be doped with p-type or n-type dopants. In some embodiments, doping may be performed by incorporating dopants during the deposition process used to form the conductive layer.

[0054] Referring to Figure 8, a dielectric material can be deposited, for example, by chemical vapor deposition, to completely fill the plurality of character line trenches TR and cover the top surface of the bottom insulating layer 107. A planarization process, such as chemical mechanical polishing, can be performed to provide a substantially flat surface for subsequent process steps and form the character line capping layer 517. In some embodiments, the character line capping layer 517 may include, for example, silicon nitride or other suitable dielectric materials. The character line dielectric layer 511, the plurality of character line bottom conductive layers 513, the plurality of character line top conductive layers 515, and the character line capping layer 517 together constitute a plurality of character line structures 510. The plurality of character line structures 510 may, respectively and accordingly, separate a plurality of common source regions 105a and a plurality of drain regions 105b.

[0055] Figure 9 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figures 10 and 11 are cross-sectional views illustrating a portion of the manufacturing process of semiconductor device 1A according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 9. Figure 12 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figure 13 is a cross-sectional view taken along sections A-A' and B-B' in Figure 12.

[0056] Referring to Figures 1 and 9 to 13, in step S13, a plurality of bit line contact openings OP1 can be formed to expose a plurality of common source regions 105a, and a plurality of contact isolation layers 723 can be formed to cover the sidewalls SW of the plurality of bit line contact openings OP1.

[0057] Referring to Figures 9 and 10, a plurality of bit line contact openings OP1 can be formed by a photolithography process and subsequent etching process. The bit line contact openings OP1 can penetrate the word line cover layer 517, the word line dielectric layer 511, and the bottom insulating layer 107, and extend to the substrate 101. The common source region 105a can be exposed through the bit line contact openings OP1. In some embodiments, the bit line contact openings OP1 can have a rectangular or square cross-sectional profile in the top perspective view.

[0058] Referring to Figure 11, a first insulating material 701 is compliantly formed within a plurality of bit-line contact openings OP1 and on the top surface of the word-line cover layer 517. In some embodiments, the first insulating material 701 may include, for example, a material having etch selectivity for the substrate 101. In some embodiments, the first insulating material 701 may include, for example, silicon nitride or other suitable insulating materials. In some embodiments, this first insulating material 701 may be formed by, for example, atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.

[0059] Referring to Figures 12 and 13, an etching process can be performed to remove the first insulating material 701 formed on the common source region 105a. In some embodiments, the etching process can be an anisotropic etching process. For example, the etching process can be an anisotropic dry etching process. After the etching process, the remaining first insulating material 701 located on the sidewalls SW of the plurality of bit line contact openings OP1 can be referred to as the plurality of contact isolation layers 723.

[0060] Referring to Figures 12 and 13, each of the plurality of contact isolation layers 723 may include two first portions 723a and two second portions 723b. In the top perspective view, the two first portions 723a may be parallel to each other and extend along the X direction. The two second portions 723b may be parallel to each other and extend along the Y direction. In the top perspective view, the first portions 723a and the second portions 723b together form a cross-sectional profile of a rectangular ring or a square ring.

[0061] Figure 14 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figures 15 and 16 are cross-sectional views illustrating a portion of the manufacturing process of semiconductor device 1A according to an embodiment of the present disclosure, taken along sections A-A' and B-B' in Figure 14. Figure 17 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figure 18 is a cross-sectional view taken along sections A-A' and B-B' in Figure 17.

[0062] Referring to Figures 1 and 14 to 18, in step S15, a plurality of contact isolation layers 723 may be partially removed to form a plurality of contact isolation spacers 533.

[0063] Referring to Figures 14 and 15, a plurality of hard mask layers 715 may be formed on the character line overlay layer 517 to selectively mask the first portion 723a. In some embodiments, the plurality of hard mask layers 715 may include a material having etch selectivity for both the character line overlay layer 517 and the substrate 101. In some embodiments, the plurality of hard mask layers 715 may be formed of materials such as boron nitride, boron silicon nitride, boron phosphorus nitride, silicon boron carbon nitride, or similar materials. In some alternative embodiments, the plurality of hard mask layers 715 may be photoresist layers.

[0064] Referring to Figure 16, a plurality of hard mask layers 715 can be used as masks for the etching process to selectively remove the second portion 723b. In some embodiments, the etching process can be an anisotropic etching process, such as anisotropic dry etching. The remaining first portion 723a can be referred to as contact spacer 533.

[0065] Referring to Figures 17 and 18, a plurality of rigid mask layers 715 can be removed. For each of the bitline contact openings OP1, two contact isolation spacers 533 can be provided on the sidewall SW of the bitline contact opening OP1, parallel to each other and extending along the X direction in the top perspective view. In some embodiments, the width W1 of the contact isolation spacers 533 may be substantially the same as the width W2 of the bitline contact opening OP1. In some embodiments, the width W1 of the contact isolation spacers 533 may be smaller than the width W2 of the bitline contact opening OP1. In some embodiments, the ratio of the width W1 of the contact isolation spacers 533 to the width W2 of the bitline contact opening OP1 may be between about 0.90 and 1.00 or between about 0.95 and 1.00.

[0066] Figure 19 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figure 20 is a cross-sectional view taken along sections A-A' and B-B' in Figure 19.

[0067] Referring to Figures 1, 19, and 20, in step S17, a plurality of bit line contacts 531 can be formed in a plurality of bit line contact openings OP1, thereby forming a plurality of bit line contact structures 530 together with a plurality of contact isolation spacers 533.

[0068] Referring to Figures 19 and 20, a conductive material (not shown) can be formed to completely fill the plurality of bit-line contact openings OP1. A planarization process, such as chemical mechanical polishing, can be performed until the top surface of the word-line overlay 517 is exposed to remove excess material, providing a substantially flat surface for subsequent process steps, and simultaneously forming the plurality of bit-line contacts 531. In some embodiments, the conductive material can be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof. In some embodiments, the conductive material can be formed by, for example, physical vapor deposition, chemical vapor deposition, or other suitable deposition processes.

[0069] In some embodiments, the plurality of bit line contacts 531 may have a square or rectangular cross-sectional profile in a top perspective view. In some embodiments, each of the plurality of bit line contacts 531 may include two first sides S1 and two second sides S2. The two first sides S1 may be parallel to each other and extend along the X direction. The two second sides S2 may be parallel to each other and extend along the Y direction. Two contact spacers 533 may respectively and correspondingly cover the two first sides S1. In some embodiments, the width W3 of the bit line contact 531 (the distance between the two second sides S2) may be substantially the same as the width W1 of the contact spacer 533. In some embodiments, the width W3 of the bit line contact 531 may be greater than the width W1 of the contact spacer 533. In some embodiments, the ratio of the width W1 of the contact spacer 533 to the width W3 of the bit line contact 531 may be between about 0.90 and 1.00 or between about 0.95 and 1.00.

[0070] Figure 21 is a top view illustrating a semiconductor device at an intermediate stage according to an embodiment of the present disclosure. Figures 22 to 29 are cross-sectional views illustrating a portion of the manufacturing process of semiconductor device 1A according to an embodiment of the present disclosure, taken along cross-sections A-A' and B-B' in Figure 21.

[0071] Referring to Figures 1 and 21 to 23, in step S19, a plurality of bit line structures 520 can be formed on a plurality of bit line contact structures 530. These plurality of bit line structures 520 are separated by a plurality of grooves TR1, and a plurality of grooves R1 can be formed extending from the plurality of grooves TR1 and adjacent to the plurality of bit line contact structures 530.

[0072] Referring to Figures 21 and 22, a first conductive material 731 can be formed on the character line overlay layer 517 and the plurality of bit line contact structures 530. In some embodiments, the first conductive material 731 may include, for example, doped polycrystalline silicon, doped polycrystalline germanium, doped polycrystalline silicon-germanium, or a combination thereof. In some embodiments, the dopants used for this first conductive material 731 may include boron, aluminum, gallium, indium, antimony, arsenic, or phosphorus. In some embodiments, this first conductive material 731 may be formed by, for example, chemical vapor deposition or other suitable deposition processes.

[0073] Referring to Figures 21 and 22, a second conductive material 733 can be formed on this first conductive material 731. In some embodiments, the second conductive material 733 may include, for example, titanium, nickel, platinum, tantalum, cobalt, silver, copper, aluminum, other suitable conductive materials, or combinations thereof. In some embodiments, this second conductive material 733 can be formed by, for example, physical vapor deposition, chemical vapor deposition, or other suitable deposition processes.

[0074] Referring to Figures 21 and 22, a second insulating material 707 can be formed on this second conductive material 733. In some embodiments, the second insulating material 707 may include, for example, silicon nitride or other suitable insulating materials. In some embodiments, this second insulating material 707 can be formed by, for example, chemical vapor deposition or other suitable deposition processes.

[0075] Referring to Figures 21 and 22, a second masking layer 713 can be formed on this second insulating material 707. In some embodiments, the second masking layer 713 may be a photoresist layer and may include a pattern of a plurality of bit line structures 520. In some embodiments, in a top perspective view, the pattern of the second masking layer 713 may include a plurality of linear cross-sectional profiles extending along the X direction and staggered along the Y direction.

[0076] Referring to Figure 23, a second mask layer 713 can be used as a mask for the etching process to remove portions of the second insulating material 707, the second conductive material 733, and the first conductive material 731. In some embodiments, the etching process can be an anisotropic etching process, such as an anisotropic dry etching process. After the etching process, the remaining first conductive material 731 can be referred to as the bottom conductive layer 521 of the plurality of bit lines. The remaining second conductive material 733 can be referred to as the top conductive layer 523 of the plurality of bit lines. The remaining second insulating material 707 can be referred to as the capping layer 525 of the plurality of bit lines. The bottom conductive layer 521, the top conductive layer 523, and the capping layer 525 together constitute the plurality of bit line structure 520.

[0077] The space between the plurality of bit line structures 520 can be referred to as a plurality of trenches TR1. The plurality of trenches TR1 can extend along the X direction. A plurality of recesses R1 can be formed to extend from the plurality of trenches TR1 and are configured to be adjacent to the plurality of bit line contact structures 530. Contact spacers 533 can be exposed through the plurality of recesses R1. In some embodiments, the bottom R1B of the plurality of recesses R1 can be lower than the bottom surface 530B of the bit line contact structure 530.

[0078] After the complex unit line structure 520 is formed, the second mask layer 713 can be removed by ashing or other applicable processes.

[0079] Referring to Figures 1 and 24 to 26, in step S21, a first spacer material 741 can be compliantly formed to cover a plurality of bit line structures 520 and located within a plurality of grooves R1. A plurality of filling layers 310 can be formed to fill the plurality of grooves R1. A second spacer material 743 can be compliantly formed on this first spacer material 741 and the plurality of filling layers 310. The bottom of the plurality of filling layers 310 is lower than the bottom surface 530B of the bit line contact structure 530.

[0080] Referring to Figure 24, this first spacer material 741 can be compliantly formed on the surfaces TR1S of the plurality of bit line structures 520, the plurality of trenches TR1, and the plurality of grooves R1. That is, the top surface 520TS and side edges S3 of the plurality of bit line structures 520, as well as the sidewalls 533S of the contact spacers 533, can be covered by this first spacer material 741.

[0081] In some embodiments, the first spacer material 741 may be, for example, silicon carbide. The molecular formula of silicon carbide film is commonly referred to as SiCO. This notation does not limit the bonding or chemical state of silicon (Si), oxygen (O), or carbon (C). In some embodiments, the first spacer material 741 may include other elements besides Si, O, and / or C, such as sulfur (S). In some embodiments, this first spacer material 741 may include Si-C bonds and / or Si-O bonds. In some embodiments, this first spacer material 741 may include both Si-C bonds and Si-O bonds, and may not include Si-N bonds. In addition to Si-C bonds and / or Si-O bonds, Si-S bonds may also be present. In some embodiments, the number of Si-O bonds in this first spacer material 741 may be greater than the number of Si-C bonds, with a ratio ranging from about 1:1 to about 10:1.

[0082] In some embodiments, the carbon content of the first spacer material 741, on an atomic basis, may range from about 0.1% to about 40%, about 0.5% to about 30%, about 1% to about 30%, or about 5% to about 20%. In some embodiments, the oxygen content of the first spacer material 741, on an atomic basis, may be at least about 20%, about 40%, or about 50%. In some embodiments, the oxygen content of the first spacer material 741, on an atomic basis, may range from 10% to about 70%, about 15% to about 50%, or about 20% to about 40%. In some embodiments, the silicon content of the first spacer material 741, on an atomic basis, may be up to about 50%. In some embodiments, the silicon content of the first spacer material 741, on an atomic basis, may be at least about 15%, about 20%, about 25%, or about 30%. In some embodiments, the silicon content of the first spacer material 741, on an atomic basis, may range from about 10% to about 50%, about 15% to about 40%, or about 20% to about 35%. In some embodiments, the sulfur content of the first spacer material 741, on an atomic basis, can be as high as about 40%. In some embodiments, the sulfur content of the first spacer material 741, on an atomic basis, can range from about 0.01% to about 40%, about 0.1% to about 40%, about 0.5% to about 30%, or about 1% to about 20%. In some embodiments, the sulfur content of the first spacer material 741, on an atomic basis, can be at least about 1%, about 10%, or about 20%.

[0083] In some embodiments, the first spacer material 741 may not contain a significant amount of nitrogen. In some embodiments, the nitrogen content of the first spacer material 741, on an atomic basis, may be less than about 30%, less than about 20%, less than about 15%, less than about 10%, less than about 5%, less than about 1%, or less than about 0.1%. In some embodiments, the first spacer material 741 does not contain nitrogen.

[0084] In some embodiments, the deposition of this first spacer material 741 can be performed using a plasma-enhanced atomic layer deposition (PEALD) process. The PEALD process may include at least one deposition cycle. Each cycle may begin by exposing the intermediate semiconductor device shown in FIG23 to a nitrogen-free gaseous silicon-containing precursor (referred to as the precursor step). This step allows the silicon-containing material to adsorb onto the surface of the intermediate semiconductor device.

[0085] Following exposure to the precursor, a purge gas and / or vacuum may be applied to remove any excess silicon precursor and reaction byproducts (referred to as the first purging step). Next, the surface of the intermediate semiconductor element may be exposed to a reactant generated by plasma, comprising hydrogen-based reactive substances (referred to as the reactant step). Plasma energy promotes the transformation of the adsorbed silicon material into this first spacer material 741, comprising SiCO. Similar to the precursor step, a purge gas and / or vacuum may be used to remove any excess reactants and byproducts (referred to as the second purging step).

[0086] These successive exposure and removal steps form a complete deposition cycle. To achieve the required thickness and composition of this first spacer material 741, the deposition cycle can be repeated multiple times.

[0087] In some embodiments, the silicon-containing precursor must be nitrogen-free. In some embodiments, the silicon-containing precursor may be halogen-free. In some embodiments, the silicon-containing precursor may be, for example, bis(triethoxysilyl)ethane (BTESE), 3-methoxypropyltrimethoxysilane (MPTMS), and / or (3-mercaptopropyl)trimethoxysilane. In some embodiments, more than one silicon-containing precursor may be used simultaneously or in alternating deposition cycles to optimize film properties. In some embodiments, the pulse duration of the precursor step may be between about 4 seconds and about 10 seconds.

[0088] In some embodiments, the reactants may include hydrogen, which is used to generate reactive substances via plasma. In some embodiments, the reactants may not contain any oxygen. In some embodiments, the reactants may include a low atomic percentage of oxygen (less than about 50 atomic% to less than 0.001 atomic%). In some embodiments, the reactants may not contain nitrogen. In some embodiments, the reactants may include a low atomic percentage of nitrogen (less than about 25 atomic% to less than 0.001 atomic%). In some alternative embodiments, nitrogen-containing substances may be intentionally introduced. In some embodiments, the reactive substances generated by the reactants may include hydrogen plasma, hydrogen atoms, hydrogen radicals, and / or hydrogen ions.

[0089] In some embodiments, the reactants may be, for example, substantially pure hydrogen; a mixture of hydrogen and an inert gas; or a mixture of hydrogen and nitrogen. In some embodiments, the inert gas may include helium, neon, argon, krypton, and xenon. In some embodiments, the atomic percentage of nitrogen in the hydrogen and nitrogen mixture may be less than 20%. In some embodiments, the reactants may include compounds having both N and H (e.g., NH3 and N2H4).

[0090] In some embodiments, the plasma power used to generate reactive substances from reactants may be between about 5 W and about 5000 W, or between about 100 W and about 300 W. In some embodiments, the plasma pulse duration may be between about 2 seconds and about 6 seconds, or about 4 seconds. In some embodiments, the generation of plasma or reactive substances in the reactant step may be performed remotely before the reactants contact the intermediate semiconductor element.

[0091] In some embodiments, the purge gas used for the first / second purge step may include, for example, argon, helium, and / or nitrogen. The purpose of the purge gas is to remove unreacted precursors / reactants and byproducts from the reaction chamber after each exposure step. In some embodiments, the purge time may be 0.5 seconds, 4 seconds, or 10 seconds. In some alternative embodiments, the first / second purge step may use a vacuum, which may involve evacuating the reaction chamber. In some cases, the first / second purge step may include a continuous flow of purge gas while stopping the flow of precursors or reactants, or even moving intermediate semiconductor elements to a different chamber that includes purge gas or is under vacuum.

[0092] In some embodiments, the temperature of the plasma-enhanced atomic layer deposition process may be below 200°C, 150°C, 100°C, 75°C, or 50°C. In some embodiments, the pressure of the plasma-enhanced atomic layer deposition process (e.g., for the precursor step and the reactant step) may be between about 6 Torr and about 500 Torr.

[0093] The first spacer material 741, comprising SiCO, exhibits strong chemical resistance. For example, the wet etch rate of this first spacer material 741 relative to the wet etch rate of the thermally oxidized silicon layer can be significantly less than 5, 0.3, or even 0.1. Therefore, this first spacer material 741 can effectively protect the bit line structure 520 in subsequent etching processes, thereby reducing defects such as bit line leakage current. This improves the yield of the semiconductor device 1A. Furthermore, the dielectric constant of the first spacer material 741 comprising SiCO can be less than 5, 4.5, or even 4.4, thereby reducing parasitic capacitance between adjacent bit line structures 520. This improves the performance of the semiconductor device 1A.

[0094] Referring to Figure 25, a plurality of filler layers 310 can be formed to fill a plurality of grooves R1. In some embodiments, the filler layers 310 can be formed of silicon nitride. These layers can be deposited using two consecutive deposition processes: low-pressure chemical vapor deposition (LPCVD) as a first deposition stage, followed by plasma-enhanced chemical vapor deposition (PECVD) as a second deposition stage. In some embodiments, the ratio of filler layer 310 deposited in the first stage to filler layer 310 deposited in the second stage can be approximately 20:80, 30:70, 40:60, or 50:50. In some embodiments, low-pressure chemical vapor deposition must be performed prior to plasma-enhanced chemical vapor deposition. In some embodiments, the two deposition stages can be performed within the same reaction chamber.

[0095] For the first deposition stage (e.g., low-pressure chemical vapor deposition), the process temperature can be between about 800°C and about 820°C. The process pressure can be between about 150 mTorr and 250 mTorr. Precursors may include ammonia and dichlorosilane. The ratio of ammonia to dichlorosilane can be maintained at about 4 to about 6. In some embodiments, the hydrogen content of silicon nitride formed by low-pressure chemical vapor deposition may be less than 5 atoms.

[0096] For the second deposition stage (e.g., plasma-enhanced chemical vapor deposition), the precursor may include silane, ammonia, and nitrogen. The ammonia to silane ratio may be between about 2 and about 15. The ammonia to nitrogen ratio may be between about 0.3 and about 2.3. The nitrogen to silane ratio may be between about 5.8 and about 20.8. The ammonia flow rate may be between about 9600 sccm and about 13500 sccm. The nitrogen flow rate may be between about 15000 sccm and about 28000 sccm, and the silane flow rate may be between about 1450 sccm and about 2800 sccm. The RF power supply may be between about 7 MHz and about 13.56 MHz. The process pressure may be between about 0.5 Torr and about 1.5 Torr, or between about 0.7 Torr and about 1.0 Torr. The process temperature can be between approximately 120°C and approximately 360°C, or between approximately 120°C and approximately 300°C.

[0097] The portion of the filler layer 310 formed by low-pressure chemical vapor deposition (e.g., the lower portion) is denser than the portion formed solely by plasma-enhanced chemical vapor deposition (PECVD), thus providing better protection for the layers beneath it. Furthermore, the upper portion of the filler layer 310 does not require such protection for the layers beneath it, therefore PECVD can be used to reduce the overall deposition time. It should be noted that the boundary between the filler layer 310 deposited by low-pressure chemical vapor deposition (lower portion) and the filler layer 310 deposited by plasma-enhanced chemical vapor deposition (upper portion) may not be visible, as the ratio between low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition can be adjusted to meet different requirements.

[0098] Referring to Figure 26, this second spacer material 743 can be compliantly formed on the first spacer material 741 and the plurality of filler layers 310. In some embodiments, the second spacer material 743 can be formed of materials such as silicon oxide or other suitable insulating oxides. In some embodiments, this second spacer material 743 can be formed by atomic layer deposition, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition or other suitable deposition processes.

[0099] Referring to Figures 1 and 27 to 29, in step S23, a first spacer etching process can be performed to transform the first spacer material 741 into a plurality of internal spacers 211, transform the second spacer material 743 into a plurality of intermediate spacers 213, and form a plurality of external spacers 215 on the plurality of intermediate spacers 213 to form a plurality of spacer structures 210.

[0100] Referring to Figure 27, the first spacer etching process can be an anisotropic etching process, such as an anisotropic dry etching process. During this process, a plurality of filler layers 310 can be recessed. Furthermore, the first spacer material 741 formed on the bit line capping layer 525 and located at the bottom TR1B of the trench TR1 can be removed. The remaining first spacer material 741 can be referred to as a plurality of internal spacers 211.

[0101] For the sake of brevity, clarity, and convenience, only one internal spacer 211 is described. The internal spacer 211 can be compliantly disposed on the side S3 of the bitline structure 520. It can extend downward along the contour of the groove R1 to the substrate 101 and cover the sidewall 533S of the contact spacer 533. Furthermore, the internal spacer 211 can surround the filler layer 310, while exposing its top surface 310TS to the trench TR1.

[0102] During the first spacer etching process, the second spacer material 743 formed on the bit line capping layer 525, on the plurality of fill layers 310, and at the bottom TR1B of the trench TR1 can be removed. The remaining second spacer material 743 can be referred to as the plurality of intermediate spacers 213. For the sake of brevity, clarity, and convenience, only one intermediate spacer 213 is described. In some embodiments, the intermediate spacers 213 can be compliantly disposed on the inner spacers 211.

[0103] Referring to Figure 28, a third spacer material 745 can be compliantly formed to cover a plurality of bit-line structures 520, a plurality of internal spacers 211, a plurality of intermediate spacers 213, and a plurality of filler layers 310. In some embodiments, the third spacer material 745 may be formed of materials such as silicon nitride or other suitable insulating materials. In some embodiments, the third spacer material 745 may be formed by atomic layer deposition, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0104] Referring to Figure 29, a second spacer etching process can be performed to remove the third spacer material 745 on the bit line capping layer 525 and located at the bottom TR1B of the trench TR1. The remaining third spacer material 745 can be referred to as a plurality of outer spacers 215. The plurality of outer spacers 215 can be respectively and correspondingly conformally disposed on a plurality of intermediate spacers 213. The plurality of outer spacers 215, the plurality of intermediate spacers 213, and the plurality of inner spacers 211 together constitute a plurality of spacer structures 210.

[0105] The plurality of internal spacers 211 formed from silicon carbide provide enhanced protection for the plurality of bit-line structures 520 due to their excellent chemical resistance. This helps reduce defects in the semiconductor device 1A and improves its yield. Furthermore, the plurality of filler layers 310 formed by a two-stage deposition process combining low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition can provide better protection for the underlying layers without affecting manufacturing efficiency. This, in turn, improves the yield and manufacturing efficiency of the semiconductor device 1A.

[0106] One aspect of this disclosure provides a spacer structure, comprising: an inner spacer located on one side of a bit line structure, wherein the inner spacer comprises silicon carbide; an intermediate spacer located on the inner spacer; and an outer spacer located on the intermediate spacer.

[0107] Another aspect of this disclosure provides a semiconductor device, comprising: a substrate; a bit line structure disposed on the substrate; and a spacer structure including an inner spacer compliantly disposed on one side of the bit line structure, an intermediate spacer compliantly disposed on the inner spacer, and an outer spacer compliantly disposed on the intermediate spacer. The inner spacer comprises silicon carbide.

[0108] Another aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming a plurality of bit line contact structures in the substrate; forming a plurality of bit line structures on the plurality of bit line contact structures, wherein the plurality of bit line structures are separated by a plurality of trenches and a plurality of recesses extending downward from the plurality of trenches and adjacent to the bit line contact structures; conformally forming a first spacer material covering the plurality of bit line structures, the plurality of bit line contact structures, the plurality of trenches and the plurality of recesses; forming a plurality of fill layers to fill the plurality of recesses; conformally forming a second spacer material covering the first spacer material and the plurality of fill layers; performing a first spacer etching process to transform the first spacer material into a plurality of internal spacers and the second spacer material into a plurality of intermediate spacers; and conformally forming a plurality of external spacers on the plurality of intermediate spacers to constitute a plurality of spacer structures. The first spacer material includes silicon carbide.

[0109] Due to the design of the semiconductor device disclosed herein, the internal spacer 211 formed of silicon oxide can effectively protect the bit line structure 520 during subsequent etching processes. Its strong chemical resistance helps reduce defects such as bit line leakage current, thereby improving the yield of the semiconductor device 1A. In addition, the low dielectric constant of the silicon oxide internal spacer 211 can reduce the parasitic capacitance between adjacent bit line structures 520, thereby improving the overall performance of the semiconductor device 1A.

[0110] While this disclosure and its advantages have been detailed, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and many of the processes described above can be replaced by other processes or combinations thereof.

[0111] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure herein that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of this application.

[0112] 1A: Semiconductor components 10: Method 101:Substrate 103: Isolation layer 105: Impurity Zone 105a: Common source pole region 105b: Drainage Zone 107: Bottom Insulation Layer 210: Spacer Structure 211: Internal spacers 213: Intermediate spacer 215: External spacers 310: Fill layer 310TS: Top Surface 510: Character Line Structure 511: Character line dielectric layer 513: Conductive layer at the bottom of the character line 515: Top conductive layer of character line 517: Character Line Overlay 520: Bitline Structure 520TS: Top Surface 521: Bottom conductive layer of bit line 523: Top conductive layer of bit line 525: Bitline overlay 530: Bit line contact structure 530B: Bottom surface 531: Bit line contact 533: Contact isolation partition 533S: Sidewall 701: First Insulation Material 707: Second Insulation Material 711: First Cover Layer 713: Second Cover Layer 715: Rigid Coverage Layer 723: Contact isolation layer 723a: Part 1 723b: Part Two 731: First Conductive Material 733: Second conductive material 741: First spacer material 743: Second spacer material 745: Third spacer material AA: Active Zone OP1: Bit line contact opening R1: Groove R1B: Bottom R1S: Surface S1: First side S2: Second side S3: Side S11: Steps S13: Steps S15: Steps S17: Steps S19: Steps S21: Steps S23: Steps SW: Sidewall TR: Character line groove TR1: Trench TR1B: Bottom TR1S: Surface W1: Width W2: Width W3: Width

Claims

1. A semiconductor device, comprising: One substrate; A single-line structure is located on the substrate; A spacer structure includes: an internal spacer compliantly located on one side of the bit line structure; An intermediate spacer compliantly located on the inner spacer; and an outer spacer compliantly located on the intermediate spacer, wherein the inner spacer comprises silicon carbide; a bit line contact structure located between the bit line structure and the substrate, wherein the inner spacer extends downward to the substrate and covers one sidewall of the bit line contact structure; and a filler layer adjacent to the bit line contact structure, wherein a bottom of the filler layer is lower than a bottom surface of the bit line contact structure.

2. The semiconductor device as claimed in claim 1, wherein the internal spacer is located between the bit line contact structure and the fill layer.

3. The semiconductor device as claimed in claim 2, wherein the carbon content of the internal spacer ranges from about 0.1% to about 40% on an atomic basis.

4. The semiconductor device as claimed in claim 2, wherein the oxygen content of the internal spacer is at least about 20% on an atomic basis.

5. The semiconductor device as claimed in claim 2, wherein the silicon content of the internal spacer is at least about 15% on an atomic basis.

6. The semiconductor element as claimed in claim 2, wherein the intermediate spacer comprises silicon oxide.

7. The semiconductor device as claimed in claim 2, wherein the external spacer comprises silicon nitride.

8. The semiconductor element as claimed in claim 2, wherein the bit line contact structure comprises: A bit line contact is located between the bit line structure and the substrate; And a contact isolation spacer located between the internal spacer and the bit line contact.

9. The semiconductor element as claimed in claim 8, wherein the material of the bit line contact includes tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides, metal nitrides, transition metal aluminum compounds, or combinations thereof.

10. The semiconductor element as claimed in claim 8, wherein the material of the contact spacer comprises silicon nitride.

11. The semiconductor device as claimed in claim 2, wherein the material of the filling layer comprises silicon nitride.

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