Wafer Scale 3D Stacked AI Inference Engine

The wafer-scale silicon substrate with 3D stacked logic and memory interconnected by on-silicon fabrics addresses latency and power challenges in AI inference systems, enabling efficient inference of large transformer models within a single silicon domain.

US20260198385A1Pending Publication Date: 2026-07-09SILVEBROOK KIA
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Patent Information

Authority / Receiving Office
US · United States
Patent Type
Applications(United States)
Current Assignee / Owner
SILVEBROOK KIA
Filing Date
2025-12-29
Publication Date
2026-07-09

AI Technical Summary

Technical Problem

Conventional AI inference systems face challenges with multi-hop latency, power overhead, thermal management, and complex interconnects due to distributing computation across multiple chips and boards, which become significant as model sizes grow, particularly for transformer models.

Method used

A wafer-scale silicon substrate with 3D stacking of logic and memory interconnected by on-silicon fabrics, utilizing systolic arrays, hybrid-bonded memory stacks, and integrated power and cooling systems to maintain native silicon distances and reduce latency.

Benefits of technology

The solution enables efficient inference of large transformer models within a single silicon domain, reducing latency and power consumption by orders of magnitude, while maintaining high performance and scalability.

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Abstract

A wafer-scale 3D stacked inference engine integrates stacked logic die and stacked memory die on a unitary silicon substrate with an on-silicon interconnect fabric to execute neural-network models using low-precision arithmetic. Compute chiplets and high-bandwidth memory stacks are coupled across reticle-stitched interconnect regions that form a single all-silicon domain. A redistribution-layer network provides ultra-short-reach links and express lanes for inter-region data movement while a control subsystem issues tile-level schedules that overlap compute and transfer. Wafer-integrated power delivery and microchannel cooling support high density operation, and test access structures enable loopback and boundary-scan verification of stacked connections. The architecture reduces multi-hop latency, improves energy efficiency, and allows large models to be inferenced at wafer scale without leaving the all-silicon domain.
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