Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a display region (100); the display region (100) comprises a base (101), a driving circuit layer (102) and a light-emitting structure layer (103); the driving circuit layer (102) comprises a plurality of circuit units, data signal lines (60), data connecting lines (70), low-voltage power supply lines (80), and power supply traces (90); the light-emitting structure layer (103) comprises a plurality of light-emitting devices; the circuit units comprise pixel driving circuits; the data signal lines (60) are configured to provide data signals for the pixel driving circuits; the low-voltage power supply lines (80) are configured to continuously provide low power supply voltage signals for the light-emitting devices; the data connecting lines (70) are connected to the data signal lines (60); and the power supply traces (90) are connected to the low-voltage power supply lines (80).

Description

Display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 15, 2022, with application number 202210670468.6 and invention name “Display Substrate and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and specifically to a display substrate and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] On the one hand, the present disclosure provides a display substrate, including a display area, wherein the display area includes a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, the driving circuit layer includes multiple circuit units, multiple data signal lines, multiple data connection lines, multiple low-voltage power lines and multiple power lines, the light-emitting structure layer includes multiple light-emitting devices, the circuit unit includes a pixel driving circuit, the data signal line is configured to provide a data signal to the pixel driving circuit, and the low-voltage power line is configured to continuously provide a low power voltage signal to the light-emitting device; the data connection line is connected to the data signal line, and the power line is connected to the low-voltage power line.

[0007] In an exemplary embodiment, the data connection line includes a first connection line extending along a first direction and a second connection line extending along a second direction, the first connection line is connected to the second connection line, the power line includes a first power line extending along the first direction and a second power line extending along the second direction, the first power line is connected to the second power line, and the first direction and the second direction intersect; on a plane parallel to the substrate, the display area includes at least a first area where the first connection line is provided, at least one circuit unit in the first area includes the first connection line, the first power line and the second power line, the data signal line and the low-voltage power line are shaped like lines extending along the second direction, the first connection line is connected to the data signal line, the second power line is provided between the low-voltage power line and the data signal line, and the second power line is connected to the low-voltage power line.

[0008] In an exemplary embodiment, the driving circuit layer includes a plurality of conductive layers sequentially arranged on a substrate; the first connecting line and the second connecting line are arranged in the same conductive layer, and the first connecting line and the data signal line are arranged in different conductive layers; in at least one circuit unit of the first area, the first connecting line is connected to the data signal line through a first connecting hole.

[0009] In an exemplary embodiment, the driving circuit layer includes a plurality of conductive layers arranged in sequence on a substrate; the first power line and the second power line are arranged in the same conductive layer, and the second power line and the low-voltage power line are arranged in different conductive layers; in at least one circuit unit of the first area, the second power line is connected to the low-voltage power line through a second connection hole.

[0010] In an exemplary embodiment, at least one circuit unit in the first area further includes a power connection electrode, which is arranged on a side of the second power line away from the data signal line and is connected to the second power line. The orthographic projection of the power connection electrode on the substrate at least partially overlaps with the orthographic projection of the low-voltage power line on the substrate, and the power connection electrode is connected to the low-voltage power line through a second connection hole.

[0011] In an exemplary embodiment, the first connection lines in the circuit units adjacent to each other in the first direction are connected to each other, and the first power supply lines in the circuit units adjacent to each other in the first direction are connected to each other.

[0012] In an exemplary embodiment, in the first region, the second power traces in the circuit units adjacent to each other in the second direction are arranged at intervals, and the first connection line is arranged between the second power traces adjacent to each other in the second direction.

[0013] In an exemplary embodiment, at least one circuit unit in the first area further includes a second compensation line extending along the second direction, the second compensation line is arranged on a side of the second power line away from the data signal line, the second compensation line is connected to the first power line, the second compensation lines in the circuit units adjacent to each other in the second direction are arranged at intervals, and the first connecting line is arranged between the second compensation lines adjacent to each other in the second direction.

[0014] In an exemplary embodiment, on a plane parallel to the substrate, the display area further includes a second area where the second connecting line is provided, at least one circuit unit in the second area includes the second connecting line, and the second connecting lines in the circuit units adjacent to each other in the second direction are connected to each other.

[0015] In an exemplary embodiment, at least one circuit unit of the second area includes two second connecting lines, the two second connecting lines include a first side connecting line and a second side connecting line, the first side connecting line is arranged between the low-voltage power line and the data signal line, and the second side connecting line is arranged on a side of the low-voltage power line away from the data signal line.

[0016] In an exemplary embodiment, at least one circuit unit of the second area further includes a dummy connecting electrode, which is arranged on a side of the second side connecting line close to the first side connecting line and is connected to the second side connecting line, and the orthographic projection of the dummy connecting electrode on the substrate at least partially overlaps with the orthographic projection of the low-voltage power line on the substrate.

[0017] In an exemplary embodiment, in at least one cell column including circuit units of the first area and circuit units of the second area, the second power supply line of the first area and the first side connection line of the second area are located on the same straight line extending along the second direction, the second compensation line of the first area and the second side connection line of the second area are located on the same straight line extending along the second direction, and the power supply connection electrode of the first area and the dummy connection electrode of the second area are located on the same straight line extending along the second direction; in at least one cell row including circuit units of the first area and circuit units of the second area, the power supply connection electrode of the first area and the dummy connection electrode of the second area are located on the same straight line extending along the first direction.

[0018] In an exemplary embodiment, at least one circuit unit of the second area further includes at least two first compensation lines extending along the first direction, the at least two first compensation lines including at least one first side compensation line and at least one second side compensation line, a first end of the first side compensation line is connected to the first side connecting line, a second end of the first side compensation line extends in a direction close to the second side connecting line, a first end of the second side compensation line is connected to the second side connecting line, and a second end of the second side compensation line extends in a direction close to the first side connecting line.

[0019] In an exemplary embodiment, in at least one unit row including circuit units of the first area and circuit units of the second area, the first power supply line of the first area and the first side compensation line of the second area are located on the same straight line extending along the first direction, and the first connection line of the first area and the second side compensation line of the second area are located on the same straight line extending along the first direction.

[0020] In an exemplary embodiment, on a plane parallel to the substrate, the display area further includes a third area that does not overlap with the orthographic projections of the first connecting line and the second connecting line on the substrate, at least one circuit unit in the third area includes the first power line and the second power line, and the second power line is connected to the low-voltage power line through a second connecting hole.

[0021] In an exemplary embodiment, the second power line is arranged between the low-voltage power line and the data signal line, and at least one circuit unit in the third area further includes a power connection electrode, which is arranged on a side of the second power line away from the data signal line and is connected to the second power line. The orthographic projection of the power connection electrode on the substrate at least partially overlaps with the orthographic projection of the low-voltage power line on the substrate, and the power connection electrode is connected to the low-voltage power line through the second connection hole.

[0022] In an exemplary embodiment, the first power supply traces in the circuit units adjacent to each other in the first direction are connected to each other, and the second power supply traces in the circuit units adjacent to each other in the second direction are connected to each other.

[0023] In an exemplary embodiment, at least one circuit unit in the third area further includes a first compensation line extending along the first direction and a second compensation line extending along the second direction, the first compensation lines in the circuit units adjacent to each other in the first direction are connected to each other, the second compensation lines in the circuit units adjacent to each other in the second direction are connected to each other, the first compensation line is connected to the second power line, the second compensation line is connected to the first power line, and the first compensation line is connected to the second compensation line.

[0024] In an exemplary embodiment, in at least one cell row including circuit cells of the first region and circuit cells of the third region, the first connecting line of the first region and the first compensation line of the third region are located on the same straight line extending along the first direction; and in at least one cell column including circuit cells of the first region and circuit cells of the third region, the second compensation line of the first region and the second compensation line of the third region are located on the same straight line extending along the second direction.

[0025] In an exemplary embodiment, on a plane parallel to the substrate, the display area further includes: a second area where the second connecting line is provided, and a third area that does not overlap with the orthographic projections of the first connecting line and the second connecting line on the substrate; in at least one unit row including the circuit unit of the first area, the circuit unit of the second area, and the circuit unit of the third area, the first power supply line of the first area, the first side compensation line of the first compensation line of the second area, and the first power supply line of the third area are located on the same straight line extending along the first direction, the first connecting line of the first area, the second side compensation line of the first compensation line of the second area, and the first compensation line of the third area are located on the same straight line extending along the first direction, and the power connection electrode of the first area, the second area, and the first compensation line of the third area are located on the same straight line extending along the first direction. The dummy connection electrode of the domain and the power connection electrode of the third area are located on the same straight line extending along the first direction; in at least one unit column including the circuit unit of the first area, the circuit unit of the second area and the circuit unit of the third area, the second power routing of the first area, the first side connection line of the second connection line of the second area and the second power routing of the third area are located on the same straight line extending along the second direction, the second compensation line of the first area, the second side connection line of the second connection line of the second area and the second compensation line of the third area are located on the same straight line extending along the second direction, and the power connection electrode of the first area, the dummy connection electrode of the second area and the power connection electrode of the third area are located on the same straight line extending along the second direction.

[0026] In an exemplary embodiment, the display substrate further includes a binding area located on one side of the display area in the second direction, the binding area including at least a binding lead, a first power connection line, and a first power pin, the first end of the first power connection line being connected to the low-voltage power line through a via, the second end of the second power connection line extending in a direction away from the display area and connected to the first power pin, and the first power pin being connected to the binding lead through a via.

[0027] In an exemplary embodiment, the display substrate further includes an upper frame area located on the opposite side of the second direction of the display area, the upper frame area includes at least an upper frame lead, a second power connection bar, a second power connection line and a second power pin, the first end of the second power connection bar is connected to the low-voltage power line through a via, the second end of the second power connection bar is connected to the first end of the second power connection line, the second end of the second power connection line extends in a direction away from the display area and is connected to the second power pin, and the second power pin is connected to the upper frame lead through a via.

[0028] In an exemplary embodiment, the display substrate further includes a side frame area located on one or both sides of the first direction of the display area, the side frame area including at least a side frame lead, a third power connection line and a third power pin, the first end of the third power connection line is connected to the power line through a via, the second end of the third power connection line extends in a direction away from the display area and is connected to the third power pin, and the third power pin is connected to the side frame lead through a via.

[0029] In an exemplary embodiment, the driving circuit layer further includes a plurality of circuit units, each of which includes a pixel driving circuit, and each of which includes at least a storage capacitor and a plurality of transistors. In a plane perpendicular to the display substrate, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, which are sequentially arranged on a base, wherein the semiconductor layer includes at least an active layer of a plurality of transistors, the first conductive layer includes at least gate electrodes of a plurality of transistors and a first plate of a storage capacitor, the second conductive layer includes at least a second plate of a storage capacitor, the third conductive layer includes at least a first electrode and a second electrode of a plurality of transistors, the fourth conductive layer includes at least the data signal line and the low-voltage power line, and the fifth conductive layer includes at least the data connection line and the power line.

[0030] In an exemplary embodiment, the third conductive layer also includes a first power line, which is configured to continuously provide a high power voltage signal to the pixel driving circuit, the orthographic projection of the low-voltage power line on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate, and has a first overlapping area, the orthographic projection of the first power line on the substrate has a first area, and the first overlapping area is greater than 0.8*the first area.

[0031] In an exemplary embodiment, the second conductive layer further includes a second initial signal line, which is configured to provide a second initial signal to the pixel driving circuit, and the orthographic projection of a first data connection line on the substrate at least partially overlaps with the orthographic projection of the second initial signal line on the substrate and has a second overlapping area, the orthographic projection of the first connection line on the substrate has a second area, and the second overlapping area is greater than 0.8*the second area.

[0032] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0033] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0035] FIG1 is a schematic structural diagram of a display device;

[0036] FIG2 is a schematic structural diagram of a display substrate;

[0037] FIG3 is a schematic diagram of a planar structure of a display area in a display substrate;

[0038] FIG4 is a schematic diagram of a cross-sectional structure of a display area in a display substrate;

[0039] FIG5 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0040] FIG6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0041] FIG7 is a schematic diagram of an arrangement of data connection lines according to an exemplary embodiment of the present disclosure;

[0042] FIG8 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0043] FIG9 is a schematic diagram showing the arrangement of data connection lines and power lines according to an exemplary embodiment of the present disclosure;

[0044] FIG10 is a schematic diagram of partitioning of a display area according to an exemplary embodiment of the present disclosure;

[0045] 11a to 11c are schematic structural diagrams of three regions of an exemplary embodiment of the present disclosure;

[0046] FIG12 is a schematic diagram of a semiconductor layer pattern formed according to an embodiment of the present disclosure;

[0047] 13a and 13b are schematic diagrams of an embodiment of the present disclosure after forming a first conductive layer pattern;

[0048] 14a and 14b are schematic diagrams of an embodiment of the present disclosure after forming a second conductive layer pattern;

[0049] FIG15 is a schematic diagram of an embodiment of the present disclosure after forming a fourth insulating layer pattern;

[0050] 16a and 16b are schematic diagrams of an embodiment of the present disclosure after forming a third conductive layer pattern;

[0051] FIG17 is a schematic diagram of an embodiment of the present disclosure after forming a first planar layer pattern;

[0052] 18a to 18d are schematic diagrams of an embodiment of the present disclosure after forming a fourth conductive layer pattern;

[0053] 19a to 19c are schematic diagrams of an embodiment of the present disclosure after forming a second planarization layer pattern;

[0054] 20a to 20f are schematic diagrams of an embodiment of the present disclosure after forming a fifth conductive layer pattern;

[0055] 21a to 21c are schematic diagrams of an embodiment of the present disclosure after forming a third planarization layer pattern;

[0056] 22a to 22d are schematic diagrams of an embodiment of the present disclosure after forming an anode conductive layer pattern;

[0057] FIG23 is a schematic diagram of a planar structure of a power supply line according to an exemplary embodiment of the present disclosure;

[0058] FIG24 is a schematic diagram of a connection between a power supply line and a binding wire according to an exemplary embodiment of the present disclosure;

[0059] FIG25 is a schematic diagram of a connection between a power supply line and an upper frame lead according to an exemplary embodiment of the present disclosure;

[0060] FIG26 is a schematic diagram of a connection between a power supply line and a side frame lead according to an exemplary embodiment of the present disclosure.

[0061] Description of the accompanying drawings:

[0062] 11—first active layer; 12—second active layer; 13—third active layer;

[0063] 14—fourth active layer; 15—fifth active layer; 16—sixth active layer;

[0064] 17—seventh active layer; 21—first scanning signal line; 21-1—gate block;

[0065] 22—second scanning signal line; 23—light emitting control line; 24—first electrode plate;

[0066] 31—first initial signal line; 32—second initial signal line; 33—second electrode plate;

[0067] 34—plate connecting wire; 35—shielding electrode; 36—opening;

[0068] 41—first connecting electrode; 42—second connecting electrode; 43—third connecting electrode;

[0069] 44—fourth connecting electrode; 45—fifth connecting electrode; 46—first power line;

[0070] 47—initial connection line; 51—first anode connection electrode; 53—second anode connection electrode;

[0071] 60—data signal line; 61—data connection electrode; 70—data connection line;

[0072] 71—first connecting line; 72—second connecting line; 73—dummy connecting electrode;

[0073] 80—Second power line; 90—Power line; 91—First power line;

[0074] 92—Second power supply wiring; 93—Power supply connection electrode; 100—Display area;

[0075] 100A—first area; 100B—second area; 100C—third area;

[0076] 101—substrate; 102—driving circuit layer; 103—light-emitting structure layer;

[0077] 104—encapsulation structure layer; 110—first compensation line; 120—second compensation line;

[0078] 200—Binding area; 201—Lead area; 210—Lead wire;

[0079] 300—frame area; 301—anode; 302—pixel definition layer;

[0080] 303—organic light-emitting layer; 304—cathode; 310—upper frame region;

[0081] 320—side frame area; 401—first encapsulation layer; 402—second encapsulation layer;

[0082] 403 — third packaging layer; 510 — binding wire; 511 — first power connection line;

[0083] 512—first power pin; 520—upper frame lead; 521—second power connection bar;

[0084] 522—Second power connection line; 523—Second power pin; 530—Side frame lead;

[0085] 531—third power connection line; 532—third power pin. DETAILED DESCRIPTION

[0086] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0087] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0088] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0089] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0090] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0091] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0092] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0093] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0094] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0095] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0096] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0097] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0098] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include at least a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a pixel row basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register and may generate an emission signal in a manner such that an emission stop signal provided in the form of an off-level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal. o may be a natural number.

[0099] Figure 2 is a schematic diagram of the structure of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a border area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area including a plurality of sub-pixels Pxij that form a pixel array. The plurality of sub-pixels Pxij are configured to display dynamic or still images. The display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being curled, bent, folded, or rolled.

[0100] In an exemplary embodiment, the binding area 200 may include a fan-out area, a bending area, a driver chip area, and a binding pin area arranged in sequence along a direction away from the display area. The fan-out area is connected to the display area 100 and includes at least a data fan-out line. The plurality of data fan-out lines are configured to connect the data signal lines of the display area in a fan-out routing manner. The bending area is connected to the fan-out area and may include a composite insulating layer provided with a groove, which is configured to bend the binding area to the back of the display area. The driver chip area may include an integrated circuit (IC), which is configured to be connected to the plurality of data fan-out lines. The binding pin area may include a binding pad, which is configured to be bound and connected to an external flexible printed circuit (FPC).

[0101] In an exemplary embodiment, the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100. The circuit area is connected to the display area 100 and may include at least a gate drive circuit, which is connected to the first scan line, the second scan line, and the light-emitting control line of the pixel drive circuit in the display area 100. The power line area is connected to the circuit area and may include at least a frame power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100. The crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulating layer. The cutting area is connected to the crack dam area and may include at least a cutting groove provided on the composite insulating layer. The cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment can cut along the cutting groove respectively.

[0102] In an exemplary embodiment, the fan-out area in the binding area 200 and the power line area in the border area 300 may be provided with a first isolation dam and a second isolation dam, and the first isolation dam and the second isolation dam may extend in a direction parallel to the edge of the display area to form a ring structure surrounding the display area 100, and the edge of the display area is the edge of one side of the display area binding area or the border area.

[0103] FIG3 is a schematic diagram of a planar structure of a display area in a display substrate. As shown in FIG3 , the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, and a third sub-pixel P3 and a fourth sub-pixel P4 that emit a third color light. Each sub-pixel may include a circuit unit and a light-emitting device. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0104] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) that emit green light. In an exemplary embodiment, the sub-pixels may be rectangular, rhombus, pentagonal, or hexagonal, and the four sub-pixels may be arranged in a diamond shape to form an RGBG pixel arrangement. In other exemplary embodiments, the four sub-pixels may be arranged horizontally, vertically, or in a square, etc., which is not limited in this disclosure.

[0105] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0106] Figure 4 is a schematic cross-sectional view of the display region of a display substrate, illustrating the structure of four sub-pixels within the display region. As shown in Figure 4, in a plane perpendicular to the display substrate, the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the drive circuit layer 102 facing away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 facing away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch-sensitive structure layer, which is not limited in this disclosure.

[0107] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of multiple transistors and a storage capacitor. The light-emitting structure layer 103 of each sub-pixel may include at least an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the pixel driving circuit, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303. The organic light-emitting layer 303 emits light of a corresponding color under the drive of the anode 301 and the cathode 304. The encapsulation structure layer 104 may include a stacked first encapsulation layer 401, a second encapsulation layer 402 and a third encapsulation layer 403. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, and the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403 to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0108] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer that is connected together, and the emissive layers of adjacent sub-pixels may have a small amount of overlap or may be isolated from each other.

[0109] Figure 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Figure 5 is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in Figure 5, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 8 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emitting signal line E, first initial signal line INIT1, second initial signal line INIT2, first power line VDD and second power line VSS).

[0110] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the second node N2 is respectively connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.

[0111] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0112] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and the second electrode of the first transistor is connected to the second node N2. When an on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits a first initialization voltage to the control electrode of the third transistor T3, thereby initializing the charge amount of the control electrode of the third transistor T3.

[0113] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0114] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the control electrode and the first electrode.

[0115] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0116] The control electrode of the fifth transistor T5 is connected to the light-emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a drive current path between the first power line VDD and the second power line VSS, causing the light-emitting device to emit light.

[0117] The control electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When the on-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transmits the second initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0118] In an exemplary embodiment, the light-emitting device can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer and a second electrode (cathode), or can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer and a second electrode (cathode).

[0119] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a continuously provided low level signal, and the signal of the first power line VDD is a continuously provided high level signal.

[0120] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0121] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, can leverage the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0122] In an exemplary embodiment, taking the case where the first transistor T1 to the seventh transistor T7 are all P-type transistors, the operation process of the pixel driving circuit may include:

[0123] The first phase A1, known as the reset phase, is characterized by a low-level signal on the second scan signal line S2, and a high-level signal on the first scan signal line S1 and the light-emitting signal line E. The low-level signal on the second scan signal line S2 turns on the first transistor T1 and the seventh transistor T7. Turning on the first transistor T1 allows the first initial voltage on the first initial signal line INIT1 to be supplied to the second node N2, initializing the storage capacitor C and clearing the existing data voltage in the storage capacitor. Turning on the seventh transistor T7 allows the second initial voltage on the second initial signal line INIT2 to be supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage within it, completing initialization and ensuring that the OLED does not emit light. The high-level signals on the first scan signal line S1 and the light-emitting signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0124] In the second phase A2, also known as the data writing phase or threshold compensation phase, the signal on the first scan signal line S1 is a low-level signal, the signals on the second scan signal line S2 and the light-emitting signal line E are high-level signals, and the data signal line D outputs a data voltage. During this phase, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The low-level signal on the first scan signal line S1 turns on the second transistor T2 and the fourth transistor T4. The conduction of the second transistor T2 and the fourth transistor T4 causes the data voltage output by the data signal line D to be provided to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the second end of the storage capacitor C (the second node N2) is Vd-|Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. The high-level signal on the second scan signal line S2 turns off the first transistor T1. The signal of the light emitting signal line E is a high level signal, which turns off the fifth transistor T5 and the sixth transistor T6.

[0125] In the third phase A3, known as the light-emitting phase, the signal on the light-emitting signal line E is a low-level signal, while the signals on the first scan signal line S1 and the second scan signal line S2 are high-level signals. The low-level signal on the light-emitting signal line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0126] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0127] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0128] With the development of OLED display technology, consumers have higher and higher requirements for the display effects of display products. Extremely narrow bezels have become a new trend in the development of display products. Therefore, the narrowing of the bezel or even the design of no bezel has received more and more attention in the design of OLED display products. In one display substrate, the binding area usually includes a fan-out area, a bending area, a driver chip area and a binding pin area arranged in sequence along the direction away from the display area. Because the width of the binding area is smaller than the width of the display area, the signal lines of the integrated circuit and the binding pad in the binding area need to pass through the fan-out area in a fan-out routing manner to be introduced into the wider display area. The greater the width difference between the display area and the binding area, the more oblique fan-out lines there are in the fan-shaped area, and the greater the distance between the driver chip area and the display area. Therefore, the fan-shaped area occupies a larger space, resulting in greater difficulty in narrowing the design of the lower bezel. The lower bezel has always been maintained at about 2.0mm. In another display substrate, power leads are usually provided in the binding area and the bezel area. The power leads are configured to transmit low-voltage power signals. In order to reduce the voltage drop of the low-voltage power signals, the width of the power leads is larger, resulting in a wider bezel of the display device.

[0129] The exemplary embodiments of the present disclosure provide a display substrate that utilizes a fanout in AA (FIAA) structure. Multiple data lines connect to corresponding data signal lines in the display area at one end, while the other ends extend to a bonding area and connect to corresponding integrated circuits in the bonding area. Because fan-shaped diagonal lines are not required in the bonding area, the width of the fanout area is reduced, effectively reducing the width of the bottom bezel.

[0130] An exemplary embodiment of the present disclosure provides a display substrate, comprising a display area, wherein the display area includes a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, the driving circuit layer including a plurality of circuit units, a plurality of data signal lines, a plurality of data connection lines, a plurality of low-voltage power lines, and a plurality of power traces; the light-emitting structure layer includes a plurality of light-emitting devices; the circuit units include pixel driving circuits; the data signal lines are configured to provide data signals to the pixel driving circuits; the low-voltage power lines are configured to continuously provide low power voltage signals to the light-emitting devices; the data connection lines are connected to the data signal lines, and the power traces are connected to the low-voltage power lines.

[0131] In an exemplary embodiment, the data connection line includes a first connection line extending along a first direction and a second connection line extending along a second direction, the power line includes a first power line extending along the first direction and a second power line extending along the second direction, the first connection line is connected to the second connection line, the first power line is connected to the second power line, and the first direction and the second direction intersect.

[0132] In an exemplary embodiment, on a plane parallel to the substrate, the display area includes at least a first area where the first connecting line is provided, at least one circuit unit in the first area includes the first connecting line, the first power line, and the second power line, the first connecting line is connected to the data signal line, and the second power line is connected to the low-voltage power line.

[0133] In an exemplary embodiment, on a plane parallel to the substrate, the display area further includes a second area where the second connecting line is provided, at least one circuit unit in the second area includes the second connecting line, and the second connecting lines in the circuit units adjacent to each other in the second direction are connected to each other.

[0134] In an exemplary embodiment, on a plane parallel to the substrate, the display area further includes a third area that does not overlap with the orthographic projections of the first connecting line and the second connecting line on the substrate, at least one circuit unit in the third area includes the first power line and the second power line, and the second power line is connected to the low-voltage power line through a second connecting hole.

[0135] In the present disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, the main portion extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In the following description, "A extends along direction B" means "the main portion of A extends along direction B." In an exemplary embodiment, the second direction Y may be a direction from the display area to the binding area, and the opposite direction of the second direction Y may be a direction from the binding area to the display area.

[0136] FIG6 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. In a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer disposed on a substrate, a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the substrate. As shown in FIG6 , in a plane parallel to the display substrate, the display substrate may include at least a display area 100, a binding area 200 located on one side of the display area 100 in the second direction Y, and a border area 300 located on the other side of the display area 100. In an exemplary embodiment, the driving circuit layer of the display area 100 may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one of which may include a pixel driving circuit configured to output a corresponding current to a connected light-emitting device. The light-emitting structure layer of the display area 100 may include a plurality of sub-pixels constituting a pixel array, at least one of which may include a light-emitting device connected to a pixel driving circuit of a corresponding circuit unit, the light-emitting device configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0137] In an exemplary embodiment, the driving circuit layer of the display area 100 may also include multiple data signal lines 60 and multiple data connection lines 70, at least one data signal line 60 is connected to multiple pixel driving circuits in a unit column, the data signal line 60 is configured to provide a data signal to the connected pixel driving circuit, at least one data connection line 70 is correspondingly connected to the data signal line 60, and the data connection line 70 is configured to connect the data signal line 60 to the lead line 210 in the binding area 200 through the data connection line 70.

[0138] In exemplary embodiments, the term "sub-pixel" in this disclosure refers to a region divided according to a light-emitting device, and the term "circuit unit" in this disclosure refers to a region divided according to a pixel driving circuit. In exemplary embodiments, the position of the orthographic projection of the sub-pixel on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the sub-pixel on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0139] In an exemplary embodiment, a plurality of circuit units sequentially arranged along a first direction X may be referred to as a unit row, and a plurality of circuit units sequentially arranged along a second direction Y may be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute an array of circuit units arranged in an array, and the first direction X intersects the second direction Y. In an exemplary embodiment, the second direction Y may be an extending direction of a data signal line (a vertical direction), and the first direction X may be perpendicular to the second direction Y (a horizontal direction).

[0140] In an exemplary embodiment, the binding area 200 may include at least a lead area 201, a bend area, and a driver chip area, arranged in sequence away from the display area. The lead area 201 is connected to the display area 100, the bend area is connected to the lead area 201, and the driver chip area is connected to the bend area. The lead area 201 may be provided with multiple lead wires 210, which may extend along a second direction Y. The first ends of the multiple lead wires 210 are connected to the integrated circuit of the composite circuit area, and the second ends of the multiple lead wires 210 extend across the bend area to the lead area 201 and then connect to the corresponding data connection lines 70, so that the integrated circuit applies data signals to the data signal lines via the lead wires and data connection lines. Since the data connection lines are arranged in the display area, the length of the lead area in the second direction Y can be effectively reduced, significantly reducing the width of the lower frame, increasing the screen-to-body ratio, and facilitating the realization of a full-screen display.

[0141] In an exemplary embodiment, the plurality of data signal lines provided in the display area 100 may be in the shape of lines extending along the second direction Y. The plurality of data connection lines 70 provided in the display area 100 may be in the shape of zigzag lines. The data connection lines 70 may include first connection lines extending along the first direction X and second connection lines extending along the second direction Y. The first ends of the plurality of first connection lines (the first ends of the data connection lines 70) are connected to the plurality of data signal lines 60 via connection holes. The second ends of the plurality of first connection lines extend along the first direction X or a direction opposite to the first direction X and are connected to the first ends of the second connection lines. The second ends of the plurality of second connection lines (the second ends of the data connection lines 70) extend toward the binding area 200 and cross the display area boundary B to connect to the plurality of lead lines 210 of the lead area 201. In an exemplary embodiment, the display area boundary B may be the junction of the display area 100 and the binding area 200.

[0142] In an exemplary embodiment, the data connection line 70 and the lead-out line 210 may be directly connected or may be connected through a via hole, which is not limited in the present disclosure.

[0143] In an exemplary embodiment, the plurality of second connection lines may be disposed in parallel with the data signal lines 60 , and the plurality of first connection lines may be disposed perpendicular to the data signal lines 60 .

[0144] In an exemplary embodiment, the intervals between adjacent second connection lines in the first direction X may be substantially the same, and the intervals between adjacent first connection lines in the second direction Y may be substantially the same, which is not limited in the present disclosure.

[0145] In an exemplary embodiment, the display area 100 may have a center line O, and the multiple data signal lines 60, the multiple data connection lines 70 and the multiple lead lines 210 in the lead area 201 in the display area 100 may be symmetrically arranged relative to the center line O. The center line O may be a straight line that bisects the multiple unit columns of the display area 100 and extends along the second direction Y.

[0146] Figure 7 is a schematic diagram illustrating the arrangement of data connection lines according to an exemplary embodiment of the present disclosure. It is an enlarged view of the C1 area in Figure 6 and illustrates the structure of seven data signal lines, seven data connection lines, and seven lead lines. As shown in Figure 7, in an exemplary embodiment, the multiple data signal lines in the display area 100 may include first to seventh data signal lines 60-1 to 60-7, the multiple data connection lines in the display area 100 may include first to seventh data connection lines 70-1 to 70-7, and the multiple lead lines in the lead area 201 may include first to seventh lead lines 210-1 to 210-7.

[0147] In an exemplary embodiment, the first data signal line 60-1 to the seventh data signal line 60-7, the first data connection line 70-1 to the seventh data connection line 70-7, and the first lead line 210-1 to the seventh lead line 210-7 can all be arranged sequentially along the first direction X, the first end of the i-th data connection line 70-i is connected to the i-th data signal line 60-i through a connection hole in the display area 100, and the second end of the i-th data connection line 70-i extends to the lead area 201 and is connected to the i-th lead line 210-i, i=1 to 7.

[0148] In an exemplary embodiment, the distances between the multiple connection holes correspondingly connecting the data connection lines 70 and the data signal lines 60 and the edge B of the display area may be different. For example, the distance between the connection hole connecting the first data connection line 70-1 and the first data signal line 60-1 and the edge B of the display area may be smaller than the distance between the connection hole connecting the second data connection line 70-2 and the second data signal line 60-2 and the edge B of the display area. For another example, the distance between the connection hole connecting the second data connection line 70-2 and the second data signal line 60-2 and the edge B of the display area may be larger than the distance between the connection hole connecting the third data connection line 70-3 and the third data signal line 60-3 and the edge B of the display area.

[0149] Figure 8 is a schematic diagram of the planar structure of another display substrate according to an exemplary embodiment of the present disclosure, and Figure 9 is an enlarged view of region C2 in Figure 8. The driving circuit layer of display region 100 may include a plurality of circuit units forming a circuit unit array, a plurality of data signal lines 60, a plurality of data connection lines 70, and a power supply line 90 having a mesh-like interconnected structure. The layout and structure of the plurality of circuit units, the plurality of data signal lines 60, and the plurality of data connection lines 70 are substantially the same as those shown in Figure 6 above.

[0150] In an exemplary embodiment, the data connection line 70 may include a first connection line 71 extending along a first direction X and a second connection line 72 extending along a second direction Y. The first connection line 71 and the second connection line 72 constitute a zigzag-line-shaped data connection line 70. The first connection line 71 and the second connection line 72 may be provided in the same conductive layer, or the first connection line 71 and the data signal line 60 may be provided in different conductive layers. The first end of the first connection line 71 is connected to the data signal line 60 through a first connection hole. The second end of the first connection line 71 extends along the first direction X or the opposite direction of the first direction X and is directly connected to the first end of the second connection line 72. The second end of the second connection line 72 extends along the second direction Y toward the lead area 201 and is connected to the lead line 210.

[0151] In an exemplary embodiment, the power supply line 90 may include a plurality of first power supply lines 91 extending along a first direction X and a plurality of second power supply lines 92 extending along a second direction Y. The plurality of first power supply lines 91 may be arranged sequentially along the second direction Y, and the plurality of second power supply lines 92 may be arranged sequentially along the first direction X. The first power supply lines 91 and the second power supply lines 92 are interconnected to form a power supply line 90 with a meshed connection structure. The power supply line 90 is configured to be connected to a low-voltage power supply line in the driving circuit layer. The low-voltage power supply line is configured to continuously provide a low power supply voltage signal to the plurality of light-emitting devices in the light-emitting structure layer.

[0152] In an exemplary embodiment, the first power line 91 and the second power line 92 can be set in the same conductive layer, the first power line 91 and the low-voltage power line can be set in different conductive layers, and the second power line can be connected to the low-voltage power line through a second connection hole, thereby realizing the connection between the power line 90 with a mesh connection structure and the low-voltage power line.

[0153] FIG10 is a schematic diagram of a partition of a display area according to an exemplary embodiment of the present disclosure. As shown in FIG10 , since data connection lines are provided in a portion of the display area, and the data connection lines include a first connection line extending along a first direction X and a second connection line extending along a second direction Y, the display area can be divided into a first area 100A, a second area 100B, and a third area 100C based on the presence or absence of data connection lines and the direction in which the data connection lines extend. The first area 100A can be an area where the first connection line 71 is provided (a fan-out line transverse routing area), the second area 100B can be an area where the second connection line 72 is provided (a fan-out line longitudinal routing area), and the third area 100C can be an area (a normal area) where the orthographic projections of the first connection line 71 and the second connection line 72 on the substrate do not overlap, that is, the third area 100C can be an area where the first connection line 71 and the second connection line 72 are not provided.

[0154] In an exemplary embodiment, the first area 100A may include multiple circuit units, the orthographic projection of the first connecting line 71 on the display substrate plane at least partially overlaps with the orthographic projection of the pixel driving circuit in the multiple circuit units of the first area 100A on the display substrate plane, and the orthographic projection of the pixel driving circuit in the multiple circuit units of the first area 100A on the display substrate plane does not overlap with the orthographic projection of the second connecting line 72 on the display substrate plane.

[0155] In an exemplary embodiment, the second area 100B may include multiple circuit units, the orthographic projection of the second connecting line 72 on the display substrate plane at least partially overlaps with the orthographic projection of the pixel driving circuit in the multiple circuit units of the second area 100B on the display substrate plane, and the orthographic projection of the pixel driving circuit in the multiple circuit units of the second area 100B on the display substrate plane does not overlap with the orthographic projection of the first connecting line 71 on the display substrate plane.

[0156] In an exemplary embodiment, the third region 100C may include a plurality of circuit units, and the orthographic projections of the pixel driving circuits in the plurality of circuit units in the third region 100C on the display substrate plane do not overlap with the orthographic projections of the first and second connection lines 71 and 72 on the display substrate plane.

[0157] In the exemplary embodiment, the division of the various regions shown in FIG10 is merely an example. Since the first region 100A, the second region 100B, and the third region 100C are divided based on the presence or absence of data connection lines and the direction in which the data connection lines extend, the shapes of the three regions can be regular polygons or irregular polygons. The display area can be divided into one or more first regions 100A, one or more second regions 100B, and one or more third regions 100C, but this disclosure does not limit this.

[0158] FIG11a is a schematic diagram of the structure of the first region of an exemplary embodiment of the present disclosure. The first region may include multiple circuit units. As shown in FIG11a, at least one circuit unit in the first region may include a data signal line 60, a first connection line 71, a second power line 80, a first power trace 91, a second power trace 92, a power connection electrode 93, and a second compensation line 120. The first connection line 71 and the first power trace 91 may be shaped as straight lines with the main portion extending along the first direction X. The data signal line 60, the second power line 80, the second power trace 92, and the second compensation line 120 may be shaped as straight lines with the main portion extending along the second direction Y. The second power line 80, as a low-voltage power line of the present disclosure, is configured to continuously provide a low power supply voltage signal (VSS). The data signal line 60 is configured to provide a data signal.

[0159] In an exemplary embodiment, in at least one circuit unit in the first area, the data signal line 60 and the second power line 92 can be arranged on one side of the second power line 80 in the first direction X, and the second power line 92 can be arranged between the second power line 80 and the data signal line 60, the second compensation line 120 can be arranged on the side of the second power line 80 away from the data signal line 60, the first power line 91 can be arranged on one side of the circuit unit in the second direction Y, and the first connecting line 71 can be arranged on the side of the circuit unit in the opposite direction of the second direction Y.

[0160] In an exemplary embodiment, the first connection line 71 and the second connection line 72 may be disposed in the same conductive layer, and the first connection line 71 and the data signal line 60 may be disposed in different conductive layers.

[0161] In an exemplary embodiment, in at least one circuit unit in the first region, the first connection line 71 extending along the first direction X is connected to the data signal line 60 extending along the second direction Y through the first connection hole K1, thereby achieving connection between the first connection line 71 and the data signal line 60.

[0162] In an exemplary embodiment, in the first region, the first connection lines 71 may be continuously disposed in a plurality of circuit cells in one cell row, and the first connection lines 71 in adjacent circuit cells in the first direction X are connected to each other.

[0163] In an exemplary embodiment, the first power trace 91 and the second power trace 92 may be disposed in the same conductive layer, and the second power trace 92 and the second power line 80 may be disposed in different conductive layers.

[0164] In an exemplary embodiment, in at least one circuit unit in the first area, the second power trace 92 extending along the second direction Y is connected to the second power line 80 extending along the second direction Y through the second connection hole K2, thereby realizing the connection between the second power trace 92 and the second power line 80.

[0165] In an exemplary embodiment, in at least one cell row in the first region, a first power trace 91 extending along the first direction X is directly connected to a plurality of second power traces 92 extending along the second direction Y, forming a mesh-connected structure of power traces.

[0166] In an exemplary embodiment, at least one circuit unit in the first area may further include a power connection electrode 93. The shape of the power connection electrode 93 may be rectangular. The power connection electrode 93 may be arranged on the side of the second power line 92 away from the data signal line 60 and connected to the second power line 92. The orthographic projection of the power connection electrode 93 on the substrate at least partially overlaps with the orthographic projection of the second power line 80 on the substrate. The power connection electrode 93 is connected to the second power line 80 through the second connection hole K2, thereby realizing the connection between the grid-shaped power lead and the second power line 80.

[0167] In an exemplary embodiment, in the first region, the first power traces 91 may be continuously disposed in a plurality of circuit cells in a cell row, and the first power traces 91 in adjacent circuit cells in the first direction X are connected to each other.

[0168] In an exemplary embodiment, in the first region, the second power lines 92 can be arranged at intervals in multiple circuit units in a unit column, that is, the second power lines 92 in the circuit units adjacent in the second direction Y are arranged at intervals, so that the first connecting line 71 is arranged between the second power lines 92 adjacent in the second direction Y, and the orthographic projection of the first connecting line 71 on the substrate does not overlap with the orthographic projection of the second power line 92 on the substrate.

[0169] In an exemplary embodiment, in the first region, the first power traces 91 extending along the first direction X are directly connected to the plurality of second compensation lines 120 extending along the second direction Y.

[0170] In an exemplary embodiment, in the first region, the second compensation lines 120 may be spaced apart in a plurality of circuit units in a unit column, that is, the second compensation lines 120 in circuit units adjacent in the second direction Y are spaced apart, so that the first connecting line 71 is disposed between the second compensation lines 120 adjacent in the second direction Y, and the orthographic projection of the first connecting line 71 on the substrate does not overlap with the orthographic projection of the second compensation line 120 on the substrate.

[0171] Figure 11b is a schematic diagram of the structure of the second region of an exemplary embodiment of the present disclosure. The second region may include multiple circuit units. As shown in Figure 11b, at least one circuit unit in the second region may include a data signal line 60, a second connection line 72, a second power line 80, and a first compensation line 110. The first compensation line 110 may be shaped as a straight line with a main portion extending along a first direction X. The data signal line 60, the second connection line 72, and the second power line 80 may be shaped as a straight line with a main portion extending along a second direction Y. The first end of the second connection line 72 is connected to the lead line located in the lead area, and the second end of the second connection line 72 is connected to the first connection line 71 located in the display area, so that the interconnected first connection line 71 and the second connection line 72 form a zigzag data connection line.

[0172] In an exemplary embodiment, two second connection lines 72 may be provided in at least one circuit unit of the second region. The two second connection lines 72 may include a first side connection line and a second side connection line, wherein the first side connection line may be provided between the second power line 80 and the data signal line 60, and the second side connection line may be provided on a side of the second power line 80 away from the data signal line 60.

[0173] In an exemplary embodiment, at least two first compensation lines 110 may be provided in at least one circuit unit in the second region. The at least two first compensation lines 110 may include at least one first side compensation line and at least one second side compensation line, wherein a first end of the first side compensation line is connected to the first side connecting line, and a second end of the first side compensation line extends toward a direction approaching the second side connecting line, and a first end of the second side compensation line is connected to the second side connecting line, and a second end of the second side compensation line extends toward a direction approaching the first side connecting line, such that the two first compensation lines 110 in the circuit unit form an interdigitated structure.

[0174] In an exemplary embodiment, at least one circuit unit in the second area may further include a dummy connecting electrode 73. The shape of the dummy connecting electrode 73 may be rectangular. The dummy connecting electrode 73 may be arranged on a side of the second connecting line 72 away from the data signal line 60 and connected to the second connecting line 72. The orthographic projection of the dummy connecting electrode 73 on the substrate at least partially overlaps with the orthographic projection of the second power line 80 on the substrate.

[0175] In an exemplary embodiment, in the second region, the second connection lines 72 may be continuously disposed in a plurality of circuit cells in one cell column, and the second connection lines 72 in adjacent circuit cells in the second direction Y are connected to each other.

[0176] In an exemplary embodiment, in the second region, the first compensation lines 110 may be disposed at intervals among a plurality of circuit cells in one cell row.

[0177] Figure 11c is a schematic diagram of the structure of the third region of an exemplary embodiment of the present disclosure. The third region may include multiple circuit units. As shown in Figure 11c, at least one circuit unit in the third region may include a data signal line 60, a second power line 80, a first power trace 91, a second power trace 92, a power connection electrode 93, a first compensation line 110, and a second compensation line 120. The first power trace 91 and the first compensation line 110 may be shaped as straight lines with their main portions extending along the first direction X. The data signal line 60, the second power line 80, the second power trace 92, and the second compensation line 120 may be shaped as straight lines with their main portions extending along the second direction Y.

[0178] In an exemplary embodiment, in at least one circuit unit in the third area, the data signal line 60 can be arranged on one side of the second power line 80 in the first direction X, the second power line 92 can be arranged between the second power line 80 and the data signal line 60, the second compensation line 120 can be arranged on the side of the second power line 80 away from the data signal line 60, the first power line 91 can be arranged on one side of the circuit unit in the second direction Y, and the first compensation line 110 can be arranged on the side of the circuit unit in the opposite direction of the second direction Y.

[0179] In an exemplary embodiment, in at least one circuit unit in the third area, the second power trace 92 extending along the second direction Y is connected to the second power line 80 extending along the second direction Y through the second connection hole K2, thereby realizing the connection between the second power trace 92 and the second power line 80.

[0180] In an exemplary embodiment, the first power supply line 91 and the second power supply line 92 can be arranged in the same conductive layer. In at least one unit row in the third area, the first power supply line 91 extending along the first direction X is directly connected to multiple second power supply lines 92 extending along the second direction Y, forming a power supply line with a meshed connection structure.

[0181] In an exemplary embodiment, in the third region, the first power traces 91 may be continuously disposed in a plurality of circuit cells in one cell row, and the first power traces 91 in adjacent circuit cells in the first direction X are connected to each other.

[0182] In an exemplary embodiment, in the first region, the second power traces 92 may be continuously disposed in a plurality of circuit cells in a cell column, and the second power traces 92 in adjacent circuit cells in the second direction Y are connected to each other.

[0183] In an exemplary embodiment, at least one circuit unit in the third area may further include a power connection electrode 93. The shape of the power connection electrode 93 may be rectangular. The power connection electrode 93 may be arranged on the side of the second power line 92 away from the data signal line 60 and connected to the second power line 92. The orthographic projection of the power connection electrode 93 on the substrate at least partially overlaps with the orthographic projection of the second power line 80 on the substrate. The power connection electrode 93 is connected to the second power line 80 through the second connection hole K2, thereby realizing the connection between the grid-shaped power lead and the second power line 80.

[0184] In an exemplary embodiment, in the third region, the first compensation lines 110 may be continuously disposed in a plurality of circuit units in one unit row, and the first compensation lines 110 in adjacent circuit units in the first direction X are connected to each other.

[0185] In an exemplary embodiment, in the third region, the second compensation lines 120 may be continuously disposed in a plurality of circuit cells in one cell column, and the second compensation lines 120 in adjacent circuit cells in the second direction Y are connected to each other.

[0186] In an exemplary embodiment, the first power trace 91 , the second power trace 92 , the first compensation line 110 , and the second compensation line 120 may be disposed in the same conductive layer.

[0187] In an exemplary embodiment, in at least one cell row in the third region, the first power trace 91 extending along the first direction X is directly connected to the plurality of second compensation lines 120 extending along the second direction Y.

[0188] In an exemplary embodiment, in at least one cell row in the third region, the second power trace 92 extending along the second direction Y is directly connected to the plurality of first compensation lines 110 extending along the first direction X.

[0189] In an exemplary embodiment, in at least one circuit unit in the third region, the first power trace 91 and the first compensation line 110 extending along the first direction X are connected to the second power trace 92 and the second compensation line 120 extending along the second direction Y to form a "well"-shaped structure.

[0190] In an exemplary embodiment, in at least one unit row including circuit units of the first region, circuit units of the second region, and circuit units of the third region, the first power trace 91 of the first region, the first side compensation line of the first compensation line 110 of the second region, and the first power trace 91 of the third region can be located on the same straight line extending along the first direction X, the first connection line 71 of the first region, the second side compensation line of the first compensation line 110 of the second region, and the first compensation line 110 of the third region can be located on the same straight line extending along the first direction X, and the power connection electrode 93 of the first region, the dummy connection electrode 73 of the second region, and the power connection electrode 93 of the third region can be located on the same straight line extending along the first direction X. In at least one cell column comprising circuit cells in a first region, circuit cells in a second region, and circuit cells in a third region, the second power supply trace 92 in the first region, the first side connection line among the second connection lines 72 in the second region, and the second power supply trace 92 in the third region may be located on the same straight line extending along the second direction Y. The second compensation line 120 in the first region, the second side connection line among the second connection lines 72 in the second region, and the second compensation line 120 in the third region may be located on the same straight line extending along the second direction Y. The power connection electrode 93 in the first region, the dummy connection electrode 73 in the second region, and the power connection electrode 93 in the third region may be located on the same straight line extending along the second direction Y. Thus, the traces in the first, second, and third regions exhibit substantially similar morphologies, which not only improves the uniformity of the manufacturing process but also enables different regions to achieve substantially the same display effects under both transmitted and reflected light, effectively avoiding poor appearance of the display substrate and improving display quality.

[0191] In an exemplary embodiment, the driving circuit layer includes, in a plane perpendicular to the display substrate, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on a substrate. The semiconductor layer includes at least an active layer of multiple transistors, the first conductive layer includes at least gate electrodes of the multiple transistors and a first plate of a storage capacitor, the second conductive layer includes at least a second plate of a storage capacitor, the third conductive layer includes at least first and second electrodes of the multiple transistors, the fourth conductive layer includes at least a data signal line 60 and a second power line 80, and the fifth conductive layer includes at least a first connecting line 71, a second connecting line 72, a first power supply trace 91, and a second power supply trace 92. The first connecting line 71 and the second connecting line 72 are interconnected as an integral structure. The first connecting line 71 is connected to the data signal line 60 via a first connecting hole. The first power supply trace 91 and the second power supply trace 92 are interconnected as an integral structure. The second power supply trace 92 is connected to the second power line 80 via a second connecting hole.

[0192] In an exemplary embodiment, the driving circuit layer may further include at least a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a first flat layer, a second flat layer and a third flat layer, the first insulating layer being arranged between the substrate and the semiconductor layer, the second insulating layer being arranged between the semiconductor layer and the first conductive layer, the third insulating layer being arranged between the first conductive layer and the second conductive layer, the fourth insulating layer being arranged between the second conductive layer and the third conductive layer, the first flat layer being arranged between the third conductive layer and the fourth conductive layer, the second flat layer being arranged between the fourth conductive layer and the fifth conductive layer, and the third flat layer being arranged on the side of the fifth conductive layer away from the substrate.

[0193] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0194] In an exemplary embodiment, taking eight circuit units (two unit rows and four unit columns) as an example, the preparation process of the substrate may include the following operations.

[0195] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming the semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on a substrate, patterning the semiconductor film through a patterning process to form a first insulating layer covering the substrate, and a semiconductor layer disposed on the first insulating layer, as shown in FIG. 12 , which is an enlarged view of the E0 region in FIG. 10 .

[0196] In an exemplary embodiment, the semiconductor layer of each circuit unit in the display area may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7. The first active layer 11 to the sixth active layer 16 are interconnected as an integrated structure. Moreover, the sixth active layer 16 and the seventh active layer 17 of adjacent circuit units in each cell column are interconnected as an integrated structure. For example, the sixth active layer 16 of the circuit unit in the Mth row and the seventh active layer 17 of the circuit unit in the M+1th row in each cell column are interconnected.

[0197] In an exemplary embodiment, the first active layer 11, the second active layer 12, the fourth active layer 14 and the seventh active layer 17 in the M-th row circuit unit can be located on the side of the third active layer 13 of the circuit unit away from the M+1-th row circuit unit, the first active layer 11 and the seventh active layer 17 can be located on the side of the second active layer 12 and the fourth active layer 14 away from the third active layer 13, and the fifth active layer 15 and the sixth active layer 16 in the M-th row circuit unit can be located on the side of the third active layer 13 close to the M+1-th row circuit unit.

[0198] In an exemplary embodiment, the first active layer 11 may have an "n" shape, the second active layer 12, the fifth active layer 15, and the sixth active layer 16 may have an "L" shape, the third active layer 13 may have an "Ω" shape, and the fourth active layer 14 and the seventh active layer 17 may have an "I" shape.

[0199] In example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.

[0200] The first region 11-1 of the first active layer 11, the first region 14-1 of the fourth active layer 14, the first region 15-1 of the fifth active layer 15 and the first region 17-1 of the seventh active layer 17 can be set separately, the second region 11-2 of the first active layer 11 can serve as the first region 12-1 (second node N2) of the second active layer 12, the first region 13-1 of the third active layer 13 can simultaneously serve as the second region 14-2 of the fourth active layer 14 and the second region 15-2 (first node N1) of the fifth active layer 15, the second region 13-2 of the third active layer 13 can simultaneously serve as the second region 12-2 of the second active layer 12 and the first region 16-1 (third node N3) of the sixth active layer 16, and the second region 12-2 of the sixth active layer 16 can simultaneously serve as the second region 17-2 of the seventh active layer 17.

[0201] In exemplary embodiments, the semiconductor patterns of the E1 and E2 regions in FIG. 10 are substantially the same as the semiconductor pattern of the E0 region.

[0202] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG13a and FIG13b, FIG13a is an enlarged view of the E0 region in FIG10, and FIG13b is a planar schematic diagram of the first conductive layer in FIG13a. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE 1) layer.

[0203] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display area includes at least a first scan signal line 21 , a second scan signal line 22 , a light emitting control line 23 and a first plate 24 of a storage capacitor.

[0204] In an exemplary embodiment, the first plate 24 of the storage capacitor may be rectangular, with chamfered corners. The orthographic projection of the first plate 24 on the substrate overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first plate 24 may serve as both a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0205] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, and the light emission control line 23 may be in the shape of a line whose main portion extends along the first direction X. The first scan signal line 21 and the second scan signal line 22 in the Mth row of circuit units may be located on a side of the first electrode plate 24 of the circuit unit away from the M+1th row of circuit units, the second scan signal line 22 may be located on a side of the first scan signal line 21 of the circuit unit away from the first electrode plate 24, and the light emission control line 23 may be located on a side of the first electrode plate 24 of the circuit unit closer to the M+1th row of circuit units.

[0206] In an exemplary embodiment, the first scan signal line 21 can be provided with a gate block 21-1 protruding toward the side of the second scan signal line 22, and the area where the first scan signal line 21 and the gate block 21-1 overlap with the second active layer can serve as the gate electrode of the second transistor T2, forming a second transistor T2 with a dual-gate structure.

[0207] In an exemplary embodiment, the region where the first scan signal line 21 overlaps with the fourth active layer 14 serves as the gate electrode of the fourth transistor T4. The region where the second scan signal line 22 overlaps with the first active layer can serve as the gate electrode of the first transistor T1 of the dual-gate structure, and the region where the second scan signal line 22 overlaps with the seventh active layer 17 serves as the gate electrode of the seventh transistor T7. The region where the light emission control line 23 overlaps with the fifth active layer 15 serves as the gate electrode of the fifth transistor T5, and the region where the light emission control line 23 overlaps with the sixth active layer 16 serves as the gate electrode of the sixth transistor T6.

[0208] In exemplary embodiments, the first conductive layer patterns of the E1 and E2 regions in FIG. 10 are substantially the same as the first conductive layer pattern of the E0 region.

[0209] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first region and the second region of the first active layer to the seventh active layer are both conductorized.

[0210] (3) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG14a and FIG14b, FIG14a is an enlarged view of the E0 region in FIG10, and FIG14b is a planar schematic diagram of the second conductive layer in FIG14a. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE 2) layer.

[0211] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display area includes at least a first initial signal line 31 , a second initial signal line 32 , a second plate 33 , a plate connection line 34 and a shielding electrode 35 .

[0212] In an exemplary embodiment, the first initial signal line 31 and the second initial signal line 32 may be in the shape of a line whose main portion may extend along the first direction X. The first initial signal line 31 in the M-th row of circuit units may be located on a side of the second scan signal line 22 of the circuit unit away from the first scan signal line 21 , and the second initial signal line 32 may be located between the first scan signal line 21 and the second scan signal line 22 of the circuit unit.

[0213] In an exemplary embodiment, the contour shape of the second electrode plate 33 can be rectangular, and the corners of the rectangle can be chamfered. There is an overlapping area between the orthographic projection of the second electrode plate 33 on the substrate and the orthographic projection of the first electrode plate 24 on the substrate. The second electrode plate 33 serves as another electrode plate of the storage capacitor and is located between the first scanning signal line 21 and the light-emitting control line 24 of this circuit unit. The first electrode plate 24 and the second electrode plate 33 constitute the storage capacitor of the pixel driving circuit.

[0214] In an exemplary embodiment, the plate connection line 34 can be disposed on one side of the second plate 33 in the first direction X or the direction opposite to the first direction X. The first end of the plate connection line 34 is connected to the second plate 33 of the circuit unit in question, and the second end of the plate connection line 34 extends along the first direction X or the direction opposite to the first direction X to connect to the second plate 33 of an adjacent circuit unit, thereby interconnecting the second plates 33 of adjacent circuit units in a unit row. In an exemplary embodiment, the plate connection line can be used to form an interconnected integrated structure for the second plates of multiple circuit units in a unit row. The integrated second plates can be reused as power signal connection lines, ensuring that the multiple second plates in a unit row have the same potential, which helps improve panel uniformity, prevent display defects on the display substrate, and ensure the display quality of the display substrate.

[0215] In an exemplary embodiment, an opening 36 is provided on the second plate 33. The opening 36 may be located in the middle of the second plate 33. The opening 36 may be rectangular, forming an annular structure for the second plate 33. The opening 36 exposes the third insulating layer covering the first plate 24, and the orthographic projection of the first plate 24 on the substrate includes the orthographic projection of the opening 36 on the substrate. In an exemplary embodiment, the opening 36 is configured to accommodate a first via hole to be formed later. The first via hole is located within the opening 36 and exposes the first plate 24, thereby connecting the second electrode of the first transistor T1 to be formed later.

[0216] In an exemplary embodiment, the shielding electrode 35 can be located between the first scanning signal line 21 and the second initial signal line 32 of the circuit unit. The shielding electrode 35 is configured to be connected to a first power line formed later. The orthographic projection of the shielding electrode 35 on the substrate at least partially overlaps with the orthographic projections of the second region of the first active layer and the first region of the second active layer on the substrate. The shielding electrode 35 is configured to shield key nodes from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the potentials of key nodes of the pixel driving circuit and improving display quality.

[0217] In an exemplary embodiment, the second conductive layer patterns of the E1 and E2 regions in FIG. 10 are substantially the same as the second conductive layer of the E0 region.

[0218] (4) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of vias are provided in each circuit unit, as shown in FIG. 15 , which is an enlarged view of the E0 region in FIG. 10 .

[0219] In an exemplary embodiment, the multiple vias of each circuit unit in the display area include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10 and an eleventh via V11.

[0220] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the opening 36 of the second electrode plate 33 on the substrate, the fourth insulating layer and the third insulating layer in the first via hole V1 are etched away to expose the surface of the first electrode plate 24, and the first via hole V1 is configured to connect the second electrode of the subsequently formed first transistor T1 to the first electrode plate 24 through the via hole.

[0221] In the exemplary embodiment, the orthographic projection of the second via V2 on the substrate is within the range of the orthographic projection of the second electrode plate 33 on the substrate. The fourth insulating layer within the second via V2 is etched away, exposing the surface of the second electrode plate 33. The second via V2 is configured to connect a subsequently formed first power line to the second electrode plate 33 through the via. In the exemplary embodiment, a plurality of second vias V2 serving as power vias may be included, and the plurality of second vias V2 may be arranged sequentially along the second direction Y to increase the reliability of the connection between the first power line and the second electrode plate 33.

[0222] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the fifth active layer, and the third via hole V3 is configured to connect a subsequently formed first power line to the first region of the fifth active layer through the via hole.

[0223] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second region of the sixth active layer (also the second region of the seventh active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are etched away to expose the surface of the second region of the sixth active layer, and the fourth via V4 is configured to connect the second electrode of the subsequently formed sixth transistor T6 (also the second electrode of the seventh transistor T7) to the second region of the sixth active layer (also the second region of the seventh active layer) through the via.

[0224] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first region of the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are etched away to expose the surface of the first region of the fourth active layer, and the fifth via V5 is configured to connect the first electrode of the subsequently formed fourth transistor T4 to the first region of the fourth active layer through the via.

[0225] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second region of the first active layer (also the first region of the second active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are etched away to expose the surface of the second region of the first active layer, and the sixth via V6 is configured to connect the second electrode of the subsequently formed first transistor T1 (also the first electrode of the second transistor T2) to the second region of the first active layer (also the first region of the second active layer) through the via.

[0226] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the seventh via V7 are etched away to expose the surface of the first region of the seventh active layer, and the seventh via V7 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the first region of the seventh active layer through the via.

[0227] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer within the eighth via V8 are etched away to expose the surface of the first region of the first active layer, and the eighth via V8 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first region of the first active layer through the via.

[0228] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first initial signal line 31 on the substrate, the fourth insulating layer in the ninth via V9 is etched away to expose the surface of the first initial signal line 31, and the ninth via V9 is configured to connect the first electrode of the subsequently formed first transistor T1 to the first initial signal line 31 through the via.

[0229] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the second initial signal line 32 on the substrate, the fourth insulating layer in the tenth via V10 is etched away, exposing the surface of the second initial signal line 32, and the tenth via V10 is configured to connect the first electrode of the subsequently formed seventh transistor T7 to the second initial signal line 32 through the via.

[0230] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the shielding electrode 35 on the substrate, the fourth insulating layer in the eleventh via hole V11 is etched away, exposing the surface of the shielding electrode 35, and the eleventh via hole V11 is configured to connect a subsequently formed first power line to the shielding electrode 35 through the via hole.

[0231] In an exemplary embodiment, the via hole patterns of the E1 and E2 regions in FIG. 10 are substantially the same as the via hole pattern of the E0 region.

[0232] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the third conductive film using a patterning process to form a third conductive layer disposed on the fourth insulating layer, as shown in FIG16a and FIG16b , where FIG16a is an enlarged view of the E0 region in FIG10 , and FIG16b is a planar schematic diagram of the third conductive layer in FIG16a . In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0233] In an exemplary embodiment, the third conductive layer pattern of the plurality of circuit units in the display area may include first connection electrodes 41 , second connection electrodes 42 , third connection electrodes 43 , fourth connection electrodes 44 , fifth connection electrodes 45 , first power lines 46 and initial connection lines 47 .

[0234] In an exemplary embodiment, the first connection electrode 41 may be in the shape of a strip extending along the second direction Y. A first end of the first connection electrode 41 is connected to the first electrode plate 24 via a first via V1, and a second end of the first connection electrode 41 is connected to the second region of the first active layer (also the first region of the second active layer) via a sixth via V6. In an exemplary embodiment, the first connection electrode 41 may serve as the second electrode of the first transistor T1 and the first electrode of the second transistor T2, so that the first electrode plate 24, the second electrode of the first transistor T1, and the first electrode of the second transistor T2 have the same potential (second node N2).

[0235] In an exemplary embodiment, the second connection electrode 42 may be rectangular in shape, and the fourth connection electrode 44 may be connected to the first region of the fourth active layer through a fifth via hole V5. In an exemplary embodiment, the fourth connection electrode 44 may serve as a first electrode of the fourth transistor T4 and may be connected to a subsequently formed data signal line.

[0236] In an exemplary embodiment, the third connection electrode 43 may be rectangular in shape and connected to the second region of the sixth active layer (also the second region of the seventh active layer) via a fourth via hole V4. In an exemplary embodiment, the third connection electrode 43 may serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, so that the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 have the same potential. The third connection electrode 43 is configured to be connected to a first anode connection electrode formed subsequently.

[0237] In an exemplary embodiment, the fourth connection electrode 44 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the fourth connection electrode 44 is connected to the first region of the seventh active layer via a seventh via hole V7, and a second end of the fourth connection electrode 44 is connected to the second initial signal line 32 via a tenth via hole V10. In an exemplary embodiment, the fourth connection electrode 44 may serve as a first electrode of the seventh transistor T7, thereby enabling the second initial signal line 32 to write the second initial signal into the seventh transistor T7.

[0238] In an exemplary embodiment, the fifth connection electrode 45 may be shaped like a zigzag line. A first end of the fifth connection electrode 45 is connected to the first region of the first active layer via an eighth via hole V8, and a second end of the fifth connection electrode 45 is connected to the first initial signal line 31 via a ninth via hole V9. The fifth connection electrode 45 may serve as the first electrode of the first transistor T1, thereby enabling the first initial signal line 31 to write the first initial signal into the first electrode of the first transistor T1.

[0239] In an exemplary embodiment, the first power line 46 may be in the shape of a line with a main portion extending along the second direction Y. The first power line 46 is connected to the second electrode plate 33 via the second via V2, to the fifth active layer via the third via V3, and to the shielding electrode 35 via the eleventh via V11, so that the first electrode of the fifth transistor T5 is at the same potential as the second electrode plate 33. The first power line 46 is configured to continuously provide a high power supply voltage signal (VDD) and may be referred to as a high-voltage power line. Because the shielding electrode 35 is connected to the first power line 46, and at least a portion of the shielding electrode 35 is located between the first connection electrode 41 (serving as the second electrode of the first transistor T1 and the first electrode of the second transistor T2, i.e., the second node N2) and the second connection electrode 42 (serving as the second electrode of the fourth transistor T4), the shielding electrode 35 can effectively shield the key nodes in the pixel driving circuit from the effects of data voltage jumps, thereby preventing the data voltage jumps from affecting the potentials of the key nodes in the pixel driving circuit and improving the display effect.

[0240] In an exemplary embodiment, the first power lines 46 of each circuit unit may be designed with unequal widths. The unequal width design of the first power lines 46 not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power lines and the data signal lines.

[0241] In an exemplary embodiment, the shape of the initial connection line 47 can be a folded shape in which the main part extends along the second direction Y, and is arranged on the side of the first connection electrode 41 away from the first power line 46. The initial connection line 47 is configured to connect the first initial signal line 31 or the second initial signal line 32 to form a mesh connection structure for transmitting the first initial signal or the second initial signal.

[0242] In an exemplary embodiment, the initial connection line 47 in the odd column circuit unit can be connected to the fifth connection electrode 45, and the initial connection line 47 in the even column circuit unit can be connected to the fourth connection electrode 44, or the initial connection line 47 in the odd column circuit unit can be connected to the fourth connection electrode 44, and the initial connection line 47 in the even column circuit unit can be connected to the fifth connection electrode 45.

[0243] In an exemplary embodiment, the initial connection lines 47 in the Nth column and the N+2th column can be connected to the fifth connection electrodes 45 of multiple circuit units in the unit column. Since the fifth connection electrode 45 is connected to the first initial signal line 31 through a via, the initial connection lines 47 and the first initial signal lines 31 are interconnected. The multiple first initial signal lines 31 extending along the first direction X and the multiple initial connection lines 47 extending along the second direction Y form an initial signal line with a mesh connection structure, which can not only effectively reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal, but also effectively improve the uniformity of the first initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0244] In an exemplary embodiment, the initial connection lines 47 in the N+1th column and the N+3th column can be connected to the fourth connection electrodes 44 of multiple circuit units in the unit column. Since the fourth connection electrode 44 is connected to the second initial signal line 32 through a via, the initial connection line 47 and the second initial signal line 32 are interconnected. The multiple second initial signal lines 32 extending along the first direction X and the multiple initial connection lines 47 extending along the second direction Y form an initial signal line with a mesh connection structure, which can not only effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0245] The present disclosure forms a mesh structure of the initial signal lines transmitting the first initial signal and a mesh structure of the initial signal lines transmitting the second initial signal, thereby realizing a mesh layout of the initial signal lines transmitting the first initial signal and the initial signal lines transmitting the second initial signal. This not only effectively reduces the resistance of the first initial signal lines and the second initial signal lines, and reduces the voltage drop between the first initial voltage and the second initial voltage, but also effectively improves the uniformity of the first initial voltage and the second initial voltage in the display substrate, effectively improves the display uniformity, and improves the display quality and display quality.

[0246] In some possible exemplary embodiments, the initial connection lines 47 may be arranged in odd-numbered rows and even-numbered rows to connect to the first initial signal line 31 and the second initial signal line 32, respectively. For example, the initial connection line 47 in the circuit unit of the odd row may be connected to the fifth connection electrode 45, and the initial connection line 47 in the circuit unit of the even row may be connected to the fourth connection electrode 44. Alternatively, the initial connection line 47 in the circuit unit of the odd row may be connected to the fourth connection electrode 44, and the initial connection line 47 in the circuit unit of the even row may be connected to the fifth connection electrode 45. The present disclosure is not limited here.

[0247] In exemplary embodiments, the third conductive layer patterns of the E1 and E2 regions in FIG. 10 are substantially the same as the third conductive layer pattern of the E0 region.

[0248] (6) Forming patterns of the fifth insulating layer and the first planar layer. In an exemplary embodiment, forming patterns of the fifth insulating layer and the first planar layer may include: depositing a fifth insulating film on the substrate on which the aforementioned pattern is formed, then coating the first planar film, patterning the first planar film and the fifth insulating film using a patterning process to form a fifth insulating layer covering the third conductive layer and a first planar layer disposed on the fifth insulating layer, wherein a plurality of vias are disposed on the fifth insulating layer and the first planar layer, as shown in FIG17 , which is an enlarged view of the E0 region in FIG10 .

[0249] In an exemplary embodiment, the plurality of via holes of the plurality of circuit units in the display area include at least a twenty-first via hole V21 and a twenty-second via hole V22 .

[0250] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second connecting electrode 42 on the substrate, the first flat layer and the fifth insulating layer in the twenty-first via hole V21 are removed, exposing the surface of the second connecting electrode 42, and the twenty-first via hole V21 is configured to connect a subsequently formed data signal line to the second connecting electrode 42 through the via hole.

[0251] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projection of the third connection electrode 43 on the substrate. The first flat layer and the fifth insulating layer in the twenty-second via hole V22 are removed to expose the surface of the third connection electrode 43. The twenty-second via hole V22 is configured to connect the subsequently formed first anode connection electrode to the third connection electrode 43 through the via hole.

[0252] In an exemplary embodiment, the via hole patterns of the E1 and E2 regions in FIG. 10 are substantially the same as the via hole pattern of the E0 region.

[0253] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the first flat layer, as shown in Figures 18a to 18d, wherein Figure 18a is an enlarged view of the E0 region and the E2 region in Figure 10, Figure 18b is a planar schematic diagram of the fourth conductive layer in Figure 18a, Figure 18c is an enlarged view of the E1 region in Figure 10, and Figure 18d is a planar schematic diagram of the fourth conductive layer in Figure 18c. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0254] In an exemplary embodiment, the fourth conductive layer patterns of the plurality of circuit units in the display area each include a first anode connection electrode 51 , a data signal line 60 , and a second power supply line 80 .

[0255] In an exemplary embodiment, the first anode connection electrode 51 may be in the shape of a strip extending along the second direction Y. The first anode connection electrode 51 is connected to the third connection electrode 43 via the twenty-second via hole V22. In an exemplary embodiment, the first anode connection electrode 51 is configured to be connected to a subsequently formed second anode connection electrode. To accommodate the connection to the subsequently formed anode, the shape and position of the first anode connection electrode 51 may be different in multiple circuit units.

[0256] In an exemplary embodiment, the shape of the data signal line 60 can be a straight line with the main portion extending along the second direction Y. The data signal line 60 is connected to the second connection electrode 42 through the twenty-first via hole V21. Since the second connection electrode 42 is connected to the first area of ​​the fourth active layer through the via hole, the data signal line 60 writes the data signal into the first electrode of the fourth transistor T4.

[0257] In an exemplary embodiment, the second power line 80 can be shaped like a broken line with the main portion extending along the second direction Y. The second power line 80 serves as a low-voltage power line of the present disclosure and is configured to continuously provide a low power voltage signal (VSS) to the subsequently formed light-emitting device.

[0258] In an exemplary embodiment, the orthographic projection of the second power line 80 on the substrate at least partially overlaps with the orthographic projection of the first power line 46 on the substrate. Since both the first power line 46 and the second power line 80 transmit constant voltage signals, they can be arranged to overlap, which can effectively improve the transmittance and space utilization of the display substrate.

[0259] In an exemplary embodiment, the area where the orthographic projection of the first power line 46 on the substrate overlaps with the orthographic projection of the second power line 80 on the substrate has a first overlapping area, and the first overlapping area can be greater than 80% of the first area.

[0260] In an exemplary embodiment, the orthographic projection of the first power line 46 on the substrate may be located within the range of the orthographic projection of the second power line 80 on the substrate.

[0261] In an exemplary embodiment, the structures of the first anode connection electrode 51 , the second power line 80 , and the data signal line 60 in the first, second, and third regions are substantially the same.

[0262] In an exemplary embodiment, the fourth conductive layer patterns of the second area (E2 area) and the third area (E0 area) of the display area are substantially the same, including only the first anode connection electrode 51, the data signal line 60 and the second power line 80, while the fourth conductive layer patterns of the multiple circuit units in the first area (E1 area) of the display area may also include the data connection electrode 61.

[0263] In an exemplary embodiment, the data connection electrode 61 may be disposed in some circuit units of the first region. The data connection electrode 61 may be rectangular in shape. The data connection electrode 61 is connected to the data signal line 60 . The data connection electrode 61 is configured to be connected to a first connection line formed subsequently.

[0264] (8) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fourth conductive layer, wherein a plurality of vias are provided on the second planar layer, as shown in FIG19a to FIG19c , FIG19a is an enlarged view of the E0 region in FIG10 , FIG19b is an enlarged view of the E1 region in FIG10 , and FIG19c is an enlarged view of the E2 region in FIG10 .

[0265] In an exemplary embodiment, the plurality of circuit units in the display area each include a thirty-first via hole V31 .

[0266] In an exemplary embodiment, the orthographic projection of the thirty-first via hole V31 on the substrate is located within the range of the orthographic projection of the first anode connecting electrode 51 on the substrate. The second planar layer within the thirty-first via hole V31 is removed, exposing the surface of the first anode connecting electrode 51. The thirty-first via hole V31 is configured to connect a subsequently formed second anode connecting electrode to the first anode connecting electrode 51 through the via hole. To accommodate connections to subsequently formed anodes, the position of the thirty-first via hole V31 may vary across multiple circuit units.

[0267] As shown in FIG. 19 a , in an exemplary embodiment, the plurality of circuit units in the third region ( E0 region) of the display region may further include a thirty-second via hole V32 .

[0268] In an exemplary embodiment, the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the second power line 80 on the substrate, the second flat layer in the thirty-second via V32 is removed to expose the surface of the second power line 80, and the thirty-second via V32 is configured to connect a subsequently formed second power line to the second power line 80 through the via.

[0269] As shown in FIG. 19 b , in an exemplary embodiment, the plurality of circuit units in the first region ( E1 region) of the display region may further include a thirty-second via hole V32 and a thirty-third via hole V33 .

[0270] In an exemplary embodiment, the structure of the thirty-second via hole V32 in the first region is substantially the same as the structure of the thirty-second via hole V32 in the third region.

[0271] In an exemplary embodiment, the orthographic projection of the thirty-third via hole V33 on the substrate is located within the range of the orthographic projection of the data connection electrode 61 on the substrate, the second flat layer in the thirty-third via hole V33 is removed, exposing the surface of the data connection electrode 61, and the thirty-third via hole V33 is configured to connect the subsequently formed first connection line to the data connection electrode 61 through the via hole.

[0272] As shown in FIG. 19 c , in an exemplary embodiment, the plurality of circuit units in the second region ( E2 region) of the display region includes only the thirty-first via hole V31 .

[0273] (9) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern may include: depositing a fifth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on the second flat layer, as shown in Figures 20a to 20f, wherein Figure 20a is an enlarged view of the E0 region in Figure 10, Figure 20b is a planar schematic diagram of the fifth conductive layer in Figure 20a, Figure 20c is an enlarged view of the E1 region in Figure 10, Figure 20d is a planar schematic diagram of the fifth conductive layer in Figure 20c, Figure 20e is an enlarged view of the E2 region in Figure 10, and Figure 20f is a planar schematic diagram of the fifth conductive layer in Figure 20e. In an exemplary embodiment, the fifth conductive layer may be referred to as a third source / drain metal (SD3) layer.

[0274] In an exemplary embodiment, the fifth conductive layer patterns of the plurality of circuit units in the display area each include the second anode connection electrode 53 .

[0275] In an exemplary embodiment, the second anode connection electrode 53 may be rectangular in shape and connected to the first anode connection electrode 51 through the thirty-first via hole V31. In an exemplary embodiment, the second anode connection electrode 53 is configured to be connected to a subsequently formed anode. To accommodate the connection to the subsequently formed anode, the shape and position of the second anode connection electrode 53 may be different in multiple circuit units.

[0276] As shown in Figures 20a and 20b, the fifth conductive layer pattern of multiple circuit units in the third area (E0 area) of the display area also includes: a first power line 91, a second power line 92, a power connection electrode 93, a first compensation line 110 and a second compensation line 120.

[0277] In an exemplary embodiment, the first power trace 91 may be in a straight line shape with a main portion extending along the first direction X. The first power traces 91 in adjacent circuit units in the first direction X in the third region are connected to each other in an integrated structure.

[0278] In an exemplary embodiment, the orthographic projection of the first power trace 91 on the substrate at least partially overlaps with the orthographic projection of the first initial signal line 31 on the substrate, which can effectively improve the transmittance and space utilization of the display substrate.

[0279] In an exemplary embodiment, the area of ​​the orthographic projection of the first power trace 91 on the substrate has a third area, and the area where the orthographic projection of the first initial signal line 31 on the substrate overlaps with the orthographic projection of the first initial signal line 31 on the substrate has a third overlapping area, and the third overlapping area can be greater than 80% of the third area.

[0280] In an exemplary embodiment, the second power trace 92 may be in the shape of a straight line with a main portion extending along the second direction Y. The second power traces 92 in adjacent circuit units in the second direction Y in the third region are interconnected as an integrated structure.

[0281] In an exemplary embodiment, an orthographic projection of the second power trace 92 on the substrate at least partially overlaps with an orthographic projection of the second plate 33 of the storage capacitor on the substrate.

[0282] In an exemplary embodiment, the plurality of second power traces 92 and the plurality of first power traces 91 in the third region are interconnected as an integrated structure, forming a grid-like power lead.

[0283] In an exemplary embodiment, the shape of the power connection electrode 93 can be rectangular, and the power connection electrode 93 can be arranged on the side of the second power line 92 away from the data signal line 60 (i.e., the side close to the second power line 80), and is connected to the second power line 92. The positive projection of the power connection electrode 93 on the substrate at least partially overlaps with the positive projection of the low-voltage power line 52 on the substrate. The power connection electrode 93 is connected to the second power line 80 through the thirty-second via V32, thereby realizing the connection between the grid-shaped power lead and the second power line 80.

[0284] In an exemplary embodiment, the first compensation line 110 may be in the shape of a straight line with a main portion extending along the first direction X. The first compensation lines 110 in adjacent circuit units in the first direction X in the third region are connected to each other in an integrated structure.

[0285] In an exemplary embodiment, the orthographic projection of the first compensation line 110 on the substrate at least partially overlaps with the orthographic projection of the second initial signal line 32 on the substrate, which can effectively improve the transmittance and space utilization of the display substrate.

[0286] In an exemplary embodiment, the area of ​​the orthographic projection of the first compensation line 110 on the substrate has a fourth area, and the area where the orthographic projection of the first compensation line 110 on the substrate overlaps with the orthographic projection of the second initial signal line 32 on the substrate has a fourth overlapping area, and the fourth overlapping area can be greater than 80% of the fourth area.

[0287] In an exemplary embodiment, the second compensation line 120 may be in the shape of a straight line with a main portion extending along the second direction Y. The second compensation lines 120 in adjacent circuit units in the second direction Y in the third region are connected to each other as an integrated structure.

[0288] In an exemplary embodiment, the orthographic projection of the second compensation line 120 on the substrate at least partially overlaps with the orthographic projection of the initial connection line 47 on the substrate, which can effectively improve the transmittance and space utilization of the display substrate.

[0289] In an exemplary embodiment, the area of ​​the orthographic projection of the second compensation line 120 on the substrate has a fifth area, and the area where the orthographic projection of the second compensation line 120 on the substrate overlaps with the orthographic projection of the initial connection line 47 on the substrate has a fifth overlapping area, and the fifth overlapping area can be greater than 80% of the fifth area.

[0290] In an exemplary embodiment, the plurality of first compensation lines 110 and the plurality of second compensation lines 120 in the third region are an integrated structure interconnected to form a grid-like compensation line. The first compensation lines 110 and the second compensation lines 120 are configured so that the fifth conductive layer pattern of the third region presents a similar morphology to the fifth conductive layer patterns of the first region and the second region. This not only improves the uniformity of the preparation process, but also enables different regions to achieve substantially the same display effect under transmitted light and reflected light, effectively avoiding the poor appearance of the display substrate and improving the display quality.

[0291] In an exemplary embodiment, the plurality of first compensation lines 110 are interconnected with the plurality of second power lines 92, and the plurality of second compensation lines 120 are interconnected with the plurality of first power lines 91, thereby achieving interconnection between the grid-like power leads and the grid-like compensation lines.

[0292] In an exemplary embodiment, in the third area, at least one first power trace 91, at least one second power trace 92, at least one first compensation line 110, and at least one second compensation line 120 may be provided in at least one circuit unit. The first power trace 91 may be provided on one side of the circuit unit in the second direction Y, the first compensation line 110 may be provided on the side of the circuit unit in the opposite direction of the second direction Y, the second power trace 92 may be provided on one side of the second power line 80 in the first direction X, and the second compensation line 120 may be provided on one side of the second power line 80 in the opposite direction of the first direction X.

[0293] In an exemplary embodiment, an orthographic projection of the second compensation line 120 on the substrate at least partially overlaps an orthographic projection of the dummy line on the substrate.

[0294] As shown in Figures 20c and 20d, the fifth conductive layer pattern of multiple circuit units in the first area (E1 area) of the display area also includes: a first connecting line 71, a first power line 91, a second power line 92, a power connection electrode 93 and a second compensation line 120.

[0295] In an exemplary embodiment, the first connection line 71 may be in the shape of a straight line with a main portion extending along the first direction X. The first connection line 71 is connected to the data connection electrode 61 through the thirty-third via hole V33. Since the data connection electrode 61 is connected to the data signal line 60, the connection between the first connection line 71 and the data signal line 60 is achieved.

[0296] In this exemplary embodiment, the orthographic projection of the first connecting line 71 on the substrate at least partially overlaps the orthographic projection of the second initial signal line 32 on the substrate. Because the first connecting line 71 is located on the fifth conductive layer (SD3) and the second initial signal line 32 is located on the second conductive layer (GATE 2), with thicker first and second planar layers interposed between them, crosstalk is eliminated between the first connecting line 71 transmitting the data signal and the second initial signal line 32 transmitting the initial voltage signal. By overlapping the first connecting line 71 and the second initial signal line 32, the transmittance and space utilization of the display substrate can be effectively improved.

[0297] In an exemplary embodiment, the area of ​​the orthographic projection of the first connecting line 71 on the substrate has a second overlapping area, and the area where the orthographic projection of the first connecting line 71 on the substrate overlaps with the orthographic projection of the second initial signal line 32 on the substrate has a second area, and the second overlapping area can be greater than 80% of the second area.

[0298] In an exemplary embodiment, the first connection lines 71 in adjacent circuit units in the first direction X in the first region are connected to each other in an integrated structure.

[0299] In an exemplary embodiment, in at least one unit row including circuit units in the first region and circuit units in the third region, the first connecting line 71 in the first region and the first compensation line 110 in the third region can be located on the same straight line extending along the first direction X, so that the wiring in the first region and the wiring in the third region have similar morphologies. This not only improves the uniformity of the manufacturing process but also enables different regions to achieve substantially the same display effects under transmitted light and reflected light, effectively avoiding a poor appearance of the display substrate and improving the display quality.

[0300] In an exemplary embodiment, in at least one cell column including circuit units in the first region and circuit units in the third region, the first power trace 91 in the first region and the first power trace 91 in the third region may be located on the same straight line extending along the second direction Y, the power connection electrode 93 in the first region and the power connection electrode 93 in the third region may be located on the same straight line extending along the second direction Y, the first power traces 91 in adjacent circuit units in the first direction X in the first region are an integrated structure connected to each other, and the power connection electrode 93 is connected to the second power line 80 through the thirty-second via V32.

[0301] In an exemplary embodiment, in at least one unit column including circuit units of a first area and circuit units of a third area, the second power trace 92 of the first area and the second power trace 92 of the third area can be located on the same straight line extending along the second direction Y, and the second compensation line 120 of the first area and the second compensation line 120 of the third area can be located on the same straight line extending along the second direction Y. The difference is that the second power trace 92 and the second compensation line 120 in the circuit units adjacent in the second direction Y in the first area are discontinuous, that is, the second power traces 92 in the circuit units adjacent in the second direction Y are arranged at intervals, and the second compensation lines 120 in the circuit units adjacent in the second direction Y are arranged at intervals, so that the first connecting line 71 is arranged between the breaks of the second power trace 92 and the second compensation line 120.

[0302] As shown in FIG. 20 e and FIG. 20 f , the fifth conductive layer pattern of the plurality of circuit units in the second region (region E2 ) of the display region further includes: a second connection line 72 , a dummy connection electrode 73 and a first compensation line 110 .

[0303] In an exemplary embodiment, the shape of the second connection line 72 can be a straight line with a main portion extending along the second direction Y, the first end of the second connection line 72 is connected to the lead line located in the lead area, and the second end of the second connection line 72 is connected to the first connection line 71 located in the display area, so that the interconnected first connection line 71 and the second connection line 72 constitute a data connection line.

[0304] In an exemplary embodiment, the second connection lines 72 in the adjacent circuit units in the second direction Y in the second region are an integrated structure connected to each other.

[0305] In an exemplary embodiment, in at least one unit column including circuit units in the second region and circuit units in the third region, the first side connection lines of the second connection lines 72 in the second region and the second power supply lines 92 in the third region can be located on the same straight line extending along the second direction Y, and the second side connection lines of the second connection lines 72 in the second region and the second compensation lines 120 in the third region can be located on the same straight line extending along the second direction Y, so that the lines in the second region and the lines in the third region have similar morphologies, which not only improves the uniformity of the manufacturing process but also enables different regions to achieve substantially the same display effects under transmitted light and reflected light, effectively avoiding poor appearance of the display substrate and improving display quality and display quality.

[0306] In an exemplary embodiment, the shape of the dummy connecting electrode 73 can be rectangular, and the dummy connecting electrode 73 can be arranged on the side of the second connecting line 72 away from the data signal line 60 (i.e., the side close to the second power line 80) and connected to the second connecting line 72, and the orthographic projection of the dummy connecting electrode 73 on the substrate at least partially overlaps with the orthographic projection of the low-voltage power line 52 on the substrate.

[0307] In an exemplary embodiment, in at least one cell row including circuit cells in the second region and circuit cells in the third region, the dummy connection electrodes 73 in the second region and the power connection electrodes 93 in the third region may be located on the same straight line extending along the first direction X. In at least one cell column including circuit cells in the second region and circuit cells in the third region, the dummy connection electrodes 73 in the second region and the power connection electrodes 93 in the third region may be located on the same straight line extending along the second direction Y. That is, the position and shape of the dummy connection electrodes 73 in the circuit cells in the second region are substantially identical to the position and shape of the power connection electrodes 93 in the circuit cells in the third region. The difference is that the dummy connection electrodes 73 are not connected to the second power line 80 through vias. The dummy connection electrodes 73 are configured so that the fifth conductive layer patterns in the second region and the third region have similar morphologies. This not only improves the uniformity of the manufacturing process but also enables different regions to achieve substantially the same display effects under transmitted light and reflected light, effectively avoiding poor appearance of the display substrate and improving display quality.

[0308] In an exemplary embodiment, the shape of the first compensation line 110 can be a straight line segment with the main portion extending along the first direction X, the first end of the first compensation line 110 is connected to the second connecting line 72, and the second end of the first compensation line 110 extends along the first direction X or the opposite direction of the first direction X.

[0309] In an exemplary embodiment, at least two second connection lines 72 and two first compensation lines 110 may be provided in at least one circuit unit in the second region. The two second connection lines 72 may include a first side connection line and a second side connection line. The first side connection line may be provided between the second power line 80 and the data signal line 60, and the second side connection line may be provided on a side of the second power line 80 away from the data signal line 60. The at least two first compensation lines 110 may include at least one first side compensation line and at least one second side compensation line. The first end of the first side compensation line is connected to the first side connection line, and the second end of the first side compensation line extends toward the second side connection line. The first end of the second side compensation line is connected to the second side connection line, and the second end of the second side compensation line extends toward the first side connection line, so that the two first compensation lines 110 in the circuit unit form an interdigitated structure.

[0310] In an exemplary embodiment, in at least one unit row including circuit units of the second region and circuit units of the third region, the first side compensation line of the second region and the first power supply line 91 of the third region can be located on the same straight line extending along the first direction X, except that the first side compensation line is arranged at intervals in multiple circuit units in one unit row.

[0311] In an exemplary embodiment, in at least one unit row including circuit units of the second region and circuit units of the first region, the second side compensation line of the second region and the first connecting line 71 of the first region may be located on the same straight line extending along the first direction X, except that the second side compensation line is arranged at intervals in multiple circuit units of one unit row.

[0312] In an exemplary embodiment, in at least one unit row including circuit units of the first region, circuit units of the second region, and circuit units of the third region, the first power trace 91 of the first region, the first side compensation line of the first compensation line 110 of the second region, and the first power trace 91 of the third region can be located on the same straight line extending along the first direction X, the first connection line 71 of the first region, the second side compensation line of the first compensation line 110 of the second region, and the first compensation line 110 of the third region can be located on the same straight line extending along the first direction X, and the power connection electrode 93 of the first region, the dummy connection electrode 73 of the second region, and the power connection electrode 93 of the third region can be located on the same straight line extending along the first direction X.

[0313] In an exemplary embodiment, in at least one unit column including a circuit unit of a first region, a circuit unit of a second region, and a circuit unit of a third region, the second power supply line 92 of the first region, the first side connection line of the second connection line 72 of the second region, and the second power supply line 92 of the third region can be located on the same straight line extending along the second direction Y, the second compensation line 120 of the first region, the second side connection line of the second connection line 72 of the second region, and the second compensation line 120 of the third region can be located on the same straight line extending along the second direction Y, and the power connection electrode 93 of the first region, the dummy connection electrode 73 of the second region, and the power connection electrode 93 of the third region can be located on the same straight line extending along the second direction Y.

[0314] (10) Forming a third planar layer pattern. In an exemplary embodiment, forming the third planar layer pattern may include: coating a third planar film on the substrate on which the aforementioned pattern is formed, patterning the third planar film using a patterning process to form a third planar layer covering the fifth conductive layer, wherein a plurality of vias are provided on the third planar layer, as shown in FIG. 21 a to FIG. 21 c , FIG. 21 a is an enlarged view of the E0 region in FIG. 10 , FIG. 21 b is an enlarged view of the E1 region in FIG. 10 , and FIG. 21 c is an enlarged view of the E2 region in FIG. 10 .

[0315] In an exemplary embodiment, the via holes of each circuit unit in the display area include at least a forty-first via hole V41. In this exemplary embodiment, the orthographic projection of the forty-first via hole V41 on the substrate is located within the range of the orthographic projection of the second anode connecting electrode 53 on the substrate. The third planar layer within the forty-first via hole V41 is removed, exposing the surface of the second anode connecting electrode 53. The forty-first via hole V41 is configured to connect a subsequently formed anode to the second anode connecting electrode 53 through the via hole. To accommodate connections with subsequently formed anodes, the position of the forty-first via hole V41 may vary across multiple circuit units.

[0316] In an exemplary embodiment, the via patterns of the first region, the second region, and the third region are substantially the same.

[0317] At this point, the driving circuit layer is prepared on the substrate. On a plane parallel to the display substrate, the driving circuit layer may include multiple circuit units, each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a light-emitting control line, a data signal line, a first power line, a second power line, a first initial signal line, and a second initial signal line connected to the pixel driving circuit. On a plane perpendicular to the display substrate, the driving circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first flat layer, a fourth conductive layer, a second flat layer, a fifth conductive layer, and a third flat layer stacked in sequence on the substrate.

[0318] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0319] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The first insulating layer can be called a buffer layer, the second insulating layer and the third insulating layer can be called a gate insulating (GI) layer, the fourth insulating layer can be called an interlayer insulating (ILD) layer, and the fifth insulating layer can be called a passivation (PVX) layer. The first planar layer, the second planar layer and the third planar layer can be made of organic materials, such as resin. The semiconductor layer can be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene and the like, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.

[0320] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0321] (11) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer pattern disposed on the third flat layer, as shown in Figures 22a to 22d, wherein Figure 22a is an enlarged view of the E0 region in Figure 10, Figure 22b is an enlarged view of the E1 region in Figure 10, and Figure 22c is an enlarged view of the E2 region in Figure 10. Figure 22d is a planar schematic diagram of the anode conductive layer in Figure 22a.

[0322] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0323] In an exemplary embodiment, the anode conductive layer pattern may include a first anode 301R of a red light-emitting device, a second anode 301B of a blue light-emitting device, a third anode 301G1 of a first green light-emitting device, and a fourth anode 301G2 of a second green light-emitting device. The area where the first anode 301R is located can form a red sub-pixel R that emits red light, the area where the second anode 301B is located can form a blue sub-pixel B that emits blue light, the area where the third anode 301G1 is located can form a first green sub-pixel G1 that emits green light, and the area where the fourth anode 301G2 is located can form a second green sub-pixel G2 that emits green light.

[0324] In an exemplary embodiment, the first anode 301A and the second anode 301B may be sequentially arranged along the second direction Y, the third anode 301C and the fourth anode 301D may be sequentially arranged along the second direction Y, and the third anode 301C and the fourth anode 301D may be arranged on one side of the first anode 301A and the second anode 301B in the first direction X. Alternatively, the first anode 301A and the second anode 301B may be sequentially arranged along the first direction X, the third anode 301C and the fourth anode 301D may be sequentially arranged along the first direction X, and the third anode 301C and the fourth anode 301D may be arranged on one side of the first anode 301A and the second anode 301B in the second direction Y.

[0325] In an exemplary embodiment, the first anode 301R, the second anode 301B, the third anode 301G1, and the fourth anode 301G2 can be connected to the second anode connection electrode 53 in the corresponding circuit unit through the forty-first via hole V41. Since each anode is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the second anode connection electrode, the first anode connection electrode, and the third connection electrode in one circuit unit, the four anodes in one pixel unit are respectively connected to the pixel driving circuits of the four circuit units, thereby enabling the pixel driving circuit to drive the light-emitting device to emit light.

[0326] In an exemplary embodiment, the two second anodes 301B respectively connected to the pixel driving circuits in the M-th row, N-th column circuit unit and the M+1-th row, N+2-th column circuit unit have the same shape and position, the two first anodes 301R respectively connected to the pixel driving circuits in the M-th row, N+2-th column circuit unit and the M+1-th row, N-th column circuit unit have the same shape and position, the two fourth anodes 301G2 respectively connected to the pixel driving circuits in the M-th row, N+1-th column circuit unit and the M+1-th row, N+3-th column circuit unit have the same shape and position, and the two third anodes 301G1 respectively connected to the pixel driving circuits in the M-th row, N+3-th column circuit unit and the M+1-th row, N+1-th column circuit unit have the same shape and position.

[0327] In an exemplary embodiment, the anode shapes and areas of the four sub-pixels in a pixel unit may be the same or different, the positional relationship between the four sub-pixels in a pixel unit and the four circuit units in a circuit unit group may be the same or different, and the shapes and positions of the first anode 301R, the second anode 301B, the third anode 301G1 and the fourth anode 301G2 in different pixel units may be the same or different, and the present disclosure is not limited thereto.

[0328] In an exemplary embodiment, at least one of the first anode 301A, the second anode 301B, the third anode 301C and the fourth anode 301D may include a main body portion and a connecting portion connected to each other, the main body portion may be rectangular, the corners of the rectangle may be chamfered in an arc shape, and the connecting portion may be shaped like a strip extending in a direction away from the main body portion, and the connecting portion is connected to the second anode connecting electrode 53 through the forty-first via V41.

[0329] As shown in Figure 22a, in the third area, the orthographic projections of the main parts of the first anode 301A and the second anode 301B on the substrate at least partially overlap with the orthographic projections of a first power trace 91 and a first compensation line 110 on the substrate, the orthographic projections of the main parts of the first anode 301A and the second anode 301B on the substrate at least partially overlap with the orthographic projections of a second power trace 92 and two second compensation lines 120 on the substrate, and the orthographic projections of the main parts of the third anode 301C and the fourth anode 301D on the substrate at least partially overlap with the orthographic projection of a second power trace 92 on the substrate.

[0330] As shown in Figure 22b, in the first area, the orthographic projections of the main parts of the first anode 301A and the second anode 301B on the substrate at least partially overlap with the orthographic projections of a first power supply line 91 and a first connecting line 71 on the substrate, the orthographic projections of the main parts of the first anode 301A and the second anode 301B on the substrate at least partially overlap with the orthographic projections of a second power supply line 92 and two second compensation lines 120 on the substrate, and the orthographic projections of the main parts of the third anode 301C and the fourth anode 301D on the substrate at least partially overlap with the orthographic projection of a second power supply line 92 on the substrate.

[0331] As shown in Figure 22c, in the second region, the orthographic projections of the main parts of the first anode 301A and the second anode 301B on the substrate at least partially overlap with the orthographic projections of the two first compensation lines 110 on the substrate, the orthographic projections of the main parts of the first anode 301A and the second anode 301B on the substrate at least partially overlap with the orthographic projections of the three second connecting lines 72 on the substrate, and the orthographic projections of the main parts of the third anode 301C and the fourth anode 301D on the substrate at least partially overlap with the orthographic projection of one second connecting line 72 on the substrate.

[0332] In an exemplary embodiment, by comparing the orthographic projections of the first anode 301A and the second anode 301B on the substrate in the first, second, and third regions, it can be seen that the main bodies of the first anode 301A and the second anode 301B overlap with two horizontal lines (straight lines extending along the first direction X), and the main bodies of the first anode 301A and the second anode 301B overlap with three vertical lines (straight lines extending along the second direction Y). Therefore, the horizontal metal lines and the vertical metal lines of the SD3 layer below the main bodies of the first anode 301A and the second anode 301B in the three regions are substantially the same, which can ensure the flatness of the first anode 301A and the second anode 301B in the three regions, and can ensure that the luminous performance of the red light-emitting devices and the blue light-emitting devices in the three regions are substantially the same.

[0333] In the exemplary embodiment, by comparing the orthographic projections of the third anode 301C and the fourth anode 301D in the first region, the second region, and the third region on the substrate, it can be seen that

[0334] The orthographic projections of the main bodies of the third anode 301C and the fourth anode 301D on the substrate overlap with a vertical line but do not overlap with the horizontal line. Therefore, the horizontal metal lines and the vertical metal lines of the SD3 layer below the main bodies of the third anode 301C and the fourth anode 301D in the three regions are basically the same, which can ensure the flatness of the third anode 301C and the fourth anode 301D in the three regions and ensure that the luminous performance of the first green light-emitting device and the second green light-emitting device in the three regions is basically the same.

[0335] In an exemplary embodiment, the subsequent preparation process may include: first forming a pixel definition layer pattern, then using an evaporation or inkjet printing process to form an organic light-emitting layer, then forming a cathode on the organic light-emitting layer, and then forming an encapsulation structure layer. The encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0336] FIG23 is a schematic diagram of a planar structure of a power supply line according to an exemplary embodiment of the present disclosure. As shown in FIG23 , the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100 in the second direction Y, and a frame area 300 located on the other side of the display area 100. The frame area 300 may include an upper frame area 310 located on the side opposite to the second direction Y of the display area 100 (away from the binding area 200) and a side frame area 320 located on one or both sides of the first direction X of the display area 100. The display area 100 is provided with a power supply line 90 with a mesh-like interconnected structure, the binding area 200 is provided with a binding lead 510, the upper frame area 310 is provided with an upper frame lead 520, and the side frame area 320 is provided with a side frame lead 530. The power supply line 90 is connected to the binding lead 510, the upper frame lead 520, and the side frame lead 530, respectively.

[0337] In an exemplary embodiment, the binding leads 510 of the binding area 200 , the upper frame leads 520 of the upper frame area 310 , and the side frame leads 530 of the side frame area 320 may be an integrated structure connected to each other.

[0338] In an exemplary embodiment, the power supply traces 90 of the display area 100 may include a plurality of first power supply traces 91 extending along a first direction X and a plurality of second power supply traces 92 extending along a second direction Y. The plurality of first power supply traces 91 may be sequentially arranged along the second direction Y, with one or both ends extending in the first direction X to the side frame region 320 and then connected to the side frame lead 530. The plurality of second power supply traces 92 may be sequentially arranged along the first direction X, with one end extending in the second direction Y to the binding region 200 and then connected to the binding lead 510, and one end in the opposite direction of the second direction Y extending to the upper frame region 310 and then connected to the upper frame lead 520.

[0339] Figure 24 is a schematic diagram illustrating a connection between a power trace and a binding lead according to an exemplary embodiment of the present disclosure, and is an enlarged view of area D1 in Figure 23. As shown in Figure 24, the binding area 200 may include at least a binding lead 510, a first power connection line 511, and a first power pin 512.

[0340] In an exemplary embodiment, the bonding wire 510 may be disposed in the fourth conductive ( SD2 ) layer and may be in the shape of a bar extending along the first direction X. The bonding wire 510 is configured to connect to a power pad in the bonding pin.

[0341] In an exemplary embodiment, the first power connection line 511 and the first power pin 512 can be set in the fifth conductive (SD3) layer, and the first end of the first power connection line 511 is connected to the second power line 80 extending to the binding area 200 through a via hole opened on the second flat layer. The second end of the second power connection line 511 extends in a direction away from the display area and is directly connected to the first power pin 512. The first power pin 512 is connected to the binding lead 510 through multiple via holes opened on the second flat layer.

[0342] In an exemplary embodiment, the first power connection line 511 may be in a bar shape extending along the second direction Y, and the first power pin 512 may be connected to the second power line 80 through a plurality of first power connection lines 511 .

[0343] In an exemplary embodiment, the first power pin 512 can be shaped like a strip extending along the first direction X. This allows the binding wires 510 located in the fourth conductive layer and the first power pins 512 located in the fifth conductive layer to form a double-layer power routing, minimizing the voltage drop of the power signal and achieving low power consumption. By connecting the power routing in the display area with the binding wires in the binding area, the present disclosure can significantly reduce the width of the binding wires, significantly reducing the width of the binding area, and facilitating the implementation of full-screen displays.

[0344] In an exemplary embodiment, the first power connection line 511 and the first power pin 512 may be an integral structure connected to each other.

[0345] Figure 25 is a schematic diagram illustrating the connection between a power trace and an upper frame lead according to an exemplary embodiment of the present disclosure, and is an enlarged view of area D2 in Figure 23. As shown in Figure 25, upper frame region 310 may include at least an upper frame lead 520, a second power connection bar 521, a second power connection line 522, and a second power pin 523.

[0346] In an exemplary embodiment, the border lead 520 can be set in the fourth conductive (SD2) layer, and the shape of the upper border lead 520 can be a strip shape extending along the first direction X, and the upper border lead 520 is configured to be connected to the binding lead in the binding area through the side border lead of the side border area.

[0347] In an exemplary embodiment, a second power connection bar 521, a second power connection line 522, and a second power pin 523 can be disposed in the fifth conductive layer (SD3). The first end of the second power connection bar 521 is connected to the second power line 80 extending to the upper frame area 310 via a via provided in the second flat layer. The second end of the second power connection bar 521 is connected to the first end of the second power connection line 522. The second end of the second power connection line 522 extends away from the display area and is connected to the second power pin 523. The second power pin 523 is connected to the upper frame lead 520 via multiple vias provided in the second flat layer. By connecting the power traces in the display area with the upper frame leads in the upper frame area, the present disclosure can significantly reduce the width of the upper frame leads, thereby significantly reducing the width of the upper frame area, which is conducive to achieving full-screen display.

[0348] In an exemplary embodiment, the shape of the second power connection bar 521 can be a bar extending along the first direction X, the shape of the second power connection line 522 can be a bar extending along the second direction Y, the shape of the second power pin 523 can be rectangular, and the second power connection bar 521 can be connected to the upper frame lead 520 through multiple second power connection lines 522 and multiple second power pins 523.

[0349] In an exemplary embodiment, the second power connection bar 521 , the second power connection line 522 , and the second power pins 523 may be an integrated structure connected to each other.

[0350] Figure 26 is a schematic diagram illustrating a connection between a power trace and a side frame lead in an exemplary embodiment of the present disclosure, and is an enlarged view of area D3 in Figure 23. As shown in Figure 26, side frame region 320 may include at least side frame lead 530, third power connection line 531, and third power pin 532.

[0351] In an exemplary embodiment, the side frame lead 530 may be disposed in the fourth conductive (SD2) layer, and the side frame lead 530 may be in a strip shape extending along the second direction Y, and the side frame lead 530 may be configured to be connected to the binding lead 510 in the binding area.

[0352] In an exemplary embodiment, a third power connection line 531 and a third power pin 532 may be disposed in the fifth conductive layer (SD3). The first end of the third power connection line 531 is connected to the power trace 90 in the display area 100 via a via provided in the second planar layer. The second end of the third power connection line 531 extends away from the display area and is directly connected to the third power pin 532. The third power pin 532 is connected to the side frame lead 530 via multiple vias provided in the second planar layer. By connecting the power trace in the display area with the side frame lead in the side frame area, the present disclosure can significantly reduce the width of the side frame lead, thereby significantly reducing the width of the side frame area, which is conducive to achieving full-screen display.

[0353] In an exemplary embodiment, the shape of the third power connection line 531 can be a broken line extending along the first direction X, the shape of the third power pin 532 can be a bar extending along the second direction Y, and the power trace 90 can be connected to the side frame lead 530 through multiple third power connection lines 531 and third power pins 532.

[0354] In an exemplary embodiment, the third power connection line 531 and the third power pin 532 may be an integrated structure connected to each other.

[0355] It can be seen from the structure and preparation process of the display substrate described above that the present invention arranges data connection lines in the display area so that the lead lines of the binding area are connected to the data signal lines through the data connection lines, so that there is no need to arrange fan-shaped oblique lines in the lead area, which effectively reduces the length of the lead area, greatly reduces the width of the lower frame, and improves the screen-to-body ratio, which is conducive to achieving full-screen display.

[0356] In a display substrate, a display area includes a routing area where data connection lines are provided and a normal area where no data connection lines are provided. Because the data connection lines in the routing area have high reflectivity when exposed to external light, while the other metal lines in the normal area have weak reflectivity, the appearance of the normal area and the routing area is significantly different, resulting in a poor appearance of the display substrate, which is particularly noticeable when the screen is off or displaying low grayscale images. The exemplary embodiments of the present disclosure provide a second compensation line in a first area, a first compensation line in a second area, and a first and second compensation lines in a third area. This not only ensures that the different areas have substantially identical structures and achieve substantially identical display effects under both transmitted and reflected light, effectively avoiding poor appearance of the display substrate, but also ensures that the horizontal and vertical metal lines beneath the anodes in the three areas are substantially identical, ensuring substantially consistent anode flatness in the three areas and substantially consistent luminous performance of the light-emitting devices, avoiding significant color shift in viewing angles, and improving display quality.

[0357] The present disclosure realizes the structure of VSS in pixel by arranging the first power line and the second power line in the display area, and the first power line and the second power line constitute the power line of the mesh-connected structure, which can not only effectively reduce the resistance of the power line, effectively reduce the voltage drop of the low-voltage power signal, and achieve low power consumption, but also effectively improve the uniformity of the power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality. The present disclosure can greatly reduce the width of the power line by connecting the power line with the power lead in the binding area and the frame area, greatly reduce the frame width, and is conducive to achieving full-screen display. The preparation process disclosed in the present disclosure is well compatible with the existing preparation process, the process is simple to implement, easy to implement, high production efficiency, low production cost, and high yield rate.

[0358] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0359] The structure and preparation process shown above in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0360] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0361] The present disclosure further provides a display device including the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system, but the embodiments of the present invention are not limited thereto.

[0362] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the present invention. Any person skilled in the art may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the present invention shall still be based on the scope defined by the appended claims.

Claims

1. A display substrate, comprising a display area, wherein the display area comprises a driving circuit layer arranged on a substrate and a light-emitting structure layer arranged on a side of the driving circuit layer away from the substrate, the driving circuit layer comprises a plurality of circuit units, a plurality of data signal lines, a plurality of data connection lines, a plurality of low-voltage power lines and a plurality of power supply lines, the light-emitting structure layer comprises a plurality of light-emitting devices, the circuit unit comprises a pixel driving circuit, the data signal line is configured to provide a data signal to the pixel driving circuit, and the low-voltage power line is configured to continuously provide a low power supply voltage signal to the light-emitting device; the data connection line is connected to the data signal line, and the power supply line is connected to the low-voltage power line.

2. The display substrate according to claim 1, wherein: The data connection line includes a first connection line extending along a first direction and a second connection line extending along a second direction, the first connection line is connected to the second connection line, the power line includes a first power line extending along the first direction and a second power line extending along the second direction, the first power line is connected to the second power line, and the first direction and the second direction intersect; on a plane parallel to the substrate, the display area at least includes a first area where the first connection line is arranged, at least one circuit unit in the first area includes the first connection line, the first power line and the second power line, the shape of the data signal line and the low-voltage power line is a line shape extending along the second direction, the first connection line is connected to the data signal line, the second power line is arranged between the low-voltage power line and the data signal line, and the second power line is connected to the low-voltage power line.

3. The display substrate according to claim 2, wherein: The driving circuit layer includes a plurality of conductive layers arranged in sequence on a substrate; the first connecting line and the second connecting line are arranged in the same conductive layer, and the first connecting line and the data signal line are arranged in different conductive layers; in at least one circuit unit in the first area, the first connecting line is connected to the data signal line through a first connecting hole.

4. The display substrate according to claim 2, wherein: The driving circuit layer includes multiple conductive layers arranged in sequence on the substrate; the first power line and the second power line are arranged in the same conductive layer, and the second power line and the low-voltage power line are arranged in different conductive layers; in at least one circuit unit in the first area, the second power line is connected to the low-voltage power line through a second connecting hole.

5. The display substrate according to claim 2, wherein: At least one circuit unit in the first area also includes a power connection electrode, which is arranged on a side of the second power line away from the data signal line and is connected to the second power line. The orthographic projection of the power connection electrode on the substrate at least partially overlaps with the orthographic projection of the low-voltage power line on the substrate, and the power connection electrode is connected to the low-voltage power line through a second connection hole.

6. The display substrate according to claim 2, wherein: In the first region, the first connection lines in the circuit units adjacent to each other in the first direction are connected to each other, and the first power supply lines in the circuit units adjacent to each other in the first direction are connected to each other.

7. The display substrate according to claim 2, wherein: In the first region, the second power lines in the circuit units adjacent to each other in the second direction are arranged at intervals, and the first connecting line is arranged between the second power lines adjacent to each other in the second direction.

8. The display substrate according to claim 2, wherein: At least one circuit unit in the first area also includes a second compensation line extending along the second direction, the second compensation line is arranged on a side of the second power line away from the data signal line, the second compensation line is connected to the first power line, the second compensation lines in the adjacent circuit units in the second direction are arranged at intervals, and the first connecting line is arranged between the adjacent second compensation lines in the second direction.

9. The display substrate according to claim 2, wherein: On a plane parallel to the substrate, the display area further includes a second area provided with the second connecting line, at least one circuit unit in the second area includes the second connecting line, and the second connecting lines in the circuit units adjacent to each other in the second direction are connected to each other.

10. The display substrate according to claim 9, wherein: At least one circuit unit in the second area includes two second connecting lines, and the two second connecting lines include a first side connecting line and a second side connecting line. The first side connecting line is arranged between the low-voltage power line and the data signal line, and the second side connecting line is arranged on a side of the low-voltage power line away from the data signal line.

11. The display substrate according to claim 10, wherein: At least one circuit unit of the second area also includes a dummy connecting electrode, which is arranged on a side of the second side connecting line close to the first side connecting line and is connected to the second side connecting line, and the orthographic projection of the dummy connecting electrode on the substrate at least partially overlaps with the orthographic projection of the low-voltage power line on the substrate.

12. The display substrate according to claim 11, wherein: In at least one unit column including the circuit units of the first area and the circuit units of the second area, the second power supply wiring of the first area and the first side connection line of the second area are located on the same straight line extending along the second direction, the second compensation line of the first area and the second side connection line of the second area are located on the same straight line extending along the second direction, and the power supply connection electrode of the first area and the dummy connection electrode of the second area are located on the same straight line extending along the second direction; In at least one unit row including the circuit units in the first region and the circuit units in the second region, the power connection electrodes in the first region and the dummy connection electrodes in the second region are located on the same straight line extending along the first direction.

13. The display substrate according to claim 10, wherein: At least one circuit unit in the second area also includes at least two first compensation lines extending along the first direction, the at least two first compensation lines include at least one first side compensation line and at least one second side compensation line, the first end of the first side compensation line is connected to the first side connecting line, the second end of the first side compensation line extends in a direction close to the second side connecting line, the first end of the second side compensation line is connected to the second side connecting line, and the second end of the second side compensation line extends in a direction close to the first side connecting line.

14. The display substrate according to claim 13, wherein: In at least one unit row including circuit units of the first area and circuit units of the second area, the first power line of the first area and the first side compensation line of the second area are located on the same straight line extending along the first direction, and the first connection line of the first area and the second side compensation line of the second area are located on the same straight line extending along the first direction.

15. The display substrate according to claim 2, wherein: On a plane parallel to the substrate, the display area also includes a third area that does not overlap with the orthographic projections of the first connecting line and the second connecting line on the substrate, and at least one circuit unit in the third area includes the first power line and the second power line, and the second power line is connected to the low-voltage power line through a second connecting hole.

16. The display substrate according to claim 15, wherein: At least one circuit unit in the third area also includes a power connection electrode, which is arranged on a side of the second power line away from the data signal line and is connected to the second power line. The orthographic projection of the power connection electrode on the substrate at least partially overlaps with the orthographic projection of the low-voltage power line on the substrate, and the power connection electrode is connected to the low-voltage power line through the second connection hole.

17. The display substrate according to claim 15, wherein: The first power supply lines in the circuit units adjacent to each other in the first direction are connected to each other, and the second power supply lines in the circuit units adjacent to each other in the second direction are connected to each other.

18. The display substrate according to claim 15, wherein: At least one circuit unit in the third area also includes a first compensation line extending along the first direction and a second compensation line extending along the second direction, the first compensation lines in the circuit units adjacent to each other in the first direction are connected to each other, the second compensation lines in the circuit units adjacent to each other in the second direction are connected to each other, the first compensation line is connected to the second power line, the second compensation line is connected to the first power line, and the first compensation line is connected to the second compensation line.

19. The display substrate according to claim 18, wherein: In at least one unit row including circuit units of the first area and circuit units of the third area, the first connecting line of the first area and the first compensation line of the third area are located on the same straight line extending along the first direction; in at least one unit column including circuit units of the first area and circuit units of the third area, the second compensation line of the first area and the second compensation line of the third area are located on the same straight line extending along the second direction.

20. The display substrate according to claim 2, wherein: On a plane parallel to the substrate, the display area further includes: a second area where the second connecting line is arranged, and a third area which does not overlap with the orthographic projections of the first connecting line and the second connecting line on the substrate; in at least one unit row including the circuit unit of the first area, the circuit unit of the second area and the circuit unit of the third area, the first power supply line of the first area, the first side compensation line of the first compensation line of the second area and the first power supply line of the third area are located on the same straight line extending along the first direction, the first connecting line of the first area, the second side compensation line of the first compensation line of the second area and the first compensation line of the third area are located on the same straight line extending along the first direction, and the power connection electrode of the first area, the dummy connection electrode of the second area The connection electrode and the power connection electrode of the third area are located on the same straight line extending along the first direction; in at least one unit column including the circuit unit of the first area, the circuit unit of the second area and the circuit unit of the third area, the second power routing of the first area, the first side connection line of the second connection line of the second area and the second power routing of the third area are located on the same straight line extending along the second direction, the second compensation line of the first area, the second side connection line of the second connection line of the second area and the second compensation line of the third area are located on the same straight line extending along the second direction, and the power connection electrode of the first area, the dummy connection electrode of the second area and the power connection electrode of the third area are located on the same straight line extending along the second direction.

21. The display substrate according to claim 2, wherein: The display substrate also includes a binding area located on one side of the display area in the second direction, and the binding area at least includes a binding lead, a first power connection line and a first power pin, a first end of the first power connection line is connected to the low-voltage power line through a via, a second end of the second power connection line extends in a direction away from the display area and is connected to the first power pin, and the first power pin is connected to the binding lead through a via.

22. The display substrate according to claim 2, wherein: The display substrate also includes an upper frame area located on the opposite side of the second direction of the display area, and the upper frame area at least includes an upper frame lead, a second power connection bar, a second power connection line and a second power pin, a first end of the second power connection bar is connected to the low-voltage power line through a via, a second end of the second power connection bar is connected to a first end of the second power connection line, a second end of the second power connection line extends in a direction away from the display area and is connected to the second power pin, and the second power pin is connected to the upper frame lead through a via.

23. The display substrate according to claim 2, wherein: The display substrate also includes a side frame area located on one side or both sides of the display area in the first direction, and the side frame area at least includes a side frame lead, a third power connection line and a third power pin, a first end of the third power connection line is connected to the power line through a via, a second end of the third power connection line extends in a direction away from the display area and is connected to the third power pin, and the third power pin is connected to the side frame lead through a via.

24. The display substrate according to claims 1 to 23, wherein: The pixel driving circuit includes at least a storage capacitor and a plurality of transistors; on a plane perpendicular to the substrate, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially arranged on the substrate, the semiconductor layer includes at least an active layer of a plurality of transistors, the first conductive layer includes at least gate electrodes of a plurality of transistors and a first plate of a storage capacitor, the second conductive layer includes at least a second plate of a storage capacitor, the third conductive layer includes at least a first electrode and a second electrode of a plurality of transistors, the fourth conductive layer includes at least the data signal line and the low-voltage power line, and the fifth conductive layer includes at least the data connection line and the power line.

25. The display substrate according to claim 24, wherein: The third conductive layer also includes a first power line, which is configured to continuously provide a high power voltage signal to the pixel driving circuit. The orthographic projection of the low-voltage power line on the substrate at least partially overlaps with the orthographic projection of the first power line on the substrate and has a first overlapping area. The orthographic projection of the first power line on the substrate has a first area, and the first overlapping area is greater than 0.8*the first area.

26. The display substrate according to claim 24, wherein: The second conductive layer also includes a second initial signal line, which is configured to provide a second initial signal to the pixel driving circuit. The orthographic projection of a first data connection line on the substrate at least partially overlaps with the orthographic projection of the second initial signal line on the substrate and has a second overlapping area. The orthographic projection of the first connection line on the substrate has a second area, and the second overlapping area is greater than 0.8*the second area.

27. A display device comprising the display substrate according to any one of claims 1 to 26.

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