Semiconductor process chamber and semiconductor process apparatus

Abstract

Disclosed in the present disclosure are a semiconductor process chamber and a semiconductor process apparatus, relating to the field of semiconductor apparatus. The semiconductor process chamber comprises a cavity and a lower electrode structure, the lower electrode structure being arranged in the cavity. In the lower electrode structure, a base is connected to the cavity by means of a cantilever, and an interface member and a bearing member are stacked on the base. A lining is annularly arranged outside the lower electrode structure, one end of the lining being electrically connected to the cavity, and the other end of the lining being electrically connected to the interface member. The first end of a shielding member is connected to the interface member, and the second end thereof is connected to the inner wall of the base. The axis of the first end of the shielding member does not coincide with the axis of the interface member, and the axis of the first end of the shielding member deviates from the axis of the interface member in the direction away from the cantilever. A radio frequency feed-in member passes through the shielding member and is connected to the bearing member. The semiconductor process apparatus comprises the semiconductor process chamber. The present disclosure may solve the problems of etching uniformity and the like caused by asymmetric geometric structures of elements in etching apparatuses.

Description

Semiconductor process chambers and semiconductor process equipment Technical Field

[0001] The present disclosure belongs to the technical field of semiconductor equipment, and particularly relates to a semiconductor process chamber and semiconductor process equipment. Background Art

[0002] With the development of semiconductor manufacturing processes, the requirements for uniformity in semiconductor etching processes are becoming increasingly stringent. In semiconductor etching process equipment, such as ICP (Inductively Coupled Plasma) etching equipment, the coil of the upper electrode generates plasma inside the chamber through inductive coupling. At the same time, radio frequency power of a certain frequency is applied to the lower electrode. The radio frequency power acts on the plasma on the wafer surface through capacitive coupling, thereby controlling the energy of the ions reaching the wafer surface. High-energy ions bombard the wafer surface, destroying the CF film produced during the etching process, which acts as a barrier to the etching reaction, thereby accelerating the etching rate.

[0003] Based on the above, we can see that the main factors affecting etching process uniformity include: plasma uniformity on the wafer surface, uniformity of ion energy distribution controlled by the lower electrode loop, and uniformity of density distribution of etching reactants reaching the wafer surface. The symmetry of the lower electrode loop is a key factor in determining etching process uniformity. However, in some etching equipment, the geometric asymmetry of components (such as the wafer transfer port, exhaust port, and cantilever) can have a significant impact on etching uniformity.

[0004] Summary of the Invention

[0005] The purpose of the embodiments of the present disclosure is to provide a semiconductor process chamber and semiconductor process equipment, which can solve the problem of the asymmetric geometric structure of components in current etching equipment affecting etching uniformity.

[0006] In order to solve the above technical problems, the present disclosure is implemented as follows:

[0007] An embodiment of the present disclosure provides a semiconductor process chamber, comprising: a cavity and a lower electrode structure, wherein the liner and the lower electrode structure are both disposed in the cavity;

[0008] The lower electrode structure includes a base, an interface component, a carrier, a radio frequency feed component and a shielding component; the carrier is used to carry the wafer;

[0009] The base is connected to the side wall of the cavity through a cantilever;

[0010] The interface component and the bearing component are sequentially stacked on the base along a first direction;

[0011] The first end of the shielding member is connected to the interface member, and the second end of the shielding member is connected to the inner wall of the base; the axis of the first end of the shielding member does not coincide with the axis of the interface member, and the axis of the first end of the shielding member is offset relative to the axis of the interface member in a direction away from the cantilever;

[0012] The radio frequency feeding component is disposed in the shielding component and connected to the supporting component after passing through the interface component along the first direction, so as to feed radio frequency power to the supporting component.

[0013] An embodiment of the present disclosure further provides a semiconductor process equipment, including the above-mentioned semiconductor process chamber.

[0014] In the embodiment of the present disclosure, a carrier is used to carry a wafer, and an RF feed is connected to the carrier for feeding RF power to the carrier, so that the RF power acts on the plasma on the wafer surface to control the ion energy reaching the wafer surface. A shield is arranged on the outside of the RF feed to play a shielding role, which can reduce energy loss; a first end of the shield is connected to the interface part, and a second end of the shield is connected to the inner wall of the base, the axis of the first end of the shield does not coincide with the axis of the interface part, and the axis of the first end of the shield is offset in a direction away from the cantilever relative to the axis of the interface part, so that the inductance on the side away from the cantilever can be increased to compensate for the impedance difference between the lower electrode loop on the side close to the cantilever and the side away from the cantilever, thereby compensating for the asymmetry of the lower electrode loop caused by the inherent asymmetry of the geometric distribution of components in the semiconductor process chamber, and further making the current density in the electrode loop more uniform to improve the uniformity of the etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG1 is a schematic structural diagram of a semiconductor process chamber disclosed in an embodiment of the present disclosure;

[0016] FIG2 is a schematic structural diagram of the lower electrode structure disclosed in an embodiment of the present disclosure;

[0017] FIG3 is a schematic diagram of the relative position relationship between the RF feedthrough and the carrier according to an embodiment of the present disclosure;

[0018] FIG4 is a schematic diagram showing the relative positional relationship of the interface component, the shielding component, the second insulating component, the RF feedthrough component, the cantilever, and the matching device according to an embodiment of the present disclosure;

[0019] FIG5 is a schematic diagram showing the relative positional relationship among the shielding member, the RF feedthrough, and one form of the second insulating member disclosed in an embodiment of the present disclosure;

[0020] FIG6 is a schematic diagram showing the relative positional relationship among the shielding member, the RF feedthrough, and another type of second insulating member disclosed in an embodiment of the present disclosure;

[0021] FIG7 is a current density distribution curve on both sides of a semiconductor process chamber when the difference between the first distance and the second distance disclosed in an embodiment of the present disclosure is 10 mm;

[0022] FIG8 is a normalized current density distribution curve on both sides of a semiconductor process chamber under conditions where the difference between the first distance and the second distance is 50 mm and 100 mm, when the second sub-insulating member is made of resin according to an embodiment of the present disclosure;

[0023] FIG9 is a normalized current density distribution curve on both sides of the semiconductor process chamber when the second sub-insulating member is air and the distance difference between the first distance and the second distance is 50 mm and 100 mm, respectively, in an embodiment of the present disclosure.

[0024] Explanation of the accompanying drawings: 100-lower electrode structure; 110-base; 111-first side wall; 120-interface component; 121-through hole; 130-first insulating component; 140-carrying component; 150-RF feeding component; 160-shielding component; 170-second insulating component; 171-first sub-insulating component; 172-second sub-insulating component; 173-interface; 200-lining; 300-grounding ring; 400-cavity; 500-cantilever; 600-matching device; a-first distance; b-second distance; e-third distance; f-fourth distance. DETAILED DESCRIPTION

[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0026] The terms "first", "second", etc. in the specification and claims of the present disclosure are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present disclosure can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects related to each other are in an "or" relationship.

[0027] The embodiments of the present disclosure are described in detail below through specific embodiments and their application scenarios with reference to the accompanying drawings.

[0028] In the electrode structure of the related art, RF power is loaded onto the electrostatic chuck by the RF source through the RF matcher. Specifically, the RF power output by the RF matcher is fed into the center of the electrostatic chuck through the RF connecting column. However, the RF connecting column, electrostatic chuck, insulating ring, interface disk, shielding sleeve and other components are all concentrically arranged. Due to the presence of the cantilever, the chamber itself is not completely geometrically symmetrical, resulting in differences in the current paths on the cantilever side and the opposite side. Specifically, in the current loop on the RF matcher side, the current on the lining is opposite to the current on the shielding sleeve, and there is a magnetic field cancellation effect, resulting in the loop inductance on the RF matcher side being smaller than the loop inductance on the opposite side, resulting in current asymmetry on both sides, affecting the uniformity of the etching process.

[0029] In order to solve the above problems, the embodiments of the present disclosure disclose an improved semiconductor process chamber, which comprehensively considers the impact of the asymmetry of geometric elements on the current, thereby effectively solving the asymmetry of the current and ensuring the uniformity of the etching process.

[0030] 1 to 9 , the disclosed semiconductor process chamber includes a cavity 400 and a lower electrode structure 100. The lower electrode structure 100 is disposed in the cavity 400.

[0031] The lower electrode structure 100 includes a base 110, an interface component 120, a carrier 140, a radio frequency feedthrough 150, and a shielding component 160. In addition, the lower electrode structure 100 may further include other components to ensure normal use of the lower electrode structure 100.

[0032] In some embodiments, the semiconductor process chamber may further include a liner 200, which is disposed within the cavity 400 and surrounds the outer side of the lower electrode structure 100 to protect the cavity 400 from plasma etching. One end of the liner 200 is electrically connected to the cavity 400, and the other end of the liner 200 is electrically connected to the interface component 120. In this way, electrical conduction between the interface component 120 and the cavity 400 can be achieved through the liner 200.

[0033] Among them, the base 110 is the basic installation component of the lower electrode structure 100, which can provide a supporting foundation for components such as the interface component 120, the supporting component 140, and the shielding component 160. In some embodiments, the base 110 can be connected to the side wall of the cavity 400 through the cantilever 500. In this way, the base 110 can be installed and supported by the cantilever 500.

[0034] The carrier 140 is used to carry the wafer, and the interface component 120 is used to connect the shielding component 160 and can also support the carrier 140. In some embodiments, the interface component 120 and the carrier 140 are stacked on the base 110 in sequence along a first direction. Under actual use conditions, the interface component 120 can be installed on top of the base 110, and the carrier 140 can be installed on top of the interface component 120, so that the interface component 120 can be supported by the base 110, and the carrier 140 can be supported by the interface component 120. Among them, the above-mentioned first direction can be understood as a direction from bottom to top under actual use conditions, as shown in Figure 2.

[0035] Exemplarily, the carrier 140 may be a carrier plate, such as an electrostatic chuck. Preferably, the carrier plate may be a circular disk having a carrier surface for supporting the wafer. Furthermore, the carrier 140 allows the fed RF power to act on the plasma on the wafer surface, thereby controlling the ion energy of the plasma reaching the wafer surface.

[0036] The interface member 120 may be an interface disk, for example, a circular disk, which may provide a mounting base for the shielding member 160 and ensure the mounting stability of the shielding member 160. In addition, the interface disk may be provided with an opening to facilitate the passage of the RF feedthrough 150.

[0037] The first end of the shielding member 160 is connected to the interface member 120, and the second end of the shielding member 160 is connected to the inner wall of the base 110. The RF feedthrough 150 is disposed within the shielding member 160 and passes through the interface member 120 in a first direction before connecting to the carrier 140, thereby feeding RF power into the carrier 140. Therefore, by placing the shielding member 160 over the outer surface of the RF feedthrough 150, a portion of the RF feedthrough 150 within the cavity of the base 110 can be shielded, achieving a shielding effect, effectively mitigating energy loss, and, to a certain extent, reducing the impact on the etching process.

[0038] To accommodate the shape of the RF feedthrough 150, the shielding member 160 may be a shielding cylinder. Specifically, the shielding member 160 may include a straight section and a curved section that are connected or integrally arranged. The end of the curved section facing away from the straight section serves as the first end of the shielding member 160, while the end of the straight section facing away from the curved section serves as the second end of the shielding member 160. Thus, the shielding member 160 can shield the portion of the RF feedthrough 150 that penetrates the base 110, thereby providing a shielding effect.

[0039] It should be noted here that the RF feedthrough 150 is used to connect to the matcher 600, and the matcher 600 is arranged on one side outside the cavity 400, so that the matcher 600 is also located on one side of the lower electrode structure 100. In this way, in the embodiment of the present disclosure, the side wall of the base 110 close to the matcher 600 (or close to the cantilever 500) can be defined as the first side wall 111.

[0040] In order to allow the RF feedthrough 150 to penetrate the base 110, an opening can be provided in the first side wall 111 of the base 110, so that the RF feedthrough 150 enters the cavity of the base 110 through the opening, passes through the interface component 120 and extends toward the carrier 140, and finally connects with the carrier 140, so as to facilitate the transmission of the RF power output by the RF source through the matcher 600 to the carrier 140, thereby controlling the ion energy reaching the surface of the wafer carried by the carrier 140.

[0041] In the embodiment of the present disclosure, the lower electrode structure 100 is fixed to the cavity 400 by the cantilever 500, thereby ensuring the firmness and stability of the installation of the lower electrode structure 100. For example, the cantilever 500 can be provided with a cantilever channel, and the shielding member 160 can pass through the first side wall 111 and then pass into the cantilever channel, and finally connect with the side wall of the cavity 400. In this way, a section of the RF feed 150 located between the first side wall 111 of the base 110 and the side wall of the cavity 400 can be shielded to achieve a shielding effect, effectively alleviate energy loss, and to a certain extent reduce the impact on the etching process; in addition, the cantilever channel is mainly used to connect external cables and pipes, and is also used to achieve grounding with the cavity 400 to form an electrical circuit.

[0042] Taking into account the existence of components such as the cantilever 500, and the RF feedthrough 150 from the side where the cantilever 500 (or the matcher 600) is located, the geometric structure of the lower electrode structure 100 is asymmetric on the side close to the cantilever 500 and the side away from the cantilever 500, resulting in differences in current density in the respective loops of the lower electrode structure 100 on the side close to the cantilever 500 and the side away from the cantilever 500, which in turn affects the uniformity of etching.

[0043] Based on the above, in the disclosed embodiment, the axis of the first end of shielding member 160 does not coincide with the axis of interface member 120, and the axis of the first end of shielding member 160 deviates from the axis of interface member 120 in a direction away from cantilever 500 to increase the inductance on that side, thereby compensating for the impedance difference between the lower electrode loop on the side closer to the cantilever and the side farther away from the cantilever. This compensates for the asymmetry of the lower electrode loop caused by the inherent asymmetric geometric distribution of components in a semiconductor process chamber, thereby making the current density in the electrode loop more uniform and improving the uniformity of the etching process.

[0044] In some embodiments, the axis of the feeding end of the RF feedthrough 150 does not coincide with the axis of the first end of the shield 160, and the axis of the feeding end of the RF feedthrough 150 is offset relative to the axis of the first end of the shield 160 toward the cantilever 500. As shown in FIG4 , the RF feedthrough 150 and the shield 160 are non-concentric structures, and the distance from the axis of the first end of the shield 160 to the first sidewall 111 is greater than the distance from the axis of the feeding end of the RF feedthrough 150 to the first sidewall 111. Specifically, the distance from the edge of the first end of the shield 160 on the side close to the first sidewall 111 to the axis of the RF feedthrough 150 is a third distance e, and the distance from the edge of the first end of the shield 160 on the side away from the first sidewall 111 to the axis of the RF feedthrough 150 is a fourth distance f, and the third distance e is less than the fourth distance f.

[0045] Furthermore, the axis of the feeding end of the RF feeding element 150 is located between the axis of the first end of the shielding element 160 and the axis of the interface element 120 .

[0046] Based on the above settings, the inductance in the respective loops on the side close to the cantilever 500 and the side away from the cantilever 500 can be adjusted, so that the current density in the loops on both sides is also adjusted, that is, the current density difference in the loops on both sides is compensated, so that the current density in the loop close to the matcher side and the current density in the loop away from the matcher side can be symmetrical, thereby ensuring the uniformity of the etching process.

[0047] Referring to FIG. 2 , since the RF feedthrough 150 passes through the interface member 120, the lower electrode structure 100 may further include a second insulating member 170 to insulate the RF feedthrough 150. Accordingly, the interface member 120 may be provided with a through hole 121, in which the second insulating member 170 is disposed, and the RF feedthrough 150 passes through the second insulating member 170. Thus, the provision of the through hole 121 provides installation space for the second insulating member 170, and the second insulating member 170 separates the RF feedthrough 150 from the interface member 120, thereby achieving insulation for the RF feedthrough 150.

[0048] Furthermore, the first end of the shielding member 160 is connected to the through hole 121 of the interface member 120, and the axis of the first end of the shielding member 160 is collinear with the axis of the second insulating member 170. At this time, the axis of the through hole 121, the axis of the first end of the shielding member 160, and the axis of the second insulating member 170 are collinear. However, since the axis of the feeding end of the RF feedthrough 150 is not collinear with the axis of the first end of the shielding member 160, the axis of the feeding end of the RF feedthrough 150 is also not collinear with the axis of the second insulating member 170. Specifically, the width dimension of the second insulating member 170 on the side of the RF feedthrough 150 close to the cantilever 500 is smaller than the width dimension of the second insulating member 170 on the side of the RF feedthrough 150 away from the cantilever 500, so as to ensure the assembly between the interface member 120 and the shielding member 160 and facilitate the assembly of the RF feedthrough 150. The width dimension is parallel to the radial direction of the through hole 121 from the cantilever 500 to away from the cantilever 500 .

[0049] To accommodate the installation of the RF feedthrough 150, the through hole 121 can be disposed on the interface member 120 at a position that is offset from the cantilever 500 relative to the axis of the interface member 120. That is, the axis of the through hole 121 is located on the side of the axis of the interface member 120 that is away from the cantilever 500. This allows the second insulating member 170 installed therein to accommodate the installation of the RF feedthrough 150, thereby preventing assembly interference between components.

[0050] In addition, the distance from the edge of the interface member 120 on the side close to the cantilever 500 to the axis of the through hole 121 is a fifth distance, and the distance from the edge of the interface member 120 on the side away from the cantilever 500 to the axis of the through hole 121 is a sixth distance, and the fifth distance is greater than the sixth distance. That is, the width of the portion of the interface member 120 close to the cantilever 500 is greater than the width of the portion away from the cantilever 500, so as to facilitate the installation of the RF feedthrough 150. It should be noted that the difference between the fifth distance and the sixth distance depends on the eccentricity of the RF feedthrough 150 and the eccentricity of the second insulating member 170. In actual design, it is sufficient to ensure the assembly of the interface member 120 and the shielding member 160.

[0051] 4 to 6 , in some embodiments, the second insulating member 170 may include a first sub-insulating member 171 and a second sub-insulating member 172 that are compatible with each other, wherein the first sub-insulating member 171 is located on a side close to the cantilever 500, and the second sub-insulating member 172 is located on a side away from the cantilever 500. Furthermore, the capacitance between the RF feedthrough 150 and the interface component 120 on the side where the first sub-insulating member 171 is located is greater than the capacitance between the interface component 120 on the side where the second sub-insulating member 172 is located. This arrangement ensures that the capacitance between the interface component 120 and the RF feedthrough 150 on the side away from the cantilever 500 is smaller, thereby reducing the impedance of the circuit on the side away from the cantilever 500 and compensating for the impedance inconsistency between the two circuits.

[0052] Furthermore, on a plane perpendicular to the axis of the second insulating member 170, the projected area of ​​the first sub-insulating member 171 is smaller than the projected area of ​​the second sub-insulating member 172. This arrangement creates asymmetry between the first sub-insulating member 171 and the second sub-insulating member 172, facilitating adjustment of the capacitance between the portion of the second insulating member 170 proximal to the cantilever 500 and the portion of the second insulating member 170 distal to the cantilever 500, thereby adjusting the impedance of the loops on both sides and, in turn, adjusting the current density in the circuits on both sides. This compensates for the difference in current density between the two circuits, making the current density more uniform and improving etching uniformity.

[0053] To achieve asymmetry, the first sub-insulator 171 and the second sub-insulator 172 may also have different relative dielectric constants. In some embodiments, the relative dielectric constant of the first sub-insulator 171 may be greater than the relative dielectric constant of the second sub-insulator 172. This further ensures that the capacitance between the interface component 120 and the RF feedthrough 150 on the side away from the cantilever 500 is smaller, thereby reducing the impedance of the loop on the side away from the cantilever 500 and compensating for the impedance disparity between the two loops.

[0054] In other embodiments, the first sub-insulator 171 and the second sub-insulator 172 may also have the same relative dielectric constant, which can be selected according to actual working conditions.

[0055] In other embodiments, the projected area of ​​the second insulating member 170 on a plane perpendicular to the axis of the second insulating member 170 is smaller than the projected area of ​​the through hole 121, and the second insulating member 170 is disposed on the side of the through hole 121 closest to the cantilever 500. In this case, the portion of the through hole 121 not provided with the second insulating member 170 can be filled with air. In this case, the air can also serve as a special medium to provide a certain degree of insulation. It can also be understood that the second insulating member 170 is not present on the side of the through hole 121 away from the cantilever 500, and insulation is achieved by air. It should be noted that air can be considered an insulating medium with a relative dielectric constant of 1. In addition, the relative dielectric constant of the second insulating member 170 is greater than 1 to reduce the loop impedance on the side away from the matcher.

[0056] In the embodiment of the present disclosure, when the second insulating member 170 includes a first sub-insulating member 171 and a second sub-insulating member 172, the material of the first sub-insulating member 171 can be ceramic, and the material of the second sub-insulating member 172 can be resin, and the relative dielectric constant of ceramic is greater than the relative dielectric constant of resin.

[0057] Figure 8 shows the current density distribution curves on both sides of the semiconductor process chamber when first sub-insulator 171 is made of ceramic and second sub-insulator 172 is made of resin. Figure 9 shows the current density distribution curves on both sides of the semiconductor process chamber when second insulator 170 made of ceramic is placed on the side of through-hole 121 near cantilever 500 and the other side is filled with air. As can be seen from Figures 8 and 9, air is more effective in improving the symmetry of the current density on both sides because air has a lower relative dielectric constant.

[0058] Continuing to refer to Figures 8 and 9, when the width difference between the first sub-insulator 171 and the second sub-insulator 172 reaches 100mm, the air dielectric etching current density can be made more symmetrical. However, taking into account factors such as the internal structure, such as the lower electrode structure 100 also has components such as a pin lifting motor and a chiller tube, it is difficult to ensure the symmetry of the current density in the loops on both sides under a large distance difference from a mechanical design perspective. Therefore, in the embodiment of the present disclosure, the width difference between the first sub-insulator 171 and the second sub-insulator 172 can be designed to be in the range of 5mm to 50mm, specifically including 5mm, 10mm, 20mm, 25mm, 30mm, 40mm, 50mm, etc., and of course, other values ​​can also be used. Preferably, the width difference can be selected as 25mm to make the current density in the loops on both sides symmetrical.

[0059] 5 and 6 , in some embodiments, the interface 173 between the first sub-insulator 171 and the second sub-insulator 172 can be a curved surface. Since the cavity 400 is a cylindrical structure, the curved surface design can accommodate the cylindrical cavity 400. For example, the interface 173 can be a circular arc that bulges toward the first sub-insulator 171, as shown in FIG5 . Alternatively, the interface 173 can be a circular arc that bulges toward the second sub-insulator 172, as shown in FIG6 .

[0060] Referring to FIG4 , in other embodiments, the interface 173 between the first sub-insulator 171 and the second sub-insulator 172 can be a plane. For example, the second insulator 170 can be a disc-shaped structure, separated into the first sub-insulator 171 and the second sub-insulator 172 by a plane. Thus, the first sub-insulator 171 and the second sub-insulator 172 can be sector-shaped disc structures. The first sub-insulator 171 can be a semi-disc structure, while the second sub-insulator 172 can be a multi-disc structure.

[0061] It should be noted that the specific shape of the interface 173 is not limited, as long as the projected area of ​​the first sub-insulator 171 is smaller than the projected area of ​​the second sub-insulator 172 on a plane perpendicular to the axis of the second insulating member 170 .

[0062] In the embodiment of the present disclosure, when the RF feedthrough 150 passes through the second insulating member 170, the axis of the feeding end of the RF feedthrough 150 can be located on the interface 173 between the first sub-insulator 171 and the second sub-insulator 172. Specifically, it can be located on the interface 173 that is a plane or a curved surface, as shown in Figures 4 and 6, to ensure that the projected area of ​​the second sub-insulator 172 on a plane perpendicular to the axis of the second insulating member 170 is larger than the projected area of ​​the first sub-insulator 171 on a plane perpendicular to the axis of the second insulating member 170.

[0063] Of course, the axis of the RF feedthrough 150 may not be on the interface 173 . Instead, the axis of the feeding end of the RF feedthrough 150 may be located on the side of the first sub-insulator 171 away from the cantilever 500 , and the RF feedthrough 150 may be located on the second sub-insulator 172 . This approach can also meet process requirements.

[0064] Referring to FIG. 5 , in a more specific embodiment, the interface 173 between the first sub-insulator 171 and the second sub-insulator 172 is an arc convex toward the first sub-insulator 171 , and the axis of the first end of the RF feedthrough 150 is located on the side of the interface 173 away from the cantilever 500 . Furthermore, a dielectric region with a relatively high relative dielectric constant (i.e., a localized region of the first sub-insulator 171 ) exists on the side of the RF feedthrough 150 away from the cantilever 500 . This dielectric region with a relatively high relative dielectric constant can increase the capacitance between the interface component 120 and the RF feedthrough 150 . Therefore, the interface 173 between the portion with a relatively high relative dielectric constant and the portion with a relatively low relative dielectric constant needs to be appropriately moved toward the cantilever 500 to provide some compensation, thereby reducing the average relative dielectric constant of the dielectric on the side of the RF feedthrough 150 away from the cantilever 500 and thereby reducing the capacitance between the interface component 120 and the RF feedthrough 150 on the side away from the cantilever 500 .

[0065] In addition, in actual situations, the cavity 400 can be a cylindrical structure, and the best effect of relative dielectric constant compensation of the two insulating parts should be an axisymmetric structure. Therefore, the arc-shaped curved surface high and low relative dielectric constant boundary surface 173 shown in Figures 5 and 6 has a better compensation effect than the planar high and low relative dielectric constant boundary surface 173 shown in Figure 4, because the planar boundary surface 173 forms a left-right symmetrical structure rather than an axisymmetric structure.

[0066] In some embodiments, the axis of the feeding end of the RF feedthrough 150 does not coincide with the axis of the carrier 140, and the axis of the feeding end of the RF feedthrough 150 is offset relative to the axis of the carrier 140 in a direction away from the cantilever 500. This arrangement allows the feeding end of the RF feedthrough 150 to be non-concentric (or non-coaxial) with the carrier 140, thereby compensating for the asymmetry between the two sides of the lower electrode structure 100 caused by the asymmetric geometric structure. This allows for more uniform current flow in the circuits of the lower electrode structure 100 on the side closer to the cantilever 500 and the side farther from the cantilever 500, thereby improving the uniformity of the etching process.

[0067] FIG3 is a top view of the eccentric relationship between the carrier 140 and the RF feedthrough 150. As can be seen from FIG3 , the distance b1 from the axis of the RF feedthrough 150 to the edge of the carrier 140 on the side away from the cantilever 500 is smaller than the distance a1 between the two on the side close to the cantilever 500.

[0068] In addition, the spacing c1 and d1 on the other two sides can be kept equal. Of course, if there is asymmetric RF loop impedance in this direction in the design of the cavity 400, c1 and d1 can also be made inconsistent, which can be determined according to actual working conditions.

[0069] In order to ensure the insulation between the interface part 120 and the supporting part 140, the lower electrode structure 100 can also include a first insulating part 130, which is connected between the supporting part 140 and the interface part 120. In this way, the first insulating part 130 can not only achieve the supporting function of the supporting part 140, but also achieve the insulation effect between the supporting part 140 and the interface part 120.

[0070] The first insulating member is provided with a through hole, and the feeding end of the RF feedthrough 150 passes through the through hole and is connected to the carrier 140 . In this way, the RF feedthrough 150 can be positioned away through the through hole to ensure that the RF feedthrough 150 can be connected to the carrier 140 .

[0071] Furthermore, the axis of the through hole does not coincide with the axis of the first insulating member 130, and the axis of the through hole is offset relative to the axis of the first insulating member 130 in a direction away from the cantilever 500. Specifically, as shown in FIG2 , the distance from the side of the first insulating member 130 closer to the cantilever 500 to the axis of the through hole is a first distance a, and the distance from the side of the first insulating member 130 farther from the cantilever 500 to the axis of the through hole is a second distance b, and the first distance a is greater than the second distance b.

[0072] Exemplarily, the diameter of the first insulating member 130 is equal to the diameter of the carrier 140, and the two are coaxially arranged to ensure symmetry in their installation and facilitate installation. In this case, the distance a1 from the side of the carrier 140 close to the cantilever 500 to the axis of the RF feedthrough 150 is equal to the first distance a, and the distance b1 from the side of the carrier 140 away from the cantilever 500 to the axis of the RF feedthrough 150 is equal to the second distance b. In this case, a1 is also greater than b1.

[0073] Through the above-mentioned setting, the inductance in the respective loops on the side close to the cantilever 500 and the side away from the cantilever 500 can be adjusted, so that the current density in the loops on both sides can be adjusted accordingly, that is, the current density difference in the loops on both sides is compensated, so that the current density in the loop on the side close to the cantilever 500 and the current density in the loop on the side away from the cantilever 500 can be symmetrical, thereby ensuring the uniformity of the etching process.

[0074] Furthermore, the distance difference between the first distance a and the second distance b ranges from 5 mm to 20 mm, including 5 mm, 8 mm, 10 mm, 12 mm, 15 mm, 18 mm, 20 mm, etc. Of course, it can also be other values. The specific value of the distance difference can be set according to the distribution of the geometric structure, and the embodiment of the present disclosure does not make specific limitations on this.

[0075] For example, the first distance a and the second distance b may differ by 10 mm. In this case, the current density distribution curves in the respective loops close to the cantilever 500 side and the side away from the cantilever 500 can be obtained through simulation, as shown in FIG7 . It can be seen from FIG7 that when the distance difference is 10 mm, the current density in the respective loops close to the cantilever 500 side and the side away from the cantilever 500 side is relatively symmetrical. This is because the current reversal on the side close to the cantilever 500 side will have a canceling effect, resulting in the inductance being smaller than that on the side away from the cantilever 500. Therefore, by adjusting the inductance on both sides to be relatively balanced, the symmetry of the current can be improved, and the uniformity of the etching process can be further ensured.

[0076] In some embodiments, the first insulating member 130 may be an insulating disk, which may be a circular disk that supports the carrier 140 and provides insulation. Furthermore, the insulating disk may also have an opening to allow the RF feedthrough 150 to pass through.

[0077] Based on the above-mentioned electrode mechanism, the embodiment of the present disclosure also discloses a semiconductor process equipment, and the disclosed semiconductor process equipment includes the above-mentioned semiconductor process chamber provided by the present disclosure. The semiconductor process chamber includes the above-mentioned lower electrode structure 100. In addition, it can also include a cavity 400, a liner 200, a grounding ring 300, a cantilever 500, a matcher 600 and other parts. Among them, the liner 200 is arranged on the inner surface of the side wall of the cavity 400, the cantilever 500 is connected to the side wall of the cavity 400, the lower electrode structure 100 is arranged in the cavity 400 and connected to the cantilever 500, the matcher 600 is arranged outside the cavity 400 and is arranged corresponding to the cantilever 500, and the grounding ring 300 is sleeved on the outside of the lower electrode structure 100 and contacts the liner 200. It should be noted here that the specific structure and working principle of the semiconductor process equipment can be referred to the relevant technology and will not be elaborated here.

[0078] In the disclosed embodiment, the current loop on the cantilever 500 side is: lining 200 - grounding ring 300 - interface part 120 - shielding part 160 - matcher 600; the current loop on the opposite side of the cantilever 500 is: lining 200 - grounding ring 300 - interface part 120 - shielding part 160 - matcher 600.

[0079] By arranging the shielding member 160 and the interface member 120 non-coaxially (or non-concentrically), the asymmetry of the lower electrode loop caused by the inherent asymmetry of the geometric distribution of components in the semiconductor process chamber can be compensated, thereby making the current density in the lower electrode loop more uniform, thereby improving the uniformity of the etching process.

[0080] The embodiments of the present disclosure are described above in conjunction with the accompanying drawings, but the present disclosure is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present disclosure, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present disclosure and the claims, all of which are protected by the present disclosure.

Claims

1. A semiconductor process chamber, It is characterized in that include: A cavity and a lower electrode structure, wherein the lower electrode structure is disposed in the cavity; The lower electrode structure comprises a base, an interface component, a carrier, a radio frequency feed-in component and a shielding component; the carrier is used to carry the wafer; The base is connected to the side wall of the cavity through a cantilever; The interface member and the bearing member are sequentially stacked on the base along a first direction; The first end of the shielding member is connected to the interface member, and the second end of the shielding member is connected to the inner wall of the base; the axis of the first end of the shielding member does not coincide with the axis of the interface member, and the axis of the first end of the shielding member is offset in a direction away from the cantilever relative to the axis of the interface member; The radio frequency feeding component is disposed in the shielding component, and is connected to the supporting component after passing through the interface component along the first direction, so as to feed radio frequency power to the supporting component.

2. The semiconductor process chamber according to claim 1, It is characterized in that The axis of the feeding end of the RF feeding element does not coincide with the axis of the first end of the shielding element, and the axis of the feeding end of the RF feeding element is offset toward the cantilever relative to the axis of the first end of the shielding element.

3. The semiconductor process chamber according to claim 2, It is characterized in that The axis of the feeding end of the radio frequency feeding component is located between the axis of the first end of the shielding component and the axis of the interface component.

4. The semiconductor process chamber according to claim 2 or 3, It is characterized in that The lower electrode structure further includes a second insulating member, the interface member is provided with a through hole, the second insulating member is arranged in the through hole, and the RF feeding member passes through the second insulating member; The first end of the shielding member is connected to the through hole, and the axis of the first end of the shielding member is colinear with the axis of the second insulating member.

5. The semiconductor process chamber according to claim 4, It is characterized in that The second insulating member includes a first sub-insulating member and a second sub-insulating member adapted to each other; The first sub-insulator is located on a side close to the cantilever, and the second sub-insulator is located on a side away from the cantilever; The capacitance between the RF feeding element and the side of the interface element where the first sub-insulating element is located is greater than the capacitance between the sides of the interface element where the second sub-insulating element is located.

6. The semiconductor process chamber according to claim 5, It is characterized in that On a plane perpendicular to the axis of the second insulating member, a projected area of ​​the first sub-insulating member is smaller than a projected area of ​​the second sub-insulating member.

7. The semiconductor process chamber according to claim 6, It is characterized in that A relative dielectric constant of the first sub-insulator is greater than or equal to a relative dielectric constant of the second sub-insulator.

8. The semiconductor process chamber according to claim 7, It is characterized in that The first sub-insulator is made of ceramic; The second sub-insulator is made of resin.

9. The semiconductor process chamber according to claim 6, It is characterized in that The width difference between the first sub-insulator and the second sub-insulator is in the range of 5 mm to 50 mm.

10. The semiconductor process chamber according to claim 5, It is characterized in that The interface between the first sub-insulator and the second sub-insulator is a curved surface.

11. The semiconductor process chamber according to claim 5, It is characterized in that The interface between the first sub-insulator and the second sub-insulator is a plane.

12. The semiconductor process chamber according to claim 10 or 11, It is characterized in that The axis of the feeding end of the radio frequency feeding element is located on the interface between the first sub-insulating element and the second sub-insulating element.

13. The semiconductor process chamber according to claim 10 or 11, It is characterized in that The axis of the feeding end of the radio frequency feeding element is located on a side of the first sub-insulating element away from the cantilever, and the radio frequency feeding element is located on the second sub-insulating element.

14. The semiconductor process chamber according to claim 4, It is characterized in that On a plane perpendicular to the axis of the second insulating member, a projected area of ​​the second insulating member is smaller than a projected area of ​​the through hole; The second insulating member is disposed on a side of the through hole close to the cantilever.

15. The semiconductor process chamber according to claim 1, It is characterized in that The axis of the feeding end of the RF feeding element does not coincide with the axis of the supporting element, and the axis of the feeding end of the RF feeding element is offset in a direction away from the cantilever relative to the axis of the supporting element.

16. The semiconductor process chamber according to claim 1, It is characterized in that The lower electrode structure further includes a first insulating member, wherein the first insulating member is connected between the supporting member and the interface member; The first insulating member is provided with a through hole, and the feeding end of the RF feeding member passes through the through hole and is connected to the supporting member; The axis of the through hole does not coincide with the axis of the first insulating member, and the axis of the through hole is offset in a direction away from the cantilever relative to the axis of the first insulating member.

17. The semiconductor process chamber according to claim 1, It is characterized in that The semiconductor process chamber also includes a liner, which is arranged in the cavity and is arranged around the outer side of the lower electrode structure. One end of the liner is electrically connected to the cavity, and the other end of the liner is electrically connected to the interface component.

18. A semiconductor process equipment, It is characterized in that A semiconductor process chamber comprising any one of claims 1 to 17.

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