Data sending method, device, and system in ethernet

Abstract

Provided are a data sending method, device, and system. A PMA sublayer of an Ethernet device acquires a data stream having undergone FEC coding, and carries out a first data processing process on the data stream to obtain an interleaved data stream, wherein the first data processing process comprises interleaving in a first interleaving mode, and the interleaving type of the first interleaving mode is specifically symbol interleaving or convolutional interleaving. The present application can expand the function of the PMA sublayer, and solve the technical problem of meeting the requirement of reducing the BER in a high-rate Ethernet data transmission scenario.

Description

Method, device and system for sending data in Ethernet

[0001] This application claims priority to Chinese patent application No. 202310149106.7, filed on February 14, 2023, entitled “A method for processing data in the Ethernet physical layer”, and Chinese patent application No. 202310247349.4, filed on March 3, 2023, entitled “A method, device and system for sending data in an Ethernet network”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of communications, and in particular to a method, device, and system for sending data in an Ethernet network. Background Art

[0003] During Ethernet data transmission, due to various factors such as environmental interference and system errors, inconsistencies between the data received by the data receiver and the data sent by the data transmitter may occur. Bit errors are inevitable. Current methods such as forward error correction (FEC) and interleavers can reduce the bit error rate (BER).

[0004] However, when the data transmission rate is further increased, the existing physical coding sublayer (PCS) interleaving method will not be able to meet the demand.

[0005] Summary of the Invention

[0006] Provided are a method, device, and system for sending data, for solving the problem that technical means for reducing BER cannot meet the demand due to the increase of data transmission rate.

[0007] In a first aspect, a method for sending data is provided, the method being performed by an Ethernet device. The Ethernet device may be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, or a pluggable optical module or electrical module in an Ethernet network. When the Ethernet device acts as a data transmitter, the physical medium attachment (PMA) sublayer of the Ethernet device obtains a data stream that has been encoded with FEC, and performs a first data processing process on the data stream to obtain an interleaved data stream. The first data processing process includes interleaving using a first interleaving method, and the interleaving type of the first interleaving method is specifically symbol interleaving or convolutional interleaving. The data stream obtained by the PMA sublayer may be one data stream or multiple data streams. The number of data streams is related to the number of data channels between the PMA sublayer and the upper sublayer. Furthermore, interleaving may refer to interleaving within one data stream or interleaving between multiple data streams. Furthermore, the interleaved data stream may be one data stream or multiple data streams.

[0008] In this application, the PMA sublayer on the data transmission side performs symbol interleaving or convolutional interleaving on the data stream. The specific interleaving method performed by the PMA sublayer can be flexibly designed to ensure that the actual demand for reducing BER in the network is met. In addition, because the PMA sublayer is relatively simple to expand, the design of the PMA sublayer does not require changes to the existing PCS. Even when the PMA sublayer is located in a pluggable module, the design of the PMA sublayer does not require changes to the main chip of the existing Ethernet physical layer (PHY). This meets the demand for reducing BER in high-speed data transmission scenarios while minimizing research and development costs.

[0009] In one possible implementation, the PMA sublayer performs symbol interleaving at a granularity of 10 bits, or in other words, the PMA sublayer performs 10-bit symbol interleaving. This 10-bit symbol interleaving is consistent with the granularity of interleaving performed by the existing PCS, and symbol interleaving at this granularity can effectively reduce BER.

[0010] In one possible implementation, the first data processing performed by the PMA sublayer on the data stream further includes bit multiplexing (bit mux) or symbol-group multiplexing (symbol-group mux), where the granularity of bit multiplexing is 1 bit, and the granularity of symbol-group multiplexing can be 20 bits or 40 bits. Through this bit multiplexing or symbol-group multiplexing, the number of data streams output by the PMA sublayer can adapt to the number of data channels between the PMA and the next sublayer in the data transmission direction. Optionally, this bit multiplexing or symbol-group multiplexing process can be performed after the interleaving process described above using the first interleaving method, or the bit multiplexing or symbol-group multiplexing process can also be included in the interleaving process described above using the first interleaving method.

[0011] In one possible implementation, the first data processing performed by the PMA sublayer on the data stream further includes bit demultiplexing (bit demux) or symbol-group demultiplexing (symbol-group demux), where the granularity of bit demultiplexing is 1 bit, and the granularity of symbol-group demultiplexing can be 20 bits or 40 bits.

[0012] In a possible implementation, the first data processing performed by the PMA sublayer on the data stream further includes alignment marker (AM) locking and deskew.

[0013] The data stream acquired by the PMA sublayer originates from the previous sublayer in the data transmission direction, which may be, for example, a PCS, a data terminal equipment extender sublayer (DTE_XS), or another PMA sublayer. The data stream from the previous sublayer can be recovered through the aforementioned bit demultiplexing or symbol group demultiplexing, as well as alignment flag locking and deskewing. Optionally, the aforementioned bit demultiplexing or symbol group demultiplexing, alignment flag locking, and deskewing can be performed before the aforementioned interleaving process using the first interleaving method, i.e., subsequent interleaving can be performed after the data stream from the previous sublayer has been recovered.

[0014] In one possible implementation, the data stream obtained by the PMA sublayer is the data stream obtained after executing a second data processing process, where the second data processing process includes interleaving using a second interleaving method. That is, the data stream obtained by the PMA sublayer may be a data stream that has already been interleaved. This second data processing process may be performed by a sublayer prior to the PMA sublayer, such as the PCS or DTE_XS. Furthermore, the sublayer performing this second data processing process may be directly adjacent to the PMA sublayer or indirectly adjacent, i.e., interposed with other sublayers. In other words, interleaving performed by the PMA sublayer does not conflict with interleaving performed by other preceding sublayers. Therefore, there is no need to modify the existing data processing methods of other sublayers, maintaining compatibility with existing Ethernet devices.

[0015] In one possible implementation, the interleaving depth of the first interleaving mode is different from that of the second interleaving mode, that is, the interleaving is changed by the interleaving of the PMA sublayer. To a certain extent, it can be considered that the interleaving of the PMA sublayer covers the interleaving of other previous sublayers. Through this interleaving change, the new error correction design can be flexibly implemented in the PMA sublayer, better meeting the demand for reducing BER brought about by the ever-increasing Ethernet data transmission rate, without the need to change other previous sublayers, and may not even require changes to the main chip of the entire Ethernet PHY layer. Specifically, the interleaving of the PMA sublayer can be different from the interleaving depth performed by other previous sublayers. The interleaving of the PMA sublayer can be flexibly designed according to actual network requirements to meet the demand for reducing BER brought about by the ever-increasing Ethernet data transmission rate.

[0016] In one possible implementation, the interleaving depth of the second interleaving mode is 2 FEC codewords. For example, when Reed-Solomon (RS) codewords are used, the interleaving depth of the second interleaving mode is 2 RS codewords, that is, 2×RS.

[0017] In one possible implementation, the first data processing process may include deinterleaving for the second interleaving mode, or the first data processing process may not include deinterleaving for the second interleaving mode. Optionally, deinterleaving for the second interleaving mode may be performed before interleaving using the first interleaving mode. That is, the PMA sublayer first deinterleaves the interleaving performed by other preceding sublayers before performing interleaving within the PMA sublayer. Furthermore, the PMA sublayer may not deinterleave the interleaving performed by other preceding sublayers but may directly perform interleaving within the PMA sublayer.

[0018] In one possible implementation, the interleaving depth of the first interleaving mode is 4×RS. Increasing the interleaving depth to 4×RS ensures that the BER reduction requirements in various high-speed Ethernet data transmission scenarios are met, and the BER of the data after error correction through FEC interleaving meets network requirements. For example, a depth of 4×RS can at least meet the BER reduction requirements in a scenario where a single physical lane rate is 200 Gbps.

[0019] In a possible implementation, the Ethernet device may include at least one of the following: a PHY chip, a forwarding device, or a pluggable module.

[0020] In one possible implementation, the single physical channel rate of the data stream obtained after interleaving by the PMA sublayer is 200 Gbps. It is easy to understand that the 200 Gbps is a value that can fluctuate within the conventional range in the field, and does not refer to the exact value of the channel rate at any time.

[0021] In a possible implementation, a rate of an interface of the PMA sublayer for receiving the data stream is at least one of the following: 200 Gbps or 400 Gbps.

[0022] In one possible implementation, the PMA sublayer obtains the data stream from any of the following interfaces: an attachment unit interface (AUI) or a common electrical interface (CEI). For example, the PMA sublayer may be electrically separate from the upper sublayer and obtain the data stream from the upper sublayer via an interface, such as an AUI or a CEI.

[0023] In a possible implementation, the PMA sublayer sends the interleaved data stream to a physical medium dependent (PMD) sublayer. In a transmitting Ethernet device, the PMD sublayer is the next sublayer of the PMD sublayer in the data transmission direction.

[0024] In a second aspect, a method for receiving data is provided, which is performed by an Ethernet device. The Ethernet device can be an Ethernet chip, an Ethernet forwarding device such as a switch or router, or a pluggable optical module or electrical module in an Ethernet network. After the PMA sublayer in the Ethernet device on the data transmitting side performs interleaving, the PMA sublayer in the Ethernet device on the data receiving side needs to perform a deinterleaving process accordingly. The PMA sublayer of the Ethernet device on the data receiving side obtains a data stream and performs a third data processing process on the data stream to obtain a deinterleaved data stream. The third data processing process includes deinterleaving using a first deinterleaving method, and the deinterleaving type of the first deinterleaving method is specifically symbol deinterleaving or convolutional deinterleaving. The data stream obtained by the PMA sublayer can be one data stream or multiple data streams. The number of data streams is related to the number of data channels between the PMA sublayer and the upper sublayer. Furthermore, deinterleaving can refer to deinterleaving within a data stream or deinterleaving between multiple data streams.

[0025] In the present application, the PMA sublayer on the data transmitting side performs symbol interleaving or convolution interleaving on the data stream, and correspondingly, the PMA sublayer on the data receiving side performs symbol deinterleaving or convolution deinterleaving on the data stream. The specific method by which the PMA sublayer performs deinterleaving can be flexibly designed to ensure that the actual demand for reducing BER in the network is met. In addition, since the expansion of the PMA sublayer is relatively simple, the design of the PMA sublayer does not require changes to the existing PCS. Even when the PMA sublayer is located in a pluggable module, the design of the PMA sublayer does not require changes to the main chip of the existing Ethernet physical PHY layer, thereby meeting the demand for reducing BER in high-speed data transmission scenarios while minimizing research and development costs.

[0026] In a possible implementation, the PMA sublayer performs symbol deinterleaving with a granularity of 10 bits, or in other words, the PMA sublayer performs 10-bit symbol deinterleaving.

[0027] In one possible implementation, the third data processing performed by the PMA sublayer on the data stream further includes bit multiplexing (bit mux) or symbol-group multiplexing (symbol-group mux), where the granularity of bit multiplexing is 1 bit, and the granularity of symbol-group multiplexing can be 20 bits or 40 bits. Through this bit multiplexing or symbol-group multiplexing, the number of data streams output by the PMA sublayer can adapt to the number of data channels between the PMA and the next sublayer in the data transmission direction. Optionally, this bit multiplexing or symbol-group multiplexing process can be performed after the deinterleaving process described above using the third interleaving method, or this bit multiplexing or symbol-group multiplexing process can also be included in the deinterleaving process described above using the third interleaving method.

[0028] In one possible implementation, the third data processing performed by the PMA sublayer on the data stream includes bit demultiplexing (bit demux) or symbol-group demultiplexing (symbol-group demux), where the granularity of bit demultiplexing is 1 bit, and the granularity of symbol-group demultiplexing can be 20 bits or 40 bits.

[0029] In a possible implementation, the third data processing performed by the PMA sublayer on the data stream includes alignment marker (AM) locking and deskew.

[0030] The data stream acquired by the PMA sublayer originates from the previous sublayer in the data transmission direction, which may be, for example, a PMD sublayer. The data stream from the previous sublayer can be recovered through the aforementioned bit demultiplexing or symbol group demultiplexing, as well as alignment flag locking and deskewing. Optionally, the aforementioned bit demultiplexing or symbol group demultiplexing, alignment flag locking, and deskewing processes can also implement a first deinterleaving mode, i.e., recovering the data stream from the previous sublayer and achieving deinterleaving through bit demultiplexing or symbol group demultiplexing, as well as alignment flag locking and deskewing.

[0031] In one possible implementation, after the PMA sublayer performs deinterleaving on the data stream in the third data processing process, it can also reinterleave the deinterleaved data stream using the second interleaving method to obtain a reinterleaved data stream. This is to coordinate with the deinterleaving processing of the PCS or DTE_XS in the existing receiving-side Ethernet equipment, eliminating the need to modify the existing PCS or DTE_XS and maximizing compatibility with existing PHY chips.

[0032] In a possible implementation, the deinterleaving depth of the first deinterleaving mode is 4×RS.

[0033] In a possible implementation, the Ethernet device may include at least one of the following: a PHY chip, a forwarding device, or a pluggable module.

[0034] In a third aspect, a method for receiving data is provided, the method being performed by an Ethernet device. The Ethernet device may be an Ethernet chip, an Ethernet forwarding device such as a switch or router, or a pluggable optical or electrical module in an Ethernet network. After the PMA sublayer in the Ethernet device on the data transmitting side performs an interleaving transformation, the PMA sublayer in the Ethernet device on the data receiving side needs to perform a corresponding interleaving transformation to convert the interleaving mode of the data stream to an interleaving mode compatible with the deinterleaving processes performed in other sublayers, thereby avoiding modifications to the PHY chip. For example, if the Ethernet PHY chip performs 2×RS deinterleaving on the data stream, the PMA sublayer may convert the interleaving mode of the obtained data stream to 2×RS interleaving, so that the 2×RS deinterleaving performed on the data stream by the PHY chip can obtain a correct data stream. Specifically, the PMA sublayer of the Ethernet device on the data receiving side obtains a data stream and performs a third data processing process on the data stream to obtain an interleaved data stream, wherein the third data processing process includes interleaving the data stream, wherein the interleaving type is symbol interleaving or convolutional interleaving. The data stream obtained by the PMA sublayer can be one data stream or multiple data streams. The number of data streams is related to the number of data channels between the PMA sublayer and the upper sublayer. Furthermore, interleaving can refer to interleaving within one data stream or interleaving between multiple data streams.

[0035] In a possible implementation, the symbol interleaving is performed with a granularity of 10 bits.

[0036] In a possible implementation, the interleaved data stream is deinterleaved by a physical coding sublayer PCS or a data terminal equipment extension sublayer DTE_XS.

[0037] In one possible implementation, the interleaving depth is 2×RS. When the Ethernet PHY chip performs 2×RS deinterleaving on the data stream, the PMA sublayer can convert the interleaving mode of the acquired data stream to 2×RS interleaving, so that the PHY chip can obtain the correct data stream after performing 2×RS deinterleaving on the data stream.

[0038] In a possible implementation, the third data processing process includes: performing deinterleaving in a first deinterleaving manner, where the deinterleaving type of the first deinterleaving manner is specifically symbol deinterleaving or convolutional deinterleaving, to obtain a deinterleaved data stream.

[0039] In a possible implementation, the third data processing process includes: bit demultiplexing or symbol group demultiplexing, wherein the granularity of bit demultiplexing is 1 bit, and the granularity of symbol group demultiplexing can be 20 bits or 40 bits.

[0040] In a possible implementation, the third data processing process includes: locking the alignment mark AM and de-skew.

[0041] The data stream acquired by the PMA sublayer originates from the previous sublayer in the data transmission direction, which may be, for example, a PMD sublayer. The data stream from the previous sublayer can be recovered through the aforementioned bit demultiplexing or symbol group demultiplexing, as well as alignment flag locking and deskewing. Optionally, the aforementioned bit demultiplexing or symbol group demultiplexing, alignment flag locking, and deskewing processes can also implement a first deinterleaving mode, i.e., recovering the data stream from the previous sublayer and achieving deinterleaving through bit demultiplexing or symbol group demultiplexing, as well as alignment flag locking and deskewing.

[0042] In one possible implementation, the third data processing process includes bit multiplexing or symbol group multiplexing. The granularity of bit multiplexing is 1 bit, and the granularity of symbol group multiplexing can be 20 bits or 40 bits. Through this bit multiplexing or symbol group multiplexing, the number of data streams output by the PMA sublayer can adapt to the number of data channels between the PMA and the next sublayer in the data transmission direction. Optionally, this bit multiplexing or symbol group multiplexing process can be performed after the deinterleaving process described above using the third interleaving method, or the bit multiplexing or symbol group multiplexing process can also be included in the deinterleaving process described above using the third interleaving method.

[0043] In a possible implementation, the Ethernet device includes at least one of the following: a physical layer PHY chip, a forwarding device, or a pluggable module.

[0044] In a fourth aspect, an Ethernet device is provided, comprising at least one module; the at least one module is configured to execute the method provided in the first aspect or any optional embodiment of the first aspect; or the at least one module is configured to execute the method provided in the second aspect or any optional embodiment of the second aspect; or the at least one module is configured to execute the method provided in the third aspect or any optional embodiment of the third aspect. The at least one module may be implemented based on software, hardware, or a combination of software and hardware, and the modules may be arbitrarily combined or divided based on the specific implementation.

[0045] In a fifth aspect, an Ethernet device is provided, comprising a memory and a processor; the memory is used to store a computer program; the processor is used to execute the computer program stored in the memory so that the Ethernet device performs the method provided in the first aspect or any optional embodiment of the first aspect, or performs the method provided in the second aspect or any optional embodiment of the second aspect; or the at least one module is used to perform the method provided in the third aspect or any optional embodiment of the third aspect.

[0046] In a sixth aspect, an Ethernet device is provided, comprising a main control board and an interface board, wherein the main control board or the interface board is used to implement the method provided in the first aspect or any optional manner of the first aspect, or the main control board or the interface board is used to implement the method provided in the second aspect or any optional manner of the second aspect; or the at least one module is used to execute the method provided in the third aspect or any optional manner of the third aspect.

[0047] In the seventh aspect, a communication system is provided, which includes an Ethernet device, wherein the Ethernet device is used to execute the method provided in the first aspect or any optional embodiment of the first aspect, or to execute the method provided in the second aspect or any optional embodiment of the second aspect; or, the at least one module is used to execute the method provided in the third aspect or any optional embodiment of the third aspect.

[0048] In an eighth aspect, a computer-readable storage medium is provided, which stores a computer program. When the computer program is executed, it implements the method provided in the first aspect or any optional method of the first aspect; or, it implements the method provided in the second aspect or any optional method of the second aspect; or, it implements the method provided in the third aspect or any optional method of the third aspect; or, the at least one module is used to execute the method provided in the third aspect or any optional method of the third aspect.

[0049] In the ninth aspect, a computer program product is provided, which includes a program or code, and when the program or code is executed, it implements the method provided in the first aspect or any optional method of the first aspect; or, it implements the method provided in the second aspect or any optional method of the second aspect; or, it implements the method provided in the third aspect or any optional method of the third aspect; or, the at least one module is used to execute the method provided in the third aspect or any optional method of the third aspect.

[0050] In a tenth aspect, a chip is provided that, when running, implements the method provided in the first aspect or any optional embodiment of the first aspect; or implements the method provided in the second aspect or any optional embodiment of the second aspect; or implements the method provided in the third aspect or any optional embodiment of the third aspect. The chip may be a control chip or a forwarding chip, the chip including programmable logic circuits and / or program instructions; or the at least one module is configured to execute the method provided in the third aspect or any optional embodiment of the third aspect.

[0051] The technical effects of the second to tenth aspects mentioned above can refer to the technical effects of the first aspect and will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] To more clearly illustrate the technical solutions of this application, the following briefly introduces the drawings used in the embodiments. Obviously, the following drawings are only drawings of some embodiments of this application. A person skilled in the art can, without inventive effort, derive other technical solutions and drawings that can also implement this application based on these drawings.

[0053] FIG1( a ) is a schematic diagram of a random bit error provided by an embodiment of the present invention;

[0054] FIG1( b ) is a schematic diagram of a random bit error provided by an embodiment of the present invention;

[0055] FIG2 is a schematic diagram of an interleaver processing process provided by an embodiment of the present invention;

[0056] FIG3 is a schematic flow chart of a method for sending data according to an embodiment of the present invention;

[0057] FIG4( a ) is a schematic diagram of an implementation of the physical layer of an Ethernet device provided by an embodiment of the present invention;

[0058] FIG4( b ) is a schematic diagram of an implementation of the physical layer of an Ethernet device provided by an embodiment of the present invention;

[0059] FIG4( c ) is a schematic diagram of an implementation of the physical layer of an Ethernet device provided by an embodiment of the present invention;

[0060] FIG5 is a schematic diagram of an interleaved data processing process provided by an embodiment of the present invention;

[0061] FIG6 is a schematic diagram of an interleaved data processing process provided by an embodiment of the present invention;

[0062] FIG7( a ) is a schematic diagram of a multiplexed data processing process provided by an embodiment of the present invention;

[0063] FIG7( b ) is a schematic diagram of a multiplexed data processing process provided by an embodiment of the present invention;

[0064] FIG7( c ) is a schematic diagram of a multiplexed data processing process provided by an embodiment of the present invention;

[0065] FIG8( a ) is a flow chart of a method for receiving data according to an embodiment of the present invention;

[0066] FIG8( b ) is a flow chart of a method for receiving data according to an embodiment of the present invention;

[0067] FIG9( a ) is a schematic flow chart of a method for sending and receiving PMA sublayer data according to an embodiment of the present invention;

[0068] FIG9( b ) is a schematic flow chart of a method for sending and receiving PMA sublayer data according to an embodiment of the present invention;

[0069] FIG9( c ) is a schematic flow chart of a method for sending and receiving PMA sublayer data according to an embodiment of the present invention;

[0070] FIG9( d ) is a flow chart of a method for sending and receiving PMA sublayer data according to an embodiment of the present invention;

[0071] FIG10 is a schematic structural diagram of an Ethernet device provided in an embodiment of the present invention;

[0072] FIG11 is a schematic structural diagram of an Ethernet device provided in an embodiment of the present invention;

[0073] FIG12 is a schematic structural diagram of an Ethernet device provided in an embodiment of the present invention;

[0074] FIG13 is a schematic diagram of a communication system provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0075] During the communication transmission process, due to various factors such as environmental interference and system errors, there is a high probability of inconsistencies between the data received by the data receiver and the data sent by the data transmitter. This inconsistency is also known as a bit error. Therefore, bit errors are inevitable during communication transmission. Bit errors can cause many problems. For example, when errors occur in critical control signals used for communication between various devices on a network, they can lead to serious problems such as system crashes and data loss. Furthermore, bit errors can significantly affect network communication latency, which in turn affects consumers' experience in activities such as watching videos, playing online games, and making calls. Therefore, the bit error rate (BER) has always been a key performance metric for communication systems. The lower the BER value at the data receiver, the higher the network transmission reliability.

[0076] To ensure high reliability of communication systems, the industry usually sets clear requirements for the BER of communication systems. For example, the Institute of Electrical and Electronics Engineers (IEEE) standard 802.3bs requires that the BER of data received by the data receiver when entering the media access control (MAC) sublayer should be less than 1×10 -13 However, when the data in the network completes the transmission in the network link and enters the data receiving end, its BER can usually reach 2.4×10 -4 At this point, the data receiving end can use FEC to correct the bit errors in the data stream and restore it to the transmitted data. FEC can eliminate most bit errors, significantly reducing the BER of the processed data.

[0077] The effectiveness of FEC is related to the error distribution. When two data streams have different error distributions, their post-correction BERs will differ even if their pre-correction BERs are the same. The pre-correction BER refers to the BER before FEC, while the post-correction BER refers to the BER after FEC. Error distribution can be primarily categorized into two types: random errors and non-random errors. For illustrative purposes, Figures 1(a) and 1(b) illustrate random and non-random errors, where b represents a correct bit and x represents an erroneous bit. Random errors manifest as random error distribution, as shown in Figure 1(a). Non-random errors manifest as multiple errors clustered within a short data sequence, as shown in Figure 1(b). Therefore, non-random errors are also called burst errors. Burst errors are common in real-world communication networks. Examples include continuous errors caused by decision feedback equalization (DFE) and continuous errors caused by fast fading due to multipath effects in wireless information. As shown above, the data in Figure 1(a) and Figure 1(b) have the same current BER, but different error distributions lead to different BERs after FEC. Under most communication transmission conditions, burst errors result in a better post-correction BER than random errors, given the same pre-correction FEC.

[0078] To address burst bit errors, an interleaver is typically introduced to further reduce the post-correction FEC error rate. Figure 2 illustrates how the interleaver is used. In Figure 2, Tx represents the data to be input into the FEC encoder at the data transmitter. After being encoded by the FEC encoder at the data transmitter, this data is input into the interleaver for interleaving. The data output by the interleaver is transmitted via a communication channel to the data receiver. At the data receiver, the data is input into the deinterleaver for deinterleaving and then into the FEC decoder for decoding. Rx represents the data output from the FEC decoder at the data receiver. After FEC and interleaving, the BER in Rx is significantly reduced. The interleaver can be located in the PCS of an Ethernet device, such as the PCS in an Ethernet PHY chip, where the PCS performs data interleaving.

[0079] As previously mentioned, with the development of internet technology, Ethernet data transmission rates continue to increase, leading to a further increase in the BER at the data receiving end. Consequently, the interleaving performed by the PCS often fails to meet the required BER reduction. Redesigning the PCS circuitry would also require redesigning the Ethernet PHY chip, which would incur significant costs.

[0080] This application proposes a method for transmitting data, which is performed by an Ethernet device on the data transmission side. This method expands the functionality of the Ethernet device's PMA sublayer and performs data interleaving within the PMA sublayer. Specifically, the PMA sublayer obtains a data stream that has undergone FEC encoding and performs data processing step 1 on the data stream to obtain an interleaved data stream. Data processing step 1 includes interleaving using a first interleaving method, specifically symbol interleaving or convolutional interleaving. Through this method, the PMA sublayer performs symbol interleaving or convolutional interleaving on the data stream. The specific interleaving method performed by the PMA sublayer can be flexibly designed to ensure that the actual requirements for reducing BER in the network are met. Furthermore, because the PMA sublayer is relatively simple to expand, its design does not require modifications to the existing PCS. Even when the PMA sublayer is located in a pluggable module, the design of the PMA sublayer does not require modifications to the main chip of the existing Ethernet physical layer (PHY). This minimizes research and development costs while meeting the requirements for reducing BER in high-speed data transmission scenarios.

[0081] FIG3 is a flow chart of a data transmission method 300 according to an embodiment of the present application. The method may include, for example:

[0082] Step 301: The physical medium of the Ethernet device connects to the PMA sublayer to obtain a data stream, which is a data stream encoded with forward error correction (FEC).

[0083] The Ethernet device can be an Ethernet chip, Ethernet forwarding devices such as switches and routers, or pluggable optical or electrical modules in Ethernet networks. In this case, the Ethernet device is a data transmitting Ethernet device. It will be readily understood that, at certain times, the Ethernet device can also function as a data receiving Ethernet device and execute the data receiving method.

[0084] In an embodiment of the present application, the Ethernet physical layer can be further divided into multiple sublayers according to the main functions, including but not limited to: PCS, PMA sublayer, physical medium dependent (PMD) sublayer, etc. The specific implementation of these sublayers can be electronic circuits. Among them, the PCS is responsible for encoding, scrambling and other processing of the data, and FEC encoding is also performed in the PCS. There are three ways to implement the Ethernet physical layer in the embodiment of the present application. The first way is shown in Figure 4 (a), where the Ethernet physical layer includes PCS, PMA sublayer and PMD sublayer, and all three sublayers are included in the PHY chip. This method is generally suitable for copper cable transmission, backplane transmission and co-packaging optics (CPO) transmission scenarios. The second approach is shown in Figure 4(b), where the Ethernet physical layer includes the PCS, PMA sublayer, and PMD sublayer. The PCS and one PMA sublayer are included in the PHY chip, while the other PMA sublayer and PMD sublayer are included in a pluggable optical module or pluggable electrical module. The pluggable optical module or pluggable electrical module is independent of the PHY chip in terms of circuit implementation and is connected to the PHY chip via an interface. The interface type shown in Figure 4(b) is AUI. It is understood that this interface type can also include other types, such as CEI. This approach is generally applicable to optical fiber transmission or electrical transmission scenarios, and is also applicable to scenarios using concatenated codes. The third method is shown in Figure 4(c), where the Ethernet physical layer includes PCS, PMA sublayer, PMD sublayer, DTE_XS and physical layer device extender sublayer (physical layer device extender sublayer, PHY_XS). DTE_XS and the first PMA sublayer are included in the PHY chip, and the second PMA sublayer, PHY_XS, PCS, the third PMA sublayer and the PMD sublayer are included in a pluggable optical module or a pluggable electrical module. The pluggable optical module or the pluggable electrical module is also independent of the PHY chip in circuit implementation and is connected to the PHY chip through an interface. The interface type shown in Figure 4(c) is AUI. It can be understood that the interface type can also include other types, such as CEI.

[0085] In an embodiment of the present application, the PMA sublayer interleaved by the first interleaving method may be the PMA sublayer in FIG. 4(a) above, the PMA sublayer located in the pluggable optical module or the pluggable electrical module in FIG. 4(b) above, the PMA sublayer located in the PHY chip in FIG. 4(c), or the second PMA sublayer located in the pluggable optical module or the pluggable electrical module in FIG. 4(c), that is, the PMA sublayer adjacent to the PCS and the PMD.

[0086] When the PMA sublayer interleaved using the first interleaving method is a PMA sublayer located in a pluggable optical module or a pluggable electrical module, in order to implement the method in the embodiment of the present application, it is only necessary to design the PMA sublayer in the pluggable module without modifying the PHY chip, and it is compatible with existing PHY chips. In addition, the same PHY chip can be matched with a variety of different pluggable optical modules or pluggable electrical modules to achieve the expansion of multiple different interleaving methods. When the Ethernet data transmission rate is further improved in the future, the error correction performance can be upgraded by directly replacing the pluggable module.

[0087] When the PMA sublayer interleaved using the first interleaving method is located within a PHY chip, implementing the method in the embodiments of the present application requires only redesigning the PMA sublayer within the chip, while the existing PCS can still be reused. As previously mentioned, the PCS has complex functionality, while the PMA sublayer is relatively simple and easier to expand. Therefore, the method in the embodiments of the present application minimizes modifications to the PHY chip.

[0088] In one optional embodiment, the PMA sublayer interleaving in the first interleaving mode obtains the data stream from the upper sublayer in the data stream transmission direction. In conjunction with the three aforementioned physical layer implementations, the upper sublayer may be PCS, PMA, or DTE_XS. When the PMA sublayer and the upper sublayer are separate in circuit implementation, the PMA sublayer obtains the data stream from the upper sublayer via an interface, such as AUI or CEI.

[0089] In an optional manner, the rate of the interface through which the PMA sublayer obtains the data stream is at least one of the following: 200 Gbps or 400 Gbps, or other rate values, which are not limited here.

[0090] In an optional manner, the data stream acquired by the PMA sublayer may be one data stream or multiple data streams.

[0091] In one optional approach, the PMA sublayer can first split a single data stream after receiving it. For example, if the interface receiving the data stream on the PMA sublayer operates at 400 Gbps, the sublayer can first split the data stream into two groups, which the PMA sublayer then interleaves separately. This facilitates breakout processing in subsequent pluggable modules.

[0092] Step 302: The PMA sublayer performs a data processing process 1 on the data stream to obtain an interleaved data stream. The first data processing process 1 includes interleaving in a first interleaving manner.

[0093] As mentioned above, the data stream acquired by the PMA sublayer may be one data stream or multiple data streams. Accordingly, the interleaving performed in the first interleaving manner may be interleaving within a data stream or interleaving between data streams.

[0094] In the embodiments of the present application, the interleaving method can have multiple attributes. The interleaving type is an attribute of the interleaving method. The interleaving type of the first interleaving method described above is symbol interleaving or convolution interleaving. Among them, symbol interleaving can also be called block interleaving. Symbol interleaving and convolution interleaving are basically the same in terms of error correction performance. However, when achieving the same error correction performance, the two methods may have different latency and power consumption.

[0095] Interleaving depth is also a property of the interleaving method. The interleaving depth indicates the number of FEC codewords involved in interleaving, which affects the error correction performance.

[0096] FIG5 exemplarily shows a schematic diagram of a data processing method of symbol interleaving.

[0097] As shown in Figure 5, multiple FEC-encoded codewords are obtained from the data stream to be interleaved as codewords participating in interleaving, such as codeword A, codeword B, codeword C, codeword D, etc. When the codewords participating in interleaving come from the same data stream, it is called intra-stream interleaving. When the codewords participating in interleaving come from different data streams, it is called inter-stream interleaving. Each codeword includes p FEC-encoded symbols, each symbol includes q bits, that is, each codeword includes p×q bits. For example, the length of each symbol can be 10 bits, that is, symbol interleaving is performed with a granularity of 10 bits. As shown in the figure, 4 codewords are selected from the data stream to be interleaved, that is, the interleaving depth is 4 codewords. When the codewords are RS codewords, the interleaving depth can be called 4×RS. These four codewords are alternately distributed at a symbol granularity as n data streams on n lanes. Adjacent symbols in each data stream come from different codewords. Symbols from these four codewords appear alternately, forming an interleaved data sequence, namely, interleaved lane 1 to interleaved lane n shown in the figure.

[0098] FIG6 exemplifies a schematic diagram of a data processing method of convolution interleaving. Convolution interleaving involves a variety of design parameters, including the number of delay lines, delay block length, and delay block number. As shown in FIG6 , multiple FEC-encoded codewords are obtained from the data stream to be interleaved for interleaving, including cwA, cwB, cwC, cwD, etc. The interleaving depth is 4 codewords, that is, 4 codewords are selected from the data stream to be interleaved, namely the above-mentioned cwA, cwB, cwC, and cwD, and the number of delay lines is 4, namely 4 lines of data from top to bottom, line 0, 1, 2, and 3. In FIG6 , D represents a delay block. Each delay block is composed of a shift register (LFSR) that can temporarily store certain data, and the number of delay blocks on each delay line is different. There is a switch on the input and output sides of the interleaver that can be switched to connect a certain delay line. FEC codeword data enters the convolutional interleaver column by column, with the delay block length as the granularity, as shown in Figure 6 (a, b, c, d). When the FEC codeword length is the same as the delay block length, the granularity entering the convolutional interleaver is the FEC codeword length. When the FEC codeword length is different from the delay block length, the FEC codeword data must be adjusted to enter the convolutional interleaver with the delay block length as the granularity. Each time a delay block length of data is input from the input side, a delay block length of data is output from the output side. The switchable connections on both sides then switch to the next delay line, polling in the order {line 0, line 1, line 2, line 3, line 0, line 1, line 2, line 3, line 0, line 1, …}. Furthermore, in Figure 6, the output side x represents the data stored in the delay block four codewords prior. Moreover, although FIG6 takes the convolution interleaving of one data stream as an example, the convolution interleaving between multiple data streams is similar to the process shown in FIG6 , the difference is that the codewords involved in the interleaving come from multiple data streams, which will not be repeated here.

[0099] In an embodiment of the present application, the first interleaving mode performed by the PMA sublayer can be implemented by the aforementioned symbol interleaving or convolutional interleaving. Optionally, the PMA sublayer needs to retain the availability of an alignment marker (AM) during the interleaving process so that data synchronization can still be performed based on the AM at the data receiving side.

[0100] In one optional approach, the data stream obtained by the PMA sublayer from the previous sublayer may have already been interleaved. That is, the data stream may have already been interleaved by other sublayers preceding the PMA sublayer. Specifically, the data stream obtained by the PMA sublayer is the data stream obtained after executing data processing step 2, which includes interleaving using the second interleaving method. This data processing step 2 may be performed by other sublayers preceding the PMA sublayer. As previously mentioned, the sublayer performing data processing step 2 may be directly adjacent to the PMA sublayer or indirectly adjacent, i.e., interleaved with other sublayers. Alternatively, the second interleaving method may be performed by the PCS or DTE_XS. This second interleaving method may also be implemented using the aforementioned symbol interleaving or convolutional interleaving. In other words, interleaving performed by the PMA sublayer does not conflict with interleaving performed by other sublayers preceding it. In particular, when the PMA sublayer is located in a pluggable optical or electrical module, there's no need to modify the PCS or DTE_XS in the PHY chip, maintaining compatibility with existing PHY chips. Simply designing the PMA sublayer in the pluggable module to meet network BER reduction requirements is sufficient. When the PMA sublayer is located in a PHY chip, the existing PCS or DTE_XS can be reused, requiring only a redesign of the PMA sublayer in the chip. This relatively simple expansion addresses network BER reduction requirements.

[0101] In one optional approach, the first and second interleaving modes can be different, i.e., interleaving can be altered by interleaving at the PMA sublayer. To some extent, the interleaving at the PMA sublayer can be considered to override the interleaving at other preceding sublayers. This interleaving alteration allows for flexible implementation of new error correction designs within the PMA sublayer, better meeting the demand for lower BER driven by the ever-increasing Ethernet data rates, without requiring modifications to preceding sublayers or even the entire Ethernet PHY layer's main chip.

[0102] In one optional embodiment, the interleaving transformation is specifically: the first interleaving mode and the second interleaving mode have different interleaving depths. Taking the PCS performing 2×RS interleaving as an example, the PMA sublayer can perform 4×RS interleaving. This means that the PMA sublayer implements deeper interleaving, which can meet the error correction requirements in scenarios where a single physical channel speed reaches 200 Gbps.

[0103] In one optional embodiment, the interleaving types of the first interleaving mode and the second interleaving mode may be the same or different. For example, the PMA sublayer and the PCS sublayer both perform symbol interleaving with a 10-bit granularity. For another example, the PCS sublayer performs symbol interleaving, while the PMA sublayer performs convolutional interleaving.

[0104] In an optional manner, before interleaving using the first interleaving method, the PMA sublayer may deinterleave for the second interleaving method, or the PMA sublayer may not deinterleave for the second interleaving method. That is, the PMA sublayer may first deinterleave the interleaving performed by other previous sublayers, and then perform interleaving within the PMA sublayer. Alternatively, the PMA sublayer may not deinterleave the interleaving performed by other previous sublayers, but directly perform interleaving within the PMA sublayer. Taking the PCS performing 2×RS interleaving as an example, the PMA sublayer first waits for the data of 2 codewords to be obtained, and then starts interleaving with the data of the 2 codewords that arrive subsequently. The total number of codewords involved in interleaving is 4, that is, the interleaving depth is 4×RS.

[0105] In one optional embodiment, the data processing process 1 performed by the PMA sublayer on the data stream also includes bit multiplexing or symbol group multiplexing. As previously mentioned, after data processing, the PMA sublayer outputs the data to the next sublayer, such as the PMD sublayer. Therefore, the PMA sublayer must ensure that the output data is compatible with the number of channels connected to the next sublayer. Specifically, bit multiplexing or symbol group multiplexing can be used to process the output data to be compatible with the number of channels connected to the next sublayer. This bit multiplexing or symbol group multiplexing can be included in the data processing corresponding to the first interleaving method described above. That is, the PMA sublayer performs interleaving while simultaneously performing bit multiplexing or symbol group multiplexing on the data, taking into account the number of channels connected to the next sublayer. This bit multiplexing or symbol group multiplexing can also be performed after the data processing corresponding to the first interleaving method described above. That is, the PMA sublayer first performs interleaving and then performs bit multiplexing or symbol group multiplexing on the data to ensure that the data stream is compatible with the number of channels connected to the next sublayer.

[0106] Figures 7(a) to 7(c) illustrate exemplary data processing methods for symbol group multiplexing. For example, there are two initial data streams participating in the multiplexing, namely data stream 1 and data stream 2. The number of initial data streams participating in the multiplexing can be any number and is not limited here. In symbol group multiplexing, each data stream is divided into symbols. The length of a symbol can be, for example, 20 bits or 40 bits. At least two symbols in each data stream can form a symbol group. The data from the two data streams are then polled and alternately multiplexed into a channel at the symbol group granularity, such as the muxed lane in Figure 7(a). The muxed lane corresponds to a channel in the inter-sublayer interface. It is easy to understand that when the inter-sublayer interface includes four channels, when multiplexing is performed in the manner shown in Figure 7(a), eight data streams will be multiplexed into four muxed lanes. In the embodiment of the present application, in the symbol group multiplexing performed by the PMA sublayer, the number of input data streams and the number of channels after multiplexing can be determined based on actual conditions and are not limited here. Furthermore, in symbol group multiplexing, when data from two data streams are alternately multiplexed into a channel using symbol group polling, this can also include swapping the data position in one of the data streams, for example, swapping the positions of two symbols front to back, as shown in Figure 7(b), or delaying the data position in one of the data streams by one symbol to form a stagger, and other operations, as shown in Figure 7(c), where x is the preceding or following symbol due to the delay. In bit multiplexing, the data streams involved in the multiplexing are divided with a granularity of one bit. Other operations are similar to those of symbol group multiplexing and are not further described here.

[0107] In an optional manner, before the PMA sublayer performs convolution interleaving, a step of bit multiplexing or symbol group multiplexing on the data stream can be added to adjust the number of data streams during convolution interleaving. The specific operation can be referred to as shown in Figures 7(a) to 7(c) above and will not be repeated here.

[0108] In an optional embodiment, the data processing process 1 performed by the PMA sublayer on the data stream may also include one or more other processes, such as bit demultiplexing (bit demux) or symbol-group demultiplexing (symbol-group demux), AM locking, and deskew. As previously described, the data stream obtained by the PMA sublayer comes from the upper sublayer, which can be, for example, the PCS, DTE_XS, or another PMA sublayer. The PMA sublayer and the upper sublayer may or may not be electrically separated. When electrically separated, the PMA sublayer and the upper sublayer may be connected via an interface, including but not limited to AUI or CEI. Before being transmitted from the upper sublayer to the PMA sublayer, these data streams may undergo bit multiplexing or symbol-group multiplexing to adapt the number of channels between sublayers. Furthermore, during transmission across the interface, the data in these data streams may experience loss of lock or skew, necessitating recovery of the received data streams within the PMA sublayer. For example, in the Ethernet physical layer implementation shown in Figure 4(b), the PMA sublayer in the pluggable module receives a data stream via the AUI. This data stream is bit-multiplexed or symbol-group-multiplexed in the PMA sublayer in the PHY chip. The PMA sublayer in the pluggable module first needs to perform targeted bit demultiplexing or symbol-group demultiplexing. Furthermore, it performs AM lock and deskew on data that may have lost lock or skewed during transmission via the AUI interface, thereby recovering the data stream sent to the channel by the previous sublayer. For example, when the previous sublayer is the PCS layer, the PCS lane data stream is recovered. Optionally, the above-mentioned bit demultiplexing or symbol-group demultiplexing, as well as alignment flag locking and deskewing, can be performed before the interleaving process described above using the first interleaving method. That is, the PMA sublayer first recovers the data stream from the previous sublayer before performing subsequent interleaving. Optionally, the granularity of the bit demultiplexing is 1 bit, and the granularity of the symbol group demultiplexing can be 20 bits or 40 bits. Optionally, in the above de-skew processing, the data can be aligned to the AM or to the symbol boundary, for example, the data can be aligned to the symbol boundary with a 10-bit granularity, or the data can be aligned to the symbol boundary with a 20-bit granularity, or the data can be aligned to the symbol boundary with a 40-bit granularity.

[0109] In an optional manner, the PMA sublayer may further perform FEC encoding to improve data error correction performance.

[0110] In one embodiment, the single physical channel rate of the data stream obtained after interleaving by the PMA sublayer is 200 Gbps. It is easy to understand that the 200 Gbps is a floating value within the conventional range in the art, and does not refer to the exact value of the channel rate at any time.

[0111] The above is a description of the method performed by the Ethernet device on the data sending side. The Ethernet device on the data receiving side needs to perform a method that cooperates with the data sending side. Figure 8(a) shows a method for receiving data. After the PMA sublayer in the Ethernet device on the data sending side performs interleaving, the PMA sublayer in the Ethernet device on the data receiving side needs to perform a deinterleaving process accordingly. The method is performed by an Ethernet device, which can be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, as well as a pluggable optical module or electrical module in the Ethernet, etc. The PMA sublayer of the Ethernet device on the data receiving side obtains a data stream and performs a data processing process 31 on the data stream to obtain a deinterleaved data stream, wherein the data processing process 31 includes deinterleaving through a first deinterleaving method, and the deinterleaving type of the first deinterleaving method is specifically symbol deinterleaving or convolutional deinterleaving. In this method, since the expansion of the PMA sublayer is relatively simple, the design of the PMA sublayer does not require changes to the existing PCS. Even when the PMA sublayer is located in a pluggable module, the design of the PMA sublayer does not require changes to the main chip of the existing Ethernet physical PHY layer. This meets the need to reduce BER in high-speed data transmission scenarios while minimizing research and development costs.

[0112] FIG8( a ) is a flow chart of a data transmission method in an embodiment of the present application. The method may include, for example:

[0113] Step 8011: The PMA sublayer of the Ethernet device obtains a data stream, which is a data stream encoded with forward error correction (FEC).

[0114] The Ethernet device can be an Ethernet chip, Ethernet forwarding devices such as switches and routers, or pluggable optical or electrical modules in Ethernet networks. In this case, the Ethernet device is a data receiving Ethernet device. It will be readily understood that, at certain times, the Ethernet device can also function as a data sending Ethernet device and execute the data sending method.

[0115] The implementation of the Ethernet physical layer in the Ethernet device on the data receiving side can also refer to the implementation shown in Figures 4(a), 4(b), and 4(c), and will not be described in detail here.

[0116] In an embodiment of the present application, the PMA sublayer deinterleaved by the first deinterleaving method may be the PMA sublayer in FIG. 4( a) above, the PMA sublayer located in the pluggable optical module or the pluggable electrical module in FIG. 4( b) above, the PMA sublayer located in the PHY chip in FIG. 4( c), or the second PMA sublayer located in the pluggable optical module or the pluggable electrical module in FIG. 4( c), that is, the PMA sublayer adjacent to the PCS and the PMD.

[0117] In one optional embodiment, the PMA sublayer obtains the data stream from the upper sublayer in the data stream transmission direction. In conjunction with the three physical layer implementations described above, the upper sublayer may be the PMD. When the PMA sublayer and the upper sublayer are separate in circuit implementation, the PMA sublayer obtains the data stream from the upper sublayer via an interface, such as the AUI or CEI.

[0118] In an optional manner, the data stream acquired by the PMA sublayer may be one data stream or multiple data streams.

[0119] Step 8012: The PMA sublayer performs data processing 31 on the data stream to obtain a deinterleaved data stream. The data processing 31 includes deinterleaving in a first deinterleaving manner.

[0120] As mentioned above, the data stream acquired by the PMA sublayer may be one data stream or multiple data streams. Accordingly, the interleaving performed in the first deinterleaving manner may be deinterleaving within a data stream or deinterleaving between data streams.

[0121] In the embodiment of the present application, the deinterleaving type of the first deinterleaving mode is symbol deinterleaving or convolutional deinterleaving. The data processing process of symbol deinterleaving or convolutional deinterleaving is the deinterleaving process corresponding to the data processing process shown in Figures 5 and 6 above, and its specific details are not repeated here.

[0122] In an optional manner, corresponding to the first interleaving manner, the deinterleaving of the first deinterleaving manner is based on a granularity of 10 bits, or in other words, the PMA sublayer performs 10-bit symbol deinterleaving.

[0123] In one optional embodiment, the data processing process 31 performed by the PMA sublayer on the receiving side also includes bit multiplexing or symbol group multiplexing, so that the number of output data streams can adapt to the number of data channels between the PMA sublayer and the next sublayer in the data transmission direction. The specific implementation method is similar to the bit multiplexing or symbol group multiplexing in the PMA sublayer on the transmitting side and will not be repeated here. The granularity of bit multiplexing is 1 bit, and the granularity of symbol group multiplexing can be 20 bits or 40 bits. Optionally, the bit multiplexing or symbol group multiplexing process can be performed after the deinterleaving process using the third interleaving method described above, or the bit multiplexing or symbol group multiplexing process can also be included in the deinterleaving process using the third interleaving method described above.

[0124] In an optional manner, the data processing process 31 performed by the PMA sublayer on the data stream further includes bit demultiplexing or symbol group demultiplexing, wherein the granularity of the bit demultiplexing is 1 bit, and the granularity of the symbol group demultiplexing can be 20 bits or 40 bits.

[0125] In an optional manner, the data processing process 31 performed by the PMA sublayer on the data stream further includes AM locking and de-skew.

[0126] The above-mentioned bit demultiplexing or symbol group demultiplexing, as well as alignment flag locking and de-skew, can restore the data stream from the previous sublayer. For example, the previous sublayer is PMD. Optionally, the above-mentioned bit demultiplexing or symbol group demultiplexing, as well as alignment flag locking and de-skew processing, can be performed before the deinterleaving processing using the first deinterleaving mode, that is, the above-mentioned bit demultiplexing or symbol group demultiplexing, as well as alignment flag locking and de-skew processing, can be performed to restore the data stream from the previous sublayer and perform deinterleaving.

[0127] In one optional approach, after the PMA sublayer performs deinterleaving on the data stream in data processing step 31, it can further interleave the deinterleaved data stream using a second interleaving method to obtain a reinterleaved data stream. This is to coordinate with the deinterleaving processing of the PCS or DTE_XS in existing receiving-side Ethernet equipment, eliminating the need to modify the existing PCS or DTE_XS and maximizing compatibility with existing PHY chips.

[0128] In an optional manner, the deinterleaving depth of the first deinterleaving manner is 4×RS.

[0129] In an optional manner, the PMA sublayer may also perform FEC decoding to improve data error correction performance.

[0130] In addition, more implementation details in the receiving-side Ethernet device can be coordinated with the above-mentioned sending-side Ethernet device, and will not be repeated here.

[0131] Figure 8(b) illustrates another method for receiving data, which is performed by an Ethernet device. The Ethernet device can be an Ethernet chip, an Ethernet forwarding device such as a switch or router, or a pluggable optical or electrical module in an Ethernet network. After the PMA sublayer in the Ethernet device on the data transmitting side performs interleaving, the interleaving method of the data stream changes. The PMA sublayer in the Ethernet device on the data receiving side needs to perform a corresponding interleaving transformation to convert the interleaving method of the data stream to an interleaving method compatible with the deinterleaving process performed in other sublayers, thereby avoiding modifications to the PHY chip. For example, if the Ethernet PHY chip performs 2×RS deinterleaving on the data stream, the PMA sublayer can transform the interleaving method of the obtained data stream to 2×RS interleaving, so that the 2×RS deinterleaving performed on the data stream by the PHY chip can obtain a correct data stream. The PMA sublayer of the Ethernet device on the data receiving side obtains the data stream and performs a data processing process 32 on the data stream to obtain an interleaved data stream. The data processing process 32 includes interleaving the data stream, where the interleaving type is symbol interleaving or convolutional interleaving. In this method, the PMA sublayer in the Ethernet device on the data receiving side performs interleaving to transform the interleaving mode of the data stream into an interleaving mode that is compatible with the deinterleaving process performed in other sublayers. That is, interleaving transformation is achieved. This can improve error correction performance and meet the BER reduction requirements in the network while avoiding changes to the PHY chip.

[0132] FIG8( b ) is a flow chart of a data transmission method in an embodiment of the present application. The method may include:

[0133] Step 8021: The PMA sublayer of the Ethernet device obtains a data stream, where the data stream is a data stream encoded with forward error correction (FEC).

[0134] The Ethernet device can be an Ethernet chip, Ethernet forwarding devices such as switches and routers, or pluggable optical or electrical modules in Ethernet networks. In this case, the Ethernet device is a data receiving Ethernet device. It will be readily understood that, at certain times, the Ethernet device can also function as a data sending Ethernet device and execute the data sending method.

[0135] The implementation of the Ethernet physical layer in the Ethernet device on the data receiving side can also refer to the implementation shown in Figures 4(a), 4(b), and 4(c), and will not be described in detail here.

[0136] In an embodiment of the present application, the PMA sublayer deinterleaved by the first deinterleaving method may be the PMA sublayer in FIG. 4( a) above, the PMA sublayer located in the pluggable optical module or the pluggable electrical module in FIG. 4( b) above, the PMA sublayer located in the PHY chip in FIG. 4( c), or the second PMA sublayer located in the pluggable optical module or the pluggable electrical module in FIG. 4( c), that is, the PMA sublayer adjacent to the PCS and the PMD.

[0137] In one optional embodiment, the PMA sublayer obtains the data stream from the upper sublayer in the data stream transmission direction. In conjunction with the three physical layer implementations described above, the upper sublayer may be the PMD. When the PMA sublayer and the upper sublayer are separate in circuit implementation, the PMA sublayer obtains the data stream from the upper sublayer via an interface, such as the AUI or CEI.

[0138] In an optional manner, the data stream acquired by the PMA sublayer may be one data stream or multiple data streams.

[0139] Step 8012: The PMA sublayer performs a data processing process 32 on the data stream to obtain an interleaved data stream. The data processing process 32 includes interleaving the data stream.

[0140] As mentioned above, the data stream acquired by the PMA sublayer may be one data stream or multiple data streams. Accordingly, the above interleaving may be interleaving within a data stream or interleaving between data streams.

[0141] In the embodiment of the present application, the interleaving type is symbol interleaving or convolution interleaving. The data processing process of symbol interleaving or convolution interleaving refers to the data processing process shown in Figures 5 and 6 above, and its specific details are not repeated here.

[0142] In an optional embodiment, the symbol interleaving is performed with a granularity of 10 bits.

[0143] In an optional manner, the interleaved data stream is deinterleaved by the PCS or DTE_XS.

[0144] In one optional manner, the interleaving depth is 2×RS. When the PCS or DTE_XS in the Ethernet PHY chip performs 2×RS deinterleaving on the data stream, the PMA sublayer can convert the interleaving mode of the acquired data stream to 2×RS interleaving, so that the PHY chip can obtain the correct data stream after performing 2×RS deinterleaving on the data stream.

[0145] In one optional embodiment, data processing 32 includes performing deinterleaving using a first deinterleaving method, where the deinterleaving type of the first deinterleaving method is specifically symbol interleaving or convolutional deinterleaving, to obtain a deinterleaved data stream. The deinterleaving of the first deinterleaving method may be 4×RS. For more details about the deinterleaving process using the first deinterleaving method, refer to the relevant description of the data transmission method shown in Figure 8(a) and are not repeated here.

[0146] In an optional manner, the data processing process 32 includes: bit demultiplexing or symbol group demultiplexing, wherein the granularity of the bit demultiplexing is 1 bit, and the granularity of the symbol group demultiplexing can be 20 bits or 40 bits.

[0147] In an optional manner, the data processing process 32 includes: alignment marker AM locking and de-skew.

[0148] The data stream acquired by the PMA sublayer originates from the previous sublayer in the data transmission direction, which may be, for example, a PMD sublayer. The data stream from the previous sublayer can be recovered through the aforementioned bit demultiplexing or symbol group demultiplexing, as well as alignment flag locking and deskewing. Optionally, the aforementioned bit demultiplexing or symbol group demultiplexing, alignment flag locking, and deskewing processes can also implement a first deinterleaving mode, i.e., recovering the data stream from the previous sublayer and achieving deinterleaving through bit demultiplexing or symbol group demultiplexing, as well as alignment flag locking and deskewing.

[0149] In one optional embodiment, data processing 32 includes bit multiplexing or symbol group multiplexing. Bit multiplexing has a granularity of 1 bit, while symbol group multiplexing can have a granularity of 20 bits or 40 bits. This bit multiplexing or symbol group multiplexing allows the number of data streams output by the PMA sublayer to adapt to the number of data channels between the PMA and the next sublayer in the data transmission direction. Optionally, this bit multiplexing or symbol group multiplexing process can be performed after the deinterleaving process using the third interleaving method, or it can be included in the deinterleaving process using the third interleaving method.

[0150] In an optional manner, the PMA sublayer may also perform FEC decoding to improve data error correction performance.

[0151] In addition, more implementation details in the receiving-side Ethernet device can be coordinated with the above-mentioned sending-side Ethernet device, and will not be repeated here.

[0152] Furthermore, in the method shown in FIG. 8( a ) or FIG. 8( b ), in the receiving-side Ethernet device, after the interleaving transformation in the PMA sublayer, the data stream may be directly AUI lane data or PCS lane data.

[0153] The main steps performed by the PMA sublayers on the receiving side and the transmitting side in the embodiment of the present application can be illustrated in Figures 9(a) to 9(d).

[0154] When applicable to the implementation of the physical layer as shown in Figure 4(b), the PMA sublayer is located in a pluggable optical module or a pluggable electrical module and is connected to the upper sublayer through an interface. The main steps performed by the PMA sublayer on the data sending side are shown on the left side of Figure 9(a), and the main steps performed by the PMA sublayer on the data receiving side are shown on the right side of Figure 9(a). The arrows in the figure indicate the direction of data transmission.

[0155] On the data transmission side, the PMA recovers PCS Lane data through the first two steps: bit demultiplexing or symbol group demultiplexing, AM lock, and deskew. The subsequent interleaving step, distribution and interleave, re-performs symbol interleaving or convolution interleaving on the PCS Lane data. The interleaving step can be implemented in different ways: Deinterleaving can be performed to recover the complete RS codewords performed in the PCS, and then the four codewords are collected for symbol interleaving or convolution interleaving, and distributed into the required number of lanes. Alternatively, deinterleaving can be omitted, meaning that the complete RS codewords are not recovered, and the PCS Lane data can be directly arranged in a specific order to obtain the required number of output lanes. The interleaving steps described above can be referenced in the description of the methods shown in Figures 5 and 6 and will not be repeated here. Furthermore, Figure 9(a) includes a symbol group pair multiplexing or bit multiplexing step, which is used to combine the data into the number of data channels required by the next sublayer. Other details in Figure 9(a) can be referenced in the description of the data transmission method shown in Figure 3 and will not be repeated here. Moreover, each step on the data receiving side corresponds to that on the data sending side, and reference may be made to the relevant description of the data receiving method shown in FIG. 8( a ) or FIG. 8( b ) above, which will not be repeated here.

[0156] When applied to the physical layer implementation shown in Figure 4(b), the PMA sublayer is located in a pluggable optical module or pluggable electrical module and is connected to the previous sublayer via an interface. The main steps performed by the PMA sublayer on the data transmission side can also be shown on the left side of Figure 9(b), and the main steps performed by the PMA sublayer on the data reception side can also be shown on the right side of Figure 9(b). The arrows in the figure indicate the direction of data transmission. Compared with Figure 9(a), the main difference between the steps shown in Figure 9(b) is that the symbol group multiplexing or bit multiplexing process is included in the interleaving step. After interleaving, the number of lanes distributed equals the number of lanes required by the next sublayer. This number of lanes can be the number of physical channels or the number of PCS lanes. Therefore, a separate mux step is no longer required. The steps on the data reception side correspond to those on the data transmission side and are not further described here.

[0157] When applicable to the physical layer implementation shown in Figure 4(b), the PMA sublayer is located in a pluggable optical module or pluggable electrical module and is connected to the previous sublayer via an interface. The main steps performed by the PMA sublayer on the data transmission side can also be shown on the left side of Figure 9(c), and the main steps performed by the PMA sublayer on the data reception side can also be shown on the right side of Figure 9(c), where the arrows indicate the direction of data transmission. Compared to Figure 9(a), the main difference between the steps shown in Figure 9(c) is that the PMA layer performs the FEC encoding step. The various steps on the data reception side correspond to those on the data transmission side and will not be repeated here.

[0158] When applicable to the physical layer implementation shown in Figure 4(b), the PMA sublayer is located in a pluggable optical module or pluggable electrical module and is connected to the previous sublayer via an interface. The main steps performed by the PMA sublayer on the data transmission side can also be shown on the left side of Figure 9(d), and the main steps performed by the PMA sublayer on the data reception side can also be shown on the right side of Figure 9(d), with arrows indicating the direction of data transmission. Compared to Figure 9(b), the main difference between the steps shown in Figure 9(d) is that the PMA layer performs the FEC encoding step. The various steps on the data reception side correspond to those on the data transmission side and will not be repeated here.

[0159] When applicable to the physical layer implementation shown in Figures 4(a) or 4(c), the PMA sublayer is not connected to the previous sublayer via an interface, and the PMA sublayer can directly obtain lane data. Therefore, compared to Figures 9(a) to (d), when applicable to the physical layer implementation shown in Figures 4(a) or 4(c), the main steps performed by the PMA sublayer on the data receiving side will not include bit demultiplexing or symbol group demultiplexing, AM lock, and deskew. Similarly, the main steps performed by the PMA sublayer on the data transmitting side will also not include bit demultiplexing or symbol group demultiplexing, AM lock, and deskew. The other steps are similar to those in Figures 9(a) to 9(d) and will not be repeated here.

[0160] The above describes the method for sending and receiving data according to the embodiment of the present application. Corresponding to the above method, the embodiment of the present application also provides an Ethernet device for sending and receiving data.

[0161] FIG10 is a schematic diagram of the structure of an Ethernet device provided in an embodiment of the present application. The Ethernet device can be used to send or receive data. The Ethernet device can be the Ethernet device in the data sending method shown in FIG3. Based on the structure shown in FIG9, the Ethernet device can perform all or part of the operations in the method shown in FIG3. It should be understood that the Ethernet device can include more additional structures than the structure shown or omit some of the structures shown therein, and the embodiment of the present application is not limited to this. As shown in FIG10, the Ethernet device includes:

[0162] The PMA circuit is configured to obtain a data stream, wherein the data stream is a data stream encoded by forward error correction (FEC); perform a first data processing process on the data stream to obtain an interleaved data stream, wherein the first data processing process includes interleaving through a first interleaving mode; wherein the interleaving type of the first interleaving mode is symbol interleaving or convolutional interleaving.

[0163] In some possible implementations, the symbol interleaving is performed with a granularity of 10 bits.

[0164] In some possible implementations, the first data processing process further includes: bit multiplexing or symbol group pair multiplexing.

[0165] In some possible implementations, before interleaving in the first interleaving manner, the first data processing process further includes: bit demultiplexing or symbol group demultiplexing.

[0166] In some possible implementations, before interleaving in the first interleaving manner, the first data processing process further includes: locking an alignment marker AM and de-skewing.

[0167] In some possible implementations, the data stream is a data stream obtained after executing a second data processing process, and the second data processing process includes interleaving using a second interleaving method.

[0168] In some possible implementations, the first interleaving mode and the second interleaving mode have different interleaving depths.

[0169] In some possible implementations, the interleaving depth of the second interleaving mode is 2×RS.

[0170] In some possible implementations, the first data processing process further includes: deinterleaving the second interleaving method.

[0171] In some possible implementations, the second data processing process is performed by a physical coding sublayer PCS or a data terminal equipment extension sublayer DTE_XS.

[0172] In some possible implementations, the interleaving depth of the first interleaving mode is 4×RS.

[0173] In some possible implementations, the channel rate of the interleaved data stream is 200 Gbps.

[0174] In some possible implementations, a rate of an interface through which the PMA circuit receives the data stream is at least one of the following: 200 Gbps or 400 Gbps.

[0175] In some possible implementations, the PMA circuit obtains the data stream from an attachment unit interface AUI or a common electrical interface CEI.

[0176] In some possible implementations, the PMA circuit sends the interleaved data stream to a physical medium dependent PMD sublayer.

[0177] For a detailed description of the operations performed by the Ethernet device, reference may be made to the detailed description of the method embodiment shown in FIG3 , which will not be repeated here.

[0178] The Ethernet device can be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, or a pluggable optical module or electrical module in the Ethernet.

[0179] When the Ethernet device is an Ethernet chip, the Ethernet chip can be implemented using the structure shown in Figure 4(a). The PMA circuit in the Ethernet device corresponds to the PMA sublayer shown in Figure 4(a). Optionally, the Ethernet device also includes PCS and PMD sublayers.

[0180] When the Ethernet device is a pluggable optical module or electrical module, the pluggable optical module or electrical module can be implemented using the structure shown in Figure 4(b) or Figure 4(c). The PMA circuit in the Ethernet device corresponds to the PMA sublayer shown in Figure 4(b) or the PMA sublayer adjacent to the PMD layer shown in Figure 4(c). Optionally, the Ethernet device also includes a PMD sublayer.

[0181] When the Ethernet device is an Ethernet forwarding device such as a switch or a router, the Ethernet device may include an Ethernet chip, or a pluggable optical module or electrical module, wherein the Ethernet chip, or the pluggable optical module or electrical module can perform all or part of the operations in the method of Figure 3.

[0182] FIG10 is a schematic diagram of the structure of an Ethernet device provided in an embodiment of the present application. The Ethernet device can be used to send or receive data. The Ethernet device can be the Ethernet device in the method for receiving data shown in FIG8(a). Based on the structure shown in FIG9, the Ethernet device can perform all or part of the operations in the method shown in FIG8(a). It should be understood that the Ethernet device can include more additional structures than the structure shown or omit some of the structures shown therein, and the embodiment of the present application does not limit this. As shown in FIG10, the Ethernet device includes:

[0183] The PMA circuit is configured to obtain a data stream, the data stream being a data stream encoded with forward error correction (FEC); perform a third data processing process on the data stream to obtain a deinterleaved data stream, the third data processing process comprising deinterleaving using a first deinterleaving mode; wherein the deinterleaving type of the first deinterleaving mode is symbol deinterleaving or convolutional deinterleaving.

[0184] In some possible implementations, the symbol deinterleaving is performed with a granularity of 10 bits.

[0185] In some possible implementations, the third data processing process includes: bit multiplexing or symbol group multiplexing.

[0186] In some possible implementations, the third data processing process includes: bit demultiplexing or symbol group demultiplexing.

[0187] In some possible implementations, the third data processing process includes: alignment mark AM locking and de-skew.

[0188] In some possible implementations, after the PMA circuit performs a third data processing process on the data stream, the method further includes: the PMA circuit interleaving the deinterleaved data stream using a second interleaving method to obtain a re-interleaved data stream.

[0189] In some possible implementations, the re-interleaved data stream is deinterleaved by a physical coding sublayer PCS or a data terminal equipment extension sublayer DTE_XS.

[0190] In some possible implementations, the interleaving depth of the first deinterleaving mode is 4×RS.

[0191] In some possible implementations, the PMA circuit acquiring the data stream includes: the PMA circuit acquiring the data stream after sending the interleaved data from a physical medium dependent (PMD) sublayer.

[0192] For a detailed description of the operations performed by the Ethernet device, reference may be made to the detailed description of the method embodiment shown in FIG. 8( a ) above, which will not be repeated here.

[0193] The Ethernet device can be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, or a pluggable optical module or electrical module in the Ethernet.

[0194] When the Ethernet device is an Ethernet chip, the Ethernet chip can be implemented using the structure shown in Figure 4(a). The PMA circuit in the Ethernet device corresponds to the PMA sublayer shown in Figure 4(a). Optionally, the Ethernet device also includes PCS and PMD sublayers.

[0195] When the Ethernet device is a pluggable optical module or electrical module, the pluggable optical module or electrical module can be implemented using the structure shown in Figure 4(b) or Figure 4(c). The PMA circuit in the Ethernet device corresponds to the PMA sublayer shown in Figure 4(b) or the PMA sublayer adjacent to the PMD layer shown in Figure 4(c). Optionally, the Ethernet device also includes a PMD sublayer.

[0196] When the Ethernet device is an Ethernet forwarding device such as a switch or a router, the Ethernet device may include an Ethernet chip, or a pluggable optical module or electrical module, wherein the Ethernet chip, or the pluggable optical module or electrical module can perform all or part of the operations in the method shown in Figure 8(a).

[0197] FIG10 is a schematic diagram of the structure of an Ethernet device provided in an embodiment of the present application. The Ethernet device can be used to send or receive data. The Ethernet device can be the Ethernet device in the method for receiving data shown in FIG8(b). Based on the structure shown in FIG9, the Ethernet device can perform all or part of the operations in the method shown in FIG8(b). It should be understood that the Ethernet device can include more additional structures than the structure shown or omit some of the structures shown therein, and the embodiment of the present application does not limit this. As shown in FIG10, the Ethernet device includes:

[0198] The PMA circuit is used to obtain a data stream, where the data stream is a data stream encoded by forward error correction (FEC); the PMA sublayer performs a third data processing process on the data stream to obtain an interleaved data stream, where the third data processing process includes interleaving the data stream; wherein the interleaving type of the interleaving is symbol interleaving or convolutional interleaving.

[0199] In some possible implementations, the symbol interleaving is performed with a granularity of 10 bits.

[0200] In some possible implementations, the interleaved data stream is deinterleaved by a physical coding sublayer PCS or a data terminal equipment extension sublayer DTE_XS.

[0201] In some possible implementations, the interleaving depth is 2×RS.

[0202] In some possible implementations, the third data processing process further includes: bit demultiplexing or symbol group demultiplexing.

[0203] In some possible implementations, the third data processing process further includes: locking an alignment mark AM and de-skewing.

[0204] In some possible implementations, the third data processing process further includes: bit multiplexing or symbol group multiplexing.

[0205] For a detailed description of the operations performed by the Ethernet device, reference may be made to the detailed description of the method embodiment shown in FIG8( b ), which will not be repeated here.

[0206] The Ethernet device can be an Ethernet chip, an Ethernet forwarding device such as a switch or a router, or a pluggable optical module or electrical module in the Ethernet.

[0207] When the Ethernet device is an Ethernet chip, the Ethernet chip can be implemented using the structure shown in Figure 4(a). The PMA circuit in the Ethernet device corresponds to the PMA sublayer shown in Figure 4(a). Optionally, the Ethernet device also includes PCS and PMD sublayers.

[0208] When the Ethernet device is a pluggable optical module or electrical module, the pluggable optical module or electrical module can be implemented using the structure shown in Figure 4(b) or Figure 4(c). The PMA circuit in the Ethernet device corresponds to the PMA sublayer shown in Figure 4(b) or the PMA sublayer adjacent to the PMD layer shown in Figure 4(c). Optionally, the Ethernet device also includes a PMD sublayer.

[0209] When the Ethernet device is an Ethernet forwarding device such as a switch or a router, the Ethernet device may include an Ethernet chip, or a pluggable optical module or electrical module, wherein the Ethernet chip, or the pluggable optical module or electrical module can perform all or part of the operations in the method shown in Figure 8(b).

[0210] Referring to Figure 12, Figure 12 shows a schematic diagram of the structure of an Ethernet device 2100 provided in another exemplary embodiment of the present application. The Ethernet device 2100 shown in Figure 12 is used to perform all or part of the operations involved in the data transmission method shown in Figure 3, or the data reception method shown in Figure 8(a) or Figure 8(b). The network device 2100 is, for example, an Ethernet forwarding device such as a switch or router. The Ethernet device 2100 can be implemented using a general bus architecture.

[0211] As shown in FIG. 12 , the Ethernet device 2100 includes a main control board 2110 and an interface board 2130 .

[0212] The main control board (MCB), also known as the main processing unit (MPU) or route processor card, is used to control and manage the various components of Ethernet device 2100, including routing calculations, device management, device maintenance, and protocol processing. MCB 2110 includes a central processing unit (CPU) 2111 and memory 2112.

[0213] Interface board 2130 is also known as a line processing unit (LPU), line card, or service board. It provides various service interfaces and implements data packet forwarding. Service interfaces include, but are not limited to, Ethernet interfaces and POS (Packet over SONET / SDH) interfaces. Ethernet interfaces, for example, are Flexible Ethernet Clients (FlexE Clients) interfaces. Interface board 2130 includes a central processing unit (CPU) 2131, a network processor (NPU) 2132, a forwarding table memory 2134, and a physical interface card (PIC) 2133.

[0214] The central processing unit 2131 on the interface board 2130 is used to control and manage the interface board 2130 and communicate with the central processing unit 2111 on the main control board 2110 .

[0215] The network processor 2132 is used to implement message forwarding processing. The network processor 2132 can be in the form of a forwarding chip. The forwarding chip can be a network processor (NP). In some embodiments, the forwarding chip can be implemented using an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA). Specifically, the network processor 2132 is used to forward received messages based on the forwarding table stored in the forwarding entry memory 2134. If the destination address of the message is the address of the Ethernet device 2100, the message is sent to the CPU (such as the central processing unit 2131) for processing. If the destination address of the message is not the address of the Ethernet device 2100, the next hop and outgoing interface corresponding to the destination address are searched in the forwarding table based on the destination address, and the message is forwarded to the outgoing interface corresponding to the destination address. The processing of uplink messages may include processing the message inbound interface and forwarding table lookup; the processing of downlink messages may include forwarding table lookup, etc. In some embodiments, the central processing unit may also perform the functions of the forwarding chip, such as implementing software forwarding based on a general-purpose CPU, thereby eliminating the need for a forwarding chip in the interface board.

[0216] Physical interface card 2133 implements physical layer interconnection. Raw traffic enters interface board 2130 through this card, and processed packets are sent out from this physical interface card 2133. Physical interface card 2133, also known as a daughter card, can be installed on interface board 2130. It converts optical and electrical signals into packets, performs a validity check on these packets, and then forwards them to network processor 2132 for processing. In some embodiments, central processing unit 2131 can also perform the functions of network processor 2132, such as implementing software forwarding based on a general-purpose CPU, thus eliminating the need for network processor 2132 in physical interface card 2133.

[0217] Optionally, the Ethernet device 2100 includes multiple interface boards. For example, the Ethernet device 2100 further includes an interface board 2140. The interface board 2140 includes a central processing unit 2141, a network processor 2142, a forwarding table entry memory 2144, and a physical interface card 2143. The functions and implementation of the components in the interface board 2140 are the same as or similar to those of the interface board 2130 and are not described in detail here.

[0218] Optionally, Ethernet device 2100 also includes a switching fabric unit (SFU) 2120. Switching fabric unit (SFU) 2120 may also be referred to as a switch fabric unit (SFU). If network device 2100 includes multiple interface boards, SFU 2120 is used to exchange data between the interface boards. For example, interface board 2130 and interface board 2140 can communicate via SFU 2120.

[0219] The main control board 2110 is coupled to the interface board. For example, the main control board 2110, the interface board 2130, the interface board 2140, and the switching network board 2120 are connected to the system backplane via a system bus to achieve intercommunication. In one possible implementation, an inter-process communication (IPC) channel is established between the main control board 2110 and the interface boards 2130 and 2140, and communication is performed between the main control board 2110 and the interface boards 2130 and 2140 via the IPC channel.

[0220] Logically, Ethernet device 2100 includes a control plane and a forwarding plane. The control plane includes a main control board 2110 and a central processing unit (CPU) 2111. The forwarding plane includes various components that perform forwarding, such as a forwarding table entry memory 2134, a physical interface card 2133, and a network processor 2132. The control plane performs functions such as routing, generating forwarding tables, processing signaling and protocol messages, and configuring and maintaining network device status. The control plane sends the generated forwarding tables to the forwarding plane. On the forwarding plane, the network processor 2132 forwards messages received by the physical interface card 2133 based on the forwarding tables sent by the control plane. The forwarding tables sent by the control plane can be stored in the forwarding table entry memory 2134. In some embodiments, the control plane and forwarding plane can be completely separate and not located on the same network device.

[0221] It's worth noting that there may be one or more main control boards (SPUs), which can include both active and standby SPUs. There may also be one or more interface boards. The higher the network device's data processing capabilities, the more interface boards it provides. Interface boards can also have one or more physical interface cards. There may be no SPUs, one or more SPUs, and multiple SPUs can be used to achieve load balancing and redundancy. In a centralized forwarding architecture, network devices may not require SPUs; the interface boards handle service data processing for the entire system. In a distributed forwarding architecture, network devices may have at least one SPU, which enables data exchange between multiple interface boards, providing high-capacity data exchange and processing capabilities. Therefore, network devices with distributed architectures have greater data access and processing capabilities than those with centralized architectures. Alternatively, a network device can consist of a single card, without a switching fabric board (SFB), integrating the functions of the interface board and the main control board. In this case, the central processing unit (CPU) on the interface board and the CPU on the main control board can be combined into a single CPU on this card, performing the combined functions of the two. This type of network device has lower data exchange and processing capabilities (for example, low-end network devices such as switches or routers). The specific architecture used depends on the specific network deployment scenario and is not specified here.

[0222] In a specific embodiment, the Ethernet device 2100 corresponds to the Ethernet device shown in FIG. 10 or FIG. 11 .

[0223] For example, Ethernet device 2100 may be an Ethernet forwarding device such as a switch or router, as shown in FIG10 or FIG11 . In this case, the Ethernet chip that executes the method shown in FIG3 , FIG8( a ), or FIG8( b ) may be located in main control board 2110 , or in interface board 2130 or interface board 2140 , and the Ethernet chip may be located in physical interface card 2133 or 2143 .

[0224] The present embodiment further provides a communication system 3000, which includes a first Ethernet device 3001 and a second Ethernet device 3002. Optionally, the first Ethernet device may be a transmitting Ethernet device that executes the data sending method shown in FIG3 , and the second Ethernet device may be a receiving Ethernet device that executes the data receiving method shown in FIG8( a ) or FIG8( b ).

[0225] An embodiment of the present application also provides a computer-readable storage medium, in which at least one instruction is stored. The instruction is loaded and executed by a processor to enable a computer to implement any of the above data sending methods or data receiving methods.

[0226] The embodiments of the present application further provide a computer program (product), which, when executed by a computer, can enable a processor or computer to execute the corresponding steps and / or processes in the above method embodiments.

[0227] An embodiment of the present application also provides a chip, including a processor, for calling and executing instructions stored in a memory from the memory, so that a communication device equipped with the chip executes any of the above data sending methods or data receiving methods.

[0228] An embodiment of the present application also provides another chip, including: an input interface, an output interface, a processor and a memory, wherein the input interface, the output interface, the processor and the memory are connected through an internal connection path, and the processor is used to execute the code in the memory. When the code is executed, the processor is used to execute any of the above data sending methods or data receiving methods.

[0229] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions according to the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state drive).

[0230] Those skilled in the art will appreciate that the various method steps and modules described in conjunction with the embodiments disclosed herein can be implemented in software, hardware, firmware, or any combination thereof. In order to clearly illustrate the interchangeability of hardware and software, the steps and components of each embodiment have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0231] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or may be accomplished by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0232] When software is used for implementation, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer program instructions. As an example, the method of the embodiment of the present application can be described in the context of a machine executable instruction, and the machine executable instruction is such as included in the program module executed in the device on the real or virtual processor of the target. Generally speaking, a program module includes a routine, a program, a library, an object, a class, a component, a data structure, etc., which performs a specific task or realizes a specific abstract data structure. In various embodiments, the function of the program module can be merged or split between the described program modules. The machine executable instruction for the program module can be executed in a local or distributed device. In a distributed device, the program module can be located in both a local and a remote storage medium.

[0233] The computer program code for realizing the method for the embodiment of the application can be written in one or more programming languages.These computer program codes can be provided to the processor of general-purpose computer, special-purpose computer or other programmable data processing device, so that program code, when being executed by computer or other programmable data processing device, causes the function / operation specified in flow chart and / or block diagram to be implemented.Program code can be executed completely on computer, partly on computer, as independent software package, partly on computer and partly on remote computer or completely on remote computer or server.

[0234] In the context of the embodiments of the present application, computer program code or related data may be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, and the like.

[0235] Examples of signals may include electrical, optical, radio, acoustic or other forms of propagated signals, such as carrier waves, infrared signals, etc.

[0236] A machine-readable medium may be any tangible medium that contains or stores a program for or in connection with an instruction execution system, apparatus, or device. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of machine-readable storage media include an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0237] Those skilled in the art will clearly understand that, for the sake of convenience and brevity of description, the specific working processes of the above-described systems, devices, and modules can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0238] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or can be electrical, mechanical or other forms of connection.

[0239] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0240] In addition, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The above-mentioned integrated modules may be implemented in the form of hardware or software functional modules.

[0241] If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0242] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items that have substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there any limitation on quantity or execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various examples, a first image may be referred to as a second image, and similarly, a second image may be referred to as a first image. The first image and the second image may both be images, and in some cases, may be separate and different images.

[0243] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0244] In this application, the term "at least one" means one or more, and the term "plurality" means two or more. For example, "plurality of second messages" means two or more second messages. The terms "system" and "network" are often used interchangeably herein.

[0245] It should be understood that the terminology used in the description of the various examples herein is for the purpose of describing particular examples only and is not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0246] It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the listed items. The term "and / or" describes an association between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, or B exists alone. Furthermore, the character " / " in this application generally indicates that the associated objects are in an "or" relationship.

[0247] It will also be understood that the term “comprise” (also known as “includes,” “including,” “comprises,” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0248] It should also be understood that the terms “if” and “if” may be interpreted to mean “when” or “upon” or “in response to determining” or “in response to detecting.” Similarly, the phrases “if it is determined that ” or “if [stated condition or event] is detected” may be interpreted to mean “upon determining ” or “in response to determining ” or “upon detecting [stated condition or event]” or “in response to detecting [stated condition or event],” depending on the context.

[0249] It should be understood that determining B based on A does not mean determining B based solely on A. B can also be determined based on A and / or other information.

[0250] It should also be understood that references throughout this specification to "one embodiment," "an embodiment," or "one possible implementation" mean that specific features, structures, or characteristics associated with that embodiment or implementation are included in at least one embodiment of the present application. Therefore, the appearance of "in one embodiment," "in an embodiment," or "one possible implementation" throughout this specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0251] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application should be included in the scope of protection of the present application.

Claims

1. A method for sending data, characterized in that: The method comprises: The physical medium of the Ethernet device is connected to the PMA sublayer to obtain a data stream, wherein the data stream is a data stream that has been encoded with forward error correction (FEC); The PMA sublayer performs a first data processing process on the data stream to obtain an interleaved data stream, wherein the first data processing process includes interleaving in a first interleaving mode; Among them, the interleaving type of the first interleaving method is symbol interleaving or convolution interleaving.

2. The method according to claim 1, characterized in that The symbol interleaving is performed with a granularity of 10 bits.

3. The method according to claim 1 or 2, characterized in that The first data processing process further includes: bit multiplexing or symbol group pair multiplexing.

4. The method according to any one of claims 1 to 3, characterized in that Before interleaving in the first interleaving manner, the first data processing process further includes: bit demultiplexing or symbol group demultiplexing.

5. The method according to any one of claims 1 to 4, characterized in that Before interleaving in the first interleaving manner, the first data processing process further includes: locking an alignment mark AM and de-skewing.

6. The method according to any one of claims 1 to 5, characterized in that The data stream is a data stream obtained after executing a second data processing process, and the second data processing process includes interleaving through a second interleaving manner.

7. The method according to claim 6, characterized in that The first interleaving mode and the second interleaving mode have different interleaving depths.

8. The method according to claim 6 or 7, characterized in that The interleaving depth of the second interleaving mode is 2×RS.

9. The method according to any one of claims 6 to 8, characterized in that The first data processing process further includes: deinterleaving for the second interleaving mode.

10. The method according to any one of claims 6 to 9, characterized in that: The second data processing process is performed by the physical coding sublayer PCS or the data terminal equipment extension sublayer DTE_XS.

11. The method according to any one of claims 1 to 10, characterized in that The interleaving depth of the first interleaving mode is 4×RS.

12. The method according to any one of claims 1 to 11, characterized in that The Ethernet device includes at least one of the following: a physical layer PHY chip, a forwarding device, or a pluggable module.

13. The method according to any one of claims 1 to 12, characterized in that The channel rate of the interleaved data stream is 200 Gbps.

14. The method according to any one of claims 1 to 13, characterized in that The rate of the interface of the PMA sublayer for receiving the data stream is at least one of the following: 200 Gbps or 400 Gbps.

15. The method according to any one of claims 1 to 14, characterized in that The PMA sublayer obtains the data stream from the connection unit interface AUI or the common electrical interface CEI.

16. The method according to any one of claims 1 to 15, characterized in that The method further comprises: The PMA sublayer sends the interleaved data stream to the physical medium dependent PMD sublayer.

17. A method for receiving data, characterized in that: The method comprises: The physical medium of the Ethernet device is connected to the PMA sublayer to obtain a data stream, wherein the data stream is a data stream that has been encoded with forward error correction (FEC); The PMA sublayer performs a third data processing process on the data stream to obtain an interleaved data stream, wherein the third data processing process includes interleaving the data stream; The interleaving type of the interleaving is symbol interleaving or convolution interleaving.

18. The method according to claim 17, characterized in that The symbol interleaving is performed with a granularity of 10 bits.

19. The method according to claim 17 or 18, characterized in that The interleaved data stream is deinterleaved by the physical coding sublayer PCS or the data terminal equipment extension sublayer DTE_XS.

20. The method according to any one of claims 17 to 19, characterized in that: The interleaving depth is 2×RS.

21. The method according to any one of claims 17 to 20, characterized in that: The third data processing process further includes: bit demultiplexing or symbol group demultiplexing.

22. The method according to any one of claims 17 to 21, characterized in that The third data processing process further includes: locking the alignment mark AM and de-skew.

23. The method according to any one of claims 17 to 22, characterized in that: The third data processing process further includes: bit multiplexing or symbol group multiplexing.

24. The method according to any one of claims 17 to 23, characterized in that The Ethernet device includes at least one of the following: a physical layer PHY chip, a forwarding device, or a pluggable module.

25. A method for receiving data, characterized in that: The physical medium of the Ethernet device is connected to the PMA sublayer to obtain a data stream, wherein the data stream is a data stream that has been encoded with forward error correction (FEC); The PMA sublayer performs a third data processing process on the data stream to obtain a deinterleaved data stream, wherein the third data processing process includes deinterleaving in the first deinterleaving manner; The deinterleaving type of the first deinterleaving mode is symbol deinterleaving or convolutional deinterleaving.

26. The method according to claim 25, characterized in that The symbol deinterleaving is performed with a granularity of 10 bits.

27. The method according to claim 25 or 26, characterized in that The third data processing process includes: bit multiplexing or symbol group multiplexing.

28. The method according to any one of claims 25 to 27, characterized in that The third data processing process includes: bit demultiplexing or symbol group demultiplexing.

29. The method according to any one of claims 25 to 28, characterized in that The third data processing process includes: locking the alignment mark AM and de-skew.

30. The method according to any one of claims 25 to 28, characterized in that After the PMA sublayer performs a third data processing process on the data stream, the method further includes: The PMA sublayer interleaves the deinterleaved data stream in a second interleaving manner to obtain a re-interleaved data stream.

31. The method according to claim 30, characterized in that The re-interleaved data stream is de-interleaved by the physical coding sublayer PCS or the data terminal equipment extension sublayer DTE_XS.

32. The method according to any one of claims 25 to 31, characterized in that The interleaving depth of the first deinterleaving mode is 4×RS.

33. The method according to any one of claims 25 to 32, characterized in that The Ethernet device includes at least one of the following: a physical layer PHY chip, a forwarding device, or a pluggable module.

34. The method according to any one of claims 25 to 33, wherein: The PMA sublayer obtains the data stream, including: The PMA sublayer obtains the data stream after sending the interleaved data from the physical medium dependent PMD sublayer.

35. An Ethernet device, characterized in that: The Ethernet device is configured to execute the method according to any one of claims 1-16, 17-24, or 25-34.

36. A chip, characterized in that: The chip is used to execute the method according to any one of claims 1-16, 17-24 or 25-34.

37. A communication system, characterized in that: The communication system includes a first Ethernet device and a second Ethernet device, The first Ethernet device is used to execute the method according to any one of claims 1 to 16, the second Ethernet device is used to execute the method according to any one of claims 17 to 24, or The first Ethernet device is used to execute the method according to any one of claims 1 to 16, and the second Ethernet device is used to execute the method according to any one of claims 25 to 34.

Images