Cache routing structure and method, and chip
By introducing request selection logic units and data transmission modules into the cache routing structure, the data transmission path is optimized, the problem of insufficient transmission efficiency in the prior art is solved, and more efficient data transmission and resource utilization are achieved.
Patent Information
- Application Number
- PCT/CN2023/077619
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2023-02-22
- Publication Date
- 2025-02-13
AI Technical Summary
In the prior art, the cache routing structure has problems of insufficient transmission efficiency during data transmission, resulting in high resource occupation and low data transmission efficiency.
A cache routing structure is adopted, including a request cache pool, a request cache logical group, a data transmission module and a routing egress, each routing egress is connected to an arbitrator. The request selection logic unit selects a cache area from the cache area according to the preset selection strategy, and transmits the target object and its route egress identification to the data transmission area, and transmits the target object to the corresponding arbitrator through the route egress identification.
It improves the data transmission efficiency between the request cache pool and the data transmission module, improves the usage rate of the data transmission area, solves the problem of route exit blockage, and significantly improves the performance of the entire cache routing structure.
Smart Images
Figure CN2023077619_13022025_PF_FP_ABST
Abstract
Description
A cache routing structure, method and chip Technical Field
[0001] Embodiments of the present disclosure relate to data transmission technology, and more particularly to a cache routing structure, method, and chip. Background Art
[0002] With the continuous advancement of chip technology and the widespread adoption of multi-core technology, on-chip network interconnect structures are becoming increasingly common, and their resource utilization is also gradually increasing. Improving throughput and optimizing resources have become the key challenges and important design criteria for excellent network interconnect structures. Routers and arbiters are essential components of network interconnect solutions. Related technologies propose a cache-routing circuit structure that uses a cache module and a routing filter module to achieve high-bandwidth, multi-port applications while balancing resources and efficiency.
[0003] SUMMARY OF THE INVENTION
[0004] The following is a summary of the subject matter described in detail herein and is not intended to limit the scope of the claims.
[0005] Embodiments of the present disclosure provide a cache routing structure, method, and chip.
[0006] The present disclosure provides a cache routing structure, which may include: a request cache pool, a request cache logic group, a data transmission module, and a routing outlet; each of the routing outlets is connected to an arbitrator; the request cache pool includes A cache areas, the request cache logic group includes B request selection logic units, and the data transmission module includes C data transmission areas; A, B, and C are all positive integers greater than 1; each data transmission area is connected to all the routing outlets; and the B request selection logic units have different priorities.
[0007] The cache area is configured to cache a target object to be transmitted and a routing exit identifier corresponding to the target object; the routing exit identifier is used to indicate a routing exit for outputting the target object;
[0008] The request selection logic unit is configured to select a cache area from the A cache areas according to a preset selection strategy, obtain a target object and a routing exit identifier corresponding to the target object from the selected cache area, and transmit the target object and the routing exit identifier corresponding to the target object to an idle data transmission area; the selection strategy includes: selecting a cache area from the A cache areas respectively according to a priority order;
[0009] The data transmission area is configured to cache the target object to be transmitted, and according to the routing exit identifier corresponding to the target object to be transmitted, transmits the target object to the corresponding arbitrator through the routing exit corresponding to the routing exit identifier.
[0010] In an exemplary embodiment of the present disclosure, the request selection logic unit is further configured to, after selecting a cache area, pass the routing exit identifier corresponding to the target object cached in the selected cache area, and the routing exit identifier corresponding to the target object cached in the cache area selected by the request selection logic unit with a priority higher than its own priority, to the request selection logic unit of the next priority.
[0011] In an exemplary embodiment of the present disclosure, the routing exit identifier may include: a routing exit number and / or an indicator for indicating a selected state of each routing exit.
[0012] In an exemplary embodiment of the present disclosure, the number of routing exits is D, where D is a positive integer greater than 1;
[0013] The indicator may include: D indicator bits, different indicator bits respectively indicating the selected status of different routing exits through a first value or a second value; wherein the first value is used to indicate that the routing exit is selected, and the second value is used to indicate that the routing exit is not selected.
[0014] In an exemplary embodiment of the present disclosure, the target object may include: cached data, a cached pointer, or a cached identity ID, where the pointer is used to indicate a storage address of the data to be transmitted.
[0015] In an exemplary embodiment of the present disclosure, when the target object includes a cached pointer, the cache routing structure may further include: a data cache module and a data output logic module;
[0016] The data cache module may include: a plurality of storage areas, each storage area being configured to cache data;
[0017] The data output logic module is respectively connected to each storage area, each data transmission area and each routing exit, and is configured to receive a pointer transmitted by the data transmission area and a routing exit identifier corresponding to the pointer, determine the address of the storage area corresponding to the received pointer, and obtain cached data from the corresponding storage area according to the address of the storage area, and transmit the cached data to the routing exit corresponding to the received routing exit identifier.
[0018] In an exemplary embodiment of the present disclosure, when the target object includes a cached id, the cache routing structure further includes: a data cache module and a data output logic module;
[0019] The data cache module includes: a plurality of storage areas, each storage area is configured to cache data;
[0020] The data output logic module is respectively connected to each storage area, each data transmission area and each routing exit, and is configured to receive the ID transmitted by the data transmission area and the routing exit identifier corresponding to the ID, compare the received ID with the ID stored by the data output logic module itself, obtain the ID that is identical to the received ID from the ID stored by the data output logic module itself, determine the address of the storage area corresponding to the identical ID, obtain cached data from the corresponding storage area according to the address of the storage area, and transmit the cached data to the routing exit corresponding to the received routing exit identifier.
[0021] In an exemplary embodiment of the present disclosure, the data output logic module includes Y request selection logic units, where Y is a positive integer greater than 1;
[0022] The number of the Y request selection logic units is the same as the number of the C data transmission areas; each of the Y request selection logic units is connected to one of the data transmission areas;
[0023] The Y request selection logic units have no priority.
[0024] In an exemplary embodiment of the present disclosure, Y request selection logic units are configured to receive the target object transmitted by the data transmission area of the connection and the routing exit identifier corresponding to the target object, determine the address of the storage area corresponding to the received target object, and obtain cache data from the corresponding storage area according to the address of the storage area, and transmit the cache data to the routing exit corresponding to the received routing exit identifier.
[0025] The present disclosure also provides a cache routing method. Based on the cache routing structure, the method may include:
[0026] The request caching logic group in the cache routing structure includes B request selection logic units, each selecting a cache area from the A cache areas included in the request cache pool in the cache routing structure according to a preset selection strategy, obtaining a target object and a routing exit identifier corresponding to the target object from the selected cache area, and transmitting the target object and the target object to an idle data transmission area among the C data transmission areas included in the data transmission module in the cache routing structure; A, B, and C are all positive integers greater than 1; the B request selection logic units each have a different priority; the selection strategy includes: selecting a cache area from the A cache areas according to the priority order;
[0027] The selected data transmission area caches the target object to be transmitted, and according to the routing exit identifier corresponding to the target object to be transmitted, transmits the target object to the corresponding arbitrator through the routing exit corresponding to the routing exit identifier.
[0028] In an exemplary embodiment of the present disclosure, the method may further include:
[0029] Each of the request selection logic units selects a cache area from the A cache areas in order of priority;
[0030] After each request selection logic unit selects a cache area, it passes the routing exit identifier corresponding to the target object cached in the selected cache area, and the routing exit identifier corresponding to the target object cached in the cache area selected by the request selection logic unit with a higher priority than its own priority, to the request selection logic unit of the next priority.
[0031] The embodiment of the present disclosure also provides a chip including the cache routing structure.
[0032] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.
[0033] Summary of the Figures
[0034] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.
[0035] FIG1 is a schematic diagram of a first cache routing structure of an embodiment of the present disclosure;
[0036] FIG2 is a schematic diagram of a second cache routing structure according to an embodiment of the present disclosure;
[0037] FIG3 is a schematic diagram of the structure of a data cache module and a data output logic module in a second cache routing structure according to an embodiment of the present disclosure;
[0038] FIG4 is a schematic diagram of a third cache routing structure of an embodiment of the present disclosure;
[0039] FIG5 is a flow chart of a cache routing method according to an embodiment of the present disclosure;
[0040] FIG6 is a block diagram of chip composition according to an embodiment of the present disclosure.
[0041] Details
[0042] The present disclosure describes a plurality of embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.
[0043] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features, and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other limitations except for the limitations set forth in the appended claims and their equivalents. In addition, various modifications and changes may be made within the scope of protection of the appended claims.
[0044] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation on the claims. In addition, the claims to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.
[0045] The present disclosure provides a cache routing structure, as shown in FIG1 , which may include: a request cache pool 1, a request cache logic group 2, a data transmission module 3, and a routing outlet 4; each of the routing outlets 4 is connected to an arbiter 5; the request cache pool 1 includes A cache areas, the request cache logic group 2 includes B request selection logic units, and the data transmission module 3 includes C data transmission areas; A, B, and C are all positive integers greater than 1; each data transmission area is connected to all of the routing outlets 4; and the B request selection logic units have different priorities.
[0046] The cache area is configured to cache a target object to be transmitted and a routing exit identifier corresponding to the target object; the routing exit identifier is used to indicate a routing exit for outputting the target object;
[0047] The request selection logic unit is configured to select a cache area from the A cache areas according to a preset selection strategy, obtain a target object and a routing exit identifier corresponding to the target object from the selected cache area, and transmit the target object and the routing exit identifier corresponding to the target object to an idle data transmission area; the selection strategy includes: selecting a cache area from the A cache areas respectively according to a priority order;
[0048] The data transmission area is configured to cache the target object to be transmitted, and according to the routing exit identifier corresponding to the target object to be transmitted, transmits the target object to the corresponding arbitrator through the routing exit corresponding to the routing exit identifier.
[0049] A known cache routing structure circuit in the related art includes: a cache module and a routing screening module; the cache module is configured to receive routing requests and cache them in its respective cache pools; and the routing screening module is configured to screen routing requests from its respective cache pools and send them to the corresponding arbitrator. Routing requests screened by different routers are sent to different arbitrators so that any arbitrator receives at most one routing request sent by a router within a processing cycle. Because the atomicity of transfer operations must be guaranteed [atomicity is a characteristic of database transactions. In the context of database transactions, atomicity means that all operations in a transaction are either completed or not completed, and do not end at any intermediate stage], the routing screening module can only complete transfer operations from one cache area of the cache module to the corresponding arbitrator within a time unit (e.g., within a circuit clock cycle). With the aforementioned computation request sending mechanism, when multiple computing units send the same access address, only one computing unit's request is received by the arbitrator unit, resulting in reduced data transmission efficiency for the overall structure. In exemplary embodiments of the present disclosure, the cache routing structure circuit in the related art is optimized to address the issue of insufficient transmission efficiency.
[0050] In an exemplary embodiment of the present disclosure, as shown in Figure 1, compared with the cache routing structure circuit in the related art, the cache routing structure of the embodiment of the present disclosure uses a request selection logic group 2, which improves the data transmission efficiency between the request cache pool 1 and the data transmission module 3, thereby improving the utilization rate of the data transmission area 31 in the data transmission module 3 and improving the performance of the entire cache routing structure.
[0051] In the exemplary embodiments of the present disclosure, the cache routing structure of the embodiment of the present disclosure is introduced in detail below.
[0052] In an exemplary embodiment of the present disclosure, the request selection logic group 2 is composed of B request selection logic units, where the number B can be arbitrary and can be defined according to needs. In the embodiment of the present disclosure, B=2 is used as an example to illustrate the embodiment of the present disclosure.
[0053] In an exemplary embodiment of the present disclosure, B request selection logic units have different priorities respectively; each request selection logic unit in the request selection logic group 2 can be called a mux (for example, mux1 and mux2), and each mux has a fixed priority, so that when the total number of muxes is large, all muxes will not conflict when requesting transmission work; the cache area in the request cache pool 1 can be called Top (for example, Top1, Top2, ..., TopA), and the data transmission area in the data transmission module 3 can be called bot (for example, bot1, bot2, ..., botC), and the target object of the request and the routing exit identifier corresponding to the target object will be cached in the cache area Top.
[0054] In an exemplary embodiment of the present disclosure, each of the request selection logic units mux is further configured to select a cache area from the A cache areas in order of priority.
[0055] In exemplary embodiments of the present disclosure, the priority order may include, but is not limited to, a descending priority order. That is, a high-priority request selection logic unit mux first selects a cache area Top from the A cache areas Top, then a next-highest-priority request selection logic unit mux first selects a cache area Top from the remaining A-1 cache areas Top, and so on, until all request selection logic units mux select a cache area Top.
[0056] In an exemplary embodiment of the present disclosure, the selection strategy of each request selection logic unit mux when selecting a cache area Top may include but is not limited to: selecting from the first to the last or from the first to the last according to the arrangement order of the multiple cache area Tops, or selecting any cache area Top from the multiple cache area Tops according to a random selection strategy (the subsequent request selection logic unit mux with a lower priority may select any cache area Top from the multiple cache area Tops after excluding the selected cache area Top when selecting a cache area Top).
[0057] In an exemplary embodiment of the present disclosure, in order to effectively eliminate the selected cache area Top, the routing exit identifier corresponding to the target object cached in the selected cache area Top can be passed to the request selection logic unit mux with a lower priority. The detailed scheme is described as follows.
[0058] In an exemplary embodiment of the present disclosure, each of the request selection logic units mux is further configured to, after selecting a cache area Top, pass the cache area identifier of the selected cache area Top and the cache area identifier of the cache area Top selected by the request selection logic unit mux with a priority higher than its own priority to the request selection logic unit mux of the next priority.
[0059] In an exemplary embodiment of the present disclosure, the B request selection logic units mux may be further divided into groups, each group including a plurality of request selection logic units, and the number of request selection logic units in different groups may be the same or different.
[0060] In an exemplary embodiment of the present disclosure, multiple groups of request selection logic units mux have different priorities; each group of mux has a fixed priority, and each mux in each group also has a fixed priority, so that when the total number of muxes is large, all muxes will not conflict when requesting transmission work.
[0061] In an exemplary embodiment of the present disclosure, each group of the request selection logic unit mux is further configured to select one first cache area from the A first cache areas in a priority order. The priority order may include but is not limited to a descending priority order.
[0062] In an exemplary embodiment of the present disclosure, there are D routing exits 4 (D is a positive integer greater than 1), and there are A cache area Tops. The values of A and D may be the same or different. When the value of A is greater than the value of D, the routing exit identifiers corresponding to the target objects cached in multiple cache area Tops will be the same routing exit identifier, that is, multiple target objects need to be transmitted out from the same routing exit. If the cache area Tops where the multiple target objects are located are selected at the same time, it is possible that the multiple target objects need to be transmitted out through the same routing exit at the same time, which will inevitably cause congestion in the routing exit and seriously affect the transmission efficiency.
[0063] In an exemplary embodiment of the present disclosure, the following solution is proposed for the above problem: each of the request selection logic units mux is also configured to, after selecting a cache area Top, pass the routing exit identifier corresponding to the target object cached by the selected cache area Top, and the routing exit identifier corresponding to the target object cached by the cache area selected by the request selection logic unit mux with a priority higher than its own priority, to the request selection logic unit mux of the next priority.
[0064] In an exemplary embodiment of the present disclosure, through the above-mentioned scheme, when selecting a cache area Top from the remaining multiple cache area Tops of each request selection logic unit mux, the cache area Tops in the remaining multiple cache area Tops that store the routing exit identifier stored in the cache area Top that has been selected within a preset time length are eliminated, that is, the remaining multiple cache area Tops are screened again, and then a cache area Top is selected from the multiple cache area Tops remaining after the re-screening, so that within a shorter period of time, the selected cache area Tops do not store the same routing exit identifier, so that the target object stored in the selected cache area Top will not be output through the same routing exit. This embodiment scheme ensures that the routing exit will not be blocked during the transmission of the target object.
[0065] In an exemplary embodiment of the present disclosure, for example, the priority of mux1 is greater than the priority of mux2. If mux1 currently selects Top1, mux1 passes the routing exit identifier corresponding to the target object cached in Top1 to mux2. Then, when mux2 selects the cache area Top in the request cache pool 1, it will skip all cache area Tops that store the same routing exit identifier as the routing exit identifier stored in Top1; similarly, when the request selection logic group 2 also includes mux3, mux4..., and so on, mux3 will avoid the routing exit identifiers stored in the cache area Top selected by mux2 and mux1 when selecting the cache area Top.
[0066] In an exemplary embodiment of the present disclosure, the routing exit identifier may include, but is not limited to: a routing exit number and / or an indicator for indicating a selected state of each routing exit.
[0067] In an exemplary embodiment of the present disclosure, the numbering of routing outlets may include, but is not limited to, numbering using letters and numbers, for example: Portout1, Portout2, ..., PortoutD.
[0068] In an exemplary embodiment of the present disclosure, the indicator may include: D indicator bits, different indicator bits indicating the selected status of different routing exits through a first numerical value or a second numerical value respectively; wherein the first numerical value is used to indicate that the routing exit is selected, and the second numerical value is used to indicate that the routing exit is not selected.
[0069] In an exemplary embodiment of the present disclosure, for example, when there are 16 routing exits, D=16, then the indicator may include 16 indication bits, for example, it may be represented by abcd efgh igkl mnop, where a, b, c, d, e, f, g, h, i, g, k, l, m, n, o, and p respectively represent an indication bit, and each indication bit represents a routing exit (for example, a may represent the first routing exit, b may represent the second routing exit, ..., and P may represent the sixteenth routing exit, or, conversely, a may represent the sixteenth routing exit, b may represent the fifteenth routing exit, ..., and P may represent the first routing exit. In the embodiment of the present disclosure, a represents the first routing exit, b represents the second routing exit, ..., and P represents the sixteenth routing exit as an example for explanation). Each indication bit may represent a selected state of the indication bit by 0 and 1, 1 may represent that the indication is not selected, and 0 may represent that the indication bit is not selected. For example, 0000 0000 0000 0001 means that the 16th routing exit is selected and the other routing exits are not selected; 1000 1000 0000 0000 means that the 1st and 5th routing exits are selected and the other routing exits are not selected.
[0070] In an exemplary embodiment of the present disclosure, the route exit identifier cached in the cache area Top may be converted into the above-mentioned indicator format before being stored.
[0071] In an exemplary embodiment of the present disclosure, when the routing exit identifier stored in Top1 selected by mux1 is used to indicate the 11th routing exit, the mask passed by mux1 to mux2 is 0000 0000 0010 0000; when the routing exit identifier stored in Top2 selected by mux2 is used to indicate the 1st routing exit, the mask passed by mux2 to mux3 is 1000 0000 0010 0000.
[0072] In the exemplary embodiments of the present disclosure, the above-mentioned embodiments can exponentially increase the rate at which the target object and the routing exit identifier are transferred from the request cache pool 1 to the data transmission module 3 .
[0073] In an exemplary embodiment of the present disclosure, the target object may include: cached data, a cached pointer PIN and / or a cached identity ID, where the pointer PIN is used to indicate a storage address of the data to be transmitted.
[0074] In an exemplary embodiment of the present disclosure, when the target object is cached data, the above embodiment scheme can be directly executed based on the structure of FIG. 1 to realize direct transmission of data.
[0075] In the exemplary embodiment of the present disclosure, because the content stored in cache area Top includes two parts: the target object and the routing exit identifier corresponding to the target object, the routing exit identifier will be used during the routing process. The target object itself remains unchanged during the routing process except for being transmitted and has no other purpose. It is simply transferred from cache area Top in request cache pool 1 to data transmission area bot in data transmission module 3. Therefore, if the target object is data, since some data is large and inevitably occupies a certain amount of space during the transmission process, it is possible to consider caching the data to be transmitted separately. In the cache routing structure of the embodiment of the present disclosure, only the pointer corresponding to the data is transmitted. This pointer is used to indicate the cache address of the data. Since the space occupied by the pointer is much smaller than the data itself, it can reduce the space occupied during the data transmission process and save resources.
[0076] In an exemplary embodiment of the present disclosure, as shown in FIG2 , when the target object includes a cached pointer pin, the cache routing structure may further include: a data cache module 11 and a data output logic module 12;
[0077] The data cache module 11 may include: a plurality of storage areas buf (for example, buf_1, buf_2, ..., buf_X, X is a positive integer), each storage area buf is set to cache data;
[0078] The data output logic module 12 is respectively connected to each storage area buf, each data transmission area bot and each routing exit 4, and is configured to receive the pointer pin transmitted by the data transmission area bot and the routing exit identifier corresponding to the pointer pin, determine the address of the storage area corresponding to the received pointer pin, and obtain cached data from the corresponding storage area according to the address of the storage area, and transmit the cached data to the routing exit 4 corresponding to the received routing exit identifier.
[0079] In an exemplary embodiment of the present disclosure, as shown in FIG3 , when the target object includes a cached id, the cache routing structure may further include: a data cache module 11 and a data output logic module 12;
[0080] The data cache module 11 may include: a plurality of storage areas buf (for example, buf_1, buf_2, ..., buf_X, where X is a positive integer), each storage area buf being configured to cache data;
[0081] The data output logic module 12 is respectively connected to each storage area buf, each data transmission area bot and each routing exit 4, and is configured to receive the ID transmitted by the data transmission area bot and the routing exit identifier corresponding to the ID, compare the received ID with the ID stored in the data output logic module 12 itself, obtain the ID that is identical to the received ID from the ID stored in the data output logic module 12 itself, and determine the address of the storage area corresponding to the identical ID, and obtain cached data from the corresponding storage area according to the address of the storage area, and transmit the cached data to the routing exit 4 corresponding to the received routing exit identifier.
[0082] In an exemplary embodiment of the present disclosure, the data output logic module 12 includes Y request selection logic units, where Y is a positive integer greater than 1;
[0083] The number of the Y request selection logic units is the same as the number of the C data transmission areas; each of the Y request selection logic units is connected to one of the data transmission areas;
[0084] The Y request selection logic units have no priority.
[0085] In an exemplary embodiment of the present disclosure, the Y request selection logic units are configured to receive the target object (pin and / or id) transmitted by the data transmission area of the connection and the routing exit identifier corresponding to the target object, determine the address of the storage area corresponding to the received target object, and obtain cached data from the corresponding storage area based on the address of the storage area, and transmit the cached data to the routing exit corresponding to the received routing exit identifier. In an exemplary embodiment of the present disclosure, as shown in Figure 3, the structure of the data output logic module 12 does not have a priority judgment. Therefore, the number of muxes (for example, mux1, mux2, ..., muxY, where Y is a positive integer) in the data output logic module 12 is the same as the number of bots (i.e., C=Y). The pointer pin of the target data transmitted by bot corresponds to the buf information in the data cache module 11, and the port_out signal completes the logical link of the mux, thereby avoiding the need for all bufs in the data cache module 11 to be directly connected to port_out, resulting in the number of buses being X*D*bitwidth. The current number of buses is (X*C+C*D)*bitwidth, but if C is small enough, (X*C+C*D) is less than X*D, reducing the scale of the logic.
[0086] In the exemplary embodiment of the present disclosure, as shown in Figure 4 , each piece of data carries a unique ID (identification number). This ID information includes the port_out information to which the data is destined, as well as the addressing information for the subsequent routing structure and the data's own serial number, resulting in each data ID being virtually unique. This ID can be stored in the Top and Bot modules. The right side of Figure 4 determines the order in which requests are transmitted. After the ID is passed to the data output logic module 12, the module performs pairing based on the ID, and only data with the same ID is transmitted.
[0087] In an exemplary embodiment of the present disclosure, the buf in the data cache module 11 stores data and its corresponding ID, and the right part in FIG4 stores another copy of the same ID.
[0088] In an exemplary embodiment of the present disclosure, each routing outlet 4 may be connected to an arbiter 5 (e.g., arbiters 51, 52, ..., 5D). When any pointer is read by the arbiter 5, the cache address of the corresponding data can be determined based on the pointer, so that the required data can be read from the cache address.
[0089] In the exemplary embodiments of the present disclosure, the above embodiment replaces the data originally cached in the cache area Top with a pointer with a smaller bit width, thereby reducing resource usage and the number of data transfer operations in the cache routing structure.
[0090] In exemplary embodiments of the present disclosure, there are at least the following advantages:
[0091] 1. The transient efficiency drop caused by insufficient request transmission efficiency between the two layers of cache in the double-layer cache routing structure circuit in the related art is reduced, thereby improving the transmission efficiency.
[0092] 2. Solve the problem of using additional cache resources due to the large bit width of data during direct data transmission.
[0093] The present disclosure also provides a cache routing method. Based on the cache routing structure, as shown in FIG5 , the method may include steps S101-S102:
[0094] S101. B request selection logic units included in a request cache logic group in the cache routing structure each select a cache area from A cache areas included in a request cache pool in the cache routing structure according to a preset selection strategy, obtain a target object and a routing exit identifier corresponding to the target object from the selected cache area, and transmit the target object and the target object to an idle data transmission area among C data transmission areas included in a data transmission module in the cache routing structure; A, B, and C are all positive integers greater than 1; the B request selection logic units each have a different priority; the selection strategy includes: selecting a cache area from the A cache areas in order of priority;
[0095] S102: The selected data transmission area caches the target object to be transmitted, and according to the routing exit identifier corresponding to the target object to be transmitted, transmits the target object to the corresponding arbitrator through the routing exit corresponding to the routing exit identifier.
[0096] In an exemplary embodiment of the present disclosure, the method may further include:
[0097] Each of the request selection logic units selects a cache area from the A cache areas in order of priority;
[0098] After each request selection logic unit selects a cache area, it passes the routing exit identifier corresponding to the target object cached in the selected cache area, and the routing exit identifier corresponding to the target object cached in the cache area selected by the request selection logic unit with a higher priority than its own priority, to the request selection logic unit of the next priority.
[0099] In the exemplary embodiments of the present disclosure, any of the aforementioned cache routing structure embodiments are applicable to the aforementioned method embodiments, and will not be described in detail herein.
[0100] The embodiment of the present disclosure further provides a chip 100 , as shown in FIG6 , including the cache routing structure 200 .
[0101] In the exemplary embodiments of the present disclosure, any of the aforementioned cache routing structure embodiments are applicable to this chip embodiment and will not be described in detail here.
[0102] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.
Claims
1. A cache routing structure, comprising: A request buffer pool, a request buffer logic group, a data transmission module and a routing exit; each of the routing exits is connected to an arbitrator; the request buffer pool includes A buffer areas, the request buffer logic group includes B request selection logic units, and the data transmission module includes C data transmission areas; A, B, and C are all positive integers greater than 1; each of the data transmission areas is connected to all the routing exits; the B request selection logic units have different priorities; The cache area is configured to cache a target object to be transmitted and a routing exit identifier corresponding to the target object; The routing exit identifier is used to indicate the routing exit for outputting the target object; The request selection logic unit is configured to select a cache area from the A cache areas according to a preset selection strategy, and obtain a target object and a routing exit identifier corresponding to the target object from the selected cache area, and transmit them to an idle data transmission area; the selection strategy includes: selecting a cache area from the A cache areas respectively according to a priority order; The data transmission area is configured to cache the target object to be transmitted, and according to the routing exit identifier corresponding to the target object to be transmitted, transmits the target object to be transmitted to the corresponding arbitrator through the routing exit corresponding to the routing exit identifier.
2. The cache routing structure according to claim 1, wherein: The request selection logic unit is also configured to, after selecting a cache area, pass the routing exit identifier corresponding to the target object cached in the selected cache area, and the routing exit identifier corresponding to the target object cached in the cache area selected by the request selection logic unit with a priority higher than its own priority, to the request selection logic unit of the next priority.
3. The cache routing structure according to claim 1, wherein: The routing exit identifier includes: the number of the routing exit and / or an indicator for indicating the selected state of each routing exit.
4. The cache routing structure according to claim 3, wherein: The number of routing exits is D; D is a positive integer greater than 1; The indicator includes: D indication bits, and different indication bits indicate the selected status of different routing exits through first values or second values respectively; wherein the first value is used to indicate that the routing exit is selected, and the second value is used to indicate that the routing exit is not selected.
5. The cache routing structure according to any one of claims 1 to 4, wherein: The target object includes: cached data, a cached pointer or a cached identity ID, and the pointer is used to indicate the storage address of the data to be transmitted.
6. The cache routing structure according to claim 5, wherein: When the target object includes a cached pointer, the cache routing structure further includes: a data cache module and a data output logic module; The data cache module includes: a plurality of storage areas, each storage area is configured to cache data; The data output logic module is respectively connected to each storage area, each data transmission area and each routing exit, and is configured to receive a pointer transmitted by the data transmission area and a routing exit identifier corresponding to the pointer, determine the address of the storage area corresponding to the received pointer, and obtain cache data from the corresponding storage area according to the address of the storage area, and transmit the cache data to the routing exit corresponding to the received routing exit identifier.
7. The cache routing structure according to claim 5, wherein: When the target object includes a cached id, the cache routing structure further includes: a data cache module and a data output logic module; The data cache module includes: a plurality of storage areas, each storage area is configured to cache data; The data output logic module is respectively connected to each storage area, each data transmission area and each routing exit, and is configured to receive an ID transmitted by the data transmission area and a routing exit identifier corresponding to the ID, compare the received ID with the ID stored in the data output logic module itself, obtain an ID identical to the received ID from the ID stored in the data output logic module itself, determine the address of the storage area corresponding to the identical ID, obtain cached data from the corresponding storage area according to the address of the storage area, and transmit the cached data to the routing exit corresponding to the received routing exit identifier.
8. The cache routing structure according to claim 6 or 7, wherein: The data output logic module includes Y request selection logic units, where Y is a positive integer greater than 1; The number of the Y request selection logic units is the same as the number of the C data transmission areas; each of the Y request selection logic units is connected to one of the data transmission areas respectively; The Y request selection logic units have no priority.
9. A cache routing method, characterized in that: Based on the cache routing structure according to any one of claims 1 to 8, the method comprises: The B request selection logic units included in the request cache logic group in the cache routing structure respectively select a cache area from the A cache areas included in the request cache pool in the cache routing structure according to a preset selection strategy, and obtain the target object and the routing exit identifier corresponding to the target object from the selected cache area, and transmit them to the idle data transmission area in the C data transmission areas included in the data transmission module in the cache routing structure; A, B, and C are all positive integers greater than 1; the B request selection logic units have different priorities respectively; the selection strategy includes: selecting a cache area from the A cache areas respectively according to the priority order; The selected data transmission area caches the target object to be transmitted, and according to the routing exit identifier corresponding to the target object to be transmitted, transmits the target object to be transmitted to the corresponding arbitrator through the routing exit corresponding to the routing exit identifier.
10. The cache routing method according to claim 9, further comprising: Each of the request selection logic units selects a cache area from the A cache areas in order of priority; After each request selection logic unit selects a cache area, it passes the routing exit identifier corresponding to the target object cached in the selected cache area and the routing exit identifier corresponding to the target object cached in the cache area selected by the request selection logic unit with a higher priority than its own priority to the request selection logic unit of the next priority.
11. A chip, characterized in that: It comprises a cache routing structure as described in any one of claims 1-8.