Memory and manufacturing method therefor, and electronic device

Abstract

The present disclosure relates to the technical field of semiconductors, and particularly relates to a memory and a manufacturing method therefor, and an electronic device, which are used for reducing the parasitic capacitance of a memory. The memory comprises a substrate (1), a word line (WL) and a transistor (2). The word line (WL) extends in a direction perpendicular to the substrate (1). The transistor (2) comprises a semiconductor layer (21) at least partially surrounding the word line (WL) and a gate insulating layer (22) disposed between the word line (WL) and the semiconductor layer (21). The semiconductor layer (21) comprises a channel region (Q3) located on at least one side of the word line (WL) in a first direction, and two contact regions located on two sides of the word line (WL) in a second direction. The first direction and the second direction are both parallel to the substrate (1), and the first direction and the second direction intersect. The shortest distance from the channel region (Q3) to the word line (WL) is less than the shortest distance from at least one contact region to the word line (WL). The two contact regions comprise a first source / drain contact region (Q1) and a second source / drain contact region (Q2).

Description

Memory and manufacturing method thereof, and electronic device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to a Chinese patent application filed with the Patent Office of China on April 13, 2023, with application number 2023103906036 and invention name “Memory and its manufacturing method, electronic device”. The entire contents of the patent application are incorporated into this disclosure by reference. Technical Field

[0003] The present disclosure relates to the field of semiconductor technology, and in particular to a memory device, a manufacturing method thereof, and an electronic device. Background Art

[0004] With the development of communication and digital technologies, people continue to pursue products with lower power consumption, lighter weight, and better performance. Three-dimensional dynamic random access memory (3D DRAM), which can achieve higher integration density and larger storage capacity, has gradually become one of the important research directions of memory.

[0005] Summary of the Invention

[0006] According to some embodiments, the present disclosure provides a memory device comprising: a substrate, a word line, and a transistor. The word line extends in a direction perpendicular to the substrate. The transistor comprises a semiconductor layer at least partially surrounding the word line and a gate insulating layer disposed between the word line and the semiconductor layer. The semiconductor layer comprises: a channel region located on at least one side of the word line in a first direction, and two contact regions located on both sides of the word line in a second direction, wherein the first direction and the second direction are both parallel to the substrate and the first direction and the second direction intersect. The shortest distance from the channel region to the word line is less than the shortest distance from at least one contact region to the word line; the two contact regions comprise: a first source / drain contact region and a second source / drain contact region.

[0007] According to some embodiments, a dimension of the word line in the first direction is smaller than a dimension of the word line in the second direction.

[0008] According to some embodiments, a cross-sectional shape of the word line along a direction parallel to the substrate includes a circle and / or an ellipse.

[0009] According to some embodiments, the semiconductor layer includes two channel regions located on both sides of the word line in the first direction; and a size of the contact region in the first direction is smaller than the shortest distance between the two channel regions.

[0010] According to some embodiments, a difference between the shortest distance from the channel region to the word line and the shortest distance from any contact region to the word line ranges from 1 nm to 30 nm.

[0011] According to some embodiments, a thickness of the gate insulating layer near the contact region is greater than a thickness near the channel region.

[0012] According to some embodiments, the thickness of the semiconductor layer in the channel region and the thickness in the contact region are the same.

[0013] According to some embodiments, the transistor further includes a first source / drain and a second source / drain. The first source / drain is connected to the first source / drain contact region and includes a first source / drain body and at least one first branch connected to the first source / drain body, the first branch extending from the first source / drain body toward the channel region. The second source / drain is connected to the second source / drain contact region and includes a second source / drain body and at least one second branch connected to the second source / drain body, the second branch extending from the second source / drain body toward the channel region.

[0014] According to some embodiments, the word line includes a sidewall extending along the second direction and a sidewall extending along the first direction. The first source / drain contact region covers the sidewall extending in the first direction, and the first branch of the first source / drain electrode partially covers the sidewall extending in the second direction. The second source / drain contact region covers the sidewall extending in the first direction, and the second branch of the second source / drain electrode partially covers the sidewall extending in the second direction.

[0015] According to some embodiments, the channel region is located between the first source / drain contact region and the second source / drain contact region in the second direction.

[0016] According to some embodiments, the memory further includes a bit line connected to the first source / drain body. The bit line, the first source / drain body, the first branch, the second source / drain body, and the second branch are formed from a single conductive film layer after patterning. The bit line, the first source / drain body, and the first branch are an integrated structure. The second source / drain body and the second branch are also an integrated structure.

[0017] According to some embodiments, the first source / drain includes two first branches, and the second source / drain includes two second branches; there is a channel region between two adjacent first branches and second branches, and the two first branches have the same length in the second direction, and the two second branches have the same length in the second direction.

[0018] According to some embodiments, the channel region extends along the second direction. The first branch contacts the channel region; the side surface of the first branch in the first direction and the side surface of the channel region in contact with the first branch in the first direction have the same position in the first direction; the second branch contacts the channel region; the side surface of the second branch in the first direction and the side surface of the channel region in contact with the second branch in the first direction have the same position in the first direction.

[0019] According to some embodiments, the present disclosure further provides a method for manufacturing a memory, comprising the following steps:

[0020] forming a conductive film layer on a substrate;

[0021] The patterned conductive film layer forms a word line hole; the word line hole extends in a direction perpendicular to the substrate, a size of the word line hole in a first direction is smaller than a size of the word line hole in a second direction, and the first direction and the second direction are both parallel to the substrate and intersect;

[0022] forming a semiconductor layer conformally covering the inner wall of the word line hole;

[0023] forming a gate insulating layer conformally covering the inner surface of the semiconductor layer;

[0024] A word line is formed that conformally covers the inner surface of the gate insulation layer and fills the word line hole. The semiconductor layer includes a channel region located on at least one side of the word line in a first direction, and two contact regions located on both sides of the word line in a second direction. The shortest distance from the channel region to the word line is less than the shortest distance from at least one of the contact regions to the word line.

[0025] According to some embodiments, the present disclosure further provides a method for manufacturing a memory, comprising the following steps:

[0026] forming a stacked structure having conductive film layers and sacrificial layers alternately stacked in a direction perpendicular to the substrate;

[0027] A patterned stack structure is formed to form a bit line extending along a first direction and branches extending along a second direction on both sides of the bit line;

[0028] Performing a patterning process on the branch to form a word line hole on the branch, wherein the word line hole penetrates the surface of the branch close to and away from the substrate; the word line hole contacts an etch stop layer provided in the same layer as the branch, thereby separating the branch into a first portion and a second portion;

[0029] forming a semiconductor layer conformally covering the inner wall of the word line hole;

[0030] forming a gate insulating layer conformally covering the inner surface of the semiconductor layer;

[0031] A gate or word line is formed that conformally covers the inner surface of the gate insulating layer and fills the word line hole. The semiconductor layer includes a channel region located on at least one side of the word line in a first direction, and two contact regions located on both sides of the word line in a second direction. The first and second directions are both parallel to the substrate and intersect with each other. The shortest distance from the channel region to the word line is less than the shortest distance from at least one contact region to the word line.

[0032] According to some embodiments, the contact regions located on both sides of the word line in the second direction include: a first source / drain contact region and a second source / drain contact region. Forming the word line hole also includes: synchronously forming a first source / drain, a second source / drain, and a bit line. The first source / drain covers the outer surface of the first source / drain contact region, includes a first source / drain body and at least one first branch connected to the first source / drain body, and the first branch extends from the first source / drain body to the channel region; the second source / drain covers the outer surface of the second source / drain contact region, includes a second source / drain body and at least one second branch connected to the second source / drain body, and the second branch extends from the second source / drain body to the channel region; the bit line extends along the first direction and contacts the first source / drain body.

[0033] According to some embodiments, the present disclosure further provides an electronic device on another aspect, comprising the memory as described in any one of the aforementioned embodiments.

[0034] The details of the embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects and advantages of the present disclosure will become apparent from the description, drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, without paying any creative work, they can also obtain drawings of other embodiments based on these drawings.

[0036] FIG1 is a schematic diagram of the structure of a memory provided in some embodiments; FIG1a is a schematic cross-sectional view of the memory shown in FIG1 at section C1; FIG1b is a schematic cross-sectional view of the memory shown in FIG1 at section C2; FIG1c is a schematic cross-sectional view of the memory shown in FIG1 at section C3;

[0037] FIG2 is a schematic diagram of the structure of a memory provided in some embodiments; FIG2a is a schematic cross-sectional view of the memory shown in FIG2 at section C1; FIG2b is a schematic cross-sectional view of the memory shown in FIG2 at section C2; FIG2c is a schematic cross-sectional view of the memory shown in FIG2 at section C3;

[0038] FIG3 is a schematic diagram of the structure of a memory provided in some embodiments; FIG3a is a schematic cross-sectional view of the memory shown in FIG3 at section C1; FIG3b is a schematic cross-sectional view of the memory shown in FIG3 at section C2; FIG3c is a schematic cross-sectional view of the memory shown in FIG3 at section C3;

[0039] FIG4 is a schematic flow chart of a method for manufacturing a memory provided in some embodiments;

[0040] FIG5 is a schematic flow chart of a method for manufacturing a memory provided in some embodiments;

[0041] FIG6 is a schematic diagram of a structure obtained after forming a first mask layer in some embodiments; FIG6a is a schematic cross-sectional view of the structure shown in FIG6 at section C1; FIG6b is a schematic cross-sectional view of the structure shown in FIG6 at section C2; and FIG6c is a schematic cross-sectional view of the structure shown in FIG6 at section C3;

[0042] FIG7 is a schematic diagram of a structure obtained after forming an etch stop layer in some embodiments; FIG7a is a schematic cross-sectional view of the structure shown in FIG7 at section C1; FIG7b is a schematic cross-sectional view of the structure shown in FIG7 at section C2; FIG7c is a schematic cross-sectional view of the structure shown in FIG7 at section C3;

[0043] FIG8 is a schematic diagram of a structure obtained after exposing the first electrode in some embodiments; FIG8a is a schematic cross-sectional view of the structure shown in FIG8 at section C1; FIG8b is a schematic cross-sectional view of the structure shown in FIG8 at section C2; FIG8c is a schematic cross-sectional view of the structure shown in FIG8 at section C3;

[0044] FIG9 is a schematic diagram of a structure obtained after forming a second electrode in some embodiments; FIG9a is a schematic cross-sectional view of the structure shown in FIG9 at section C1; FIG9b is a schematic cross-sectional view of the structure shown in FIG9 at section C2; and FIG9c is a schematic cross-sectional view of the structure shown in FIG9 at section C3;

[0045] FIG10 is a schematic diagram of a structure obtained after forming word line holes in some embodiments; FIG10a is a schematic cross-sectional view of the structure shown in FIG10 at section C1; FIG10b is a schematic cross-sectional view of the structure shown in FIG10 at section C2; and FIG10c is a schematic cross-sectional view of the structure shown in FIG10 at section C3;

[0046] FIG11 is a schematic diagram of a structure obtained after word lines are formed in some embodiments; FIG11a is a schematic cross-sectional view of the structure shown in FIG11 at section C1; FIG11b is a schematic cross-sectional view of the structure shown in FIG11 at section C2; and FIG11c is a schematic cross-sectional view of the structure shown in FIG11 at section C3;

[0047] FIG12 is a schematic diagram of a structure obtained after forming a through hole in some embodiments; FIG12a is a schematic cross-sectional view of the structure shown in FIG12 at section C1; FIG12b is a schematic cross-sectional view of the structure shown in FIG12 at section C2; FIG12c is a schematic cross-sectional view of the structure shown in FIG12 at section C3;

[0048] FIG13 is a schematic diagram of the structure obtained after removing the sacrificial pattern layer in some embodiments; FIG13a is a schematic cross-sectional view of the structure shown in FIG13 at section C1; FIG13b is a schematic cross-sectional view of the structure shown in FIG13 at section C2; FIG13c is a schematic cross-sectional view of the structure shown in FIG13 at section C3;

[0049] Figure 14 is a structural schematic diagram of the structure obtained after forming an insulating layer in some embodiments; Figure 14a is a cross-sectional schematic diagram of the structure shown in Figure 14 on the C1 section; Figure 14b is a cross-sectional schematic diagram of the structure shown in Figure 14 on the C2 section; Figure 14c is a cross-sectional schematic diagram of the structure shown in Figure 14 on the C3 section. DETAILED DESCRIPTION

[0050] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0052] It should be understood that when an element or layer is referred to as being “on,” “adjacent,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0053] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0054] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0055] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure, and variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Accordingly, embodiments of the present disclosure should not be limited to the specific shapes of regions illustrated herein, but rather include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of regions of a device and do not limit the scope of the present disclosure.

[0056] Some embodiments of the present disclosure provide a memory. Referring to FIG. 1 and FIG. 1a, FIG. 1b, and FIG. 1c, the memory includes a substrate 1, a word line WL, and a transistor 2. The word line WL extends in a direction perpendicular to the substrate 1 (e.g., the Z direction). The transistor 2 includes a semiconductor layer 21 that at least partially surrounds the word line WL and a gate insulating layer 22 disposed between the word line WL and the semiconductor layer 21. The semiconductor layer 21 includes a channel region Q3 located on at least one side of the word line WL in a first direction (e.g., the Y direction), and two contact regions (e.g., Q1 and Q2) located on either side of the word line WL in a second direction (e.g., the X direction). The first direction (e.g., the Y direction) and the second direction (e.g., the X direction) are both parallel to the substrate 1 and intersect with each other. The shortest distance D1 from the channel region Q3 to the word line WL is less than the shortest distance D2 from at least one contact region (e.g., Q1 and Q2) to the word line WL. The two contact regions include a first source / drain contact region Q1 and a second source / drain contact region Q2.

[0057] In some embodiments, the channel region Q3 may be located only on one side of the word line WL in the first direction (eg, the Y direction), or may be located on both sides of the word line WL in the first direction (eg, the Y direction).

[0058] In some embodiments, the shortest distance from the channel region Q3 to the word line WL can be less than the shortest distance from one contact region (e.g., Q1 or Q2) to the word line WL, or less than two. If the shortest distance is less than the shortest distance from the first source / drain contact region Q1 (on the bit line side) to the word line WL, the isolation between the word line WL and the bit line BL can be improved. If the shortest distance is less than the shortest distance from the second source / drain contact region Q2 (on the capacitor side) to the word line WL, the isolation between the word line WL and the capacitor 3 can be improved.

[0059] In an embodiment of the present application, the semiconductor layer 21 surrounding the word line WL includes two channel regions Q3 and two contact regions (e.g., Q1 and Q2). The channel region Q3 is located on both sides of the word line WL relative to each other in a first direction (e.g., the Y direction), and the contact regions (e.g., Q1 and Q2) are located on both sides of the word line relative to each other in a second direction (e.g., the X direction). By utilizing the fact that the distance D1 from the channel region Q3 to the word line WL is smaller than the distance D2 from the contact regions (e.g., Q1 and Q2) to the word line WL, the gate insulating layer 22 can be made thinner near the channel region Q3 and thicker near the contact regions (e.g., Q1 and Q2), thereby effectively increasing the distance between the word line WL and the bit line BL, and between the word line WL and the capacitor 3, thereby reducing parasitic capacitance. This can further improve memory performance.

[0060] In some embodiments, the memory includes one or more memory layers stacked in a direction perpendicular to substrate 1 (e.g., in the Z direction). Each memory layer comprises multiple memory cells distributed in a two-dimensional direction, each memory cell having at least one transistor 2. In some embodiments, multiple memory layers are stacked and distributed, and accordingly, multiple transistors 2 may be distributed in different memory layers stacked in a direction perpendicular to substrate 1.

[0061] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate.

[0062] For example, each transistor 2 in each storage layer can be respectively used as a transistor 2 of a corresponding storage unit, which can be, for example, a 1T or 2T architecture, and can have a capacitor for storing read and write signals, or no capacitor for storing read and write signals. Whether there are capacitors with other functions is not discussed in this application. For example, some application scenarios include storage unit architectures such as 1T1C, 1T0C or 2T0C. Taking the 1T1C architecture as an example, the storage unit may include a capacitor 3 and a transistor 2 connected to the capacitor 3. For example, in a three-dimensional dynamic random access memory, a plurality of storage cells can be arrayed in a plane parallel to the substrate 1 (e.g., an XY plane), and periodically stacked in a direction perpendicular to the substrate 1 (e.g., in the Z direction) to form a multi-layer storage layer.

[0063] In some embodiments, please refer to Figure 1a for understanding. Figure 1a illustrates an embodiment in which two columns of memory cells share a bit line (BL). In this memory layer, the bit line (BL) is parallel to the substrate 1 and extends along the Y direction. Multiple transistors 2 can be arranged in rows along the Y direction on both sides of the corresponding bit line (BL). This allows the memory cells to be arranged on both sides of the corresponding bit line (BL) (which can be understood as each transistor 2 being arranged in the two regions separated by the bit line (BL)).

[0064] In some embodiments, the dimension of the word line WL in a first direction (eg, Y direction) is smaller than the dimension of the word line WL in a second direction (eg, X direction). The cross-sectional shape of the word line WL along a direction parallel to the substrate 1 (eg, XY plane) includes a circle and / or an ellipse.

[0065] For example, the cross-sectional shape of the word line WL in a direction parallel to the substrate 1 (eg, XY plane) further includes a polygon, which includes but is not limited to a rectangle, a rhombus, or a hexagon.

[0066] For example, the size of the word line WL in the second direction (eg, X direction) may be 2, 3, or more times the size of the word line WL in the first direction (eg, Y direction). The orthographic projection shape of the word line WL on the substrate 1 may be a regular pattern or an irregular pattern.

[0067] For example, the orthographic projection shape of the word line WL on the substrate 1 includes, but is not limited to, an ellipse with a major axis much larger than a minor axis.

[0068] For example, the orthographic projection shape of the word line WL on the substrate 1 includes, but is not limited to, a hexagon symmetrically arranged in both the first and second directions. For further example, the boundary of the hexagon intersecting the second direction is an arc, and the center of curvature of the arc is located outside the hexagon.

[0069] According to some embodiments, semiconductor layer 21 includes two channel regions Q3 located on either side of word line WL in a first direction (e.g., Y direction). A dimension D3 of the contact regions (e.g., Q1 and Q2) in the first direction (e.g., Y direction) is smaller than a shortest distance D4 between the two channel regions Q3. The connection between the contact regions (e.g., Q1 and Q2) and the corresponding channel regions Q3 may have an oblique or rounded transition angle.

[0070] In some embodiments, a difference between a shortest distance D1 from the channel region Q3 to the sidewall of the word line WL and a shortest distance D2 from any contact region (eg, Q1 and Q2 ) to the word line ranges from 1 nm to 30 nm.

[0071] For example, the difference between the shortest distance D1 from the channel region Q3 to the sidewall of the word line WL and the shortest distance D2 from any contact region (eg, Q1 and Q2) to the word line may be 10 nm, 15 nm, 20 nm, or 25 nm.

[0072] In some embodiments, the thickness of the semiconductor layer 21 in each channel region Q3 and each contact region (eg, Q1 and Q2 ) is the same.

[0073] In some embodiments, a thickness D2 of the gate insulating layer 22 near the contact regions (eg, Q1 and Q2 ) is greater than a thickness D1 near the channel region Q3 .

[0074] In some embodiments, a thickness difference between a thickness D2 of the gate insulating layer 22 near the contact regions (eg, Q1 and Q2 ) and a thickness D1 of the gate insulating layer 22 near the channel region Q3 ranges from 1 nm to 30 nm.

[0075] Preferably, the difference in thickness between the thickness D2 of the gate insulating layer 22 near the contact regions (eg, Q1 and Q2 ) and the thickness D1 near the channel region Q3 may be 10 nm, 15 nm, 20 nm, 25 nm, or the like.

[0076] In some embodiments, a thickness D2 of the gate insulating layer 22 near any contact region (eg, Q1 and Q2 ) is greater than a thickness D1 of the gate insulating layer 22 near the channel region Q3 .

[0077] In some embodiments, transistor 2 further includes a first source / drain S and a second source / drain D. The first source / drain S is connected to the first source / drain contact region Q1 and includes a first source / drain body 111 and at least one first branch 112 connected to the first source / drain body 111. The first branch 112 extends from the first source / drain body 111 toward the channel region Q3. The second source / drain D is connected to the second source / drain contact region Q2 and includes a second source / drain body 121 and at least one second branch 122 connected to the second source / drain body 121. The second branch 122 extends from the second source / drain body 121 toward the channel region Q3.

[0078] In some examples, the number of the first branch 112 may be one or two, and the number of the second branch 122 may be one or two.

[0079] In some embodiments, the word line WL includes sidewalls extending along a second direction (e.g., the X direction) and sidewalls extending along a first direction (e.g., the Y direction). The first source / drain contact region Q1 covers the sidewalls extending in the first direction, and the first branch 112 of the first source / drain S partially covers the sidewalls extending in the second direction (e.g., the X direction). The second source / drain contact region Q2 covers the sidewalls extending in the first direction (e.g., the Y direction), and the two second branches 122 of the second source / drain D partially cover the sidewalls extending in the second direction (e.g., the X direction).

[0080] In some embodiments, the two channel regions Q3 are located between the first source / drain contact region Q1 and the second source / drain contact region Q2 in the second direction (eg, the X direction).

[0081] According to some embodiments, referring to FIG. 1 a , the channel region Q3 extends along a second direction (e.g., the X direction). A first branch 112 contacts the channel region Q3; a side surface of the first branch 112 in a first direction (e.g., the Y direction) and a side surface of the channel region Q3 in contact therewith in the first direction (e.g., the Y direction) are co-located in the first direction (e.g., the Y direction); a second branch 122 contacts the channel region Q3; a side surface of the second branch 122 in the first direction (e.g., the Y direction) and a side surface of the channel region Q3 in contact therewith in the first direction (e.g., the Y direction) are co-located in the first direction (e.g., the Y direction).

[0082] In some embodiments, the memory further includes a bit line BL connected to the first source / drain body 111. The bit line BL is connected to a plurality of first sources / drains S arranged in a first direction (eg, Y direction).

[0083] In some embodiments, two adjacent transistors 2 along the second direction (eg, X direction) share a bit line BL; and the shortest distance D5 between the semiconductor layers 21 in the two adjacent transistors 2 is not less than a dimension D6 of the bit line BL in the second direction (eg, X direction).

[0084] Here, when the shortest distance D5 between the semiconductor layers 21 in two adjacent transistors 2 is equal to the dimension D6 of the bit line BL in the second direction (e.g., the X direction), the first source / drain S includes two first branches 112, which extend toward the channel region Q3 and are connected to the bit line BL.

[0085] For example, the material of the semiconductor layer 21 is not limited and may include silicon or a metal oxide. Taking a metal oxide semiconductor as an example, the semiconductor layer 21 may be an indium gallium zinc oxide (IGZO) layer, but is not limited thereto. The metal oxide material may be indium gallium zinc oxide (IGZO). When the metal oxide material is IGZO, the leakage current of the transistor 2 is small (less than or equal to 10-15A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO and other materials, as long as the leakage current of transistor 2 can meet the requirements, the specific adjustment can be made according to actual conditions.

[0086] For example, the gate insulating layer 22 includes but is not limited to a HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer with a high dielectric constant K, where the high dielectric constant K is, for example, greater than 3.9.

[0087] In addition, the word line WL is a gate word line, which can be used as a memory word line WL and also serve as a gate of the transistor 2 in each corresponding memory cell, thereby controlling the on and off of the transistor 2.

[0088] By way of example, the material of the word line WL includes a metal or metal oxide conductor, such as metal tungsten, metal copper, or ITO.

[0089] In some embodiments, referring to FIG. 2 and FIG. 2a , FIG. 2b , and FIG. 2c , such as a 1T1C scenario, the memory further includes a capacitor 3. The capacitor 3 includes a first electrode A correspondingly connected to the second source / drain body 121. The first electrode A extends along a second direction (e.g., the X direction).

[0090] In some embodiments, referring to FIG. 2 a and FIG. 2 c , the capacitor 3 further includes a dielectric layer 31 and a second electrode B stacked on the outer surface of the first electrode A.

[0091] For example, the dielectric layer 31 includes but is not limited to a HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer with a high dielectric constant K, where the high dielectric constant K is, for example, greater than 3.9.

[0092] For example, the material of the second electrode B includes but is not limited to metal, metal nitride, polysilicon, etc.

[0093] In some embodiments, referring to FIG. 2 a , the first source / drain body 111, the first branch 112, the second source / drain body 121, the second branch 122, and the bit line BL are formed from a single patterned conductive film layer. The bit line BL, the first source / drain body 111, and the first branch 112 are an integrated structure. The second source / drain body 121 and the second branch 122 are also an integrated structure. The first source / drain body 111, the first branch 112, the second source / drain body 121, the second branch 122, and the bit line BL have the same film thickness, which is the dimension perpendicular to the substrate 1 (e.g., the Z direction).

[0094] Here, the first source / drain body 111 , the first branch 112 , the second source / drain body 121 , the second branch 122 and the bit line BL are formed based on a patterning process of the same conductive film layer, which is beneficial to simplifying the manufacturing process of the memory and improving production efficiency.

[0095] For example, the first source / drain S includes two first branches 112, and the second source / drain D includes two second branches 122; the channel region Q3 is between adjacent first branches 112 and second branches 122, and the two first branches 112 and the two second branches 122 have the same length in the second direction (for example, the X direction).

[0096] For example, the conductive film layer may be a metal layer, a metal nitride (such as TiN), polysilicon, an alloy, or a metal oxide conductive layer (such as ITO). The metal may be a tungsten metal layer or a copper metal layer. Accordingly, the material of the bit line BL and the first electrode A may both be a metal layer, such as a tungsten metal layer or a copper metal layer.

[0097] In some embodiments, referring to FIG. 2 b , the semiconductor layers 21 in the plurality of transistors 2 stacked along a direction perpendicular to the substrate 1 (eg, the Z direction) are spaced apart along the direction perpendicular to the substrate 1 (eg, the Z direction).

[0098] It should be added that, please continue to refer to Figure 2, Figure 2a and Figure 2c. In the same storage layer of some embodiments, multiple dielectric layers 31 of a column of capacitors 3 arranged along the first direction (for example, the Y direction) can be connected as a whole, and multiple second electrodes B of the column of capacitors 3 can be connected as a whole.

[0099] In addition, optionally, in different storage layers of some embodiments, as shown in FIG. 2 c , the dielectric layers 31 of the capacitors 3 that are adjacently arranged in a direction perpendicular to the substrate 1 (eg, the Z direction) are integrally connected.

[0100] Optionally, as shown in FIG. 2 c , in the storage layer adjacent to the substrate 1 , the dielectric layer 31 further extends and is located between the second electrode B and the substrate 1 .

[0101] In some embodiments, referring to Figures 3 and 3a, 3b, and 3c, such as in a 1T1C scenario, the memory further includes a capacitor 3. Opposing contact regions of the semiconductor layer 21 in a second direction (e.g., the X direction) include a first source / drain contact region Q1 and a second source / drain contact region Q2. The transistor 2 further includes a first source / drain electrode S. The first source / drain electrode S covers the outer surface of the first source / drain contact region Q1 and includes a first source / drain body 111 and two first branches 112 connected to the first source / drain body 111. The first branches 112 extend toward the channel region Q3. The capacitor 3 includes a first electrode A correspondingly connected to the second source / drain contact region Q2. The first electrode A includes a first electrode body 131 and two third branches 132. The first electrode body 131 extends along the second direction (e.g., the X direction). The third branches 132 extend toward the channel region Q3.

[0102] Here, the connection between the first source / drain S and the corresponding bit line BL can refer to the related description in some of the aforementioned embodiments and will not be described in detail again.

[0103] According to some embodiments, referring to FIG. 3 a , the channel region Q3 extends along a second direction (e.g., the X direction). A first branch 112 contacts the channel region Q3; a side surface of the first branch 112 in a first direction (e.g., the Y direction) and a side surface of the channel region Q3 in contact therewith in the first direction (e.g., the Y direction) are co-located in the first direction (e.g., the Y direction); a second branch 122 contacts the channel region Q3; a side surface of the second branch 122 in the first direction (e.g., the Y direction) and a side surface of the channel region Q3 in contact therewith in the first direction (e.g., the Y direction) are co-located in the first direction (e.g., the Y direction).

[0104] In some embodiments, referring to FIG. 3 a , the first source / drain body 111, the first branch 112, the first electrode body 131, the third branch 132, and the bit line BL are formed from a single conductive film layer after patterning. The first source / drain body 111, the first branch 112, the first electrode body 131, the third branch 132, and the bit line BL have the same film thickness, which is the dimension perpendicular to the substrate 1 (e.g., the Z direction).

[0105] Here, the first source / drain body 111 , the first branch 112 , the first electrode body 131 , the third branch 132 and the bit line BL are formed based on a patterning process of the same conductive film layer, which is beneficial to simplify the manufacturing process of the memory and improve production efficiency.

[0106] For example, the conductive film layer may be a metal layer, such as a tungsten metal layer or a copper metal layer, etc. Accordingly, the materials of the bit line BL and the first electrode A may both be metal layers, such as a tungsten metal layer or a copper metal layer, etc.

[0107] In some embodiments, referring to FIG. 3 a and FIG. 3 c , the capacitor 3 further includes a dielectric layer 31 and a second electrode B stacked on the outer surface of the first electrode A.

[0108] Here, the materials and structures of the dielectric layer 31 and the second electrode B can be found in the related descriptions of some of the aforementioned embodiments and will not be described in detail.

[0109] It should be noted that the semiconductor layers 21 arranged adjacent to each other in a direction perpendicular to the substrate 1 (e.g., the Z direction) in each storage layer can be manufactured by etching the same initial semiconductor layer, and the corresponding manufacturing method is detailed in the relevant description later in this specification. The disclosed embodiment can minimize unnecessary semiconductor material between the capacitor 3 and the bit line BL to minimize parasitic capacitance, thereby further optimizing memory performance.

[0110] It is worth mentioning that in order to match the settings of the conductive elements in the above-mentioned memory (such as the bit line BL, the word line WL, the first electrode A, and the second electrode B), the memory may also include elements such as an insulating layer to meet the insulation requirements between adjacent conductive elements or between the conductive elements and the outside, and the corresponding manufacturing method is detailed in the relevant records later in this specification.

[0111] Some embodiments of the present disclosure also provide a method for manufacturing a memory, which is used to prepare the memory in some of the above embodiments. The manufacturing method also has the technical advantages of the above memories.

[0112] Please refer to FIG. 4 and understand in combination with FIG. 1 , FIG. 1 a , FIG. 1 b and FIG. 1 c , the manufacturing method includes the following steps.

[0113] S10, forming a conductive film layer on the substrate 1;

[0114] S20, patterning the conductive film layer to form word line holes; the word line holes extend in a direction perpendicular to the substrate 1 (e.g., the Z direction); a dimension of the word line holes in a first direction (e.g., the Y direction) is smaller than a dimension of the word line holes in a second direction (e.g., the X direction); the first direction (e.g., the Y direction) and the second direction (e.g., the X direction) are both parallel to the substrate 1 and intersect with each other;

[0115] S30, forming a semiconductor layer 21 conformally covering the inner wall of the word line hole;

[0116] S40, forming a gate insulating layer 22 conformally covering the inner surface of the semiconductor layer 21;

[0117] S50 , forming a word line WL that conformally covers the inner surface of the gate insulating layer 22 and fills the word line hole.

[0118] In which, the semiconductor layer 21 includes: a channel region Q3 located on at least one side of the word line WL in a first direction (for example, the Y direction), and two contact regions (for example, Q1 and Q2) located on both sides of the word line WL in a second direction (for example, the X direction); the shortest distance from the channel region Q3 to the word line WL is less than the shortest distance from at least one contact region (for example, Q1 and Q2) to the word line WL.

[0119] Some embodiments of the present disclosure also provide a method for manufacturing a memory, which is used to prepare the memory in some of the above embodiments. The manufacturing method also has the technical advantages of the above memories.

[0120] Please refer to FIG. 5 and understand in combination with FIG. 1 , FIG. 1 a , FIG. 1 b and FIG. 1 c , the manufacturing method includes the following steps.

[0121] S10′, forming a stacked structure having conductive film layers and sacrificial layers alternately stacked in a direction perpendicular to the substrate;

[0122] S20′, patterning the stack structure to form a bit line extending along a first direction and branches extending along a second direction on both sides of the bit line;

[0123] S30′, performing a patterning process on the branch to form a wordline hole on the branch, wherein the wordline hole penetrates the surface of the branch close to and away from the substrate; the wordline hole contacts an etch stop layer provided in the same layer as the branch, so that the branch is divided into a first portion and a second portion; the wordline hole penetrates into the first portion and the second portion of the branch in the second direction;

[0124] S40 ′, forming a semiconductor layer conformally covering the inner wall of the word line hole;

[0125] S50', forming a gate insulating layer conformally covering the inner surface of the semiconductor layer;

[0126] S60 ′, forming a gate or word line that conformally covers the inner surface of the gate insulating layer and fills the word line hole.

[0127] In which, the semiconductor layer 21 includes: a channel region Q3 located on at least one side of the word line WL in a first direction (for example, the Y direction), and two contact regions (for example, Q1 and Q2) located on both sides of the word line WL in a second direction (for example, the X direction), the first direction (for example, the Y direction) and the second direction (for example, the X direction) are both parallel to the substrate 1 and the first direction (for example, the Y direction) and the second direction (for example, the X direction) intersect; the shortest distance from the channel region Q3 to the word line WL is less than the shortest distance from at least one contact region (for example, Q1 and Q2) to the word line WL.

[0128] To more clearly illustrate the memory manufacturing methods described in some of the above embodiments, the following embodiments illustrate possible specific implementations of each step or portion of the steps using the memory manufacturing method shown in FIG2 as an example. The memory manufacturing methods shown in FIG1 and FIG3 can be adapted by referring to the following steps.

[0129] In step S10 ′, referring to FIG. 6 and FIG. 6 a , FIG. 6 b , and FIG. 6 c , a stacked structure having conductive film layers L1 and sacrificial layers L2 alternately stacked in a direction perpendicular to the substrate 1 (eg, the Z direction) is formed.

[0130] For example, the substrate 1 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI) substrate, or a silicon-germanium-on-insulator (SiGe) substrate.

[0131] For example, the conductive film layer L1 includes a metal layer or a metal nitride layer, such as a metal tungsten layer or a titanium nitride layer.

[0132] For example, the sacrificial layer L2 includes but is not limited to a silicon nitride layer, a silicon oxide layer, or other film layers suitable for serving as an etch stop layer.

[0133] Here, the number of stacked conductive film layers L1 can be set based on the number of stacked memory layers in the memory. Furthermore, the sacrificial layer L2 can be located between adjacent conductive film layers L1 or on one side of the first and last conductive film layers L1. The number of sacrificial layers L2 can match the number of stacked conductive film layers L1. Each conductive film layer L1 and each sacrificial layer L2 can be formed using a deposition process.

[0134] It should be noted that the deposition processes mentioned above and below include but are not limited to atomic layer deposition (ALD) process, chemical vapor deposition (CVD) process, molecular layer deposition (MLD) process, etc.

[0135] In addition, after forming the alternating stack of multi-layer conductive film layers L1 and multi-layer sacrificial layers L2, a first mask layer Y11, such as a photoresist layer and / or a hard mask layer, can be formed on the upper surface of the top sacrificial layer L2, thereby facilitating the subsequent etching of each conductive film layer L1 and each sacrificial layer L2 based on the mask pattern in the graphic first mask layer Y1.

[0136] Of course, the top sacrificial layer L2 can also be used as a hard mask.

[0137] In step S20 ′, referring to FIG. 7 and FIG. 7 a , FIG. 7 b , and FIG. 7 c , the stacked structure is patterned to form a bit line BL extending along a first direction (eg, Y direction) and branches L11 extending along a second direction (eg, X direction) on both sides of the bit line BL.

[0138] For example, forming the bit line BL and the branch L11 includes: anisotropically etching the multi-layer conductive film layer L1 and the multi-layer sacrificial layer L2 to transfer the mask pattern in the patterned first mask layer Y1 to each conductive film layer L1 and each sacrificial layer L2 to form a plurality of alternatingly stacked initial conductive pattern layers (not shown) and a plurality of sacrificial pattern layers L21; isotropically etching the side walls of the plurality of initial conductive pattern layers to form a bit line BL extending along a first direction (e.g., Y direction) and branches L11 extending along a second direction (e.g., X direction) on both sides of the bit line BL.

[0139] Here, the orthographic projection of the branch L11 on the substrate 1 is located within the orthographic projection of the sacrificial pattern layer L21 on the substrate 1 , and there is a gap between the outer boundary of the orthographic projection of the branch L11 on the substrate 1 and the outer boundary of the orthographic projection of the sacrificial pattern layer L21 on the substrate 1 .

[0140] For example, the branches L11 extend along the X direction and are arranged at intervals in the Y direction. Optionally, the branches L11 are symmetrically distributed around the bit line BL.

[0141] In some embodiments, please continue to refer to Figures 7, 7a, 7b, and 7c. After obtaining multiple branches L11 and multiple sacrificial pattern layers L21 that are alternately stacked, the manufacturing method also includes: forming an etching barrier layer L3 that covers the side walls of the branches L11 and the sacrificial pattern layer L21 and fills the gaps between adjacent branches L11.

[0142] For example, the material of the etch stop layer L3 includes but is not limited to nitride or oxide, such as silicon nitride or silicon oxide. Of course, it can also be other materials, such as an aluminum oxide film layer.

[0143] For example, the etch stop layer L3 is formed by a deposition process, and the outline size of the etch stop layer L3 can be determined to match the locations of the branches L11 , the sacrificial pattern layer L21 and the subsequent capacitors 4 .

[0144] It should be added that, in some embodiments, the etch stop layer L3 may be formed before removing the aforementioned patterned first mask layer Y1 .

[0145] In some embodiments, referring to Figures 8a, 8b, and 8c, after forming the etch stop layer L3, the manufacturing method further includes forming a second mask layer Y2 on the upper surface of the patterned first mask layer Y1. The second mask layer Y2 has an opening pattern for defining the location where the capacitor 3 is formed.

[0146] An etching process is performed on the structure after the etch stop layer L3 is formed based on the second mask layer Y2 to remove the etch stop layer L3 and the sacrificial pattern layer L21 exposed by the opening pattern, exposing the first electrode A. The first electrode A is the end of the branch L11.

[0147] It should be added that the "one-time etching process" mentioned in some of the above embodiments can be understood as: etching based on the pattern of the same mask layer to form the same pattern; and it is not limited to a specific etching method, for example, it can be implemented by dry etching, it can be implemented by wet etching, or it can be implemented by both dry etching and wet etching, etc.

[0148] In some embodiments, referring to Figures 9a, 9b, and 9c, after exposing the first electrode A, the manufacturing method further includes: removing the patterned first mask layer Y1 and the second mask layer Y2; depositing a dielectric material to form a dielectric layer 31 that conformally covers the outer surface of the first electrode A and the etched surface of the sacrificial pattern layer L21.

[0149] For example, a grinding process including but not limited to chemical mechanical polishing (CMP) can be used to remove the patterned first mask layer Y1 and the second mask layer Y2 and ensure that the surfaces of the etch stop layer L3 and the top sacrificial pattern layer L21 are smooth.

[0150] For example, the dielectric layer 31 can be formed simultaneously by a deposition process. The material of the dielectric layer 31 includes HK dielectric material. The deposition thickness of the dielectric layer 31 can be set according to requirements.

[0151] For example, in different storage layers, the dielectric layers 31 of capacitors 3 arranged adjacent to each other in a direction perpendicular to the substrate 1 (eg, the Z direction) are integrally connected. Optionally, in the storage layer adjacent to the substrate 1 , the dielectric layer 31 also extends to cover the surface of the substrate 1 .

[0152] In some examples, after forming the dielectric layer 31 , the manufacturing method further includes: depositing a conductive material to form a second electrode B covering the dielectric layer 31 .

[0153] Illustratively, the material of the second electrode B includes but is not limited to polysilicon.

[0154] For example, after the second electrode B is formed by a deposition process, the upper surface of the second electrode B may be polished by a CMP process.

[0155] For example, in the same storage layer, multiple second electrodes B of a column of capacitors 3 may be connected as one. In different storage layers, multiple second electrodes B of capacitors 3 located on the same side of the bit line BL may be connected as one.

[0156] In step S30', referring to Figure 10 and Figures 10a, 10b, and 10c, a patterning process is performed on the branch L11 to form a word line hole G1 on the branch L11. The word line hole G1 penetrates the surface of the branch L11 close to and away from the substrate 1; the word line hole G1 contacts the etch stop layer L3 provided in the same layer as the branch L11, so that the branch L11 is broken into a first portion L111 and a second portion L112; the word line hole G1 penetrates into the first portion L111 and the second portion L112 of the branch L11 in a second direction (e.g., the X direction).

[0157] In some examples, the word line hole G1 penetrates both the surface of the sacrificial pattern layer L21 near and the surface far from the substrate 1. For example, the orthographic projection shape of the word line hole G1 on the substrate 1 includes, but is not limited to, a cross. For further example, the size of the word line hole G1 in the second direction (e.g., the X direction) can be 2 times, 3 times, or more times the size of the word line hole G1 in the first direction (e.g., the Y direction).

[0158] For example, an isotropic etching process may be used to pattern the branch L11 .

[0159] In step S40 ′, referring to FIG. 11 and FIG. 11 a , FIG. 11 b , and FIG. 11 c , a semiconductor layer 21 is formed conformally covering the inner wall of the word line hole G1 .

[0160] In step S50 ′, referring to FIG. 11 and FIG. 11 a , FIG. 11 b , and FIG. 11 c , a gate insulating layer 22 is formed conformally covering the inner surface of the semiconductor layer 21 .

[0161] In step S60', referring to Figures 11 and 11a, 11b, and 11c, a word line WL is formed conformally covering the inner surface of the gate insulation layer 22 and filling the word line hole. The semiconductor layer 21 includes a channel region Q3 located on at least one side of the word line WL in a first direction (e.g., the Y direction), and two contact regions (e.g., Q1 and Q2) located on either side of the word line WL in a second direction (e.g., the X direction). The first direction (e.g., the Y direction) and the second direction (e.g., the X direction) are both parallel to the substrate 1 and intersect with each other. The shortest distance from the channel region Q3 to the word line WL is shorter than the shortest distance from at least one of the contact regions (e.g., Q1 and Q2) to the word line WL.

[0162] In some embodiments, the contact regions on both sides of the word line WL in the second direction (e.g., the X direction) include a first source / drain contact region Q1 and a second source / drain contact region Q2. Step S30' forms the word line hole G1 and also includes simultaneously forming a bit line BL, a first source / drain electrode S, and a second source / drain electrode D. The first source / drain electrode S covers the outer surface of the first source / drain contact region Q1 and includes a first source / drain body 111 and at least one first branch 112 connected to the first source / drain body 111. The first branch 112 extends from the first source / drain body 111 toward the channel region Q3. The second source / drain electrode D covers the outer surface of the second source / drain contact region Q2 and includes a second source / drain body 121 and at least one second branch 122 connected to the second source / drain body 121. The second branch 122 extends from the second source / drain body 121 toward the channel region Q3. The bit line BL is connected to a plurality of first source / drain electrodes S arranged in the first direction (e.g., the Y direction).

[0163] In some embodiments, the simultaneous formation of the bit line BL, the first source / drain S, and the second source / drain D also includes the simultaneous formation of the first electrode A of the capacitor 3. The capacitor 3 includes the first electrode A correspondingly connected to the second source / drain body 121. The first electrode A extends along the second direction (eg, the X direction).

[0164] For example, the semiconductor layer 21 includes but is not limited to a metal oxide semiconductor layer, such as an IGZO layer.

[0165] For example, the semiconductor layer 21 may be formed by a deposition process, such as an ALD process.

[0166] Illustratively, the gate insulating layer 22 includes, but is not limited to, a HK dielectric layer.

[0167] For example, the gate insulating layer 22 may be formed by a deposition process, such as an ALD process.

[0168] For example, the word line WL extends in a direction perpendicular to the substrate 1 (eg, the Z direction), and the material of the word line WL includes but is not limited to metal tungsten.

[0169] For example, the word line WL may be formed by a deposition process, so that when the word line material is filled, the portion close to the contact region tends to be closed, thereby forming the word line WL having a specific irregular shape as described above.

[0170] Furthermore, after the word lines WL are formed by a deposition process, a CMP process may be used to grind the upper surface of the resulting structure to ensure that the exposed word lines WL have good surface quality.

[0171] In some embodiments, referring to FIG. 12 and FIG. 12a , FIG. 12b , and FIG. 12c , after forming the word line WL, the manufacturing method further includes: removing the etching stop layer L3 on the side wall of the sacrificial pattern layer L21 to form a through hole G2 ; the through hole G2 exposes part of the side wall of the sacrificial pattern layer L21 and part of the surface of the dielectric layer 31 .

[0172] For example, the through hole G2 may be formed by using an isotropic etching process.

[0173] In some embodiments, referring to FIG. 13 and FIG. 13 a , FIG. 13 b , and FIG. 13 c , after forming the through hole G2 , the manufacturing method further includes: removing the sacrificial pattern layer L21 .

[0174] For example, an isotropic etching process may be used to remove the sacrificial pattern layer L21 .

[0175] In some embodiments, please refer to FIG. 14 , FIG. 14 a , FIG. 14 b , FIG. 14 c and FIG. 2 to understand that after removing the sacrificial pattern layer L21 , the manufacturing method further includes: etching the semiconductor layer 21 to expose the gate insulating layer 22 .

[0176] For example, the semiconductor layer 21 may be etched using an isotropic etching process.

[0177] In some embodiments, referring to Figures 14 and 14a, 14b, and 14c, an insulating material is filled in the etched region of the semiconductor layer 21 to form an insulating layer L4 together with the remaining etch stop layer L3. The insulating material includes but is not limited to silicon oxide.

[0178] Here, the insulating layer L4 may be formed by a deposition process. After the insulating layer L4 is formed by the deposition process, the upper surface of the insulating layer may be polished by a CMP process to ensure that the upper surface of the insulating layer L4 is flat and the upper surface of the word line WL is exposed with good surface quality.

[0179] Some embodiments of the present disclosure also provide electronic devices, such as data storage devices, photocopiers, network devices, household appliances, instruments, mobile phones, computers, and other devices with data storage capabilities. The electronic device may include a housing, a circuit board disposed within the housing, and a memory integrated on the circuit board. For the structure of the memory, please refer to the relevant descriptions in some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited by the embodiments of the present disclosure.

[0180] In some embodiments, an external control device, such as a processor or actuator, coupled to the memory may also be integrated on the circuit board. For example, the electronic device may further include a processor integrated on the circuit board. The processor is coupled to the memory and can control read and write operations of the memory.

[0181] In some embodiments, the memory is a three-dimensional dynamic random access memory.

[0182] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0183] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A memory, comprising: substrate; A word line extending in a direction perpendicular to the substrate; a transistor including a semiconductor layer at least partially surrounding the word line and a gate insulating layer disposed between the word line and the semiconductor layer; Wherein, the semiconductor layer includes: a channel region located on at least one side of the word line in a first direction, and two contact regions located on both sides of the word line in a second direction, the first direction and the second direction are both parallel to the substrate and the first direction and the second direction intersect; the shortest distance from the channel region to the word line is less than the shortest distance from at least one of the contact regions to the word line; the two contact regions include: a first source / drain contact region and a second source / drain contact region.

2. The memory according to claim 1, wherein: A dimension of the word line in the first direction is smaller than a dimension of the word line in the second direction.

3. The memory according to claim 1, wherein: The cross-sectional shape of the word line along a direction parallel to the substrate includes a circle, a polygon or an ellipse.

4. The memory according to any one of claims 1 to 3, wherein: The semiconductor layer includes two channel regions located at both sides of the word line in the first direction; a size of the contact region in the first direction is smaller than the shortest distance between the two channel regions.

5. The memory according to any one of claims 1 to 4, wherein: The difference between the shortest distance from the channel region to the word line and the shortest distance from the contact region to the word line ranges from 1 nm to 30 nm.

6. The memory according to any one of claims 1 to 5, wherein: The thickness of the gate insulating layer close to the contact region is greater than the thickness of the gate insulating layer close to the channel region.

7. The memory according to any one of claims 1 to 6, wherein: The thickness of the semiconductor layer in the channel region is the same as the thickness of the semiconductor layer in the contact region.

8. The memory according to any one of claims 1 to 7, wherein: The transistor further comprises: a first source / drain connected to the first source / drain contact region, comprising a first source / drain body and at least one first branch connected to the first source / drain body, wherein the first branch extends from the first source / drain body to the channel region; The second source / drain is connected to the second source / drain contact region, and includes a second source / drain body and at least one second branch connected to the second source / drain body, wherein the second branch extends from the second source / drain body to the channel region.

9. The memory according to claim 8, wherein: The word line includes a sidewall extending along the second direction and a sidewall extending along the first direction; The first source / drain contact region covers the sidewall extending in the first direction, and the first branch of the first source / drain electrode covers part of the sidewall extending in the second direction; The second source / drain contact region covers a sidewall extending in the first direction, and the second branch of the second source / drain covers a portion of the sidewall extending along the second direction.

10. The memory according to claim 9, wherein: The channel region is located between the first source / drain contact region and the second source / drain contact region in the second direction.

11. The memory according to claim 9 or 10, wherein: It also includes a bit line connected to the first source / drain body, wherein the bit line, the first source / drain body, the first branch, the second source / drain body and the second branch are formed by patterning the same conductive film layer; The bit line, the first source / drain body, and the first branch are an integrated structure; The second source / drain body and the second branch are an integrated structure.

12. The memory according to any one of claims 9 to 11, wherein: The first source / drain includes two first branches, and the second source / drain includes two second branches; the channel region is between adjacent first branches and second branches, and the two first branches have the same length in the second direction, and the two second branches have the same length in the second direction.

13. The memory according to any one of claims 9 to 12, wherein: The channel region extends along the second direction; The first branch is in contact with the channel region; the side surface of the first branch in the first direction and the side surface of the channel region in contact with the first branch in the first direction have the same position in the first direction; The second branch is in contact with the channel region; The side surface of the second branch in the first direction and the side surface of the channel region in contact with the second branch in the first direction have the same position in the first direction.

14. A method for manufacturing a memory, comprising: forming a conductive film layer on a substrate; patterning the conductive film layer to form word line holes; The word line hole extends in a direction perpendicular to the substrate, a size of the word line hole in the first direction is smaller than a size of the word line hole in the second direction, and the first direction and the second direction are both parallel to the substrate and intersect; forming a semiconductor layer conformally covering the inner wall of the word line hole; forming a gate insulating layer conformally covering the inner surface of the semiconductor layer; forming a word line that conformally covers the inner surface of the gate insulating layer and fills the word line hole; Wherein, the semiconductor layer includes: a channel region located on at least one side of the word line in the first direction, and two contact regions located on both sides of the word line in the second direction; the shortest distance from the channel region to the word line is smaller than the shortest distance from at least one of the contact regions to the word line.

15. A method for manufacturing a memory, comprising: forming a stacked structure having conductive film layers and sacrificial layers alternately stacked in a direction perpendicular to the substrate; Patterning the stack structure to form a bit line extending along a first direction and branches extending along a second direction on both sides of the bit line; Performing a patterning process on the branch to form a word line hole on the branch, wherein the word line hole penetrates the surface of the branch close to and away from the substrate; The word line hole contacts an etching stop layer disposed in the same layer as the branch, so that the branch is broken into a first part and a second part; forming a semiconductor layer conformally covering the inner wall of the word line hole; forming a gate insulating layer conformally covering the inner surface of the semiconductor layer; forming a gate or a word line that conformally covers the inner surface of the gate insulating layer and fills the word line hole; Wherein, the semiconductor layer includes: a channel region located on at least one side of the word line in the first direction, and two contact regions located on both sides of the word line in the second direction, the first direction and the second direction are both parallel to the substrate and the first direction and the second direction intersect; the shortest distance from the channel region to the word line is less than the shortest distance from at least one of the contact regions to the word line.

16. The method for manufacturing a memory according to claim 14 or 15, wherein: The contact regions located on both sides of the word line in the second direction include: a first source / drain contact region and a second source / drain contact region; The forming of the word line hole also includes: synchronously forming a first source / drain, a second source / drain and a bit line; wherein the first source / drain covers the outer surface of the first source / drain contact area, includes a first source / drain body and at least one first branch connected to the first source / drain body, and the first branch extends from the first source / drain body to the channel area; the second source / drain covers the outer surface of the second source / drain contact area, includes a second source / drain body and at least one second branch connected to the second source / drain body, and the second branch extends from the second source / drain body to the channel area; the bit line extends along the first direction and contacts the first source / drain body.

17. An electronic device comprising: The memory according to any one of claims 1 to 13.

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