Display substrate and display apparatus

Abstract

The present disclosure provides a display substrate and a display apparatus. The display substrate comprises a display area and a peripheral area, wherein the peripheral area comprises a first bezel area and a second bezel area which are oppositely provided, and the display area is located between the first bezel area and the second bezel area. The display substrate further comprises a plurality of first power branch lines, wherein at least some of the first power branch lines are located in the display area; and a first power bus, wherein the first power bus comprises a first power sub-line, the first power sub-line is located in the first bezel area, the first power sub-line comprises a first power portion and a second power portion, the first power portion is located between the display area and the second power portion, the first power portion is coupled to the plurality of first power branch lines respectively, the first power portion and the second power portion are coupled by means of a plurality of first conductive connection portions, and the number of first conductive connection portions is less than that of first power branch lines.

Description

Display substrate and display device

[0001] Cross-reference of related applications

[0002] This application claims priority to Chinese Patent Application No. 202310409744.8, filed in China on April 17, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0004] With the continuous development of display technology, people have increasingly higher requirements for the resolution of display products. High-resolution display products can be applied to 3D display products. These 3D display products divide pixels into multiple view zones, each displaying object information from a different perspective. Combined with microlenses, 3D display functionality can be achieved. For 3D displays, the more pixels within a view zone, the better the 3D display effect. However, a larger number of pixels within a view zone requires more pixel drive signal lines and more drive channels for the drive unit, leading to greater layout difficulty in the peripheral areas of the display product and higher loading of signal lines in the peripheral areas.

[0005] Therefore, there is an urgent need for a layout method to solve the problems of difficult layout in the peripheral area of ​​high-resolution display products and large loading of signal lines.

[0006] Summary of the Invention

[0007] The purpose of this disclosure is to provide a display substrate and a display device.

[0008] To achieve the above objectives, this disclosure provides the following technical solution:

[0009] A first aspect of this disclosure provides a display substrate, including a substrate, the substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a first border area and a second border area disposed opposite to each other, the display area being located between the first border area and the second border area; the display substrate further includes:

[0010] Multiple first power supply branches, at least a portion of which are located in the display area;

[0011] A first power bus, the first power bus includes a first sub-power line, the first sub-power line is located in the first frame area, the first sub-power line includes a first power part and a second power part, the first power part is located between the display area and the second power part, the first power part is coupled to the plurality of first power branches respectively, the first power part and the second power part are coupled through a plurality of first conductive connections, the number of first conductive connections is less than the number of first power branches.

[0012] Optionally, the first power bus includes a second sub-power line;

[0013] The second sub-power line is located in the second frame area. The second sub-power line includes a third power section and a fourth power section. The third power section is located between the display area and the fourth power section. The third power section is coupled to the plurality of first power branches respectively. The third power section and the fourth power section are coupled through a plurality of second conductive connections. The number of second conductive connections is less than the number of first power branches.

[0014] Optionally, the surrounding area further includes a third border area and a fourth border area that are disposed opposite to each other, and the display area is located between the third border area and the fourth border area;

[0015] The first power bus further includes: at least one third sub-power line, the third sub-power line being located in the third frame area and / or the fourth frame area, the third sub-power line being coupled to at least two of the first power unit, the second power unit, the third power unit and the fourth power unit.

[0016] Optionally, the display substrate further includes:

[0017] Multiple data lines, at least a portion of which are located in the display area;

[0018] A plurality of first electrostatic discharge units are located between the third power supply unit and the fourth power supply unit. Each first electrostatic discharge unit is coupled to a corresponding data line and is used to perform electrostatic discharge on the data line.

[0019] Optionally, the display substrate further includes:

[0020] A first level signal line and two second level signal lines, wherein the first level signal line is located between the two second level signal lines, and both the first level signal line and the second level signal line are located between the third power supply section and the fourth power supply section;

[0021] The plurality of first electrostatic discharge units are divided into two rows of first electrostatic discharge units. The first row of first electrostatic discharge units is located between the first level signal line and one of the second level signal lines, and the second row of first electrostatic discharge units is located between the first level signal line and the other second level signal line.

[0022] The first electrostatic discharge unit is coupled to its adjacent second-level signal line and first-level signal line respectively. The first electrostatic discharge unit is used to conduct or disconnect the electrical connection between the data line and the first-level signal line under the control of the data line. The first electrostatic discharge unit is also used to conduct or disconnect the electrical connection between the data line and the second-level signal line under the control of the data line.

[0023] Optionally, the data lines coupled to the first electrostatic discharge unit in the first row and the data lines coupled to the first electrostatic discharge unit in the second row are alternately arranged.

[0024] Optionally, the display substrate further includes:

[0025] A cathode layer, at least a portion of which is located in the display area;

[0026] The second power bus includes a fourth sub-power line and a fifth sub-power line; the fourth sub-power line is located in the first bezel area and on the side of the second power unit away from the display area; the fifth sub-power line is located in the second bezel area and on the side of the fourth power unit away from the display area; the fourth sub-power line and the fifth sub-power line are respectively coupled to the cathode layer.

[0027] Optionally, the display substrate further includes:

[0028] Multiple data lines, at least a portion of which are located in the display area;

[0029] At least two multiplexing lines are located between the first power supply section and the second power supply section;

[0030] A first multiplexer circuit is located between the first power supply section and the second power supply section, and the first multiplexer circuit is coupled to the plurality of data lines and the at least two multiplexed lines respectively.

[0031] Optionally, the display substrate further includes:

[0032] A plurality of first driving units are located on the side of the fourth sub-power line away from the display area, and the plurality of first driving units are respectively coupled to the second power supply unit.

[0033] Optionally, the first driving unit includes two first ports, one of which is located at a first end of the first driving unit and the other is located at a second end of the first driving unit; the first ports are coupled to the second power supply unit through a third conductive connection portion.

[0034] Optionally, the first drive unit further includes two second ports, one of which is located at the first end of the first drive unit and the other is located at the second end of the first drive unit; the second ports are coupled to the fourth sub-power line through a fourth conductive connection portion.

[0035] Optionally, the first driving unit further includes two sets of third ports, one set of third ports located at the first end of the first driving unit and the other set of third ports located at the second end of the first driving unit; each set of third ports includes at least two third ports, and the third ports are coupled to the corresponding multiplexed line through the fifth conductive connection portion.

[0036] Optionally, the second port, the first port, and the third port are arranged sequentially along the direction from the center portion of the first driving unit to the end of the first driving unit; the fourth conductive connection portion, the third conductive connection portion, and the fifth conductive connection portion are arranged sequentially.

[0037] Optionally, in adjacent first drive units, the two closest third ports are coupled to the same multiplexed line, and the fifth conductive connection portion coupled to the two closest third ports is coupled to each other.

[0038] Optionally, the display substrate further includes:

[0039] A plurality of second driving units are located on the side of the fifth sub-power line away from the display area. The second driving units are coupled to at least one of the fourth power supply unit, the fifth sub-power line, the first level signal line, and the two second level signal lines.

[0040] Optionally, the display substrate further includes: a first gate metal layer, a second gate metal layer, a first source / drain metal layer, and a second source / drain metal layer sequentially stacked on the substrate in a direction away from the substrate.

[0041] At least one of the first power supply unit, the second power supply unit, and the multiplexing line is disposed in the same layer and with the same material as the first source / drain metal layer.

[0042] Optionally, the first conductive connection portion and the second source / drain metal layer are disposed in the same layer and made of the same material.

[0043] Optionally, the fourth sub-power line adopts a double-layer stacked structure, wherein the first layer of the double-layer stacked structure is made of the same material as the first gate metal layer, and the second layer of the double-layer stacked structure is made of the same material as the second source / drain metal layer.

[0044] Optionally, at least one of the third power supply unit, the fourth power supply unit, and the fifth sub-power line is disposed in the same layer and with the same material as the first source / drain metal layer.

[0045] Optionally, at least one of the third power supply unit, the fourth power supply unit, and the fifth sub-power line adopts a double-layer stacked structure, wherein the first layer of the double-layer stacked structure is disposed in the same layer and with the same material as the first source / drain metal layer, and the second layer of the double-layer stacked structure is disposed in the same layer and with the same material as the second source / drain metal layer.

[0046] Optionally, the display substrate further includes: a plurality of fan-out lines, the fan-out lines including a first fan-out portion and a second fan-out portion, at least a portion of the orthographic projection of the first fan-out portion on the substrate is located between the orthographic projection of the second power supply on the substrate and the orthographic projection of the fourth sub-power line on the substrate; the orthographic projection of the second fan-out portion on the substrate is located on the side of the orthographic projection of the fourth sub-power line on the substrate away from the display area.

[0047] The first fan-out portion is disposed in the same layer and material as the first gate metal layer or the second source / drain metal layer;

[0048] The second fan-out portion is disposed in the same layer and with the same material as the first gate metal layer or the first source / drain metal layer.

[0049] Optionally, the display substrate further includes:

[0050] A gate driving circuit, the gate driving circuit being located in the third border region and / or the fourth border region, the gate driving circuit including a plurality of shift register units arranged along a first direction;

[0051] A third driving unit, at least a portion of which is arranged with the gate driving circuit along the first direction, is coupled to the gate driving circuit.

[0052] Optionally, the third drive unit is coupled to the third sub-power line.

[0053] Based on the technical solution of the display substrate, a second aspect of this disclosure provides a display device including the aforementioned display substrate. Attached Figure Description

[0054] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0055] Figure 1 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0056] Figure 2 is a schematic diagram of the lower left corner of the display substrate provided in the embodiment of this disclosure;

[0057] Figure 3 is an enlarged schematic diagram of part A1 in Figure 2;

[0058] Figure 4 is an enlarged schematic diagram of part A2 in Figure 2;

[0059] Figure 5 is an enlarged schematic diagram of part A3 in Figure 2;

[0060] Figure 6 is an enlarged schematic diagram of part A4 in Figure 2;

[0061] Figure 7 is an enlarged schematic diagram of part A5 in Figure 2;

[0062] Figure 8 is an enlarged schematic diagram of part A6 in Figure 2;

[0063] Figure 9 is a schematic diagram of the structure of the lower frame of the display substrate provided in the embodiment of this disclosure;

[0064] Figure 10 is an enlarged schematic diagram of part A7 in Figure 9;

[0065] Figure 11 is an enlarged schematic diagram of part A8 in Figure 10;

[0066] Figure 12 is an enlarged schematic diagram of part A9 in Figure 10;

[0067] Figure 13 is a schematic diagram of the structure of the display substrate provided in the embodiment of this disclosure in the upper left corner;

[0068] Figure 14 is an enlarged schematic diagram of part A10 in Figure 13;

[0069] Figure 15 is an enlarged schematic diagram of part A11 in Figure 13;

[0070] Figure 16 is a circuit diagram of the first electrostatic discharge unit provided in an embodiment of this disclosure. Detailed Implementation

[0071] To further illustrate the display substrate and display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0072] Please refer to Figures 1 to 6, and Figures 9 to 11. This disclosure provides a display substrate, including a substrate base. The substrate base includes a display area 10 and a peripheral area 20 surrounding the display area 10. The peripheral area 20 includes a first border area 201 and a second border area 202 disposed opposite to each other. The display area 10 is located between the first border area 201 and the second border area 202. The display substrate further includes:

[0073] Multiple first power supply branches VDD1, at least a portion of which are located in the display area 10;

[0074] A first power bus VDD2 includes a first sub-power line VDD21 located in the first frame area 201. The first sub-power line VDD21 includes a first power section VDD211 and a second power section VDD212. The first power section VDD211 is located between the display area 10 and the second power section VDD212. The first power section VDD211 is coupled to the plurality of first power branches VDD1 respectively. The first power section VDD211 and the second power section VDD212 are coupled through a plurality of first conductive connections VDD213. The number of first conductive connections VDD213 is less than the number of first power branches VDD1.

[0075] For example, the display substrate includes a display area 10 and a peripheral area 20 surrounding the display area 10, wherein the peripheral area 20 may at least partially surround the display area 10. For example, the peripheral area 20 surrounds the display area 10.

[0076] For example, the surrounding area 20 includes a first border area 201 and a second border area 202 disposed opposite to each other along a first direction. The first border area 201 includes a lower border area, and the second border area 202 includes an upper border area.

[0077] For example, the display area 10 of the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixel pixels are arranged in an array. The plurality of sub-pixel driving circuits are divided into multiple rows of sub-pixel driving circuits and multiple columns of sub-pixel driving circuits. The multiple rows of sub-pixel driving circuits are arranged along a first direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. The multiple columns of sub-pixel driving circuits are arranged along the second direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along the first direction. For example, the first direction intersects with the second direction. For example, the first direction includes a vertical direction, and the second direction includes a horizontal direction. For example, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to the anode of the light-emitting element and is used to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0078] For example, the display substrate further includes a plurality of virtual sub-pixels located in the dum-pixel region shown in FIG1, the plurality of virtual sub-pixels surrounding the plurality of sub-pixels. The first power supply unit VDD211, the second power supply unit VDD212, the third power supply unit VDD221, and the fourth power supply unit VDD222 are all located on the side of the virtual sub-pixels away from the display area 10.

[0079] For example, the plurality of first power branches VDD1 are arranged along the second direction, and each first power branch VDD1 includes at least a portion extending along the first direction. Each first power branch VDD1 is coupled to a corresponding column of sub-pixel driving circuits within the display area 10, and is used to provide a first power signal to the sub-pixel driving circuits. This first power signal may be a positive power signal, but is not limited to this.

[0080] For example, within the display area 10, the plurality of first power branches VDD1 are electrically connected by a plurality of conductive parts extending along a second direction, and a mesh structure is formed between the plurality of first power branches VDD1 and the conductive parts.

[0081] For example, the first power bus VDD2 includes a first sub-power line VDD21, the first sub-power line VDD21 includes a first power portion VDD211 and a second power portion VDD212, the first power portion VDD211 and the second power portion VDD212 are arranged along a first direction, the first power portion VDD211 includes at least a portion extending along a second direction, and the second power portion VDD212 includes at least a portion extending along the second direction.

[0082] For example, the width of the first power supply unit VDD211 in the direction perpendicular to its own extension is between 45 micrometers and 55 micrometers, and may include, but is not limited to, endpoint values.

[0083] For example, the width of the second power supply unit VDD212 in the direction perpendicular to its own extension is between 1350 micrometers and 1450 micrometers, and may include, but is not limited to, endpoint values.

[0084] As shown in Figures 2, 3, 5, and 6, exemplarily, the plurality of first power supply branches VDD1 extend from the display area 10 to the first bezel area 201 and are coupled to the first power supply portion VDD211. The plurality of first conductive connections VDD213 are arranged along the second direction, each first conductive connection VDD213 including at least a portion extending along the first direction, and at least a portion of the orthographic projection of the first conductive connection VDD213 onto the substrate is located between the orthographic projection of the first power supply portion VDD211 onto the substrate and the orthographic projection of the second power supply portion VDD212 onto the substrate.

[0085] As shown in Figures 5 and 11, by way of example, the orthographic projection of the first conductive connection portion VDD213 on the substrate and the orthographic projection of the first power supply portion VDD211 on the substrate have an overlapping area. The first conductive connection portion VDD213 is coupled to the first power supply portion VDD211 through a via (e.g., Via3) in the overlapping area. The orthographic projection of the first conductive connection portion VDD213 on the substrate and the orthographic projection of the second power supply portion VDD212 on the substrate also have an overlapping area. The first conductive connection portion VDD213 is coupled to the second power supply portion VDD212 through a via (e.g., Via5) in the overlapping area.

[0086] For example, the first conductive connection portion VDD213 and the first power supply portion VDD211 are formed as an integral structure; and / or, the first conductive connection portion VDD213 and the second power supply portion VDD212 are formed as an integral structure.

[0087] For example, the number of the first conductive connection portions VDD213 is less than or equal to half the number of the first power branch VDD1, but is not limited thereto.

[0088] As can be seen from the specific structure of the display substrate described above, in the display substrate provided in this embodiment, the first power bus VDD2 includes a first sub-power line VDD21. The first sub-power line VDD21 includes a first power part VDD211 and a second power part VDD212. The first power part VDD211 is close to the display area 10, and the second power part VDD212 is close to the edge of the display substrate. The first power part VDD211 and the second power part VDD212 are electrically connected through multiple first conductive connection parts VDD213. This arrangement allows the first power part VDD211 to be coupled to multiple first power branches VDD1 located in the display area 10, and the second power part VDD212 to be coupled to the driving structure located at the edge of the display substrate. This effectively reduces the difficulty of connecting the first power part VDD211 to a large number of first power branches VDD1 in a high-resolution display substrate, and also reduces the difficulty of connecting the second power part VDD212 to the driving structure. Meanwhile, the first power supply section VDD211 and the second power supply section VDD212 are connected by a number of first conductive connection sections VDD213, which is less than the number of first power supply branches VDD1. This not only reduces the layout difficulty of the first power bus VDD2, but also effectively reduces the border size of the first border area 201.

[0089] Furthermore, in the display substrate provided in this embodiment, by setting the first power bus VDD2 to include the first power supply section VDD211, the second power supply section VDD212, and the plurality of first conductive connection sections VDD213, the loading of the first power bus VDD2 is effectively reduced.

[0090] As shown in Figures 1, 13 to 15, in some embodiments, the first power bus VDD2 includes a second sub-power line VDD22.

[0091] The second sub-power line VDD22 is located in the second frame area 202. The second sub-power line VDD22 includes a third power part VDD221 and a fourth power part VDD222. The third power part VDD221 is located between the display area 10 and the fourth power part VDD222. The third power part VDD221 is coupled to the plurality of first power branches VDD1 respectively. The third power part VDD221 and the fourth power part VDD222 are coupled through a plurality of second conductive connections VDD223. The number of second conductive connections VDD223 is less than the number of first power branches VDD1.

[0092] For example, the first power bus VDD2 includes a second sub-power line VDD22, the second sub-power line VDD22 includes a third power section VDD221 and a fourth power section VDD222, the third power section VDD221 and the fourth power section VDD222 are arranged along a first direction, the third power section VDD221 includes at least a portion extending along a second direction, and the fourth power section VDD222 includes at least a portion extending along the second direction.

[0093] For example, the width of the third power supply unit VDD221 perpendicular to its own extension direction is between 45 micrometers and 55 micrometers, and may include, but is not limited to, endpoint values.

[0094] For example, the width of the fourth power supply unit VDD222 perpendicular to its own extension direction is between 350 micrometers and 450 micrometers, and may include, but is not limited to, endpoint values.

[0095] For example, the plurality of first power branches VDD1 extend from the display area 10 to the second bezel area 202 and are coupled to the third power section VDD221. The plurality of second conductive connections VDD223 are arranged along the second direction, and the second conductive connection VDD223 includes at least a portion extending along the first direction. At least a portion of the orthographic projection of the second conductive connection VDD223 on the substrate is located between the orthographic projection of the third power section VDD221 on the substrate and the orthographic projection of the fourth power section VDD222 on the substrate.

[0096] For example, the orthographic projection of the second conductive connection portion VDD223 on the substrate and the orthographic projection of the third power supply portion VDD221 on the substrate have an overlapping area, and the second conductive connection portion VDD223 is coupled to the third power supply portion VDD221 through a via (e.g., via Via8) in the overlapping area. The orthographic projection of the second conductive connection portion VDD223 on the substrate and the orthographic projection of the fourth power supply portion VDD222 on the substrate also have an overlapping area, and the second conductive connection portion VDD223 is coupled to the fourth power supply portion VDD222 through a via in the overlapping area.

[0097] For example, the second conductive connection portion VDD223 and the third power supply portion VDD221 are formed as an integral structure; and / or, the second conductive connection portion VDD223 and the fourth power supply portion VDD222 are formed as an integral structure.

[0098] For example, the number of the second conductive connection portions VDD223 is less than or equal to half the number of the first power branch VDD1, but is not limited thereto.

[0099] For example, the second conductive connection portion VDD223 is disposed in the same layer and with the same material as the second source / drain metal layer.

[0100] In the display substrate provided in the above embodiments, the third power supply unit VDD221 can be coupled to multiple first power supply branches VDD1 located in the display area 10, and the fourth power supply unit VDD222 can be coupled to the driving structure located at the edge of the display substrate. This effectively reduces the connection difficulty between the third power supply unit VDD221 and a large number of first power supply branches VDD1 in a high-resolution display substrate, and also reduces the connection difficulty between the fourth power supply unit VDD222 and the driving structure. Simultaneously, by connecting the third power supply unit VDD221 and the fourth power supply unit VDD222 through multiple second conductive connection parts VDD223 (fewer than the number of first power supply branches VDD1), not only is the layout difficulty of the first power bus VDD2 reduced, but the border size of the second border area 202 is also effectively reduced. Furthermore, in the display substrate provided in the above embodiments, by including the third power supply unit VDD221, the fourth power supply unit VDD222, and the multiple second conductive connection parts VDD223 in the first power bus VDD2, the loading of the first power bus VDD2 is effectively reduced.

[0101] In the display substrate provided in the above embodiments, the first power bus VDD2 has two power supply sections in both the first border area 201 and the second border area 202 of the display substrate, which effectively reduces the loading of the first power bus VDD2.

[0102] As shown in Figures 1 and 2, in some embodiments, the peripheral area 20 further includes a third border area 203 and a fourth border area 204 disposed opposite to each other, and the display area 10 is located between the third border area 203 and the fourth border area 204;

[0103] The first power bus VDD2 further includes: at least one third sub-power line VDD23, the third sub-power line VDD23 being located in the third border area 203 and / or the fourth border area 204, the third sub-power line VDD23 being coupled to at least two of the first power unit VDD211, the second power unit VDD212, the third power unit VDD221 and the fourth power unit VDD222.

[0104] As shown in Figure 4, the third sub-power line VDD23 is electrically connected to the second power supply section VDD212 via the sixth conductive connection portion VDD231. Exemplarily, the sixth conductive connection portion VDD231 has a comb-like structure, and it is disposed in the same layer and material as the second source / drain metal layer. The comb teeth of the sixth conductive connection portion VDD231 are coupled to the second power supply section VDD212 via vias. The handle portion of the sixth conductive connection portion VDD231 is coupled to the third sub-power line VDD23 via vias. Exemplarily, the third sub-power line VDD23 is disposed in the same layer and material as the first source / drain metal layer.

[0105] As shown in Figure 4, for example, the comb-like portion of the sixth conductive connection VDD231 has the same structure as the overlapping portion of the third sub-power line VDD23, meaning both can include multiple openings. This arrangement helps improve the current-side-following effect and also facilitates better heat dissipation. Similarly, the second power supply VDD212 can also have multiple openings. When the second power supply VDD212 includes a multi-layer structure, each layer can have multiple openings.

[0106] For example, the third border area 203 and the fourth border area 204 are arranged opposite to each other along the second direction, the third border area 203 includes a left border area, and the fourth border area 204 includes a right border area.

[0107] For example, the first power bus VDD2 includes two third sub-power lines VDD23, one of which is located in the third frame area 203 and the other is located in the fourth frame area 204. The third sub-power lines VDD23 are coupled to the first power unit VDD211, the second power unit VDD212, the third power unit VDD221 and the fourth power unit VDD222 respectively.

[0108] In the display substrate provided in the above embodiments, the first power bus VDD2 is configured to include the third sub-power line VDD23, so that the third sub-power line VDD23 can couple the first sub-power line VDD21 and the second sub-power line VDD22, thereby further reducing the loading of the first power bus VDD2.

[0109] In the display substrate provided in the above embodiments, the first power bus VDD2 is configured to include two third sub-power lines VDD23, which enables the first power bus VDD2 to form a ring structure. In this way, when the first power bus VDD2 malfunctions at a certain position, the first power signal can be provided from other directions, thereby improving the lighting yield of the display substrate.

[0110] As shown in Figures 1, 13 to 15, in some embodiments, the display substrate further includes:

[0111] Multiple data lines DATA, at least a portion of which are located in the display area 10;

[0112] Multiple first electrostatic discharge units ESD1 are located between the third power supply unit VDD221 and the fourth power supply unit VDD222. Each first electrostatic discharge unit ESD1 is coupled to the corresponding data line DATA and is used to perform electrostatic discharge on the data line DATA.

[0113] For example, the plurality of data lines DATA are arranged along the second direction, and the data lines DATA include at least a portion extending along the first direction. Each data line DATA is coupled to a corresponding column of sub-pixel driving circuits.

[0114] For example, the orthographic projection of the first electrostatic discharge unit ESD1 on the substrate is located between the orthographic projection of the third power supply unit VDD221 on the substrate and the orthographic projection of the fourth power supply unit VDD222 on the substrate.

[0115] In the display substrate provided in the above embodiments, by placing the first electrostatic discharge unit ESD1 between the third power supply unit VDD221 and the fourth power supply unit VDD222, the first electrostatic discharge unit ESD1 is located in the second border area 202, thereby avoiding the first electrostatic discharge unit ESD1 from occupying the layout space of the first border area 201, thereby effectively reducing the border width of the first border area 201 of the display substrate.

[0116] As shown in Figures 1, 13 to 15, in some embodiments, the display substrate further includes:

[0117] A first level signal line VGH and two second level signal lines VGL, wherein the first level signal line VGH is located between the two second level signal lines VGL, and both the first level signal line VGH and the second level signal lines VGL are located between the third power supply section VDD221 and the fourth power supply section VDD222;

[0118] The plurality of first electrostatic discharge units ESD1 are divided into two rows of first electrostatic discharge units ESD1. The first row of first electrostatic discharge units ESD1 is located between the first level signal line VGH and one of the second level signal lines VGL, and the second row of first electrostatic discharge units ESD1 is located between the first level signal line VGH and another second level signal line VGL.

[0119] The first electrostatic discharge unit ESD1 is coupled to its adjacent second level signal line VGL and first level signal line VGH. The first electrostatic discharge unit ESD1 is used to connect or disconnect the electrical connection between the data line and the first level signal line VGH under the control of the data line. The first electrostatic discharge unit ESD1 is also used to connect or disconnect the electrical connection between the data line and the second level signal line VGL under the control of the data line.

[0120] It should be noted that when there is a positive high charge on the data line, the positive high charge can be released to the first level signal line VGH, and when there is a negative high charge on the data line, the negative high charge can be released to VGL.

[0121] As shown in Figure 16, the first electrostatic discharge unit ESD1 includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4 connected as shown in Figure 16.

[0122] For example, the first level signal line VGH includes a high-level signal line, and the second level signal line VGL includes a low-level signal line. The first level signal line VGH includes at least a portion extending along the second direction. The second level signal line VGL includes at least a portion extending along the second direction.

[0123] For example, the plurality of first electrostatic discharge units ESD1 are divided into two rows of first electrostatic discharge units ESD1, and each row of first electrostatic discharge units ESD1 includes a plurality of first electrostatic discharge units ESD1 arranged along the second direction.

[0124] For example, the first level signal line VGH and the second level signal line VGL are disposed in the same layer and with the same material as the first gate metal layer.

[0125] For example, both the first level signal line VGH and the second level signal line VGL include a double-layer structure, wherein one layer is disposed in the same layer and with the same material as the first gate metal layer, and the other layer is disposed in the same layer and with the same material as the first source and drain metal layer.

[0126] In the display substrate provided in the above embodiments, by dividing the plurality of first electrostatic discharge units ESD1 into two rows of first electrostatic discharge units ESD1, the problem of limited layout space of high-resolution display substrates is effectively overcome.

[0127] In some embodiments, the data lines DATA coupled to the first row of first electrostatic discharge units ESD1 are alternately arranged with the data lines DATA coupled to the second row of first electrostatic discharge units ESD1.

[0128] For example, the first row of first electrostatic discharge unit ESD1 is coupled to an odd number of data lines DATA, and the second row of first electrostatic discharge unit ESD1 is coupled to an even number of data lines DATA; or, the first row of first electrostatic discharge unit ESD1 is coupled to an even number of data lines DATA, and the second row of first electrostatic discharge unit ESD1 is coupled to an odd number of data lines DATA.

[0129] The above configuration can reduce the difficulty of connecting the multiple data lines DATA with the multiple first electrostatic discharge units ESD1.

[0130] As shown in Figures 1, 2, and 8, in some embodiments, the display substrate further includes:

[0131] A cathode layer, at least a portion of which is located in the display area 10;

[0132] The second power bus VSS includes a fourth sub-power line VSS1 and a fifth sub-power line VSS2. The fourth sub-power line VSS1 is located in the first bezel area 201 and is located on the side of the second power supply section VDD212 away from the display area 10. The fifth sub-power line VSS2 is located in the second bezel area 202 and is located on the side of the fourth power supply section VDD212 away from the display area 10. The fourth sub-power line VSS1 and the fifth sub-power line VSS2 are respectively coupled to the cathode layer.

[0133] For example, the cathode layer can extend from the display area 10 to the peripheral area 20 to achieve coupling with the second power bus VSS. The cathode layer receives a second power signal provided by the second power bus VSS, which includes, but is not limited to, a negative power signal.

[0134] For example, the fourth sub-power line VSS1 includes at least a portion extending along the second direction. The fifth sub-power line VSS2 includes at least a portion extending along the second direction.

[0135] In the display substrate provided in the above embodiments, the second power bus VSS includes the fourth sub-power line VSS1 and the fifth sub-power line VSS2, which not only helps to reduce the loading of the second power bus VSS, but also helps to reduce the layout difficulty of the second power bus VSS.

[0136] As shown in Figures 1, 2, 3, 5, 6, 7, 9, 10, and 12, in some embodiments, the display substrate further includes:

[0137] Multiple data lines DATA, at least a portion of which are located in the display area 10;

[0138] At least two multiplexed lines MUX-L are located between the first power supply section VDD211 and the second power supply section VDD212;

[0139] The first multiplexer circuit MUX1 is located between the first power supply section VDD211 and the second power supply section VDD212. The first multiplexer circuit MUX1 is coupled to the multiple data lines DATA and the at least two multiplexer lines MUX-L.

[0140] As shown in Figure 5, Via1 and Via2 are vias that connect the first multiplexer circuit MUX1 to the multiplexing line MUX-L via signal lines.

[0141] For example, the orthographic projection of the first multiplexer circuit MUX1 on the substrate is located between the display area 10 and the orthographic projections of the at least two multiplexed lines MUX-L on the substrate, but is not limited thereto.

[0142] For example, the first multiplexer circuit MUX1 includes multiple first multiplexer units, which can be selected as 2-to-1, 4-to-1, 6-to-1, etc. Taking the 2-to-1 structure as an example, the first multiplexer unit includes two transistors. The control terminals of the two transistors are coupled one-to-one with two multiplexing lines MUX-L. The input terminals of the two transistors are coupled to the corresponding data lines DATA, and the output terminals of the two transistors are coupled together and connected to the same fan-out line FL. The multiplexing line MUX-L controls the on / off state of its coupled transistors.

[0143] In the display substrate provided in the above embodiments, the first multiplexer circuit MUX1 is located between the first power supply section VDD211 and the second power supply section VDD212. The first power supply section VDD211 and the second power supply section VDD212 are coupled together by a small number of first conductive connection sections VDD213, which reduces the layout difficulty of the first frame area 201.

[0144] As shown in Figures 1, 2, and 9, in some embodiments, the display substrate further includes:

[0145] A plurality of first driving units 31 are located on the side of the fourth sub-power line VSS1 away from the display area 10, and the plurality of first driving units 31 are respectively coupled to the second power supply section VDD212.

[0146] For example, the first driving unit 31 includes a chip-on-film (COF) film, but is not limited to this.

[0147] For example, the plurality of first drive units 31 are arranged at intervals along the second direction.

[0148] In the display substrate provided in the above embodiments, by setting the display substrate to include a plurality of first driving units 31, and the plurality of first driving units 31 being coupled to the second power supply unit VDD212 respectively, the first power signal can be uniformly written to the second power supply unit VDD212 at multiple points by the plurality of first driving units 31.

[0149] In the display substrate provided in the above embodiments, the multiple first driving units 31 are avoided from being directly coupled to the first power supply VDD211, which reduces the wiring difficulty and is conducive to achieving high-resolution display.

[0150] As shown in Figures 1, 2 and 9, in some embodiments, the first driving unit 31 includes two first ports, one of which is located at a first end of the first driving unit 31 and the other is located at a second end of the first driving unit 31; the first ports are coupled to the second power supply unit VDD212 through a third conductive connection portion VDD214.

[0151] For example, the first driving unit 31 includes multiple fan-out ports located between the two first ports, and the multiple fan-out ports are coupled to corresponding fan-out lines FL. For example, the multiple fan-out lines FL included in the display substrate can be divided into multiple groups of fan-out lines FL, each group of fan-out lines FL including multiple fan-out lines FL, and the multiple groups of fan-out lines FL correspond one-to-one with the multiple first driving units 31, and the fan-out ports in the first driving unit 31 are coupled to the corresponding fan-out lines FL in the corresponding group of fan-out lines FL.

[0152] The above configuration allows the first driving unit 31 to be coupled to the second power supply unit VDD212 via first ports located at both ends and third conductive connection portions VDD214 coupled to these ports. This enables the first power signal to be uniformly written to the second power supply unit VDD212 from multiple points by multiple first driving units 31. Furthermore, by positioning the two first ports at both ends of the first driving unit 31, the fan-out line FL coupled to the first driving unit 31 can be located between the two third conductive connection portions VDD214, effectively reducing the layout complexity of the first driving unit 31, the fan-out line FL, and the third conductive connection portions VDD214.

[0153] As shown in Figures 1, 2 and 9, in some embodiments, the first driving unit 31 further includes two second ports, one of which is located at the first end of the first driving unit 31 and the other is located at the second end of the first driving unit 31; the second ports are coupled to the fourth sub-power line VSS1 through the fourth conductive connection portion VSS3.

[0154] For example, in the same first driving unit 31, the two second ports are located between the two first ports, and the two fourth conductive connections VSS3 coupled to the two second ports are located between the two third conductive connections VDD214 coupled to the two first ports.

[0155] The above configuration allows the first driving unit 31 to be coupled to the fourth sub-power line VSS1 via second ports located at both ends and fourth conductive connection portions VSS3 coupled to these ports. This enables the second power signal to be uniformly written to the fourth sub-power line VSS1 from multiple points by the multiple first driving units 31. Furthermore, by placing the two second ports at both ends of the first driving unit 31, the fan-out line FL coupled to the first driving unit 31 can be located between the two fourth conductive connection portions VSS3, effectively reducing the layout complexity of the first driving unit 31, the fan-out line FL, and the fourth conductive connection portions VSS3.

[0156] As shown in Figures 1, 2 and 9, in some embodiments, the first driving unit 31 further includes two sets of third ports, one set of third ports being located at the first end of the first driving unit 31 and the other set of third ports being located at the second end of the first driving unit 31; each set of third ports includes at least two third ports, and the third ports are coupled to the corresponding multiplexed line MUX-L through the fifth conductive connection part MUX-D.

[0157] For example, the two first ports and the two second ports are all located between the two sets of third ports.

[0158] For example, the display substrate includes two multiplexed lines MUX-L, and each group of third ports includes two third ports, which are coupled one-to-one with the two multiplexed lines MUX-L.

[0159] For example, the third conductive connection VDD214 and the fourth conductive connection VSS3 are located between the two sets of fifth conductive connections MUX-D coupled to the two sets of third ports. It should be noted that all the fifth conductive connections MUX-D coupled to each set of third ports constitute a set of fifth conductive connections MUX-D.

[0160] The above configuration allows the first driving unit 31 to be coupled to the multiplexing line MUX-L via the third port located at both ends and the fifth conductive connection part MUX-D coupled to the port. This enables the multiplexed signal to be uniformly written to the multiplexing line MUX-L from multiple points by multiple first driving units 31, reducing the delay differences caused by signal loading differences at different locations. Moreover, by setting the third port at both ends of the first driving unit 31, the fan-out line FL coupled to the first driving unit 31 can be located between the two sets of fifth conductive connection parts MUX-D, effectively reducing the layout difficulty of the first driving unit 31, the fan-out line FL, and the fifth conductive connection part MUX-D.

[0161] As shown in Figures 1, 2, and 9, in some embodiments, the second port, the first port, and the third port are arranged sequentially along the direction from the center portion of the first driving unit 31 to the end of the first driving unit 31; the fourth conductive connection VSS3, the third conductive connection VDD214, and the fifth conductive connection MUX-D are arranged sequentially.

[0162] The above configuration effectively reduces the layout difficulty of the first drive unit 31, the fan-out line FL, and the conductive connection part.

[0163] As shown in Figures 1, 2, 9, 10 and 12, in some embodiments, in adjacent first drive units 31, the two closest third ports are coupled to the same multiplexed line MUX-L, and the fifth conductive connection MUX-D coupled to the two closest third ports is coupled to each other.

[0164] As shown in Figure 12, the fifth conductive connection part MUX-D includes a first part MUX-D1, a second part MUX-D2 and a third part MUX-D3. The first part adopts a single-layer structure, which is made of the same material as the second source and drain metal layer.

[0165] As shown in Figure 12, the second part adopts a three-layer structure with stacked layers. The first layer is made of the same material as the first gate metal layer, the second layer is made of the same material as the first source / drain metal layer, and the third layer is made of the same material as the second source / drain metal layer. The layers are electrically connected through vias.

[0166] As shown in Figure 12, the third part adopts a two-layer structure with stacked layers. The first layer is made of the same material as the first gate metal layer, and the second layer is made of the same material as the first source and drain metal layer. The layers are electrically connected through vias.

[0167] The above configuration not only reduces the loading of the multiplexing line MUX-L, but also reduces the layout difficulty of the fifth conductive connection part MUX-D.

[0168] As shown in Figure 1, in some embodiments, the display substrate further includes:

[0169] A plurality of second driving units 32 are located on the side of the fifth sub-power line VSS2 away from the display area 10. The second driving units 32 are coupled to at least one of the fourth power supply VDD222, the fifth sub-power line VSS2, the first level signal line VGH and the two second level signal lines VGL.

[0170] For example, the second drive unit 32 includes a flexible circuit board, but is not limited to this.

[0171] For example, the plurality of second drive units 32 are arranged at intervals along the second direction.

[0172] For example, among the plurality of second drive units 32, the second drive units 32 located at both ends are respectively coupled to the fourth power supply section VDD222, the fifth sub-power supply line VSS2, the first level signal line VGH and the two second level signal lines VGL.

[0173] For example, among the plurality of second drive units 32, at least the middle portion of the second drive unit 32 is coupled to the fourth power supply section VDD222 and the fifth sub-power supply line VSS2, respectively.

[0174] The above configuration enables the multiple second drive units 32 to uniformly write signals to their coupled signal lines at multiple points.

[0175] As shown in FIG1, in some embodiments, the display substrate further includes: a first gate metal layer, a second gate metal layer, a first source / drain metal layer and a second source / drain metal layer sequentially stacked on the substrate along a direction away from the substrate.

[0176] At least one of the first power supply unit VDD211, the second power supply unit VDD212, and the multiplexing line MUX-L is disposed in the same layer and with the same material as the first source / drain metal layer.

[0177] For example, the first power supply unit VDD211, the second power supply unit VDD212, and the multiplexing line MUX-L are all disposed in the same layer and with the same material as the first source-drain metal layer.

[0178] For example, the first gate metal layer and the second gate metal layer are generally made of Mo. The first source / drain metal layer and the second source / drain metal layer are generally formed into a stacked structure using low-resistivity metals, such as a Ti / Al / Ti stacked structure.

[0179] The above configuration allows at least one of the first power supply section VDD211, the second power supply section VDD212, and the multiplexing line MUX-L to be formed simultaneously with the first source / drain metal layer in the same patterning process, effectively reducing the manufacturing process of the display substrate and lowering the manufacturing cost of the display substrate.

[0180] The above configuration results in the first power supply unit VDD211, the second power supply unit VDD212, and the multiplexing line MUX-L having low impedance, which helps to reduce signal transmission delay.

[0181] In some embodiments, the first conductive connection portion VDD213 and the second source / drain metal layer are disposed in the same layer and with the same material.

[0182] The above configuration allows the first conductive connection portion VDD213 and the second source / drain metal layer to be formed simultaneously in the same patterning process, effectively reducing the manufacturing process of the display substrate and lowering the manufacturing cost of the display substrate.

[0183] Furthermore, the above-described configuration allows the first conductive connection VDD213 to better traverse the structure located between the first power supply VDD211 and the second power supply VDD212, preventing a short circuit between the first conductive connection VDD213 and the structure between the first power supply VDD211 and the second power supply VDD212. This configuration also results in the first conductive connection VDD213 having lower impedance, which helps reduce signal transmission delay.

[0184] In some embodiments, the fourth sub-power line VSS1 adopts a double-layer stacked structure, wherein the first layer of the double-layer stacked structure is disposed in the same layer and with the same material as the first gate metal layer, and the second layer of the double-layer stacked structure is disposed in the same layer and with the same material as the second source drain metal layer.

[0185] For example, the first layer of the fourth sub-power line VSS1 includes a plurality of power patterns arranged along the second direction, with adjacent power patterns coupled together by a conductive portion, which can be disposed in the same layer and material as the second gate metal layer. The second layer of the fourth sub-power line VSS1 can extend from the left side of the lower border area to the right side of the lower border area without interruption.

[0186] The above configuration allows the first layer of the fourth sub-power line VSS1 to be formed in the same patterning process as the first gate metal layer, and the second layer of the fourth sub-power line VSS1 to be formed in the same patterning process as the second source / drain metal layer, effectively reducing the manufacturing process of the display substrate and lowering the manufacturing cost of the display substrate.

[0187] The above configuration results in the fourth sub-power line VSS1 having a lower impedance, which helps to reduce signal transmission delay.

[0188] In some embodiments, the fourth sub-power line VSS1 may further include a third layer, which may be disposed on the same layer and made of the same material as the anode layer in the display substrate. This arrangement can further reduce the impedance of the fourth sub-power line VSS1, which is beneficial for reducing signal transmission delay.

[0189] In some embodiments, the fourth sub-power line VSS1 adopts a four-layer structure, wherein the first layer is disposed on the same layer and with the same material as the first gate metal layer, the second layer is disposed on the same layer and with the same material as the first source / drain metal layer, the third layer is disposed on the same layer and with the same material as the second source / drain metal layer, and the fourth layer is disposed on the same layer and with the same material as the anode layer in the display substrate. As shown in Figure 8, the via Via4 schematically illustrated in Figure 8 is a via that connects all four layers.

[0190] In some embodiments, at least one of the third power supply unit VDD221, the fourth power supply unit VDD222, and the fifth sub-power line VSS2 is disposed in the same layer and with the same material as the first source / drain metal layer.

[0191] For example, the third power supply unit VDD221, the fourth power supply unit VDD222, and the fifth sub-power line VSS2 are all disposed in the same layer and with the same material as the first source / drain metal layer.

[0192] The above configuration allows at least one of the third power supply section VDD221, the fourth power supply section VDD222, and the fifth sub-power line VSS2 to be formed in the same patterning process as the first source / drain metal layer, effectively reducing the fabrication process of the display substrate and lowering its manufacturing cost. This configuration also ensures that at least one of the third power supply section VDD221, the fourth power supply section VDD222, and the fifth sub-power line VSS2 has low impedance, which helps reduce signal transmission delay.

[0193] In some embodiments, at least one of the third power supply unit VDD221, the fourth power supply unit VDD222, and the fifth sub-power line VSS2 adopts a double-layer stacked structure, wherein the first layer of the double-layer stacked structure is disposed in the same layer and with the same material as the first source / drain metal layer, and the second layer of the double-layer stacked structure is disposed in the same layer and with the same material as the second source / drain metal layer.

[0194] The above configuration allows the first layer of the third power supply section VDD221, the fourth power supply section VDD222, and the fifth sub-power line VSS2 to be formed in the same patterning process as the first source / drain metal layer, and the second layer of the third power supply section VDD221, the fourth power supply section VDD222, and the fifth sub-power line VSS2 to be formed in the same patterning process as the second source / drain metal layer. This effectively reduces the manufacturing process of the display substrate and lowers the manufacturing cost of the display substrate.

[0195] The above configuration allows at least one of the third power supply section VDD221, the fourth power supply section VDD222, and the fifth sub-power supply line VSS2 to have a low impedance, which helps to reduce signal transmission delay.

[0196] In some embodiments, the fourth power supply unit VDD222 adopts a three-layer structure with stacked configurations. The first layer is made of the same material as the first gate metal layer, the second layer is made of the same material as the first source / drain metal layer, and the third layer is made of the same material as the second source / drain metal layer. Electrical connections between the layers in the three-layer structure are achieved through vias. Each layer in the three-layer structure may include an opening, which helps to improve the current gravitational effect.

[0197] As shown in Figures 9 to 11, both the third conductive connection VDD214 and the fourth conductive connection VSS3 can adopt a double-layer structure. One layer is made of the same material as the first gate metal layer, and the other layer is made of the same material as the first source / drain metal layer. The two layers are electrically connected through vias.

[0198] For example, the portion of the fourth conductive connection VSS3 that is disposed on the same layer as the first gate metal layer can be formed into an integral structure with the power pattern included in the fourth sub-power line VSS1.

[0199] As shown in Figures 2, 6, and 7, in some embodiments, the display substrate further includes: multiple fan-out lines FL, each fan-out line FL including a first fan-out portion F-L1 and a second fan-out portion F-L2. At least a portion of the orthographic projection of the first fan-out portion F-L1 onto the substrate is located between the orthographic projection of the second power supply VDD212 onto the substrate and the orthographic projection of the fourth sub-power line VSS1 onto the substrate. The orthographic projection of the second fan-out portion F-L2 onto the substrate is located on the side of the orthographic projection of the fourth sub-power line VSS1 onto the substrate that is away from the display area 10.

[0200] The first fan-out portion F-L1 is disposed in the same layer and material as the first gate metal layer or the second source / drain metal layer;

[0201] The second fan-out portion F-L2 is disposed in the same layer and with the same material as the first gate metal layer or the first source / drain metal layer.

[0202] For example, the first end of the first fan-out portion F-L1 is coupled to the multiplexer circuit, the second end of the first fan-out portion F-L1 is coupled to the first end of the second fan-out portion F-L2, and the second end of the second fan-out portion F-L2 is coupled to the corresponding first drive unit 31.

[0203] The aforementioned configuration, where the first fan-out portion F-L1 and the first gate metal layer are made of the same layer and material, allows them to be formed in the same patterning process. This effectively reduces the manufacturing process of the display substrate and lowers its production cost. Furthermore, it helps reduce scratches on the first fan-out portion F-L1 caused by subsequent manufacturing processes.

[0204] The above-mentioned configuration of the second fan-out portion F-L2 being disposed in the same layer and with the same material as the first gate metal layer or the first source / drain metal layer allows the second fan-out portion F-L2 to be formed in the same patterning process as the first gate metal layer or the first source / drain metal layer, effectively reducing the manufacturing process of the display substrate and reducing the manufacturing cost of the display substrate.

[0205] The above configuration helps to reduce the layout difficulty of the fan-out line (FL) and ensure the yield of the display substrate.

[0206] As shown in Figures 1 and 2, in some embodiments, the display substrate further includes:

[0207] A gate driving circuit, located in the third border region 203 and / or the fourth border region 204, the gate driving circuit including a plurality of shift register units (such as GOA1 to GOA9) arranged along a first direction.

[0208] A third driving unit 33, at least a portion of which is arranged with the gate driving circuit along the first direction, is coupled to the gate driving circuit.

[0209] For example, both the third border region 203 and the fourth border region 204 include the gate driving circuit, that is, both the third border region 203 and the fourth border region 204 include a plurality of shift register units arranged along the first direction.

[0210] For example, the third drive unit 33 includes a flexible circuit board, but is not limited to this.

[0211] For example, at least a portion of the third driving unit 33 is located at the lower left and lower right corners of the display substrate.

[0212] For example, the display substrate further includes a second multiplexer circuit MUX2, and the multiple frame start signal lines coupled to the multiple shift register units are coupled to the second multiplexer circuit MUX2. The second multiplexer circuit MUX2 can adopt a two-to-one structure, and the second multiplexer circuit MUX2 is coupled to the third driving unit 33.

[0213] For example, the display substrate further includes a second electrostatic discharge unit ESD2, which is located in the third frame area 203 and / or the fourth frame area 204. The second electrostatic discharge unit ESD2 is connected to a signal line (such as a clock signal line) coupled to the gate driving circuit and is used to perform electrostatic discharge on the signal line.

[0214] It should be noted that Figures 1 and 2 also illustrate a PLG, which represents multiple signal lines that can be used to transmit different signals. Figure 1 also illustrates the initialization signal line Vinit and the reference signal line Vref. As shown in Figure 11, the initialization signal line Vinit is electrically connected to the conductive pattern 40 through via Via6, and the conductive pattern 40 is coupled to the fan-out line corresponding to the initialization signal line Vinit through via Via7. The initialization signal line Vinit is disposed in the same layer and with the same material as the second source / drain metal layer, the conductive pattern is disposed in the same layer and with the same material as the first source / drain metal layer, and the fan-out line is disposed in the same layer and with the same material as the first gate metal layer.

[0215] The above configuration allows the gate driving circuit to receive the corresponding signal from the third driving unit 33, shortens the length of the signal line connecting the gate driving circuit and the third driving unit 33, and avoids the signal line from extending down the bezel area after turning the corner area, which is beneficial to reducing the bezel width of the display substrate.

[0216] As shown in Figures 1 and 2, in some embodiments, the third drive unit 33 is coupled to the third sub-power line VDD23.

[0217] The above configuration allows the first power signal to be provided from other directions when the first power bus VDD2 malfunctions at a certain location, thereby improving the lighting yield of the display substrate.

[0218] This disclosure also provides a display device, including the display substrate provided in the above embodiments.

[0219] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0220] In the display substrate provided in the above embodiments, the first power bus includes a first sub-power line, which includes a first power section and a second power section. The first power section is located near the display area, and the second power section is located near the edge of the display substrate. The first power section and the second power section are electrically connected through multiple first conductive connections. This arrangement allows the first power section to be coupled to multiple first power branches located in the display area, and the second power section to be coupled to the driving structure located at the edge of the display substrate. This effectively reduces the difficulty of connecting the first power section to a large number of first power branches in a high-resolution display substrate, as well as the difficulty of connecting the second power section to the driving structure. Furthermore, connecting the first power section and the second power section through multiple first conductive connections (fewer than the number of first power branches) not only reduces the layout difficulty of the first power bus but also effectively reduces the bezel size of the first bezel area. Moreover, in the display substrate provided in the above embodiments, by including the first power section, the second power section, and the multiple first conductive connections in the first power bus, the loading of the first power bus is effectively reduced.

[0221] The display device provided in this disclosure embodiment has the same beneficial effects as described above when including the display substrate, and will not be repeated here.

[0222] It should be noted that the signal line extending along the X direction means that the signal line includes a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along the X direction, and the length of the main part extending along the X direction is greater than the length of the secondary part extending in other directions.

[0223] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0224] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0225] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0226] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0227] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0228] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0229] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising a substrate, the substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a first border area and a second border area disposed opposite to each other, the display area being located between the first border area and the second border area; the display substrate further comprising: Multiple first power supply branches, at least a portion of which are located in the display area; A first power bus, the first power bus includes a first sub-power line, the first sub-power line is located in the first frame area, the first sub-power line includes a first power part and a second power part, the first power part is located between the display area and the second power part, the first power part is coupled to the plurality of first power branches respectively, the first power part and the second power part are coupled through a plurality of first conductive connections, the number of first conductive connections is less than the number of first power branches.

2. The display substrate according to claim 1, wherein, The first power bus includes a second sub-power line; The second sub-power line is located in the second frame area. The second sub-power line includes a third power section and a fourth power section. The third power section is located between the display area and the fourth power section. The third power section is coupled to the plurality of first power branches respectively. The third power section and the fourth power section are coupled through a plurality of second conductive connections. The number of second conductive connections is less than the number of first power branches.

3. The display substrate according to claim 2, wherein, The surrounding area also includes a third border area and a fourth border area that are disposed opposite to each other, and the display area is located between the third border area and the fourth border area; The first power bus further includes: at least one third sub-power line, the third sub-power line being located in the third frame area and / or the fourth frame area, the third sub-power line being coupled to at least two of the first power unit, the second power unit, the third power unit and the fourth power unit.

4. The display substrate according to claim 2, wherein, The display substrate further includes: Multiple data lines, at least a portion of which are located in the display area; A plurality of first electrostatic discharge units are located between the third power supply unit and the fourth power supply unit. Each first electrostatic discharge unit is coupled to a corresponding data line and is used to perform electrostatic discharge on the data line.

5. The display substrate according to claim 4, wherein, The display substrate further includes: A first level signal line and two second level signal lines, wherein the first level signal line is located between the two second level signal lines, and both the first level signal line and the second level signal line are located between the third power supply section and the fourth power supply section; The plurality of first electrostatic discharge units are divided into two rows of first electrostatic discharge units. The first row of first electrostatic discharge units is located between the first level signal line and one of the second level signal lines, and the second row of first electrostatic discharge units is located between the first level signal line and the other second level signal line. The first electrostatic discharge unit is coupled to its adjacent second-level signal line and first-level signal line respectively. The first electrostatic discharge unit is used to conduct or disconnect the electrical connection between the data line and the first-level signal line under the control of the data line. The first electrostatic discharge unit is also used to conduct or disconnect the electrical connection between the data line and the second-level signal line under the control of the data line.

6. The display substrate according to claim 5, wherein, The data lines coupled to the first electrostatic discharge unit in the first row and the data lines coupled to the first electrostatic discharge unit in the second row are alternately arranged.

7. The display substrate according to claim 5, wherein, The display substrate further includes: A cathode layer, at least a portion of which is located in the display area; The second power bus includes a fourth sub-power line and a fifth sub-power line; the fourth sub-power line is located in the first bezel area and on the side of the second power unit away from the display area; the fifth sub-power line is located in the second bezel area and on the side of the fourth power unit away from the display area; the fourth sub-power line and the fifth sub-power line are respectively coupled to the cathode layer.

8. The display substrate according to claim 7, wherein, The display substrate further includes: Multiple data lines, at least a portion of which are located in the display area; At least two multiplexing lines are located between the first power supply section and the second power supply section; A first multiplexer circuit is located between the first power supply section and the second power supply section, and the first multiplexer circuit is coupled to the plurality of data lines and the at least two multiplexed lines respectively.

9. The display substrate according to claim 8, wherein, The display substrate further includes: A plurality of first driving units are located on the side of the fourth sub-power line away from the display area, and the plurality of first driving units are respectively coupled to the second power supply unit.

10. The display substrate according to claim 9, wherein, The first driving unit includes two first ports, one of which is located at a first end of the first driving unit and the other is located at a second end of the first driving unit; the first ports are coupled to the second power supply unit through a third conductive connection portion.

11. The display substrate according to claim 10, wherein, The first driving unit further includes two second ports, one of which is located at the first end of the first driving unit and the other is located at the second end of the first driving unit; the second ports are coupled to the fourth sub-power line through the fourth conductive connection portion.

12. The display substrate according to claim 11, wherein, The first driving unit further includes two sets of third ports, one set of third ports being located at the first end of the first driving unit and the other set of third ports being located at the second end of the first driving unit; each set of third ports includes at least two third ports, and the third ports are coupled to the corresponding multiplexed lines through the fifth conductive connection portion.

13. The display substrate according to claim 12, wherein, Along the direction from the center of the first driving unit to the end of the first driving unit, the second port, the first port, and the third port are arranged in sequence; the fourth conductive connection portion, the third conductive connection portion, and the fifth conductive connection portion are arranged in sequence.

14. The display substrate according to claim 13, wherein, In adjacent first drive units, the two closest third ports are coupled to the same multiplexed line, and the fifth conductive connection portion coupled to the two closest third ports is coupled to each other.

15. The display substrate according to claim 8, wherein, The display substrate further includes: A plurality of second driving units are located on the side of the fifth sub-power line away from the display area. The second driving units are coupled to at least one of the fourth power supply unit, the fifth sub-power line, the first level signal line, and the two second level signal lines.

16. The display substrate according to claim 8, wherein, The display substrate further includes: a first gate metal layer, a second gate metal layer, a first source / drain metal layer and a second source / drain metal layer sequentially stacked on the substrate along a direction away from the substrate. At least one of the first power supply unit, the second power supply unit, and the multiplexing line is disposed in the same layer and with the same material as the first source / drain metal layer.

17. The display substrate according to claim 16, wherein, The first conductive connection portion is disposed in the same layer and made of the same material as the second source / drain metal layer.

18. The display substrate according to claim 16, wherein, The fourth sub-power line adopts a double-layer stacked structure. The first layer of the double-layer stacked structure is made of the same material as the first gate metal layer, and the second layer of the double-layer stacked structure is made of the same material as the second source and drain metal layers.

19. The display substrate according to claim 16, wherein, At least one of the third power supply unit, the fourth power supply unit, and the fifth sub-power line is disposed in the same layer and with the same material as the first source / drain metal layer.

20. The display substrate according to claim 16, wherein, At least one of the third power supply unit, the fourth power supply unit, and the fifth sub-power line adopts a double-layer stacked structure. The first layer of the double-layer stacked structure is made of the same material as the first source / drain metal layer, and the second layer of the double-layer stacked structure is made of the same material as the second source / drain metal layer.

21. The display substrate according to claim 16, wherein, The display substrate further includes: a plurality of fan-out lines, the fan-out lines including a first fan-out portion and a second fan-out portion, at least a portion of the orthographic projection of the first fan-out portion on the substrate is located between the orthographic projection of the second power supply on the substrate and the orthographic projection of the fourth sub-power line on the substrate; the orthographic projection of the second fan-out portion on the substrate is located on the side of the orthographic projection of the fourth sub-power line on the substrate away from the display area. The first fan-out portion is disposed in the same layer and material as the first gate metal layer or the second source / drain metal layer; The second fan-out portion is disposed in the same layer and with the same material as the first gate metal layer or the first source / drain metal layer.

22. The display substrate according to claim 3, wherein, The display substrate further includes: A gate driving circuit, the gate driving circuit being located in the third border region and / or the fourth border region, the gate driving circuit including a plurality of shift register units arranged along a first direction; A third driving unit, at least a portion of which is arranged with the gate driving circuit along the first direction, is coupled to the gate driving circuit.

23. The display substrate according to claim 22, wherein, The third drive unit is coupled to the third sub-power line.

24. A display device comprising a display substrate as claimed in any one of claims 1 to 23.

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