Pixel circuit, driving method, and display apparatus

Abstract

Provided in the present disclosure are a pixel circuit, a driving method, and a display apparatus. The pixel circuit comprises a driving circuit, a first on-off control circuit, a light-emitting element, a second on-off control circuit, a first control circuit and a second control circuit, wherein the first on-off control circuit controls the connection or disconnection between a second node and a third node under the control of the potential of a first control node; and the second on-off control circuit controls the connection or disconnection between a second electrode of the light-emitting element and a first voltage end thereof under the control of the potential of a second control node; the first control circuit controls the potential of the first control node according to a first time control data voltage under the control of a first control signal; and the second control circuit controls the potential of the second control node according to a second time control data voltage under the control of a second control signal. In the present disclosure, different grayscales are realized by mean of the cooperation of current adjustment and light-emission time adjustment.

Description

Pixel circuit, driving method and display device

[0001] Cross-reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202310611988.4, filed on May 26, 2023 in China, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit, a driving method and a display device. BACKGROUND

[0004] With the listing and promotion of Mini LED (Mini Light Emitting Diode) direct display products, Micro LED (Micro Light Emitting Diode) display technology is also imminent. The photoelectric characteristics of Micro LED and Mini LED are that the photoelectric conversion efficiency is high at high current density, the photoelectric conversion efficiency is low at low current density, and the brightness between LED chips is different at low current density, as well as the characteristics of color shift. As the size of LED decreases from Mini LED to Micro LED level, the proportion of photoelectric efficiency decline caused by defects in LED process will be amplified, resulting in very low efficiency of Micro LED. The low photoelectric efficiency of Micro LED and the problems of color and brightness at low current density result in that the pixel driving circuit used by Mini LED cannot be directly applied, and the corresponding pixel circuit needs to be developed according to the characteristics of Micro LED.

[0005] SUMMARY

[0006] In one aspect, the embodiments of the present disclosure provide a pixel circuit, comprising a driving circuit, a first on-off control circuit, a light emitting element, a second on-off control circuit, a first control circuit and a second control circuit;

[0007] A first end of the driving circuit is electrically connected with a first node, and a second end of the driving circuit is electrically connected with a second node; the driving circuit is configured to generate a driving current for driving the light emitting element under the control of a potential at a control end thereof;

[0008] The first on-off control circuit is configured to control the second node and a third node to be connected or disconnected under the control of a potential at the first control node;

[0009] A first pole of the light emitting element is electrically connected with the third node;

[0010] The second on-off control circuit is configured to control a second pole of the light emitting element and a first voltage end to be connected or disconnected under the control of a potential at the second control node;

[0011] The first control circuit is electrically connected with the first control terminal, the data line, the first light-emitting time control terminal, the second light-emitting time control terminal and the first control node respectively, and is used for controlling the first control node to be in communication with the first light-emitting time control terminal or the second light-emitting time control terminal under the control of a first control signal provided by the first control terminal and according to a first time control data voltage provided by the data line;

[0012] The second control circuit is electrically connected with the second control terminal, the data line, the second light-emitting time control terminal, the third light-emitting time control terminal and the second control node respectively, and is used for controlling the second control node to be in communication with the second light-emitting time control terminal or the third light-emitting time control terminal under the control of a second control signal provided by the second control terminal and according to a second time control data voltage provided by the data line.

[0013] Optionally, the first control circuit comprises a first write-in circuit, a first energy storage circuit, a first switch control circuit and a second switch control circuit.

[0014] The first write-in circuit is electrically connected with the first control terminal, the data line and a first switch node respectively, and is used for writing the first time control data voltage into the first switch node under the control of a first control signal provided by the first control terminal.

[0015] The first energy storage circuit is electrically connected with the first switch node, and is used for maintaining the potential of the first switch node.

[0016] The first switch control circuit is electrically connected with the first switch node, the second light-emitting time control terminal and the first control node respectively, and is used for controlling the first control node to be in communication with or disconnected from the second light-emitting time control terminal under the control of the potential of the first switch node.

[0017] The second switch control circuit is electrically connected with the first switch node, the first light-emitting time control terminal and the first control node respectively, and is used for controlling the first control node to be in communication with or disconnected from the first light-emitting time control terminal under the control of the potential of the first switch node.

[0018] Optionally, the second control circuit comprises a second write-in circuit, a second energy storage circuit, a third switch control circuit and a fourth switch control circuit.

[0019] The second write-in circuit is electrically connected with the second control terminal, the data line and a second switch node respectively, and is used for writing the second time control data voltage provided by the data line into the second switch node under the control of a second control signal provided by the second control terminal.

[0020] The second energy storage circuit is electrically connected with the second switch node, for maintaining the potential of the second switch node;

[0021] The third switch control circuit is electrically connected with the second switch node, the third light-emitting time control end and the second control node respectively, for controlling the second control node and the third light-emitting time control end to be connected or disconnected under the control of the potential of the second switch node;

[0022] The fourth switch control circuit is electrically connected with the second switch node, the second light-emitting time control end and the second control node respectively, for controlling the second control node and the second light-emitting time control end to be connected or disconnected under the control of the potential of the second switch node.

[0023] Optionally, the first control circuit comprises a third write-in circuit, a fourth write-in circuit, a fifth switch control circuit, a sixth switch control circuit, a third energy storage circuit and a fourth energy storage circuit; the first control end comprises a first reset control end and a second reset control end;

[0024] The third write-in circuit is electrically connected with the first reset control end, the data line and the third switch node respectively, for writing the third time control data voltage provided by the data line into the third switch node under the control of the first reset control signal provided by the first reset control end;

[0025] The third energy storage circuit is electrically connected with the third switch node, for maintaining the potential of the third switch node;

[0026] The fourth write-in circuit is electrically connected with the second reset control end, the data line and the fourth switch node respectively, for writing the fourth time control data voltage provided by the data line into the fourth switch node under the control of the second reset control signal provided by the second reset control end;

[0027] The fourth energy storage circuit is electrically connected with the fourth switch node, for maintaining the potential of the fourth switch node;

[0028] The fifth switch control circuit is electrically connected with the third switch node, the second light-emitting time control end and the first control node respectively, for controlling the second light-emitting time control end and the first control node to be connected or disconnected under the control of the potential of the third switch node;

[0029] The sixth switch control circuit is electrically connected with the fourth switch node, the first light-emitting time control end and the first control node respectively, and is used for controlling the first light-emitting time control end and the first control node to be in communication or disconnected under the control of the potential of the fourth switch node.

[0030] Optionally, the second control circuit comprises a fifth write-in circuit, a sixth write-in circuit, a seventh switch control circuit, an eighth switch control circuit, a fifth energy storage circuit and a sixth energy storage circuit; and the second control end comprises a third reset control end and a fourth reset control end.

[0031] The fifth write-in circuit is electrically connected with the third reset control end, the data line and a fifth switch node respectively, and is used for writing fifth time control data voltage provided by the data line into the fifth switch node under the control of a third reset control signal provided by the third reset control end.

[0032] The fifth energy storage circuit is electrically connected with the fifth switch node, and is used for maintaining the potential of the fifth switch node.

[0033] The sixth write-in circuit is electrically connected with the fourth reset control end, the data line and a sixth switch node respectively, and is used for writing sixth time control data voltage provided by the data line into the sixth switch node under the control of a fourth reset control signal provided by the fourth reset control end.

[0034] The sixth energy storage circuit is electrically connected with the sixth switch node, and is used for maintaining the potential of the sixth switch node.

[0035] The seventh switch control circuit is electrically connected with the fifth switch node, a second light-emitting time control end and a second control node respectively, and is used for controlling the second light-emitting time control end and the second control node to be in communication or disconnected under the control of the potential of the fifth switch node.

[0036] The eighth switch control circuit is electrically connected with the sixth switch node, a third light-emitting time control end and a second control node respectively, and is used for controlling the third light-emitting time control end and the second control node to be in communication or disconnected under the control of the potential of the sixth switch node.

[0037] Optionally, the driving circuit comprises a driving transistor.

[0038] The gate of the driving transistor is electrically connected with the control end of the driving circuit, the first pole of the driving circuit is electrically connected with the first node, and the second pole of the driving circuit is electrically connected with the second node.

[0039] The first on-off control circuit comprises a first control transistor, and the second on-off control circuit comprises a second control transistor;

[0040] The gate of the first control transistor is electrically connected with the first control node, the first pole of the first control transistor is electrically connected with the second node, and the second pole of the first control transistor is electrically connected with the third node;

[0041] The gate of the second control transistor is electrically connected with the second control node, the first pole of the second control transistor is electrically connected with the second pole of the light-emitting element, and the second pole of the second control transistor is electrically connected with the first voltage terminal.

[0042] Optionally, the first write-in circuit comprises a first transistor, the first energy storage circuit comprises a first capacitor, the first switch control circuit comprises a second transistor, and the second switch control circuit comprises a third transistor;

[0043] The gate of the first transistor is electrically connected with the first control terminal, the first pole of the first transistor is electrically connected with the data line, and the second pole of the first transistor is electrically connected with a first switch node;

[0044] The first end of the first capacitor is electrically connected with the first switch node, and the second end of the first capacitor is electrically connected with an initial voltage terminal;

[0045] The gate of the second transistor is electrically connected with the first switch node, the first pole of the second transistor is electrically connected with the second light-emitting time control terminal, and the second pole of the second transistor is electrically connected with the first control node;

[0046] The gate of the third transistor is electrically connected with the first switch node, the first pole of the third transistor is electrically connected with the first light-emitting time control terminal, and the second pole of the third transistor is electrically connected with the first control node.

[0047] Optionally, the second write-in circuit comprises a fourth transistor, the second energy storage circuit comprises a second capacitor, the third switch control circuit comprises a fifth transistor, and the fourth switch control circuit comprises a sixth transistor;

[0048] The gate of the fourth transistor is electrically connected with the second control terminal, the first pole of the fourth transistor is electrically connected with the data line, and the second pole of the fourth transistor is electrically connected with a second switch node;

[0049] The first end of the second capacitor is electrically connected with the second switch node, and the second end of the second capacitor is electrically connected with an initial voltage terminal;

[0050] The gate of the fifth transistor is electrically connected with the second switch node, the first pole of the fifth transistor is electrically connected with the second light-emitting time control end, and the second pole of the fifth transistor is electrically connected with the second control node;

[0051] The gate of the sixth transistor is electrically connected with the second switch node, the first pole of the sixth transistor is electrically connected with the second light-emitting time control end, and the second pole of the sixth transistor is electrically connected with the second control node.

[0052] Optionally, the third write circuit comprises a seventh transistor, the fourth write circuit comprises an eighth transistor, the third energy storage circuit comprises a third capacitor, the fourth energy storage circuit comprises a fourth capacitor, the fifth switch control circuit comprises a ninth transistor, and the sixth switch control circuit comprises a tenth transistor;

[0053] The gate of the seventh transistor is electrically connected with the first reset control end, the first pole of the seventh transistor is electrically connected with the data line, and the second pole of the seventh transistor is electrically connected with the third switch node;

[0054] The first end of the third capacitor is electrically connected with the third switch node, and the second end of the third capacitor is electrically connected with an initial voltage end;

[0055] The gate of the eighth transistor is electrically connected with the second reset control end, the first pole of the eighth transistor is electrically connected with the data line, and the second pole of the eighth transistor is electrically connected with the fourth switch node;

[0056] The first end of the fourth capacitor is electrically connected with the fourth switch node, and the second end of the fourth capacitor is electrically connected with the initial voltage end;

[0057] The gate of the ninth transistor is electrically connected with the third switch node, the first pole of the ninth transistor is electrically connected with the second light-emitting time control end, and the second pole of the ninth transistor is electrically connected with the first control node;

[0058] The gate of the tenth transistor is electrically connected with the fourth switch node, the first pole of the tenth transistor is electrically connected with the first light-emitting time control end, and the second pole of the tenth transistor is electrically connected with the first control node.

[0059] Optionally, the fifth write circuit comprises an eleventh transistor, the sixth write circuit comprises a twelfth transistor, the seventh switch control circuit comprises a thirteenth transistor, the eighth switch control circuit comprises a fourteenth transistor, the fifth energy storage circuit comprises a fifth capacitor, and the sixth energy storage circuit comprises a sixth capacitor;

[0060] The gate of the eleventh transistor is electrically connected with the third reset control end, the first pole of the eleventh transistor is electrically connected with the data line, and the second pole of the eleventh transistor is electrically connected with the fifth switch node.

[0061] The first end of the fifth capacitor is electrically connected with the fifth switch node, and the second end of the fifth capacitor is electrically connected with an initial voltage end.

[0062] The gate of the twelfth transistor is electrically connected with the fourth reset control end, the first pole of the twelfth transistor is electrically connected with the data line, and the second pole of the twelfth transistor is electrically connected with the sixth switch node.

[0063] The first end of the sixth capacitor is electrically connected with the sixth switch node, and the second end of the sixth capacitor is electrically connected with the initial voltage end.

[0064] The gate of the thirteenth transistor is electrically connected with the fifth switch node, the first pole of the thirteenth transistor is electrically connected with the second light-emitting time control end, and the second pole of the thirteenth transistor is electrically connected with the second control node.

[0065] The gate of the fourteenth transistor is electrically connected with the sixth switch node, the first pole of the fourteenth transistor is electrically connected with the third light-emitting time control end, and the second pole of the fourteenth transistor is electrically connected with the second control node.

[0066] Optionally, the pixel circuit further comprises a data writing circuit, a compensation control circuit and a seventh energy storage circuit.

[0067] The data writing circuit is electrically connected with a scan line, the data line and the first node respectively, and is configured to write a current control data voltage provided by the data line to the first node under control of a scan signal provided by the scan line.

[0068] The compensation control circuit is electrically connected with the scan line, a control end of the driving circuit and the second node respectively, and is configured to control the control end of the driving circuit and the second node to be connected or disconnected under control of the scan signal.

[0069] The seventh energy storage circuit is electrically connected with the control end of the driving circuit, and is configured to store electric energy.

[0070] Optionally, the pixel circuit further comprises a first initialization circuit and a second initialization circuit.

[0071] The first initialization circuit is electrically connected with the first control end, the initial voltage end and the control end of the driving circuit respectively, and is used for writing the initial voltage provided by the initial voltage end into the control end of the driving circuit under the control of a first control signal provided by the first control end.

[0072] The second initialization circuit is electrically connected with the first control end, the initial voltage end and the first electrode of the light-emitting element respectively, and is used for writing the initial voltage into the first electrode of the light-emitting element under the control of the first control signal.

[0073] Optionally, the pixel circuit further comprises a light-emitting control circuit.

[0074] The light-emitting control circuit is electrically connected with a second light-emitting time control end, a power voltage end and the first node respectively, and is used for controlling the power voltage end to be in communication with the first node under the control of a second light-emitting time control signal provided by the second light-emitting time control end.

[0075] Optionally, the first control end comprises a first reset control end and a second reset control end.

[0076] The pixel circuit further comprises a first initialization circuit and a second initialization circuit.

[0077] The first initialization circuit is electrically connected with the first reset control end, the initial voltage end and the control end of the driving circuit respectively, and is used for writing the initial voltage provided by the initial voltage end into the control end of the driving circuit under the control of a first reset control signal provided by the first reset control end.

[0078] The second initialization circuit is electrically connected with the first reset control end, the initial voltage end and the first electrode of the light-emitting element respectively, and is used for writing the initial voltage into the first electrode of the light-emitting element under the control of the first reset control signal.

[0079] Optionally, the pixel circuit further comprises a compensation control circuit, a data writing circuit and an eighth energy storage circuit; the first node is electrically connected with a power voltage end.

[0080] The first end of the eighth energy storage circuit is electrically connected with the control end of the driving circuit; and the eighth energy storage circuit is used for storing electric energy.

[0081] The compensation control circuit is electrically connected with a scanning line, the control end of the driving circuit and a second node respectively, and is used for controlling the control end of the driving circuit to be in communication or disconnection with the second node under the control of a scanning signal provided by the scanning line.

[0082] The data writing circuit is electrically connected with the scan line, the data line and the second end of the eighth energy storage circuit respectively, and is used for writing a current control data voltage provided by the data line into the second end of the eighth energy storage circuit under the control of the scan signal.

[0083] Optionally, the pixel circuit further comprises a reference voltage writing circuit.

[0084] The reference voltage writing circuit is electrically connected with the first control end, the second light-emitting time control end, the reference voltage end and the second end of the eighth energy storage circuit respectively, and is used for writing a reference voltage provided by the reference voltage end into the second end of the eighth energy storage circuit under the control of a first control signal provided by the first control end, and writing the reference voltage into the second end of the eighth energy storage circuit under the control of a second light-emitting time control signal provided by the second light-emitting time control end.

[0085] Optionally, the data writing circuit comprises a fifteenth transistor, the compensation control circuit comprises a sixteenth transistor, and the seventh energy storage circuit comprises a first storage capacitor.

[0086] The gate of the fifteenth transistor is electrically connected with the scan line, the first pole of the fifteenth transistor is electrically connected with the data line, and the second pole of the fifteenth transistor is electrically connected with the first node.

[0087] The gate of the sixteenth transistor is electrically connected with the scan line, the first pole of the sixteenth transistor is electrically connected with the control end of the driving circuit, and the second pole of the sixteenth transistor is electrically connected with the second node.

[0088] The first end of the first storage capacitor is electrically connected with the control end of the driving circuit, and the second end of the first storage capacitor is electrically connected with a power voltage end.

[0089] Optionally, the first initialization circuit comprises a seventeenth transistor, and the second initialization circuit comprises an eighteenth transistor.

[0090] The gate of the seventeenth transistor is electrically connected with the first control end, the first pole of the seventeenth transistor is electrically connected with the initial voltage end, and the second pole of the seventeenth transistor is electrically connected with the control end of the driving circuit.

[0091] The gate of the eighteenth transistor is electrically connected with the first control end, the first pole of the eighteenth transistor is electrically connected with the initial voltage end, and the second pole of the eighteenth transistor is electrically connected with the first pole of the light-emitting element.

[0092] Optionally, the light-emitting control circuit comprises a nineteenth transistor.

[0093] A gate of the nineteenth transistor is electrically connected with the second light-emitting time control end, a first pole of the nineteenth transistor is electrically connected with the power voltage end, and a second pole of the nineteenth transistor is electrically connected with the first node.

[0094] Optionally, the first initialization circuit comprises a seventeenth transistor, and the second initialization circuit comprises an eighteenth transistor.

[0095] A gate of the seventeenth transistor is electrically connected with the first reset control end, a first pole of the seventeenth transistor is electrically connected with the initial voltage end, and a second pole of the seventeenth transistor is electrically connected with the control end of the driving circuit.

[0096] A gate of the eighteenth transistor is electrically connected with the first reset control end, a first pole of the eighteenth transistor is electrically connected with the initial voltage end, and a second pole of the eighteenth transistor is electrically connected with the first pole of the light-emitting element.

[0097] Optionally, the compensation control circuit comprises a sixteenth transistor, the data writing circuit comprises a fifteenth transistor, and the eighth energy storage circuit comprises a second storage capacitor.

[0098] A first end of the second storage capacitor is electrically connected with the control end of the driving circuit.

[0099] A gate of the sixteenth transistor is electrically connected with the scanning line, a first pole of the sixteenth transistor is electrically connected with the control end of the driving circuit, and a second pole of the sixteenth transistor is electrically connected with the second node.

[0100] A gate of the fifteenth transistor is electrically connected with the scanning line, a first pole of the fifteenth transistor is electrically connected with the data line, and a second pole of the fifteenth transistor is electrically connected with a second end of the second storage capacitor.

[0101] Optionally, the reference voltage writing circuit comprises a nineteenth transistor and a twentieth transistor.

[0102] A gate of the nineteenth transistor is electrically connected with the first control end, a first pole of the nineteenth transistor is electrically connected with the reference voltage end, and a second pole of the nineteenth transistor is electrically connected with the second end of the eighth energy storage circuit.

[0103] A gate of the twentieth transistor is electrically connected with the second light-emitting time control end, a first pole of the twentieth transistor is electrically connected with the reference voltage end, and a second pole of the twentieth transistor is electrically connected with the second end of the eighth energy storage circuit.

[0104] In a second aspect, the present disclosure provides a driving method applied to the pixel circuit, and the driving method comprises:

[0105] The driving circuit generates a driving current for driving the light emitting element under the control of the potential at the control end thereof;

[0106] The first on-off control circuit controls the communication or disconnection between the second node and the third node under the control of the potential at the first control node;

[0107] The second on-off control circuit controls the communication or disconnection between the second electrode of the light emitting element and the first voltage terminal under the control of the potential at the second control node;

[0108] The first control circuit controls the communication between the first light emitting time control end or the second light emitting time control end and the first control node under the control of the first control signal and according to the first time control data voltage provided by the data line;

[0109] The second control circuit controls the communication between the second light emitting time control end or the third light emitting time control end and the second control node under the control of the second control signal and according to the second time control data voltage provided by the data line.

[0110] In a third aspect, the present disclosure provides a display device comprising the pixel circuit. BRIEF DESCRIPTION OF DRAWINGS

[0111] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0112] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0113] FIG. 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0114] FIG. 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0115] FIG. 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0116] FIG. 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0117] FIG. 7 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0118] FIG. 8 is a timing diagram of the operation of the pixel circuit according to at least one embodiment of the present disclosure;

[0119] FIG. 9A is a schematic diagram of the working state of the pixel circuit according to at least one embodiment of the present disclosure in a first stage;

[0120] FIG. 9B is a schematic diagram of an operating state of at least one embodiment of the pixel circuit shown in FIG. 7 in a second stage;

[0121] FIG. 9C is a schematic diagram of an operating state of at least one embodiment of the pixel circuit shown in FIG. 7 in a third stage;

[0122] FIG. 9D is a schematic diagram of an operating state of at least one embodiment of the pixel circuit shown in FIG. 7 in a fourth stage;

[0123] FIG. 9E is a schematic diagram of an operating state of at least one embodiment of the pixel circuit shown in FIG. 7 in a fifth stage;

[0124] FIG. 10 is a timing diagram of an operation of at least one embodiment of the pixel circuit shown in FIG. 7;

[0125] FIG. 11 is a timing diagram of an operation of at least one embodiment of the pixel circuit shown in FIG. 7;

[0126] FIG. 12 is a timing diagram of an operation of at least one embodiment of the pixel circuit shown in FIG. 7;

[0127] FIG. 13 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0128] FIG. 14 is a timing diagram of an operation of at least one embodiment of the pixel circuit shown in FIG. 13;

[0129] FIG. 15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0130] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present disclosure.

[0131] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two poles of the transistor other than the gate, one of the poles is referred to as the first pole and the other is referred to as the second pole.

[0132] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole can be a drain and the second pole can be a source, or the first pole can be a source and the second pole can be a drain.

[0133] The pixel driving circuit of the Micro LED according to the present disclosure can realize high-quality Micro LED display devices with lossless gamma, and can realize high gray scale, low gray scale, medium gray scale, and even super low gray scale through the pixel driving circuit and the matching time sequence.

[0134] The Gamma 2.2 curve is a gray scale curve that is more suitable for the human eye. However, due to the intrinsic defects of the TFT (Thin Film Transistor) device or the defects of the light-emitting device, the OLED (Organic Light Emitting Diode) display panel or the LED display panel cannot fit the Gamma 2.2 curve at low gray scale or super low gray scale. The lossless gamma can realize that all points of 8bit (bit, 8bit is 256 gray scale) or 10bit (1024 gray scale) are on the Gamma 2.2 curve through the cooperation of several light-emitting time lengths.

[0135] In at least one embodiment of the present disclosure, when there are 256 gray scales, L128 to L255 can be medium-high gray scales, L0 to L127 can be medium-low gray scales, L16 or below can be super low gray scales, and low gray scales can be L17 to L127, wherein L128 is gray scale 128, L255 is gray scale 255, L0 is gray scale 0, L127 is gray scale 127, and L17 is gray scale 17.

[0136] However, the present disclosure is not limited thereto.

[0137] The pixel circuit described in the embodiments of the present disclosure realizes different gray scales through the cooperation of current regulation and light-emitting time regulation, and realizes medium-high gray scales, medium-low gray scales, low gray scales, and super low gray scales through different light-emitting currents and the duty cycles of the light-emitting time control signals provided by the light-emitting time control terminals.

[0138] As shown in FIG. 1, the pixel circuit described in at least one embodiment of the present disclosure includes a driving circuit 10, a first on-off control circuit 11, a light-emitting element EL, a second on-off control circuit 12, a first control circuit 13, and a second control circuit 14.

[0139] The first end of the driving circuit 10 is electrically connected with a first node N1, and the second end of the driving circuit 10 is electrically connected with a second node N2. The driving circuit 10 is used to generate a driving current for driving the light-emitting element EL under the control of the potential at the control terminal thereof.

[0140] The first on-off control circuit 11 is electrically connected with a first control node NC1, the second node N2, and a third node N3, respectively, and is used to control the communication or disconnection between the second node N2 and the third node N3 under the control of the potential at the first control node NC1.

[0141] The first pole of the light-emitting element EL is electrically connected with the third node N3.

[0142] The second on-off control circuit 12 is electrically connected with the second control node NC2, the second electrode of the light emitting element EL and the first voltage terminal V1 respectively, for controlling the communication or disconnection between the second electrode of the light emitting element EL and the first voltage terminal V1 under the control of the potential of the second control node NC2;

[0143] The first control circuit 13 is electrically connected with the first control terminal R1, the data line DL, the first light emitting time control terminal HF, the second light emitting time control terminal EML and the first control node NC1 respectively, for controlling the communication between the first light emitting time control terminal HF or the second light emitting time control terminal EML and the first control node NC1 under the control of the first control signal provided by the first control terminal R1 according to the first time control data voltage provided by the data line DL.

[0144] The second control circuit 14 is electrically connected with the second control terminal SL, the data line DL, the second light emitting time control terminal EML, the third light emitting time control terminal EMS and the second control node NC2 respectively, for controlling the communication between the second light emitting time control terminal EML or the third light emitting time control terminal EMS and the second control node NC2 under the control of the second control signal provided by the second control terminal SL according to the second time control data voltage provided by the data line DL.

[0145] Optionally, the first voltage terminal can be a low voltage terminal, but is not limited thereto.

[0146] At least one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure, when in operation, the display period can include a first stage, a second stage and a third stage arranged in sequence;

[0147] In the first stage, under the control of the first control signal provided by the first control terminal R1, the first control circuit 13 controls the communication between the first light emitting time control terminal HF or the second light emitting time control terminal EML and the first control node NC1 according to the first time control data voltage provided by the data line DL.

[0148] When displaying an ultra-low gray scale, the first control circuit 13 can control the communication between the first light emitting time control terminal HF and the first control node NC1.

[0149] When displaying a medium-high gray scale and a medium-low gray scale, the first control circuit 13 can control the communication between the second light emitting time control terminal EML and the first control node NC1.

[0150] The first control circuit 13 can control the first light emitting time control end HF to be in communication with the first control node NC1 when displaying a low gray scale;

[0151] The first light emitting time control end HF is configured to provide a first light emitting time control signal, and the second light emitting time control end EML is configured to provide a second light emitting time control signal.

[0152] The second stage is a compensation stage and a data voltage writing time for controlling a light emitting current.

[0153] In the third stage, the second control circuit 14 controls the second light emitting time control end EML or the third light emitting time control end EMS to be in communication with the second control node NC2 under the control of the second control signal according to a second time control data voltage provided by the data line DL.

[0154] The second control circuit 14 controls the third light emitting time control end EMS to be in communication with the second control node NC2 when displaying an ultra-low gray scale.

[0155] The second control circuit 14 controls the second light emitting time control end EML to be in communication with the second control node NC2 when displaying a medium-high gray scale.

[0156] The second control circuit 14 controls the third light emitting time control end EMS to be in communication with the second control node NC2 when displaying a medium-low gray scale.

[0157] The second control circuit 14 controls the third light emitting time control end EMS to be in communication with the second control node NC2 when displaying a low gray scale.

[0158] The third light emitting time control end EMS is configured to provide a third light emitting time control signal.

[0159] In a specific implementation, when the transistor included in the first on-off control circuit 11 is a p-type transistor and the transistor included in the second on-off control circuit 12 is a p-type transistor, the duty cycle of the first light emitting time control signal provided by the first light emitting time control end HF is greater than the duty cycle of the third light emitting time control signal provided by the third light emitting time control end EMS, and the duty cycle of the third light emitting time control signal is greater than the duty cycle of the second light emitting time control signal provided by the second light emitting time control end EML.

[0160] When the transistor included in the first on-off control circuit 11 is an n-type transistor and the transistor included in the second on-off control circuit 12 is an n-type transistor, the duty ratio of the first light emission time control signal provided by the first light emission time control terminal HF is less than the duty ratio of the third light emission time control signal provided by the third light emission time control terminal EMS, and the duty ratio of the third light emission time control signal is less than the duty ratio of the second light emission time control signal provided by the second light emission time control terminal EML.

[0161] However, the application is not limited thereto.

[0162] In at least one embodiment of the present disclosure, the first control circuit includes a first write circuit, a first energy storage circuit, a first switch control circuit, and a second switch control circuit.

[0163] The first write circuit is electrically connected with the first control terminal, the data line, and the first switch node respectively, and is configured to write the first time control data voltage into the first switch node under the control of the first control signal provided by the first control terminal.

[0164] The first energy storage circuit is electrically connected with the first switch node, and is configured to maintain the potential of the first switch node.

[0165] The first switch control circuit is electrically connected with the first switch node, the second light emission time control terminal, and the first control node respectively, and is configured to control the first control node and the second light emission time control terminal to be connected or disconnected under the control of the potential of the first switch node.

[0166] The second switch control circuit is electrically connected with the first switch node, the first light emission time control terminal, and the first control node respectively, and is configured to control the first control node and the first light emission time control terminal to be connected or disconnected under the control of the potential of the first switch node.

[0167] In specific implementation, the first control circuit can include a first write circuit, a first energy storage circuit, a first switch control circuit, and a second switch control circuit. The first write circuit writes the first time control data voltage into the first switch node under the control of the first control signal. The first energy storage circuit maintains the potential of the first switch node. The first switch control circuit controls the first control node and the second light emission time control terminal to be connected or disconnected under the control of the potential of the first switch node. The second switch control circuit controls the first control node and the first light emission time control terminal to be connected or disconnected under the control of the potential of the first switch node.

[0168] In at least one embodiment of the present disclosure, the second control circuit comprises a second write circuit, a second energy storage circuit, a third switch control circuit and a fourth switch control circuit;

[0169] The second write circuit is electrically connected with the second control end, the data line and the second switch node respectively, and is configured to write a second time control data voltage provided by the data line into the second switch node under control of a second control signal provided by the second control end;

[0170] The second energy storage circuit is electrically connected with the second switch node, and is configured to maintain the potential of the second switch node;

[0171] The third switch control circuit is electrically connected with the second switch node, the third light-emitting time control end and the second control node respectively, and is configured to control the second control node and the third light-emitting time control end to be in communication or disconnected under control of the potential of the second switch node;

[0172] The fourth switch control circuit is electrically connected with the second switch node, the second light-emitting time control end and the second control node respectively, and is configured to control the second control node and the second light-emitting time control end to be in communication or disconnected under control of the potential of the second switch node.

[0173] In a specific implementation, the second control circuit can comprise a second write circuit, a second energy storage circuit, a third switch control circuit and a fourth switch control circuit; the second write circuit writes a second time control data voltage into the second switch node under control of a second control signal; the second energy storage circuit maintains the potential of the second switch node; the third switch control circuit controls the second control node and the third light-emitting time control end to be in communication or disconnected under control of the potential of the second switch node; and the fourth switch control circuit controls the second control node and the second light-emitting time control end to be in communication or disconnected under control of the potential of the second switch node.

[0174] As shown in FIG. 2, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the first control circuit comprises a first write circuit 21, a first energy storage circuit 22, a first switch control circuit 23 and a second switch control circuit 24;

[0175] The first write circuit 21 is electrically connected with a first control end R1, the data line DL and a first switch node NK1 respectively, and is configured to write a first time control data voltage provided by the data line DL into the first switch node NK1 under control of a first control signal provided by the first control end R1;

[0176] The first energy storage circuit 22 is electrically connected with the first switch node NK1, and is configured to maintain the potential of the first switch node NK1;

[0177] The first switch control circuit 23 is electrically connected with the first switch node NK1, the second light-emitting time control terminal EML and the first control node NC1 respectively, and is configured to control the first control node NC1 to be connected or disconnected with the second light-emitting time control terminal EML under the control of the potential of the first switch node NK1;

[0178] The second switch control circuit 24 is electrically connected with the first switch node NK1, the first light-emitting time control terminal HF and the first control node NC1 respectively, and is configured to control the first control node NC1 to be connected or disconnected with the first light-emitting time control terminal HF under the control of the potential of the first switch node NK1;

[0179] The second control circuit includes a second write circuit 25, a second energy storage circuit 26, a third switch control circuit 27 and a fourth switch control circuit 28;

[0180] The second write circuit 25 is electrically connected with a second control terminal SL, the data line DL and a second switch node NK2 respectively, and is configured to write the second time control data voltage provided by the data line DL into the second switch node NK2 under the control of the second control signal provided by the second control terminal SL;

[0181] The second energy storage circuit 26 is electrically connected with the second switch node NK2, and is configured to maintain the potential of the second switch node NK2;

[0182] The third switch control circuit 27 is electrically connected with the second switch node NK2, a third light-emitting time control terminal EMS and the second control node NC2 respectively, and is configured to control the second control node NC2 to be connected or disconnected with the third light-emitting time control terminal EMS under the control of the potential of the second switch node NK2;

[0183] The fourth switch control circuit 28 is electrically connected with the second switch node NK2, the second light-emitting time control terminal EML and the second control node NC2 respectively, and is configured to control the second control node NC2 to be connected or disconnected with the second light-emitting time control terminal EML under the control of the potential of the second switch node NK2.

[0184] At least one embodiment of the pixel circuit shown in FIG. 2 of the present disclosure works in a display period including a first stage, a second stage and a third stage arranged in sequence;

[0185] In the first stage, the first write circuit 21 writes the first time control data voltage provided by the data line DL into the first switch node NK1 under the control of the first control signal provided;

[0186] In the display of the ultra-low gray scale, the second switch control circuit 24 controls the communication between the first control node NC1 and the first light-emitting time control end HF under the control of the potential of the first switch node NK1;

[0187] In the display of the medium-high gray scale, the first switch control circuit 23 controls the communication between the first control node NC1 and the second light-emitting time control end EML under the control of the potential of the first switch node NK1;

[0188] In the display of the medium-low gray scale, the first switch control circuit 23 controls the communication between the first control node NC1 and the second light-emitting time control end EML under the control of the potential of the first switch node NK1;

[0189] In the display of the low gray scale, the second switch control circuit 24 controls the communication between the first control node NC1 and the first light-emitting time control end HF under the control of the potential of the first switch node NK1;

[0190] In the third stage, the second write circuit 25 writes the second time control data voltage provided by the data line DL into the second switch node NK2 under the control of the second control signal provided by the second control end SL;

[0191] In the display of the ultra-low gray scale, the third switch control circuit 27 controls the communication between the second control node NC2 and the third light-emitting time control end EMS under the control of the potential of the second switch node NK2;

[0192] In the display of the medium-high gray scale, the fourth switch control circuit 28 controls the communication between the second control node NC2 and the second light-emitting time control end EML under the control of the potential of the second switch node NK2;

[0193] In the display of the medium-low gray scale, the third switch control circuit 27 controls the communication between the second control node NC2 and the third light-emitting time control end EMS under the control of the potential of the second switch node NK2;

[0194] In the display of the low gray scale, the third switch control circuit 27 controls the communication between the second control node NC2 and the third light-emitting time control end EMS under the control of the potential of the second switch node NK2.

[0195] In at least one embodiment of the present disclosure, the first control circuit comprises a third write-in circuit, a fourth write-in circuit, a fifth switch control circuit, a sixth switch control circuit, a third energy storage circuit and a fourth energy storage circuit; the first control terminal comprises a first reset control terminal and a second reset control terminal;

[0196] The third write-in circuit is electrically connected with the first reset control terminal, the data line and a third switch node respectively, and is used for writing a third time control data voltage provided by the data line into the third switch node under the control of a first reset control signal provided by the first reset control terminal;

[0197] The third energy storage circuit is electrically connected with the third switch node, and is used for maintaining the potential of the third switch node;

[0198] The fourth write-in circuit is electrically connected with the second reset control terminal, the data line and a fourth switch node respectively, and is used for writing a fourth time control data voltage provided by the data line into the fourth switch node under the control of a second reset control signal provided by the second reset control terminal;

[0199] The fourth energy storage circuit is electrically connected with the fourth switch node, and is used for maintaining the potential of the fourth switch node;

[0200] The fifth switch control circuit is electrically connected with the third switch node, a second light-emitting time control terminal and the first control node respectively, and is used for controlling the second light-emitting time control terminal and the first control node to be connected or disconnected under the control of the potential of the third switch node;

[0201] The sixth switch control circuit is electrically connected with the fourth switch node, a first light-emitting time control terminal and the first control node respectively, and is used for controlling the first light-emitting time control terminal and the first control node to be connected or disconnected under the control of the potential of the fourth switch node.

[0202] In a specific implementation, the first control circuit can include a third write-in circuit, a fourth write-in circuit, a fifth switch control circuit, a sixth switch control circuit, a third energy storage circuit, and a fourth energy storage circuit; the first control end includes a first reset control end and a second reset control end; the third write-in circuit writes a third time control data voltage into the third switch node under control of a first reset control signal; the third energy storage circuit maintains the potential of the third switch node; the fourth write-in circuit writes a fourth time control data voltage into the fourth switch node under control of a second reset control signal; the fourth energy storage circuit maintains the potential of the fourth switch node; the fifth switch control circuit controls the communication or disconnection between the second light-emitting time control end and the first control node under control of the potential of the third switch node; and the sixth switch control circuit controls the communication or disconnection between the first light-emitting time control end and the first control node under control of the potential of the fourth switch node.

[0203] In at least one embodiment of the present disclosure, the second control circuit includes a fifth write-in circuit, a sixth write-in circuit, a seventh switch control circuit, an eighth switch control circuit, a fifth energy storage circuit, and a sixth energy storage circuit; the second control end includes a third reset control end and a fourth reset control end;

[0204] The fifth write-in circuit is electrically connected with the third reset control end, the data line, and a fifth switch node respectively, and is configured to write a fifth time control data voltage provided by the data line into the fifth switch node under control of a third reset control signal provided by the third reset control end;

[0205] The fifth energy storage circuit is electrically connected with the fifth switch node, and is configured to maintain the potential of the fifth switch node;

[0206] The sixth write-in circuit is electrically connected with the fourth reset control end, the data line, and a sixth switch node respectively, and is configured to write a sixth time control data voltage provided by the data line into the sixth switch node under control of a fourth reset control signal provided by the fourth reset control end;

[0207] The sixth energy storage circuit is electrically connected with the sixth switch node, and is configured to maintain the potential of the sixth switch node;

[0208] The seventh switch control circuit is electrically connected with the fifth switch node, a second light-emitting time control end, and a second control node respectively, and is configured to control the communication or disconnection between the second light-emitting time control end and the second control node under control of the potential of the fifth switch node;

[0209] The eighth switch control circuit is electrically connected with the sixth switch node, the third light-emitting time control end and the second control node respectively, and is used for controlling the second control node and the third light-emitting time control end to be connected or disconnected under the control of the potential of the sixth switch node.

[0210] In a specific implementation, the second control circuit can include a fifth write-in circuit, a sixth write-in circuit, a seventh switch control circuit, an eighth switch control circuit, a fifth energy storage circuit and a sixth energy storage circuit; the second control end includes a third reset control end and a fourth reset control end; the fifth write-in circuit writes a fifth time control data voltage into the fifth switch node under the control of a third reset control signal; the fifth energy storage circuit maintains the potential of the fifth switch node; the sixth write-in circuit writes a sixth time control data voltage into the sixth switch node under the control of a fourth reset control signal; the sixth energy storage circuit maintains the potential of the sixth switch node; the seventh switch control circuit controls the second control node and the second light-emitting time control end to be connected or disconnected under the control of the potential of the fifth switch node; and the eighth switch control circuit controls the second control node and the third light-emitting time control end to be connected or disconnected under the control of the potential of the sixth switch node.

[0211] As shown in FIG. 3, based on at least one embodiment of the pixel circuit shown in FIG. 1, the first control circuit includes a third write-in circuit 31, a fourth write-in circuit 32, a fifth switch control circuit 33, a sixth switch control circuit 34, a third energy storage circuit 35 and a fourth energy storage circuit 36; the first control end includes a first reset control end RA and a second reset control end RB;

[0212] The third write-in circuit 31 is electrically connected with the first reset control end RA, the data line DL and a third switch node NK3 respectively, and is used for writing a third time control data voltage provided by the data line DL into the third switch node NK3 under the control of a first reset control signal provided by the first reset control end RA;

[0213] The third energy storage circuit 35 is electrically connected with the third switch node NK3, and is used for maintaining the potential of the third switch node NK3;

[0214] The fourth write-in circuit 32 is electrically connected with the second reset control end RB, the data line DL and a fourth switch node NK4 respectively, and is used for writing a fourth time control data voltage provided by the data line DL into the fourth switch node NK4 under the control of a second reset control signal provided by the second reset control end RB;

[0215] The fourth energy storage circuit 36 is electrically connected with the fourth switch node NK4, and is configured to maintain the potential of the fourth switch node NK4;

[0216] The fifth switch control circuit 33 is electrically connected with the third switch node NK3, the second light-emitting time control terminal EML and the first control node NC1 respectively, and is configured to control the communication or disconnection between the second light-emitting time control terminal EML and the first control node NC1 under the control of the potential of the third switch node NK3;

[0217] The sixth switch control circuit 34 is electrically connected with the fourth switch node NK4, the first light-emitting time control terminal HF and the first control node NC1 respectively, and is configured to control the communication or disconnection between the first light-emitting time control terminal HF and the first control node NC1 under the control of the potential of the fourth switch node NK4;

[0218] The second control circuit comprises a fifth write-in circuit 37, a sixth write-in circuit 38, a seventh switch control circuit 39, an eighth switch control circuit 310, a fifth energy storage circuit 311 and a sixth energy storage circuit 312; and the second control terminal comprises a third reset control terminal RC and a fourth reset control terminal RD.

[0219] The fifth write-in circuit 37 is electrically connected with the third reset control terminal RC, the data line DL and a fifth switch node NK5 respectively, and is configured to write a fifth time control data voltage provided by the data line DL into the fifth switch node NK5 under the control of a third reset control signal provided by the third reset control terminal RC;

[0220] The fifth energy storage circuit 311 is electrically connected with the fifth switch node NK5, and is configured to maintain the potential of the fifth switch node NK5;

[0221] The sixth write-in circuit 38 is electrically connected with the fourth reset control terminal RD, the data line DL and a sixth switch node NK6 respectively, and is configured to write a sixth time control data voltage provided by the data line DL into the sixth switch node NK6 under the control of a fourth reset control signal provided by the fourth reset control terminal RD;

[0222] The sixth energy storage circuit 312 is electrically connected with the sixth switch node NK6, and is configured to maintain the potential of the sixth switch node NK6;

[0223] The seventh switch control circuit 39 is electrically connected with the fifth switch node NK5, the second light-emitting time control end EML and the second control node NC2 respectively, and is used for controlling the second light-emitting time control end EML and the second control node NC2 to be connected or disconnected under the control of the potential of the fifth switch node NK5.

[0224] The eighth switch control circuit 310 is electrically connected with the sixth switch node NK6, the third light-emitting time control end EMS and the second control node NC2 respectively, and is used for controlling the third light-emitting time control end EMS and the second control node NC2 to be connected or disconnected under the control of the potential of the sixth switch node NK6.

[0225] At least one embodiment of the pixel circuit shown in FIG. 3 of the present disclosure works in the display period, which can include a first stage, a second stage and a third stage arranged in sequence.

[0226] In the first stage, the third write circuit 31 writes the third time control data voltage provided by the data line DL into the third switch node NK3 under the control of the first reset control signal provided by the first reset control end RA; the third energy storage circuit 35 maintains the potential of the third switch node NK3; the fourth write circuit 32 writes the fourth time control data voltage provided by the data line DL into the fourth switch node NK4 under the control of the second reset control signal provided by the second reset control end RB; and the fourth energy storage circuit 36 maintains the potential of the fourth switch node NK4.

[0227] When displaying ultra-low gray scale and low gray scale, the sixth switch control circuit 34 controls the first light-emitting time control end HF and the first control node NC1 to be connected under the control of the potential of the fourth switch node NK4.

[0228] When displaying medium-high gray scale and medium-low gray scale, the fifth switch control circuit 33 controls the second light-emitting time control end EML and the first control node NC1 to be connected under the control of the potential of the third switch node NK3.

[0229] In the third stage, the fifth write circuit 37 writes the fifth time control data voltage provided by the data line DL into the fifth switch node NK5 under the control of the third reset control signal provided by the third reset control end RC; the fifth energy storage circuit 311 maintains the potential of the fifth switch node NK5; the sixth write circuit 38 writes the sixth time control data voltage provided by the data line DL into the sixth switch node NK6 under the control of the fourth reset control signal provided by the fourth reset control end RD; and the sixth energy storage circuit 312 maintains the potential of the sixth switch node NK6.

[0230] The eighth switch control circuit 310 controls the third light-emitting time control end EMS to be in communication or disconnected with the second control node NC2 under the control of the potential of the sixth switch node NK6 when displaying ultra-low gray scale, medium-low gray scale and low gray scale;

[0231] The seventh switch control circuit 39 controls the second light-emitting time control end EML to be in communication with the second control node NC2 under the control of the potential of the fifth switch node NK5 when displaying medium-high gray scale.

[0232] Optionally, the first write-in circuit includes a first transistor, the first energy storage circuit includes a first capacitor, the first switch control circuit includes a second transistor, and the second switch control circuit includes a third transistor.

[0233] The gate of the first transistor is electrically connected with the first control end, the first pole of the first transistor is electrically connected with the data line, and the second pole of the first transistor is electrically connected with the first switch node.

[0234] The first end of the first capacitor is electrically connected with the first switch node, and the second end of the first capacitor is electrically connected with an initial voltage end.

[0235] The gate of the second transistor is electrically connected with the first switch node, the first pole of the second transistor is electrically connected with the second light-emitting time control end, and the second pole of the second transistor is electrically connected with the first control node.

[0236] The gate of the third transistor is electrically connected with the first switch node, the first pole of the third transistor is electrically connected with the first light-emitting time control end, and the second pole of the third transistor is electrically connected with the first control node.

[0237] Optionally, the second write-in circuit includes a fourth transistor, the second energy storage circuit includes a second capacitor, the third switch control circuit includes a fifth transistor, and the fourth switch control circuit includes a sixth transistor.

[0238] The gate of the fourth transistor is electrically connected with the second control end, the first pole of the fourth transistor is electrically connected with the data line, and the second pole of the fourth transistor is electrically connected with the second switch node.

[0239] The first end of the second capacitor is electrically connected with the second switch node, and the second end of the second capacitor is electrically connected with an initial voltage end.

[0240] The gate of the fifth transistor is electrically connected with the second switch node, the first pole of the fifth transistor is electrically connected with the second light-emitting time control end, and the second pole of the fifth transistor is electrically connected with the second control node;

[0241] The gate of the sixth transistor is electrically connected with the second switch node, the first pole of the sixth transistor is electrically connected with the second light-emitting time control end, and the second pole of the sixth transistor is electrically connected with the second control node.

[0242] Optionally, the third write circuit comprises a seventh transistor, the fourth write circuit comprises an eighth transistor, the third energy storage circuit comprises a third capacitor, the fourth energy storage circuit comprises a fourth capacitor, the fifth switch control circuit comprises a ninth transistor, and the sixth switch control circuit comprises a tenth transistor;

[0243] The gate of the seventh transistor is electrically connected with the first reset control end, the first pole of the seventh transistor is electrically connected with the data line, and the second pole of the seventh transistor is electrically connected with the third switch node;

[0244] The first end of the third capacitor is electrically connected with the third switch node, and the second end of the third capacitor is electrically connected with an initial voltage end;

[0245] The gate of the eighth transistor is electrically connected with the second reset control end, the first pole of the eighth transistor is electrically connected with the data line, and the second pole of the eighth transistor is electrically connected with the fourth switch node;

[0246] The first end of the fourth capacitor is electrically connected with the fourth switch node, and the second end of the fourth capacitor is electrically connected with the initial voltage end;

[0247] The gate of the ninth transistor is electrically connected with the third switch node, the first pole of the ninth transistor is electrically connected with the second light-emitting time control end, and the second pole of the ninth transistor is electrically connected with the first control node;

[0248] The gate of the tenth transistor is electrically connected with the fourth switch node, the first pole of the tenth transistor is electrically connected with the first light-emitting time control end, and the second pole of the tenth transistor is electrically connected with the first control node.

[0249] Optionally, the fifth write circuit comprises an eleventh transistor, the sixth write circuit comprises a twelfth transistor, the seventh switch control circuit comprises a thirteenth transistor, the eighth switch control circuit comprises a fourteenth transistor, the fifth energy storage circuit comprises a fifth capacitor, and the sixth energy storage circuit comprises a sixth capacitor;

[0250] The gate of the eleventh transistor is electrically connected with the third reset control end, the first pole of the eleventh transistor is electrically connected with the data line, and the second pole of the eleventh transistor is electrically connected with the fifth switch node.

[0251] The first end of the fifth capacitor is electrically connected with the fifth switch node, and the second end of the fifth capacitor is electrically connected with an initial voltage end.

[0252] The gate of the twelfth transistor is electrically connected with the fourth reset control end, the first pole of the twelfth transistor is electrically connected with the data line, and the second pole of the twelfth transistor is electrically connected with the sixth switch node.

[0253] The first end of the sixth capacitor is electrically connected with the sixth switch node, and the second end of the sixth capacitor is electrically connected with the initial voltage end.

[0254] The gate of the thirteenth transistor is electrically connected with the fifth switch node, the first pole of the thirteenth transistor is electrically connected with the second light-emitting time control end, and the second pole of the thirteenth transistor is electrically connected with the second control node.

[0255] The gate of the fourteenth transistor is electrically connected with the sixth switch node, the first pole of the fourteenth transistor is electrically connected with the third light-emitting time control end, and the second pole of the fourteenth transistor is electrically connected with the second control node.

[0256] The pixel circuit provided in at least one embodiment of the present disclosure further comprises a data writing circuit, a compensation control circuit and a seventh energy storage circuit.

[0257] The data writing circuit is electrically connected with a scanning line, the data line and the first node respectively, and is configured to write a current control data voltage provided by the data line into the first node under the control of a scanning signal provided by the scanning line.

[0258] The compensation control circuit is electrically connected with the scanning line, a control end of the driving circuit and the second node respectively, and is configured to control the control end of the driving circuit and the second node to be in communication or disconnected under the control of the scanning signal.

[0259] The seventh energy storage circuit is electrically connected with the control end of the driving circuit, and is configured to store electric energy.

[0260] In a specific implementation, the pixel circuit can further comprise a data writing circuit, a compensation control circuit and a seventh energy storage circuit. The data writing circuit writes a current control data voltage provided by the data line into the first node under the control of a scanning signal. The compensation control circuit controls the control end of the driving circuit and the second node to be in communication or disconnected under the control of the scanning signal.

[0261] The pixel circuit in at least one embodiment of the present disclosure further comprises a first initialization circuit and a second initialization circuit.

[0262] The first initialization circuit is electrically connected with the first control terminal, the initial voltage terminal and the control terminal of the driving circuit respectively, and is configured to write the initial voltage provided by the initial voltage terminal to the control terminal of the driving circuit under the control of the first control signal provided by the first control terminal.

[0263] The second initialization circuit is electrically connected with the first control terminal, the initial voltage terminal and the first electrode of the light-emitting element respectively, and is configured to write the initial voltage to the first electrode of the light-emitting element under the control of the first control signal.

[0264] In specific implementation, the pixel circuit can further comprise a first initialization circuit and a second initialization circuit; the first initialization circuit writes the initial voltage provided by the initial voltage terminal to the control terminal of the driving circuit under the control of the first control signal, so as to initialize the potential of the control terminal of the driving circuit; and the second initialization circuit writes the initial voltage to the first electrode of the light-emitting element under the control of the first control signal, so as to initialize the potential of the first electrode of the light-emitting element.

[0265] The pixel circuit in at least one embodiment of the present disclosure further comprises a light-emitting control circuit.

[0266] The light-emitting control circuit is electrically connected with the second light-emitting time control terminal, the power supply voltage terminal and the first node respectively, and is configured to control the power supply voltage terminal and the first node to be connected or disconnected under the control of the second light-emitting time control signal provided by the second light-emitting time control terminal.

[0267] In specific implementation, the pixel circuit can further comprise a light-emitting control circuit, which is configured to control the power supply voltage terminal and the first node to be connected or disconnected under the control of the second light-emitting time control signal provided by the second light-emitting time control terminal, so as to perform light-emitting control.

[0268] As shown in FIG. 4, on the basis of at least one embodiment of the pixel circuit shown in FIG. 2, the pixel circuit in at least one embodiment of the present disclosure can further comprise a data writing circuit 41, a compensation control circuit 42 and a seventh energy storage circuit 43.

[0269] The data writing circuit 41 is electrically connected with a scan line GL, the data line DL and the first node N1 respectively, and is configured to write the current control data voltage provided by the data line DL to the first node N1 under the control of the scan signal provided by the scan line GL.

[0270] The compensation control circuit 42 is electrically connected with the scan line GL, the control end of the driving circuit 10 and the second node N2 respectively, for controlling the connection or disconnection between the control end of the driving circuit 10 and the second node N2 under the control of the scan signal;

[0271] The seventh energy storage circuit 43 is electrically connected with the control end of the driving circuit 10, for storing energy;

[0272] The pixel circuit in at least one embodiment of the present disclosure can further include a first initialization circuit 44 and a second initialization circuit 45;

[0273] The first initialization circuit 44 is electrically connected with the first control end R1, the initial voltage end I1 and the control end of the driving circuit 10 respectively, for writing the initial voltage Vinit provided by the initial voltage end I1 into the control end of the driving circuit 10 under the control of the first control signal provided by the first control end R1;

[0274] The second initialization circuit 45 is electrically connected with the first control end R1, the initial voltage end I1 and the first electrode of the light emitting element EL respectively, for writing the initial voltage Vinit into the first electrode of the light emitting element EL under the control of the first control signal;

[0275] The pixel circuit in at least one embodiment of the present disclosure can further include a light emitting control circuit 46;

[0276] The light emitting control circuit 46 is electrically connected with the second light emitting time control end EML, the power voltage end ELVDD and the first node N1 respectively, for controlling the connection or disconnection between the power voltage end ELVDD and the first node N1 under the control of the second light emitting time control signal provided by the second light emitting time control end EML.

[0277] In at least one embodiment of the pixel circuit shown in FIG. 4 of the present disclosure, the display period can include a first stage and a second stage arranged in sequence;

[0278] In the first stage, the first initialization circuit 44 writes the initial voltage Vinit provided by the initial voltage end I1 into the control end of the driving circuit 10 under the control of the first control signal provided by the first control end R1, so that the driving circuit 10 can turn on the connection between its first end and second end at the beginning of the second stage; the second initialization circuit 45 writes the initial voltage Vinit into the first electrode of the light emitting element EL under the control of the first control signal, to control the light emitting element EL not to emit light and clear the residual charge in the first electrode of the light emitting element EL;

[0279] In the second stage, the data writing circuit 41 writes the current control data voltage Vdata provided by the data line DL into the first node N1 under the control of the scanning signal provided by the scanning line GL; the compensation control circuit 42 controls the communication between the control end of the driving circuit 10 and the second node N2 under the control of the scanning signal;

[0280] At the beginning of the second stage, the driving circuit 10 turns on the connection between the first node N1 and the second node N2 to charge the seventh energy storage circuit 43 by the current control data voltage Vdata, so as to raise the potential of the control end of the driving circuit 10, until the potential of the control end of the driving circuit 10 becomes Vdata+Vth, Vth is the threshold voltage of the driving transistor included in the driving circuit 10, the driving circuit 10 turns off the connection between the first node N1 and the second node N2 to stop charging, so as to perform threshold voltage compensation.

[0281] In at least one embodiment of the present disclosure, the first control end includes a first reset control end and a second reset control end;

[0282] The pixel circuit further includes a first initialization circuit and a second initialization circuit;

[0283] The first initialization circuit is electrically connected with the first reset control end, the initial voltage end and the control end of the driving circuit respectively, and is configured to write the initial voltage provided by the initial voltage end into the control end of the driving circuit under the control of the first reset control signal provided by the first reset control end;

[0284] The second initialization circuit is electrically connected with the first reset control end, the initial voltage end and the first pole of the light emitting element respectively, and is configured to write the initial voltage into the first pole of the light emitting element under the control of the first reset control signal.

[0285] As shown in FIG. 5, on the basis of at least one embodiment of the pixel circuit shown in FIG. 3, the pixel circuit in at least one embodiment of the present disclosure can further include a data writing circuit 41, a compensation control circuit 42 and a seventh energy storage circuit 43;

[0286] The data writing circuit 41 is electrically connected with the scanning line GL, the data line DL and the first node N1 respectively, and is configured to write the current control data voltage provided by the data line DL into the first node N1 under the control of the scanning signal provided by the scanning line GL;

[0287] The compensation control circuit 42 is electrically connected with the scan line GL, the control end of the driving circuit 10 and the second node N2 respectively, and is configured to control the control end of the driving circuit 10 and the second node N2 to be connected or disconnected under the control of the scan signal.

[0288] The seventh energy storage circuit 43 is electrically connected with the control end of the driving circuit 10, and is configured to store electric energy.

[0289] The pixel circuit in at least one embodiment of the present disclosure can further include a first initialization circuit 44 and a second initialization circuit 45.

[0290] The first initialization circuit 44 is electrically connected with the first reset control end RA, the initial voltage end I1 and the control end of the driving circuit 10 respectively, and is configured to write the initial voltage Vinit provided by the initial voltage end I1 into the control end of the driving circuit 10 under the control of the first reset control signal provided by the first reset control end RA.

[0291] The second initialization circuit 45 is electrically connected with the first reset control end RA, the initial voltage end I1 and the first electrode of the light emitting element EL respectively, and is configured to write the initial voltage Vinit into the first electrode of the light emitting element EL under the control of the first reset control signal.

[0292] The pixel circuit in at least one embodiment of the present disclosure can further include a light emitting control circuit 46.

[0293] The light emitting control circuit 46 is electrically connected with the second light emitting time control end EML, the power voltage end ELVDD and the first node N1 respectively, and is configured to control the power voltage end ELVDD and the first node N1 to be connected or disconnected under the control of the second light emitting time control signal provided by the second light emitting time control end EML.

[0294] In at least one embodiment of the pixel circuit shown in FIG. 5 of the present disclosure, the display period can include a first stage and a second stage arranged in sequence.

[0295] In the first stage, the first initialization circuit 44 writes the initial voltage Vinit provided by the initial voltage end I1 into the control end of the driving circuit 10 under the control of the first reset control signal, so that the driving circuit 10 can turn on the connection between the first end and the second end at the beginning of the second stage; the second initialization circuit 45 writes the initial voltage Vinit into the first electrode of the light emitting element EL under the control of the first reset control signal, so as to control the light emitting element EL not to emit light and clear the residual charge in the first electrode of the light emitting element EL;

[0296] In the second stage, the data writing circuit 41 writes the current control data voltage Vdata provided by the data line DL into the first node N1 under the control of the scanning signal provided by the scanning line GL; the compensation control circuit 42 controls the communication between the control end of the driving circuit 10 and the second node N2 under the control of the scanning signal;

[0297] At the beginning of the second stage, the driving circuit 10 turns on the connection between the first node N1 and the second node N2 to charge the seventh energy storage circuit 43 by the current control data voltage Vdata, so as to raise the potential of the control end of the driving circuit 10, until the potential of the control end of the driving circuit 10 becomes Vdata+Vth, Vth is the threshold voltage of the driving transistor included in the driving circuit 10, the driving circuit 10 turns off the connection between the first node N1 and the second node N2 to stop charging, so as to perform threshold voltage compensation.

[0298] The pixel circuit provided in at least one embodiment of the present disclosure further comprises a compensation control circuit, a data writing circuit and an eighth energy storage circuit; the first node is electrically connected with a power voltage end;

[0299] The first end of the eighth energy storage circuit is electrically connected with the control end of the driving circuit; the eighth energy storage circuit is used for storing electric energy;

[0300] The compensation control circuit is electrically connected with a scanning line, the control end of the driving circuit and a second node respectively, and is used for controlling the communication or disconnection between the control end of the driving circuit and the second node under the control of a scanning signal provided by the scanning line;

[0301] The data writing circuit is electrically connected with the scanning line, a data line and the second end of the eighth energy storage circuit respectively, and is used for writing a current control data voltage provided by the data line into the second end of the eighth energy storage circuit under the control of the scanning signal.

[0302] The pixel circuit provided in at least one embodiment of the present disclosure further comprises a reference voltage writing circuit;

[0303] The reference voltage writing circuit is electrically connected with the first control end, a second light-emitting time control end, a reference voltage end and the second end of the eighth energy storage circuit respectively, and is used for writing a reference voltage provided by the reference voltage end into the second end of the eighth energy storage circuit under the control of a first control signal provided by the first control end, and writing the reference voltage into the second end of the eighth energy storage circuit under the control of a second light-emitting time control signal provided by the second light-emitting time control end.

[0304] As shown in FIG. 6, on the basis of at least one embodiment of the pixel circuit shown in FIG. 2,

[0305] The pixel circuit in at least one embodiment of the present disclosure further comprises a compensation control circuit 42, a data writing circuit 41 and an eighth energy storage circuit 40; the first node N1 is electrically connected with a power supply voltage terminal ELVDD;

[0306] The first end of the eighth energy storage circuit 40 is electrically connected with the control terminal of the driving circuit 10; the eighth energy storage circuit 40 is used for storing electric energy;

[0307] The compensation control circuit 42 is electrically connected with the scan line GL, the control terminal of the driving circuit 10 and the second node respectively, and is used for controlling the control terminal of the driving circuit 10 and the second node N2 to be connected or disconnected under the control of the scan signal provided by the scan line GL;

[0308] The data writing circuit 41 is electrically connected with the scan line GL, the data line DL and the second end of the eighth energy storage circuit 40 respectively, and is used for writing the current control data voltage Vdata provided by the data line DL into the second end of the eighth energy storage circuit 40 under the control of the scan signal;

[0309] The pixel circuit in at least one embodiment of the present disclosure further comprises a first initialization circuit 44;

[0310] The first initialization circuit 44 is electrically connected with the first control terminal R1, the initial voltage terminal I1 and the control terminal of the driving circuit 10 respectively, and is used for writing the initial voltage Vinit provided by the initial voltage terminal I1 into the control terminal of the driving circuit 10 under the control of the first control signal provided by the first control terminal R1;

[0311] The pixel circuit in at least one embodiment of the present disclosure further comprises a reference voltage writing circuit 47;

[0312] The reference voltage writing circuit 47 is electrically connected with the first control terminal R1, the second light-emitting time control terminal EML, the reference voltage terminal VR and the second end of the eighth energy storage circuit 40 respectively, and is used for writing the reference voltage Vref provided by the reference voltage terminal VR into the second end of the eighth energy storage circuit 40 under the control of the first control signal provided by the first control terminal R1, and writing the reference voltage Vref into the second end of the eighth energy storage circuit 40 under the control of the second light-emitting time control signal provided by the second light-emitting time control terminal EML.

[0313] In at least one embodiment of the pixel circuit shown in FIG. 6 of the present disclosure, the display period can include a first stage and a second stage arranged in sequence in working time;

[0314] In the first stage, the first initialization circuit 44 writes the initial voltage Vinit provided by the initial voltage terminal I1 to the control terminal of the driving circuit 10 under the control of the first control signal provided by the first control terminal R1, so that the driving circuit 10 can turn on the connection between the power voltage terminal ELVDD and the second node N2 at the beginning of the second stage; the reference voltage writing circuit 47 writes the reference voltage Vref provided by the reference voltage terminal VR to the second terminal of the eighth energy storage circuit 40 under the control of the first control signal, so as to initialize the potential of the second terminal of the eighth energy storage circuit 40, so that the potential of the second terminal of the eighth energy storage circuit 40 is Vref.

[0315] In the second stage, the data writing circuit 41 is electrically connected with the scan line GL, the data line DL and the second terminal of the eighth energy storage circuit 40, respectively, for writing the current control data voltage Vdata provided by the data line DL to the second terminal of the eighth energy storage circuit 40 under the control of the scan signal; the compensation control circuit 42 controls the communication between the control terminal of the driving circuit 10 and the second node N2 under the control of the scan signal, so as to charge the eighth energy storage circuit 40, until the driving circuit 10 turns off the connection between the power voltage terminal ELVDD and the second node N2 under the control of the potential of the control terminal thereof, so as to perform threshold voltage compensation.

[0316] Optionally, the data writing circuit comprises a fifteenth transistor, the compensation control circuit comprises a sixteenth transistor, and the seventh energy storage circuit comprises a first storage capacitor.

[0317] The gate of the fifteenth transistor is electrically connected with the scan line, the first pole of the fifteenth transistor is electrically connected with the data line, and the second pole of the fifteenth transistor is electrically connected with the first node.

[0318] The gate of the sixteenth transistor is electrically connected with the scan line, the first pole of the sixteenth transistor is electrically connected with the control terminal of the driving circuit, and the second pole of the sixteenth transistor is electrically connected with the second node.

[0319] The first terminal of the first storage capacitor is electrically connected with the control terminal of the driving circuit, and the second terminal of the first storage capacitor is electrically connected with the power voltage terminal.

[0320] Optionally, the first initialization circuit comprises a seventeenth transistor, and the second initialization circuit comprises an eighteenth transistor.

[0321] A gate of the seventeenth transistor is electrically connected with the first control end, a first pole of the seventeenth transistor is electrically connected with the initial voltage end, and a second pole of the seventeenth transistor is electrically connected with the control end of the drive circuit.

[0322] A gate of the eighteenth transistor is electrically connected with the first control end, a first pole of the eighteenth transistor is electrically connected with the initial voltage end, and a second pole of the eighteenth transistor is electrically connected with the first pole of the light emitting element.

[0323] Optionally, the light emitting control circuit comprises a nineteenth transistor.

[0324] A gate of the nineteenth transistor is electrically connected with the second light emitting time control end, a first pole of the nineteenth transistor is electrically connected with the power voltage end, and a second pole of the nineteenth transistor is electrically connected with the first node.

[0325] Optionally, the first initialization circuit comprises a seventeenth transistor, and the second initialization circuit comprises an eighteenth transistor.

[0326] A gate of the seventeenth transistor is electrically connected with the first reset control end, a first pole of the seventeenth transistor is electrically connected with the initial voltage end, and a second pole of the seventeenth transistor is electrically connected with the control end of the drive circuit.

[0327] A gate of the eighteenth transistor is electrically connected with the first reset control end, a first pole of the eighteenth transistor is electrically connected with the initial voltage end, and a second pole of the eighteenth transistor is electrically connected with the first pole of the light emitting element.

[0328] Optionally, the compensation control circuit comprises a sixteenth transistor, the data writing circuit comprises a fifteenth transistor, and the eighth energy storage circuit comprises a second storage capacitor.

[0329] A first end of the second storage capacitor is electrically connected with the control end of the drive circuit.

[0330] A gate of the sixteenth transistor is electrically connected with the scanning line, a first pole of the sixteenth transistor is electrically connected with the control end of the drive circuit, and a second pole of the sixteenth transistor is electrically connected with the second node.

[0331] A gate of the fifteenth transistor is electrically connected with the scanning line, a first pole of the fifteenth transistor is electrically connected with the data line, and a second pole of the fifteenth transistor is electrically connected with a second end of the second storage capacitor.

[0332] Optionally, the reference voltage writing circuit comprises a nineteenth transistor and a twentieth transistor.

[0333] A gate of the nineteenth transistor is electrically connected with the first control end, a first pole of the nineteenth transistor is electrically connected with the reference voltage end, and a second pole of the nineteenth transistor is electrically connected with the second end of the eighth energy storage circuit;

[0334] A gate of the twentieth transistor is electrically connected with the second light-emitting time control end, a first pole of the twentieth transistor is electrically connected with the reference voltage end, and a second pole of the twentieth transistor is electrically connected with the second end of the eighth energy storage circuit.

[0335] In at least one embodiment of the present disclosure, the light-emitting element can be a micro light-emitting diode, but is not limited thereto. In actual operation, the light-emitting element can also be a mini light-emitting diode, an organic light-emitting diode, or other types of light-emitting elements.

[0336] As shown in FIG. 7, on the basis of at least one embodiment of the pixel circuit shown in FIG. 4, the light-emitting element is a micro light-emitting diode ML;

[0337] The first write-in circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1, the first switch control circuit includes a second transistor T2, and the second switch control circuit includes a third transistor T3.

[0338] A gate of the first transistor T1 is electrically connected with the first control end R1, a source of the first transistor T1 is electrically connected with the data line DL, and a drain of the first transistor T1 is electrically connected with a first switch node NK1.

[0339] A first end of the first capacitor C1 is electrically connected with the first switch node NK1, and a second end of the first capacitor is electrically connected with an initial voltage end I1; the initial voltage end I1 is configured to provide an initial voltage Vinit.

[0340] A gate of the second transistor T2 is electrically connected with the first switch node NK1, a source of the second transistor T2 is electrically connected with the second light-emitting time control end EML, and a drain of the second transistor T2 is electrically connected with the first control node NC1.

[0341] A gate of the third transistor T3 is electrically connected with the first switch node NK1, a source of the third transistor T3 is electrically connected with the first light-emitting time control end HF, and a drain of the third transistor T3 is electrically connected with the first control node NC1.

[0342] T1 and T2 are p-type transistors, and T3 is an n-type transistor.

[0343] The second write circuit comprises a fourth transistor T4, the second energy storage circuit comprises a second capacitor C2, the third switch control circuit comprises a fifth transistor T5, and the fourth switch control circuit comprises a sixth transistor T6;

[0344] The gate of the fourth transistor T4 is electrically connected with the second control end SL, the source of the fourth transistor T4 is electrically connected with the data line DL, and the drain of the fourth transistor T4 is electrically connected with the second switch node NK2;

[0345] The first end of the second capacitor C2 is electrically connected with the second switch node NK2, and the second end of the second capacitor C2 is electrically connected with an initial voltage end I1;

[0346] The gate of the fifth transistor T5 is electrically connected with the second switch node NK2, the source of the fifth transistor T5 is electrically connected with the third light-emitting time control end EMS, and the drain of the fifth transistor T5 is electrically connected with the second control node NC2;

[0347] The gate of the sixth transistor T6 is electrically connected with the second switch node NK2, the source of the sixth transistor T6 is electrically connected with the second light-emitting time control end EML, and the drain of the sixth transistor T6 is electrically connected with the second control node NC2;

[0348] The fourth transistor T4 and the fifth transistor T5 are p-type transistors, and the sixth transistor T6 is an n-type transistor;

[0349] The driving circuit comprises a driving transistor T0;

[0350] The gate of the driving transistor T0 is connected with a driving control node N0, the source of the driving transistor T0 is electrically connected with the first node N1, and the drain of the driving transistor T0 is electrically connected with the second node N2;

[0351] The first on-off control circuit comprises a first control transistor TC1, and the second on-off control circuit comprises a second control transistor TC2;

[0352] The gate of the first control transistor TC1 is electrically connected with the first control node NC1, the source of the first control transistor TC1 is electrically connected with the second node N2, and the drain of the first control transistor TC1 is electrically connected with the third node N3; the third node N3 is electrically connected with the anode of the micro light-emitting diode ML;

[0353] A gate of the second control transistor TC2 is electrically connected with the second control node NC2, a source of the second control transistor TC2 is electrically connected with the cathode of the micro light emitting diode ML, and a drain of the second control transistor TC2 is electrically connected with a low voltage terminal ELVSS;

[0354] T0 is a p-type transistor, TC1 and TC2 are p-type transistors;

[0355] The data writing circuit comprises a fifteenth transistor T15, the compensation control circuit comprises a sixteenth transistor T16, and the seventh energy storage circuit comprises a first storage capacitor Cs1;

[0356] A gate of the fifteenth transistor T15 is electrically connected with the scan line GL, a source of the fifteenth transistor T15 is electrically connected with the data line DL, and a drain of the fifteenth transistor T15 is electrically connected with the first node N1;

[0357] A gate of the sixteenth transistor T16 is electrically connected with the scan line GL, a source of the sixteenth transistor T16 is electrically connected with the driving control node N0, and a drain of the sixteenth transistor T16 is electrically connected with the second node N2;

[0358] T15 and T16 are p-type transistors;

[0359] A first end of the first storage capacitor Cs1 is electrically connected with a control terminal of the driving circuit 10, and a second end of the first storage capacitor Cs1 is electrically connected with a power voltage terminal ELVDD;

[0360] The first initialization circuit comprises a seventeenth transistor T17, and the second initialization circuit comprises an eighteenth transistor T18;

[0361] A gate of the seventeenth transistor T17 is electrically connected with the first control terminal R1, a source of the seventeenth transistor T17 is electrically connected with the initial voltage terminal I1, and a drain of the seventeenth transistor T17 is electrically connected with the driving control node N0;

[0362] A gate of the eighteenth transistor T18 is electrically connected with the first control terminal R1, a source of the eighteenth transistor T18 is electrically connected with the initial voltage terminal I1, and a drain of the eighteenth transistor T18 is electrically connected with the anode of the micro light emitting diode ML;

[0363] The light emitting control circuit comprises a nineteenth transistor T19;

[0364] The gate of the nineteenth transistor T19 is electrically connected with the second light-emitting time control end EML, the source of the nineteenth transistor T19 is electrically connected with the power supply voltage end ELVDD, and the drain of the nineteenth transistor T19 is electrically connected with the first node N1.

[0365] T17, T18 and T19 are p-type transistors.

[0366] As shown in FIG. 8, at least one embodiment of the pixel circuit shown in FIG. 7 in operation, when displaying an ultra-low gray scale, the display period includes a first stage t1, a second stage t2, a third stage t3, a fourth stage t4 and a fifth stage t5 arranged in sequence;

[0367] In the first stage t1, EML provides a high voltage signal, R1 provides a low voltage signal, GL provides a high voltage signal, SL provides a high voltage signal, DL provides a high voltage signal, EMS provides a high voltage signal, and HF provides a high voltage signal, as shown in FIG. 9A, T1 is turned on, C1 maintains the potential of NK1 as a high voltage, T3 is turned on to control the communication between NC1 and HF, and TC1 is turned off; T17 is turned on to write the initial voltage Vinit to the driving control node N0, so that T0 can be turned on at the beginning of the second stage t2; T18 is turned on to write Vinit to the anode of ML to initialize the anode potential of ML and clear the residual charge of the anode of ML;

[0368] As shown in FIG. 9A, in the first stage t1, T19 is turned off, T16 is turned off, T15 is turned off, and T4 is turned off;

[0369] In the second stage t2, EML provides a high voltage signal, R1 provides a high voltage signal, GL provides a low voltage signal, SL provides a high voltage signal, DL provides a current control data voltage Vdata, EMS provides a high voltage signal, and HF provides a high voltage signal; as shown in FIG. 9B, C1 maintains the potential of NK1 as a high voltage, T3 is turned on to control the communication between NC1 and HF, and TC1 is turned off; T15 is turned on to write Vdata to the first node N1, and T16 is turned on;

[0370] At the beginning of the second stage t2, T0 is turned on to charge Cs1 through Vdata until T0 is turned off, and the potential of N0 becomes Vdata+Vth, where Vth is the threshold voltage of T0;

[0371] As shown in FIG. 9B, in the second stage t2, T19 is turned off, T17 is turned off, T18 is turned off, T1 is turned off, and T4 is turned off;

[0372] In the third stage t3, the EML provides a high voltage signal, the R1 provides a high voltage signal, the GL provides a high voltage signal, the SL provides a low voltage signal, the DL provides a low voltage signal, the EMS provides a high voltage signal, and the HF provides a high voltage signal; as shown in FIG. 9C, the T4 is turned on, the C2 maintains the potential of the NK2 as a low voltage, the T5 is turned on, the communication between the NK2 and the EMS is controlled, so that the potential of the NK2 is a high voltage, and the TC2 is turned off;

[0373] As shown in FIG. 9C, in the third stage t3, the T19 is turned off, the T15 is turned off, the T17 is turned off, the T16 is turned off, the T18 is turned off, the TC1 is turned off, the T1 is turned off, the T2 is turned off, and the T6 is turned off.

[0374] In the fourth stage t4, the EML provides a low voltage signal, the R1 provides a high voltage signal, the GL provides a high voltage signal, the SL provides a high voltage signal, the DL provides a low voltage signal, and the EMS provides a high voltage signal; as shown in FIG. 9D, the T19 is turned on, the C1 maintains the potential of the NK1 as a high voltage, the T3 is turned on to control the communication between the HF and the NC1, the TC1 is turned on when the HF provides a low voltage signal, the C2 maintains the potential of the NK2 as a low voltage, the T5 is turned on, the communication between the NC2 and the EMS is controlled, the TC2 is turned off, and the O1 does not emit light.

[0375] As shown in FIG. 9D, the T15 is turned off, the T17 is turned off, the T18 is turned off, the T16 is turned off, the T1 is turned off, the T2 is turned off, the T4 is turned off, and the T6 is turned off.

[0376] In the fifth stage t5, the R1 provides a high voltage signal, the GL provides a high voltage signal, and the SL provides a high voltage signal; as shown in FIG. 9E, the T3 is turned on, the communication between the HF and the NC1 is controlled, the T5 is turned on, the communication between the EMS and the NC2 is controlled, and as shown in FIG. 9E, the T0 drives the O1 to emit light when the EML, the HF, and the EMS all provide low voltage signals.

[0377] As shown in FIG. 9E, the T2 is turned off, the T1 is turned off, the T4 is turned off, the T6 is turned off, the T16 is turned off, the T17 is turned off, and the T17 is turned off.

[0378] The first stage t1 can be an initialization stage and a first data writing stage, the second stage t2 can be a second data writing stage and a compensation stage, the third stage t3 can be a third data writing stage, a long-time light emitting stage, and a short-time light emitting stage selection stage, and the fourth stage t4 can be a selection light emitting stage, and the fifth stage t5 can be a light emitting stage.

[0379] In FIG. 8, Id is the driving current generated by the driving transistor T0.

[0380] At least one embodiment of the pixel circuit shown in FIG. 7 of the present disclosure works as follows. In the second stage t2, the Vdata written by the DL determines the light-emitting current, and the value range of Vdata can be greater than or equal to 12V and less than or equal to 18V. In the first stage t1 and the third stage t3, the voltage value of the voltage signal written by the DL controls the corresponding transistor to be turned on or turned off. When the n-type transistor is controlled to be turned on by the voltage signal written by the DL, the voltage value of the voltage signal can be greater than or equal to 14V and less than or equal to 18V. When the p-type transistor is controlled to be turned on by the voltage signal written by the DL, the voltage value of the voltage signal can be greater than or equal to -2V and less than or equal to 0V.

[0381] In at least one embodiment of the present disclosure, the voltage value of the low-voltage signal provided by the ELVSS can be 2V, and the voltage value of the power supply voltage signal provided by the ELVDD can be 16V, but the present disclosure is not limited thereto.

[0382] At least one embodiment of the pixel circuit shown in FIG. 7 of the present disclosure works as follows. In the second stage t2,

[0383] When displaying a medium-high gray scale, the voltage value of Vdata provided by the DL can be greater than or equal to 12V and less than or equal to 15V.

[0384] When displaying a medium-low gray scale, the voltage value of Vdata provided by the DL can be greater than or equal to 15V and less than or equal to 18V.

[0385] but the present disclosure is not limited thereto.

[0386] FIG. 10 is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 7 of the present disclosure when displaying a medium-high gray scale. FIG. 11 is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 7 of the present disclosure when displaying a medium-low gray scale.

[0387] FIG. 12 is a timing diagram of at least one embodiment of the pixel circuit shown in FIG. 7 of the present disclosure when displaying a low gray scale.

[0388] As shown in FIG. 10, at least one embodiment of the pixel circuit shown in FIG. 7 of the present disclosure when displaying a medium-high gray scale,

[0389] In the first stage t1, the DL provides a low-voltage signal, T2 is turned on, and the EML is in communication with the NCl;

[0390] In the third stage t3, the DL provides a high-voltage signal, T6 is turned on, and the EML is in communication with the NC2.

[0391] As shown in FIG. 11, at least one embodiment of the pixel circuit shown in FIG. 7 of the present disclosure when displaying a medium-low gray scale,

[0392] In the first stage t1, the DL provides a low voltage signal, T2 is turned on, and the EML is connected with the NCl;

[0393] In the third stage t3, the DL provides a low voltage signal, T5 is turned on, and the EMS is connected with the NC2.

[0394] As shown in FIG. 12, at least one embodiment of the pixel circuit shown in FIG. 7 is based on the pixel circuit shown in FIG. 5, and the light emitting element is a micro light emitting diode ML;

[0395] In the first stage t1, the DL provides a high voltage signal, T3 is turned on, and the HF is connected with the NCl;

[0396] In the third stage t3, the DL provides a low voltage signal, T5 is turned on, and the EMS is connected with the NC2.

[0397] As shown in FIG. 13, at least one embodiment of the pixel circuit shown in FIG. 5 is based on the pixel circuit shown in FIG. 5, and the light emitting element is a micro light emitting diode ML;

[0398] The third write-in circuit comprises a seventh transistor T7, the fourth write-in circuit comprises an eighth transistor T8, the third energy storage circuit comprises a third capacitor C3, the fourth energy storage circuit comprises a fourth capacitor C4, the fifth switch control circuit comprises a ninth transistor T9, and the sixth switch control circuit comprises a tenth transistor T10;

[0399] The gate of the seventh transistor T7 is electrically connected with the first reset control end RA, the source of the seventh transistor T7 is electrically connected with the data line DL, and the drain of the seventh transistor T7 is electrically connected with a third switch node NK3;

[0400] The first end of the third capacitor C3 is electrically connected with the third switch node NK3, and the second end of the third capacitor C3 is electrically connected with an initial voltage end I1; the initial voltage end I1 is used for providing an initial voltage Vinit;

[0401] The gate of the eighth transistor T8 is electrically connected with the second reset control end RB, the source of the eighth transistor T8 is electrically connected with the data line DL, and the drain of the eighth transistor T8 is electrically connected with a fourth switch node NK4;

[0402] The first end of the fourth capacitor C4 is electrically connected with the fourth switch node NK4, and the second end of the fourth capacitor C4 is electrically connected with the initial voltage end I1;

[0403] The gate of the ninth transistor T9 is electrically connected with the third switch node NK3, the source of the ninth transistor T9 is electrically connected with the second light emitting time control end EML, and the drain of the ninth transistor T9 is electrically connected with the first control node NCl;

[0404] a tenth transistor T10, a gate of the tenth transistor T10 being electrically connected with the fourth switch node NK4, a source of the tenth transistor T10 being electrically connected with the first light-emitting time control terminal HF, and a drain of the tenth transistor T10 being electrically connected with the first control node NC1;

[0405] the fifth write-in circuit comprises an eleventh transistor T11, the sixth write-in circuit comprises a twelfth transistor T12, the seventh switch control circuit comprises a thirteenth transistor T13, the eighth switch control circuit comprises a fourteenth transistor T14, the fifth energy storage circuit comprises a fifth capacitor C5, and the sixth energy storage circuit comprises a sixth capacitor C6;

[0406] a gate of the eleventh transistor T11 being electrically connected with the third reset control terminal RC, a source of the eleventh transistor T11 being electrically connected with the data line DL, and a drain of the eleventh transistor T11 being electrically connected with the fifth switch node NK5;

[0407] a first end of the fifth capacitor C5 being electrically connected with the fifth switch node NK5, and a second end of the fifth capacitor C5 being electrically connected with the initial voltage terminal I1;

[0408] a gate of the twelfth transistor T12 being electrically connected with the fourth reset control terminal RD, a source of the twelfth transistor T12 being electrically connected with the data line DL, and a drain of the twelfth transistor T12 being electrically connected with the sixth switch node NK6;

[0409] a first end of the sixth capacitor C6 being electrically connected with the sixth switch node NK6, and a second end of the sixth capacitor C6 being electrically connected with the initial voltage terminal I1;

[0410] a gate of the thirteenth transistor T13 being electrically connected with the fifth switch node NK5, a source of the thirteenth transistor T13 being electrically connected with the second light-emitting time control terminal EML, and a drain of the thirteenth transistor T13 being electrically connected with the second control node NC2;

[0411] a gate of the fourteenth transistor T14 being electrically connected with the sixth switch node NK6, a source of the fourteenth transistor T14 being electrically connected with the third light-emitting time control terminal EMS, and a drain of the fourteenth transistor T14 being electrically connected with the second control node NC2;

[0412] the driving circuit comprises a driving transistor T0;

[0413] A gate of the driving transistor T0 is connected with the driving control node N0, a source of the driving transistor T0 is electrically connected with the first node N1, and a drain of the driving transistor T0 is electrically connected with the second node N2;

[0414] The first on-off control circuit comprises a first control transistor TC1, and the second on-off control circuit comprises a second control transistor TC2;

[0415] A gate of the first control transistor TC1 is electrically connected with the first control node NC1, a source of the first control transistor TC1 is electrically connected with the second node N2, and a drain of the first control transistor TC1 is electrically connected with the third node N3; the third node N3 is electrically connected with the anode of the micro light emitting diode ML;

[0416] A gate of the second control transistor TC2 is electrically connected with the second control node NC2, a source of the second control transistor TC2 is electrically connected with the cathode of the micro light emitting diode ML, and a drain of the second control transistor TC2 is electrically connected with a low voltage end ELVSS;

[0417] The data writing circuit comprises a fifteenth transistor T15, the compensation control circuit comprises a sixteenth transistor T16, and the seventh energy storage circuit comprises a first storage capacitor Cs1;

[0418] A gate of the fifteenth transistor T15 is electrically connected with the scan line GL, a source of the fifteenth transistor T15 is electrically connected with the data line DL, and a drain of the fifteenth transistor T15 is electrically connected with the first node N1;

[0419] A gate of the sixteenth transistor T16 is electrically connected with the scan line GL, a source of the sixteenth transistor T16 is electrically connected with the driving control node N0, and a drain of the sixteenth transistor T16 is electrically connected with the second node N2;

[0420] A first end of the first storage capacitor Cs1 is electrically connected with the driving control node N0, and a second end of the first storage capacitor Cs1 is electrically connected with a power voltage end ELVDD;

[0421] The first initialization circuit comprises a seventeenth transistor T17, and the second initialization circuit comprises an eighteenth transistor T18;

[0422] A gate of the seventeenth transistor T17 is electrically connected with the first reset control end RA, a source of the seventeenth transistor T17 is electrically connected with the initial voltage end I1, and a drain of the seventeenth transistor T17 is electrically connected with the driving control node N0; the initial voltage end I1 is used for providing an initial voltage Vinit;

[0423] The gate of the eighteenth transistor T18 is electrically connected with the first reset control end RA, the source of the eighteenth transistor T18 is electrically connected with the initial voltage end I1, and the drain of the eighteenth transistor T18 is electrically connected with the anode of the micro light emitting diode ML;

[0424] The light emitting control circuit comprises a nineteenth transistor T19.

[0425] The gate of the nineteenth transistor T19 is electrically connected with the second light emitting time control end EML, the source of the nineteenth transistor T19 is electrically connected with the power voltage end ELVDD, and the drain of the nineteenth transistor T19 is electrically connected with the first node N1.

[0426] In at least one embodiment of the pixel circuit shown in FIG. 13, all the transistors are p-type transistors, but are not limited thereto.

[0427] As shown in FIG. 14, at least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure in operation, when displaying an ultra-low gray scale, the display period comprises a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, a fifth stage t5 and a sixth stage t6 arranged in sequence;

[0428] In the first stage t1, the RA provides a low voltage signal, the T17 and the T18 are turned on, the I1 provides the initial voltage Vinit to the driving control node N0 and the third node N3; the DL provides a high voltage signal, the T7 is turned on, the potential of the NK3 is high voltage, and the T9 is turned off; the RB, the RC and the RD provide high voltage signals, the EML provides a high voltage signal, the T19 is turned off, the GL provides a high voltage signal, and the ML does not emit light;

[0429] In the second stage t2, the EML provides a high voltage signal, the T19 is still turned off, the EMS provides a high voltage signal, the HF provides a high voltage signal, the RA provides a high voltage signal, the T17 and the T18 are turned off, the GL provides a low voltage signal, the T15 and the T16 are turned on, the DL provides the current control data voltage Vdata, and the N0 and the N2 are connected;

[0430] At the beginning of the second stage t2, the T0 is turned on to charge the Cs1 through the Vdata until the T0 is turned off, and the potential of the N0 is Vdata+Vth; the Vth is the threshold voltage of the T0.

[0431] In the third stage t3, the EML provides a high voltage signal, T19 remains off, RA, RC and RD all provide a high voltage signal, T7, T11 and T12 are off, RB provides a low voltage signal, T8 is on, DL provides a low voltage signal, the potential of NK4 is a low voltage, T10 is on, NC1 is connected with HF, HF provides a high voltage signal, the potential of NC1 is a high voltage;

[0432] In the fourth stage t4, the EML provides a high voltage signal, T19 remains off, RA, RB and RD all provide a high voltage signal, T7, T8 and T12 are off, RC provides a low voltage signal, T11 is on, DL provides a high voltage signal, the potential of NK5 is a high voltage signal, T13 is off;

[0433] In the fifth stage t5, the EML provides a high voltage signal, T9 remains off, RA, RB and RC all provide a high voltage signal, T7, T8 and T11 are off, RD provides a low voltage signal, T12 is on, DL provides a low voltage signal, the potential of NK6 is a low voltage signal, T14 is on, NC2 is connected with EMS, the potential of NC2 is a high voltage.

[0434] In the sixth stage t6, RA, RB, RC and RD all provide a high voltage signal, GL provides a high voltage signal, the EML provides a low voltage signal, T19 is on, C3 and C5 maintain the potentials of NK3 and NK5 as high voltages, C4 and C6 maintain the potentials of NK4 and NK6 as low voltages, T10 and T14 are open, when HF and EMS provide a low voltage signal at the same time, the potentials of NC1 and NC2 are low voltages, TC1 and TC2 are on, T0 drives O1 to emit light.

[0435] At least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure displays low gray scales,

[0436] In the first stage, RA provides a low voltage signal, RB provides a high voltage signal, RC and RD both provide a high voltage signal, DL provides a low voltage signal, T7 and T9 are on, the EML is connected with NC1;

[0437] In the third stage, RC provides a high voltage signal, RD provides a low voltage signal, RA and RB both provide a high voltage signal, DL provides a low voltage signal, T12 and T14 are on, EMS is connected with NC2.

[0438] At least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure displays low gray scales,

[0439] In the first stage, RA provides a high voltage signal, RB provides a low voltage signal, RC and RD both provide a high voltage signal, DL provides a low voltage signal, T8 and T10 are turned on, and HF is in communication with NC1;

[0440] In the third stage, RC provides a high voltage signal, RD provides a low voltage signal, RA and RB both provide a high voltage signal, DL provides a low voltage signal, T12 and T14 are turned on, and EMS is in communication with NC2.

[0441] In at least one embodiment of the pixel circuit shown in FIG. 13 of the present disclosure, the gate of T17 and the gate of T18 can also be replaced with electrical connection with the first control end R1.

[0442] As shown in FIG. 15, on the basis of at least one embodiment of the pixel circuit shown in FIG. 6, the light emitting element is a micro light emitting diode ML;

[0443] The first write-in circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1, the first switch control circuit includes a second transistor T2, and the second switch control circuit includes a third transistor T3.

[0444] The gate of the first transistor T1 is electrically connected with the first control end R1, the source of the first transistor T1 is electrically connected with the data line DL, and the drain of the first transistor T1 is electrically connected with a first switch node NK1.

[0445] The first end of the first capacitor C1 is electrically connected with the first switch node NK1, and the second end of the first capacitor is electrically connected with an initial voltage end I1; the initial voltage end I1 is used to provide an initial voltage Vinit.

[0446] The gate of the second transistor T2 is electrically connected with the first switch node NK1, the source of the second transistor T2 is electrically connected with the second light emitting time control end EML, and the drain of the second transistor T2 is electrically connected with the first control node NC1.

[0447] The gate of the third transistor T3 is electrically connected with the first switch node NK1, the source of the third transistor T3 is electrically connected with the first light emitting time control end HF, and the drain of the third transistor T3 is electrically connected with the first control node NC1.

[0448] T1 and T2 are p-type transistors, and T3 is an n-type transistor.

[0449] The second write-in circuit includes a fourth transistor T4, the second energy storage circuit includes a second capacitor C2, the third switch control circuit includes a fifth transistor T5, and the fourth switch control circuit includes a sixth transistor T6.

[0450] a gate of the fourth transistor T4 is electrically connected with the second control end SL, a source of the fourth transistor T4 is electrically connected with the data line DL, and a drain of the fourth transistor T4 is electrically connected with the second switch node NK2;

[0451] a first end of the second capacitor C2 is electrically connected with the second switch node NK2, and a second end of the second capacitor C2 is electrically connected with the initial voltage end I1;

[0452] a gate of the fifth transistor T5 is electrically connected with the second switch node NK2, a source of the fifth transistor T5 is electrically connected with the third light-emitting time control end EMS, and a drain of the fifth transistor T5 is electrically connected with the second control node NC2;

[0453] a gate of the sixth transistor T6 is electrically connected with the second switch node NK2, a source of the sixth transistor T6 is electrically connected with the second light-emitting time control end EML, and a drain of the sixth transistor T6 is electrically connected with the second control node NC2;

[0454] T4 and T5 are p-type transistors, and T6 is an n-type transistor;

[0455] the driving circuit comprises a driving transistor T0;

[0456] a gate of the driving transistor T0 is connected with a driving control node N0, a source of the driving transistor T0 is electrically connected with a power voltage end ELVDD, and a drain of the driving transistor T0 is electrically connected with the second node N2;

[0457] the first on-off control circuit comprises a first control transistor TC1, and the second on-off control circuit comprises a second control transistor TC2;

[0458] a gate of the first control transistor TC1 is electrically connected with the first control node NC1, a source of the first control transistor TC1 is electrically connected with the second node N2, and a drain of the first control transistor TC1 is electrically connected with the third node N3; the third node N3 is electrically connected with an anode of the micro light-emitting diode ML;

[0459] a gate of the second control transistor TC2 is electrically connected with the second control node NC2, a source of the second control transistor TC2 is electrically connected with a cathode of the micro light-emitting diode ML, and a drain of the second control transistor TC2 is electrically connected with a low voltage end ELVSS;

[0460] T0 is a p-type transistor, and TC1 and TC2 are p-type transistors;

[0461] The first initialization circuit comprises a seventeenth transistor T17;

[0462] The gate of the seventeenth transistor T17 is electrically connected with the first control end R1, the source of the seventeenth transistor T17 is electrically connected with the initial voltage end I1, and the drain of the seventeenth transistor T17 is electrically connected with the driving control node N0.

[0463] T17 is a p-type transistor.

[0464] The compensation control circuit comprises a sixteenth transistor T16, the data writing circuit comprises a fifteenth transistor T15, and the eighth energy storage circuit comprises a second storage capacitor Cs2.

[0465] The first end of the second storage capacitor Cs2 is electrically connected with the driving control node N0.

[0466] The gate of the sixteenth transistor T16 is electrically connected with the scan line GL, the source of the sixteenth transistor T16 is electrically connected with the driving control node N0, and the drain of the sixteenth transistor T16 is electrically connected with the second node N2.

[0467] The gate of the fifteenth transistor T15 is electrically connected with the scan line GL, the source of the fifteenth transistor T15 is electrically connected with the data line DL, and the drain of the fifteenth transistor T15 is electrically connected with the second end of the second storage capacitor Cs2.

[0468] T15 and T16 are both p-type transistors.

[0469] The reference voltage writing circuit comprises a nineteenth transistor T19 and a twentieth transistor T20.

[0470] The gate of the nineteenth transistor T19 is electrically connected with the first control end R1, the source of the nineteenth transistor T19 is electrically connected with the reference voltage end VR, and the drain of the nineteenth transistor T19 is electrically connected with the second end of the second storage capacitor Cs2.

[0471] The gate of the twentieth transistor T20 is electrically connected with the second light-emitting time control end EML, the source of the twentieth transistor T20 is electrically connected with the reference voltage end VR, and the drain of the twentieth transistor T20 is electrically connected with the second end of the second storage capacitor Cs2.

[0472] T19 and T20 are both p-type transistors.

[0473] At least one embodiment of the driving circuit shown in FIG. 15 of the present disclosure, when in operation, during display of an ultra-low gray scale, a display period includes first, second, third, fourth and fifth stages t5 arranged in sequence;

[0474] In the first stage, EML provides a high voltage signal, R1 provides a low voltage signal, GL provides a high voltage signal, SL provides a high voltage signal, DL provides a high voltage signal, EMS provides a high voltage signal, HF provides a high voltage signal, T1 is on, C1 maintains the potential of NK1 as a high voltage, T3 is on to control communication between NC1 and HF, and TC1 is off; T17 is on to write an initial voltage Vinit to the driving control node N0, so that when the second stage t2 starts, T0 can be turned on; VR provides a reference voltage Vref, and T19 is on to write Vref to the second end of Cs2;

[0475] In the second stage, EML provides a high voltage signal, R1 provides a high voltage signal, GL provides a low voltage signal, SL provides a high voltage signal, DL provides a current control data voltage Vdata, EMS provides a high voltage signal, and HF provides a high voltage signal; C1 maintains the potential of NK1 as a high voltage, T3 is on to control communication between NC1 and HF, and TC1 is off; T15 is on to write Vdata to the second end of C2, and T16 is on;

[0476] At the beginning of the second stage, T0 is on to charge Cs2 until T0 is off, and the potential of N0 becomes Vdd+Vth, where Vdd is the voltage value of the power supply voltage signal provided by ELVDD, and Vth is the threshold voltage of T0;

[0477] In the third stage, EML provides a high voltage signal, R1 provides a high voltage signal, GL provides a high voltage signal, SL provides a low voltage signal, DL provides a low voltage signal, EMS provides a high voltage signal, and HF provides a high voltage signal; T4 is on, C2 maintains the potential of NK2 as a low voltage, T5 is on to control communication between NK2 and EMS, so that the potential of NK2 is a high voltage, and TC2 is off;

[0478] In the fourth stage, EML provides a low voltage signal, R1 provides a high voltage signal, GL provides a high voltage signal, SL provides a high voltage signal, DL provides a low voltage signal, EMS provides a high voltage signal, T19 is on, C1 maintains the potential of NK1 as a high voltage, T3 is on to control communication between HF and NC1, TC1 is on when HF provides a low voltage signal; C2 maintains the potential of NK2 as a low voltage, T5 is on to control communication between NC2 and EMS, TC2 is off, and O1 does not emit light;

[0479] In the fourth stage, the VR provides a reference voltage Vref, the EML provides a low voltage signal, the T20 is turned on, the potential of the Cs2 is changed from Vdata to Vref, and the potential of the N0 is changed to Vdd+Vth+Vref-Vdata;

[0480] In the fifth stage, the R1 provides a high voltage signal, the GL provides a high voltage signal, the SL provides a high voltage signal, the T3 is turned on, the HF is communicated with the NC1, the T5 is turned on, the EMS is communicated with the NC2, and the T0 drives the O1 to emit light when the EML, the HF and the EMS all provide low voltage signals.

[0481] At least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure is used when displaying a high gray scale,

[0482] In the first stage, the DL provides a low voltage signal, the T2 is turned on, and the EML is communicated with the NC1.

[0483] In the third stage, the DL provides a high voltage signal, the T6 is turned on, and the EML is communicated with the NC2.

[0484] At least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure is used when displaying a low gray scale,

[0485] In the first stage, the DL provides a low voltage signal, the T2 is turned on, and the EML is communicated with the NC1.

[0486] In the third stage, the DL provides a low voltage signal, the T5 is turned on, and the EMS is communicated with the NC2.

[0487] At least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure is used when displaying a low gray scale,

[0488] In the first stage, the DL provides a high voltage signal, the T3 is turned on, and the HF is communicated with the NC1.

[0489] In the third stage, the DL provides a low voltage signal, the T5 is turned on, and the EMS is communicated with the NC2.

[0490] The timing diagram of at least one embodiment of the pixel circuit shown in FIG. 15 of the present disclosure can be the same as the timing diagram of at least one embodiment of the pixel circuit shown in FIG. 7 of the present disclosure, but is not limited thereto.

[0491] The driving method provided by the embodiment of the present disclosure is applied to the pixel circuit described above, and the driving method comprises the following steps.

[0492] The driving circuit generates a driving current for driving the light-emitting element under the control of the potential at the control end thereof;

[0493] The first on-off control circuit controls the communication or disconnection between the second node and the third node under the control of the potential at the first control node.

[0494] The second on-off control circuit controls the second pole of the light emitting element to be connected or disconnected with the first voltage terminal under the control of the potential of the second control node;

[0495] The first control circuit controls the first light emitting time control terminal or the second light emitting time control terminal to be connected with the first control node under the control of the first control signal according to the first time control data voltage provided by the data line;

[0496] The second control circuit controls the second light emitting time control terminal or the third light emitting time control terminal to be connected with the second control node under the control of the second control signal according to the second time control data voltage provided by the data line.

[0497] The display device provided by the embodiment of the present disclosure comprises the pixel circuit.

[0498] The above is the preferred embodiment of the present disclosure, it should be pointed out that, for the ordinary skilled in the art, without departing from the principles of the present disclosure, can also make a number of improvements and refinements, these improvements and refinements should also be considered as the protection scope of the present disclosure.

Claims

1. A pixel circuit, comprising a driving circuit, a first on-off control circuit, a light emitting element, a second on-off control circuit, a first control circuit and a second control circuit; a first end of the driving circuit is electrically connected with a first node, and a second end of the driving circuit is electrically connected with a second node; the driving circuit is configured to generate a driving current for driving the light emitting element under the control of a potential at a control end thereof; the first on-off control circuit is configured to control the second node and a third node to be connected or disconnected under the control of a potential at a first control node; a first pole of the light emitting element is electrically connected with the third node; the second on-off control circuit is configured to control a second pole of the light emitting element and a first voltage end to be connected or disconnected under the control of a potential at a second control node; the first control circuit is electrically connected with a first control end, a data line, a first light emitting time control end, a second light emitting time control end and the first control node respectively, and is configured to control the first light emitting time control end or the second light emitting time control end and the first control node to be connected under the control of a first control signal provided by the first control end according to a first time control data voltage provided by the data line; the second control circuit is electrically connected with a second control end, the data line, a second light emitting time control end, a third light emitting time control end and the second control node respectively, and is configured to control the second light emitting time control end or the third light emitting time control end and the second control node to be connected under the control of a second control signal provided by the second control end according to a second time control data voltage provided by the data line.

2. The pixel circuit of claim 1, wherein, the first control circuit comprises a first write-in circuit, a first energy storage circuit, a first switch control circuit and a second switch control circuit; the first write-in circuit is electrically connected with the first control end, the data line and a first switch node respectively, and is configured to write the first time control data voltage into the first switch node under the control of a first control signal provided by the first control end; the first energy storage circuit is electrically connected with the first switch node, and is configured to maintain a potential of the first switch node; the first switch control circuit is electrically connected with the first switch node, the second light emitting time control end and the first control node respectively, and is configured to control the first control node and the second light emitting time control end to be connected or disconnected under the control of a potential of the first switch node; the second switch control circuit is electrically connected with the first switch node, the first light emitting time control end and the first control node respectively, and is configured to control the first control node and the first light emitting time control end to be connected or disconnected under the control of a potential of the first switch node.

3. The pixel circuit of claim 1, wherein, the second control circuit comprises a second write-in circuit, a second energy storage circuit, a third switch control circuit and a fourth switch control circuit; the second write-in circuit is electrically connected with the second control end, the data line and a second switch node respectively, and is configured to write the second time control data voltage provided by the data line into the second switch node under the control of a second control signal provided by the second control end; the second energy storage circuit is electrically connected with the second switch node, and is configured to maintain a potential of the second switch node; the third switch control circuit is electrically connected with the second switch node, the second light emitting time control end and the second control node respectively, and is configured to control the second control node and the second light emitting time control end to be connected or disconnected under the control of a potential of the second switch node; the fourth switch control circuit is electrically connected with the second switch node, the third light emitting time control end and the second control node respectively, and is configured to control the second control node and the third light emitting time control end to be connected or disconnected under the control of a potential of the second switch node. writing the second switch node; The second energy storage circuit is electrically connected with the second switch node, for maintaining the potential of the second switch node; The third switch control circuit is electrically connected with the second switch node, the third light-emitting time control end and the second control node respectively, for controlling the communication or disconnection between the second control node and the third light-emitting time control end under the control of the potential of the second switch node; The fourth switch control circuit is electrically connected with the second switch node, the second light-emitting time control end and the second control node respectively, for controlling the communication or disconnection between the second control node and the second light-emitting time control end under the control of the potential of the second switch node.

4. The pixel circuit of claim 1, wherein, The first control circuit includes a third write circuit, a fourth write circuit, a fifth switch control circuit, a sixth switch control circuit, a third energy storage circuit and a fourth energy storage circuit; the first control end includes a first reset control end and a second reset control end; The third write circuit is electrically connected with the first reset control end, the data line and the third switch node respectively, for writing the third time control data voltage provided by the data line into the third switch node under the control of the first reset control signal provided by the first reset control end; The third energy storage circuit is electrically connected with the third switch node, for maintaining the potential of the third switch node; The fourth write circuit is electrically connected with the second reset control end, the data line and the fourth switch node respectively, for writing the fourth time control data voltage provided by the data line into the fourth switch node under the control of the second reset control signal provided by the second reset control end; The fourth energy storage circuit is electrically connected with the fourth switch node, for maintaining the potential of the fourth switch node; The fifth switch control circuit is electrically connected with the third switch node, the second light-emitting time control end and the first control node respectively, for controlling the communication or disconnection between the second light-emitting time control end and the first control node under the control of the potential of the third switch node; The sixth switch control circuit is electrically connected with the fourth switch node, the first light-emitting time control end and the first control node respectively, for controlling the communication or disconnection between the first light-emitting time control end and the first control node under the control of the potential of the fourth switch node.

5. The pixel circuit of claim 1, wherein, The second control circuit includes a fifth write circuit, a sixth write circuit, a seventh switch control circuit, an eighth switch control circuit, a fifth energy storage circuit and a sixth energy storage circuit; the second control end includes a third reset control end and a fourth reset control end; The fifth write circuit is electrically connected with the third reset control end, the data line and the fifth switch node respectively, for writing the fifth time control data voltage provided by the data line into the fifth switch node under the control of the third reset control signal provided by the third reset control end; The fifth energy storage circuit is electrically connected with the fifth switch node, for maintaining the potential of the fifth switch node; The sixth energy storage circuit is electrically connected with the sixth switch node, for maintaining the potential of the sixth switch node. The sixth write circuit is electrically connected with the fourth reset control end, the data line and the sixth switch node respectively, and is used for writing sixth time control data voltage provided by the data line into the sixth switch node under the control of a fourth reset control signal provided by the fourth reset control end; The sixth energy storage circuit is electrically connected with the sixth switch node, and is used for maintaining the potential of the sixth switch node; The seventh switch control circuit is electrically connected with the fifth switch node, the second light-emitting time control end and the second control node respectively, and is used for controlling the second light-emitting time control end and the second control node to be connected or disconnected under the control of the potential of the fifth switch node; The eighth switch control circuit is electrically connected with the sixth switch node, the third light-emitting time control end and the second control node respectively, and is used for controlling the third light-emitting time control end and the second control node to be connected or disconnected under the control of the potential of the sixth switch node.

6. The pixel circuit of claim 1, wherein, The drive circuit comprises a drive transistor; The gate of the drive transistor is electrically connected with the control end of the drive circuit, the first pole of the drive circuit is electrically connected with the first node, and the second pole of the drive circuit is electrically connected with the second node; The first control transistor comprises the first control node, the second node and the third node. The gate of the second control transistor is electrically connected with the second control node, the first pole of the second control transistor is electrically connected with the second pole of the light-emitting element, and the second pole of the second control transistor is electrically connected with the first voltage end. The first write circuit comprises a first transistor, the first energy storage circuit comprises a first capacitor, the first switch control circuit comprises a second transistor, and the second switch control circuit comprises a third transistor; 7. The pixel circuit of claim 2, wherein, The gate of the first transistor is electrically connected with the first control end, the first pole of the first transistor is electrically connected with the data line, and the second pole of the first transistor is electrically connected with the first switch node; The first end of the first capacitor is electrically connected with the first switch node, and the second end of the first capacitor is electrically connected with an initial voltage end; The gate of the second transistor is electrically connected with the first switch node, the first pole of the second transistor is electrically connected with the second light-emitting time control end, and the second pole of the second transistor is electrically connected with the first control node; The gate of the third transistor is electrically connected with the first switch node, the first pole of the third transistor is electrically connected with the first light-emitting time control end, and the second pole of the third transistor is electrically connected with the first control node. The second write circuit comprises a fourth transistor, the second energy storage circuit comprises a second capacitor, the third switch control circuit comprises a fifth transistor, and the fourth switch control circuit comprises a sixth transistor; 8. The pixel circuit of claim 3, wherein, ​ The gate of the fourth transistor is electrically connected with the second control end, the first electrode of the fourth transistor is electrically connected with the data line, and the second electrode of the fourth transistor is electrically connected with the second switch node; The first end of the second capacitor is electrically connected with the second switch node, and the second end of the second capacitor is electrically connected with an initial voltage end; The gate of the fifth transistor is electrically connected with the second switch node, the first electrode of the fifth transistor is electrically connected with the third light-emitting time control end, and the second electrode of the fifth transistor is electrically connected with the second control node; The gate of the sixth transistor is electrically connected with the second switch node, the first electrode of the sixth transistor is electrically connected with the second light-emitting time control end, and the second electrode of the sixth transistor is electrically connected with the second control node.

9. The pixel circuit of claim 4, wherein, The third write circuit comprises a seventh transistor, the fourth write circuit comprises an eighth transistor, the third energy storage circuit comprises a third capacitor, the fourth energy storage circuit comprises a fourth capacitor, the fifth switch control circuit comprises a ninth transistor, and the sixth switch control circuit comprises a tenth transistor; The gate of the seventh transistor is electrically connected with the first reset control end, the first electrode of the seventh transistor is electrically connected with the data line, and the second electrode of the seventh transistor is electrically connected with a third switch node; The first end of the third capacitor is electrically connected with the third switch node, and the second end of the third capacitor is electrically connected with an initial voltage end; The gate of the eighth transistor is electrically connected with the second reset control end, the first electrode of the eighth transistor is electrically connected with the data line, and the second electrode of the eighth transistor is electrically connected with the fourth switch node; The first end of the fourth capacitor is electrically connected with the fourth switch node, and the second end of the fourth capacitor is electrically connected with an initial voltage end; The gate of the ninth transistor is electrically connected with the third switch node, the first electrode of the ninth transistor is electrically connected with the second light-emitting time control end, and the second electrode of the ninth transistor is electrically connected with the first control node; The gate of the tenth transistor is electrically connected with the fourth switch node, the first electrode of the tenth transistor is electrically connected with the first light-emitting time control end, and the second electrode of the tenth transistor is electrically connected with the first control node.

10. The pixel circuit of claim 5, wherein, The fifth write circuit comprises an eleventh transistor, the sixth write circuit comprises a twelfth transistor, the seventh switch control circuit comprises a thirteenth transistor, the eighth switch control circuit comprises a fourteenth transistor, the fifth energy storage circuit comprises a fifth capacitor, and the sixth energy storage circuit comprises a sixth capacitor; The gate of the eleventh transistor is electrically connected with the third reset control end, the first electrode of the eleventh transistor is electrically connected with the data line, and the second electrode of the eleventh transistor is electrically connected with a fifth switch node; The first end of the fifth capacitor is electrically connected with the fifth switch node, and the second end of the fifth capacitor is electrically connected with an initial voltage end; A gate of the twelfth transistor is electrically connected with the fourth reset control end, a first pole of the twelfth transistor is electrically connected with the data line, and a second pole of the twelfth transistor is electrically connected with the sixth switch node; A first end of the sixth capacitor is electrically connected with the sixth switch node, and a second end of the sixth capacitor is electrically connected with the initial voltage end; A gate of the thirteenth transistor is electrically connected with the fifth switch node, a first pole of the thirteenth transistor is electrically connected with the second light-emitting time control end, and a second pole of the thirteenth transistor is electrically connected with the second control node; A gate of the fourteenth transistor is electrically connected with the sixth switch node, a first pole of the fourteenth transistor is electrically connected with The third light-emitting time control end, and a second pole of the fourteenth transistor is electrically connected with the second control node.

11. The pixel circuit of any one of claims 1 to 10, wherein, Further comprising a data writing circuit, a compensation control circuit and a seventh energy storage circuit; The data writing circuit is electrically connected with the scanning line, the data line and the first node respectively, and is used for writing a current control data voltage provided by the data line into the first node under the control of a scanning signal provided by the scanning line; The compensation control circuit is electrically connected with the scanning line, the control end of the driving circuit and the second node respectively, and is used for controlling the control end of the driving circuit and the second node to be in communication or disconnected under the control of the scanning signal; The seventh energy storage circuit is electrically connected with the control end of the driving circuit, and is used for storing electric energy.

12. The pixel circuit of any one of claims 1 to 3, wherein, Further comprising a first initialization circuit and a second initialization circuit; The first initialization circuit is electrically connected with the first control end, the initial voltage end and the control end of the driving circuit respectively, and is used for writing an initial voltage provided by the initial voltage end into the control end of the driving circuit under the control of a first control signal provided by the first control end; The second initialization circuit is electrically connected with the first control end, the initial voltage end and the first pole of the light-emitting element respectively, and is used for writing the initial voltage into the first pole of the light-emitting element under the control of the first control signal.

13. The pixel circuit of claim 11, wherein, Further comprising a light-emitting control circuit; The light-emitting control circuit is electrically connected with the second light-emitting time control end, a power voltage end and the first node respectively, and is used for controlling the power voltage end and the first node to be in communication under the control of a second light-emitting time control signal provided by the second light-emitting time control end.

14. The pixel circuit of claim 4 or 5, wherein, The first control end comprises a first reset control end and a second reset control end; The pixel circuit further comprises a first initialization circuit and a second initialization circuit; The first initialization circuit is electrically connected with the first reset control end, the initial voltage end and the control end of the driving circuit respectively, and is used for writing an initial voltage provided by the initial voltage end into the control end of the driving circuit under the control of a first reset control signal provided by the first reset control end; The second initialization circuit is electrically connected with the first reset control end, the initial voltage end and the first pole of the light-emitting element respectively, and is used for writing the initial voltage into the first pole of the light-emitting element under the control of the first reset control signal.

15. The pixel circuit of any one of claims 1 to 3, wherein, The compensation control circuit, the data writing circuit and the eighth energy storage circuit are further included; the first node is electrically connected with the power voltage terminal; The first end of the eighth energy storage circuit is electrically connected with the control terminal of the driving circuit; and the eighth energy storage circuit is used for storing electric energy. The compensation control circuit is electrically connected with the scan line, the control terminal of the driving circuit and the second node respectively, and is used for controlling the control terminal of the driving circuit and the second node to be connected or disconnected under the control of the scan signal provided by the scan line; The control terminal of the driving circuit and the second node are connected or disconnected under the control of the scan signal provided by the scan line; The data writing circuit is electrically connected with the scan line, the data line and the second end of the eighth energy storage circuit respectively, and is used for writing the current control data voltage provided by the data line into the second end of the eighth energy storage circuit under the control of the scan signal.

16. The pixel circuit of claim 15, wherein, A reference voltage writing circuit is further included; The reference voltage writing circuit is electrically connected with the first control terminal, the second light-emitting time control terminal, the reference voltage terminal and the second end of the eighth energy storage circuit respectively, and is used for writing the reference voltage provided by the reference voltage terminal into the second end of the eighth energy storage circuit under the control of the first control signal provided by the first control terminal, and writing the reference voltage into the second end of the eighth energy storage circuit under the control of the second light-emitting time control signal provided by the second light-emitting time control terminal.

17. The pixel circuit of claim 11, wherein, The data writing circuit includes a fifteenth transistor, the compensation control circuit includes a sixteenth transistor, and the seventh energy storage circuit includes a first storage capacitor; The gate of the fifteenth transistor is electrically connected with the scan line, the first pole of the fifteenth transistor is electrically connected with the data line, and the second pole of the fifteenth transistor is electrically connected with the first node; The gate of the sixteenth transistor is electrically connected with the scan line, the first pole of the sixteenth transistor is electrically connected with the control terminal of the driving circuit, and the second pole of the sixteenth transistor is electrically connected with the second node; The first end of the first storage capacitor is electrically connected with the control terminal of the driving circuit, and the second end of the first storage capacitor is electrically connected with the power voltage terminal.

18. The pixel circuit of claim 12, wherein, The first initialization circuit includes a seventeenth transistor, and the second initialization circuit includes an eighteenth transistor; The gate of the seventeenth transistor is electrically connected with the first control terminal, the first pole of the seventeenth transistor is electrically connected with the initial voltage terminal, and the second pole of the seventeenth transistor is electrically connected with the control terminal of the driving circuit; The gate of the eighteenth transistor is electrically connected with the first control terminal, the first pole of the eighteenth transistor is electrically connected with the initial voltage terminal, and the second pole of the eighteenth transistor is electrically connected with the first pole of the light-emitting element.

19. The pixel circuit of claim 13, wherein, The light-emitting control circuit includes a nineteenth transistor; The gate of the nineteenth transistor is electrically connected with the second light-emitting time control terminal, the first pole of the nineteenth transistor is electrically connected with the power voltage terminal, and the second pole of the nineteenth transistor is electrically connected with the first node.

20. The pixel circuit of claim 14, wherein, The first initialization circuit includes a seventeenth transistor, and the second initialization circuit includes an eighteenth transistor; A gate of the seventeenth transistor is electrically connected with the first reset control end, a first pole of the seventeenth transistor is electrically connected with the initial voltage end, and a second pole of the seventeenth transistor is electrically connected with the control end of the drive circuit. A gate of the eighteenth transistor is electrically connected with the first reset control end, a first pole of the eighteenth transistor is electrically connected with the initial voltage end, and a second pole of the eighteenth transistor is electrically connected with the first pole of the light emitting element.

21. The pixel circuit of claim 15, wherein, The compensation control circuit comprises a sixteenth transistor, the data write-in circuit comprises a fifteenth transistor, and the eighth energy storage circuit comprises a second storage capacitor. A first end of the second storage capacitor is electrically connected with the control end of the drive circuit. A gate of the sixteenth transistor is electrically connected with the scanning line, a first pole of the sixteenth transistor is electrically connected with the control end of the drive circuit, and a second pole of the sixteenth transistor is electrically connected with the second node. A gate of the fifteenth transistor is electrically connected with the scanning line, a first pole of the fifteenth transistor is electrically connected with the data line, and a second pole of the fifteenth transistor is electrically connected with a second end of the second storage capacitor.

22. The pixel circuit of claim 16, wherein, The reference voltage write-in circuit comprises a nineteenth transistor and a twentieth transistor. A gate of the nineteenth transistor is electrically connected with the first control end, a first pole of the nineteenth transistor is electrically connected with the reference voltage end, and a second pole of the nineteenth transistor is electrically connected with the second end of the eighth energy storage circuit. A gate of the twentieth transistor is electrically connected with the second light emitting time control end, a first pole of the twentieth transistor is electrically connected with the reference voltage end, and a second pole of the twentieth transistor is electrically connected with the second end of the eighth energy storage circuit.

23. A driving method applied to the pixel circuit according to any one of claims 1 to 22, the driving method comprising: The drive circuit generates a drive current for driving the light emitting element under the control of the potential at the control end thereof; The first on-off control circuit controls the communication or disconnection between the second node and the third node under the control of the potential at the first control node; The second on-off control circuit controls the communication or disconnection between the second pole of the light emitting element and the first voltage end under the control of the potential at the second control node; The first control circuit controls the communication between the first light emitting time control end or the second light emitting time control end and the first control node according to the first time control data voltage provided by the data line under the control of the first control signal; The second control circuit controls the communication between the second light emitting time control end or the third light emitting time control end and the second control node according to the second time control data voltage provided by the data line under the control of the second control signal.

24. A display device comprising the pixel circuit according to any one of claims 1 to 22.

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