Data processing method and apparatus, device, and medium

Abstract

The present application relates to the technical field of data processing, and discloses a data processing method and apparatus, a device, and a medium. The method comprises: on the basis of a bus address space allocated for a first slave device, writing data to be processed into a storage component of the first slave device by means of a first peripheral component interconnect express link, so that the first slave device processes said data to obtain result data; obtaining the result data sent by the first slave device; and determining a destination address of the result data, and if the destination address points to a storage space of a second slave device, writing the result data into a storage component of the second slave device by means of a second peripheral component interconnect express link. The problems of high communication delay and high hardware resource overhead during data transmission exist in the prior art. The present application can reduce cross-node communication delay and hardware resource overhead.

Description

Data processing method, device, equipment and medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on June 9, 2023, with application number 202310686129.1 and entitled “A Data Processing Method, Device, Equipment and Medium,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of data processing technology, and in particular to a data processing method, apparatus, device and medium. Background Art

[0004] Currently, cross-node communication between GPU (Graphics Processing Unit) cards and traditional FPGA (Field Programmable Gate Array) cards typically relies on the server's CPU (Central Processing Unit), memory, and PCIe (Peripheral Component Interconnect Express) chipset. This means they must be tightly coupled to the server via the PCIe interface bus, making it difficult to operate independently from the host CPU. This results in high data transmission latency and significant hardware resource overhead.

[0005] Summary of the Invention

[0006] In view of this, the purpose of this application is to provide a data processing method, apparatus, device, and medium that can reduce cross-node communication latency and hardware resource overhead. The specific solution is as follows:

[0007] In a first aspect, the present application discloses a data processing method applied to a master field programmable gate array device, comprising:

[0008] Based on the bus address space allocated to the first slave device, the data to be processed is written into the storage component of the first slave device via the first high-speed serial computer expansion bus standard link, so that the first slave device processes the data to be processed and obtains result data;

[0009] Obtain result data sent by the first slave device;

[0010] The destination address of the result data is determined, and if the destination address points to the storage space of the second slave device, the result data is written into the storage component of the second slave device via the second high-speed serial computer expansion bus standard link.

[0011] Optionally, after writing the to-be-processed data into the storage component of the first slave device through the first high-speed serial computer expansion bus standard link based on the bus address space allocated to the first slave device, the method further includes:

[0012] An interrupt data packet is sent to notify the first slave device to process the data to be processed.

[0013] Optionally, sending an interrupt data packet to notify the first slave device to process the pending data includes:

[0014] Based on the mapping relationship between the registers in the first slave device and the master FPGA device bus, the interrupt data packet is written into the designated register of the first slave device to notify the first slave device to process the data to be processed.

[0015] Optionally, also include:

[0016] If the destination address points to the storage space of the local device, the result data is written into the local storage component.

[0017] Optionally, also include:

[0018] If the destination address points to the local network module, the result data is sent to the network module and then sent to the network through the network module.

[0019] Optionally, also include:

[0020] If the destination address points to a local acceleration core module, the result data is sent to the acceleration core module, and the acceleration core module calls the preset processing logic to process the result data.

[0021] Optionally, also include:

[0022] Determining a data processing type based on a descriptor corresponding to the result data;

[0023] Correspondingly, the acceleration core module calls the preset processing logic to process the result data, including: the acceleration core module calls the preset processing logic corresponding to the data processing type to process the result data.

[0024] Optionally, the acceleration core module calls the preset processing logic corresponding to the data processing type to process the result data, including:

[0025] If the data processing type is encryption processing, the encryption processing logic is called by the acceleration core module to encrypt the result data;

[0026] If the data processing type is compression processing, the compression processing logic is called by the acceleration core module to compress the result data;

[0027] If the data processing type is compression processing first and encryption processing later, the acceleration core module calls the compression processing logic to compress the result data to obtain compressed data, and calls the encryption processing logic to encrypt the compressed data.

[0028] Optionally, after sending the interrupt data packet to notify the first slave device, the method further includes:

[0029] When a notification sent by the first slave device is obtained, result data is read from a storage component of the first slave device;

[0030] The result data is stored by the first slave device into a storage component of the first slave device.

[0031] Optionally, after reading the result data from the storage component of the first slave device, the method further includes:

[0032] Cache the result data to the storage component of the local device.

[0033] Optionally, also include:

[0034] The result data is compressed using the acceleration core module to obtain compressed data, and the compressed data is encrypted to obtain encrypted data.

[0035] Optionally, after encrypting the compressed data to obtain encrypted data, the following steps are further included:

[0036] The encrypted data is encapsulated using the network module and sent to other nodes through the optical network.

[0037] Optionally, reading result data from a storage component of the first slave device includes:

[0038] The result data is read from the storage component of the first slave device using a direct data access engine.

[0039] Optionally, also include:

[0040] Discover the slave devices in place and allocate bus address space to each slave device in place to complete the registration of the slave devices in place;

[0041] Allocate bus address space for each local module.

[0042] Optionally, the first slave device is a graphics processor accelerator card or a field programmable gate array accelerator card, and the second slave device is a graphics processor accelerator card or a field programmable gate array accelerator card.

[0043] Optionally, based on the bus address space allocated to the first slave device, writing the to-be-processed data into the storage component of the first slave device via the first high-speed serial computer expansion bus standard link includes:

[0044] Obtaining the data to be processed from the network, and if the data to be processed is encrypted data, decrypting it to obtain the decrypted data;

[0045] The decrypted data is written into the storage component of the first slave device based on the bus address space allocated to the first slave device and via the first high-speed serial computer expansion bus standard link.

[0046] Optionally, based on the bus address space allocated to the first slave device, writing the to-be-processed data into the storage component of the first slave device via the first high-speed serial computer expansion bus standard link includes:

[0047] Obtain the data to be processed from the network. If the data to be processed is compressed data, decompress it to obtain the decompressed data.

[0048] The decompressed data is written into the storage component of the first slave device based on the bus address space allocated for the first slave device and via a first high-speed serial computer expansion bus standard link.

[0049] In a second aspect, the present application discloses a data processing device, which is applied to a master field programmable logic gate array device, comprising:

[0050] a module for writing data to be processed, configured to write the data to be processed into a storage component of the first slave device based on a bus address space allocated to the first slave device and via a first high-speed serial computer expansion bus standard link, so that the first slave device processes the data to be processed and obtains result data;

[0051] A result data acquisition module, used to acquire result data sent by the first slave device;

[0052] The result data forwarding module is used to determine the destination address of the result data, and if the destination address points to the storage space of the second slave device, write the result data into the storage component of the second slave device through the second high-speed serial computer expansion bus standard link.

[0053] In a third aspect, the present application discloses an electronic device, including a memory and a processor, wherein:

[0054] Memory, used to store computer programs;

[0055] The processor is used to execute the computer program to implement the aforementioned data processing method.

[0056] In a fourth aspect, the present application discloses a computer non-volatile readable storage medium for storing a computer program, wherein the computer program implements the aforementioned data processing method when executed by a processor.

[0057] As can be seen, the present application is applied to a master field programmable logic gate array device, which, based on the bus address space allocated to the first slave device, writes the data to be processed into the storage component of the first slave device via a first high-speed serial computer expansion bus standard link, so that the first slave device processes the data to be processed to obtain result data, then obtains the result data sent by the first slave device, determines the destination address of the result data, and if the destination address points to the storage space of the second slave device, writes the result data into the storage component of the second slave device via a second high-speed serial computer expansion bus standard link. That is, the master field programmable logic gate array device in the embodiment of the present application allocates bus address space to the slave device, based on the bus address space allocated to the first slave device, writes the data to be processed into the storage component of the first slave device via a first high-speed serial computer expansion bus standard link, obtains the result data obtained by processing the data to be processed sent by the first slave device, and if the destination address of the result data points to the storage space of the second slave device, writes the result data into the storage component of the second slave device via a second high-speed serial computer expansion bus standard link. In this way, the bus address space is allocated to the slave device through the master field programmable logic gate array device to achieve cross-node communication of the slave device. The slave device can be a graphics processor accelerator card or a field programmable logic gate array accelerator card.

[0058] The beneficial effects of this application are: reducing the coupling between the slave device and the server, and reducing the cross-node communication delay and hardware resource overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0060] FIG1 is a schematic diagram of a GPUDirect P2P data interaction provided by an embodiment of the present application;

[0061] FIG2 is a schematic diagram of GPUDirect RDMA data interaction provided in an embodiment of the present application;

[0062] FIG3 is a flow chart of a data processing method provided in an embodiment of the present application;

[0063] FIG4 is a schematic diagram of a specific slave device provided in an embodiment of the present application;

[0064] FIG5 is a schematic diagram of a specific master device provided in an embodiment of the present application;

[0065] FIG6 is a schematic diagram of a mapping relationship between hardware storage resources of a slave device GPU card on a 64-bit bus of a master device provided by an embodiment of the present application;

[0066] FIG7 is a schematic diagram of a mapping relationship between internal storage resources of a master FPGA device on a bus according to an embodiment of the present application;

[0067] FIG8 is a schematic diagram of a mapping relationship between storage resources of multiple slave devices on a master device FPGA bus according to an embodiment of the present application;

[0068] FIG9 is a device registration flow chart provided in an embodiment of the present application;

[0069] FIG10 is a schematic diagram of the structure of a data processing device provided in an embodiment of the present application;

[0070] FIG11 is a structural diagram of an electronic device provided in an embodiment of the present application. Specific embodiments

[0071] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0072] GPUDirect Shared Memory (i.e., direct shared memory) supports GPU and third-party PCIe devices to realize shared memory through shared host memory. GPUDirect P2P (i.e., GPUDirect Peer-to-Peer) is a method in which two GPU devices under the same PCIe Root Complex (root device) domain directly access each other's GPU memory. GPUs do not need to copy data to the host memory for transfer. Compared with the GPUDirect Shared Memory solution, it reduces the steps of copying data from GPU memory to host memory and from host memory to GPU memory, reduces data path latency, and improves data transmission efficiency. See Figure 1, which is a schematic diagram of GPUDirect P2P data interaction provided by an embodiment of the present application. However, this solution is a solution for realizing GPU memory data interaction within a single node of the same server. The solution relies on the participation of the host CPU or the same PCIe domain to realize memory data interaction between GPUs. Among them, the video memory can be GDDR (i.e., Graphics Double Data Rate, a high-performance video memory). GPUDirect (direct) RDMA (Remote Direct Memory Access) utilizes RDMA-related technologies, physical network cards, and transmission networks to enable direct memory data exchange between GPUs in different nodes. This technology addresses the problems of traditional network data transmission (such as TCP (Transmission Control Protocol) / IP (Internet Protocol), where data transmission requires passing through the CPU and host cache, resulting in high latency and CPU utilization). It enables direct access to GPU memory between different nodes through network cards. See Figure 2, which is a schematic diagram of GPUDirect RDMA data exchange provided in an embodiment of the present application.

[0073] GPUDirect P2P technology is developed and implemented based on GPUs acting as PCIe devices within the host. Communication with other devices relies on the host CPU, memory, and PCIe switch system. Devices are tightly coupled to the server CPU and memory via PCIe, and communication is limited to GPUs within a single node. When using GPUDirect P2P technology for inter-GPU memory data exchange, direct memory data exchange is limited to GPUs within the same PCIe domain via the PCIe chipset. If the PCIe domain spans two CPUs, the CPU and CPU memory must also be involved in data transfer. This solution still results in significant latency and CPU overhead for inter-CPU inter-GPU memory data exchange. While GPUDirect RDMA technology utilizes RDMA to address inter-node GPU communication, it requires high-performance network cards within the same PCIe domain and the local server CPU running the relevant network protocol software to facilitate cross-node GPU data transfer. The GPU and server remain tightly coupled via PCIe connections, preventing the GPU from operating independently of the server. Inter-node GPU communication can only be achieved through network card connections to switches, resulting in inflexible network topology, low packet forwarding efficiency, and high communication latency. When deploying a distributed computing system platform based on the above two technologies, a huge number of hardware devices such as host CPU, memory and network card are required, which takes up a lot of data center rack space and has high deployment and maintenance costs.

[0074] Currently, when communicating between cross-node GPU cards and traditional FPGA cards, it is usually necessary to rely on the participation of the server CPU, memory, and PCIe chipset. In other words, it is necessary to use it through a PCIe interface bus tightly coupled with the server, making it difficult to operate independently without the host CPU. This results in high communication latency during data transmission and high hardware resource overhead. To this end, the present application provides a method that can reduce cross-node communication latency and hardware resource overhead.

[0075] As shown in FIG3 , an embodiment of the present application discloses a data processing method applied to a master field programmable gate array device, including:

[0076] Step S11: Based on the bus address space allocated to the first slave device, the data to be processed is written into the storage component of the first slave device via the first high-speed serial computer expansion bus standard link, so that the first slave device processes the data to be processed and obtains result data.

[0077] In one embodiment, the data to be processed can be obtained from the network. If the data to be processed is encrypted data, it is decrypted to obtain decrypted data; based on the bus address space allocated to the first slave device, the decrypted data is written to the storage component of the first slave device via a first high-speed serial computer expansion bus standard link. In another embodiment, the data to be processed can be obtained from the network. If the data to be processed is compressed data, it is decompressed to obtain decompressed data; based on the bus address space allocated to the first slave device, the decompressed data is written to the storage component of the first slave device via a first high-speed serial computer expansion bus standard link. In one embodiment, the data to be processed can be obtained and parsed by a network module, specifically a RoCE (i.e., RDMA over Converged Ethernet) module, and the data to be processed can be decrypted and decompressed by an acceleration core module to obtain decompressed data, which is then encrypted in the bus address space allocated to the first slave device, and the decompressed data is written to the storage component of the first slave device via a first high-speed serial computer expansion bus standard link. The storage component can be GDDR. The data to be processed may be data sent by a remote management and control platform, data sent by other master devices, or data sent by other slave devices with a network sending function.

[0078] It can be understood that the master field programmable logic gate array device is the master device, and the master device is a field programmable logic gate array device. The embodiment of the present application can detect the in-place slave device and allocate a bus address space to each in-place slave device to complete the in-place device registration; and the master device allocates a bus address space to each local module. The slave device allocates a bus address space to each module of the slave device itself based on the bus address space allocated by the master device. Specifically, different bus address spaces and base addresses of registers and memories can be allocated to each module. The mapping relationship of the storage resources in the slave device on the bus is: starting from the base address obtained on the master device bus, it is the configuration space register, BAR register and GDDR memory resources in sequence. The mapping relationship of the storage resources inside the master device on the bus is: starting from the base address, it is the configuration space register, BAR register space and GDDR memory resources in sequence. Registers and GDDR memory resources correspond to modules.

[0079] In the embodiment of the present application, all slave devices can use universal PCIe accelerator cards, such as graphics processor accelerator cards or field programmable gate array accelerator cards. That is, the first slave device is a graphics processor accelerator card or a field programmable gate array accelerator card. FPGA is a highly programmable multi-heterogeneous chip with rich hardware resources inside, such as lookup tables, registers, DSP (Digital Signal Processing) cores, AI (Artificial Intelligence) cores, PCIe HIP (Hard Intellectual Property), high-speed Serdes (serializers and deserializers) and bus interconnection resources, etc. Users can use these resources to implement various data processing engines, complex bus protocols and network protocols, etc. GPU is a dedicated graphics processing chip, which has been used for graphics and image processing in the early days and is currently widely used in the field of AI artificial intelligence computing. It is also an important computing chip. Currently, GPUs are PCIe devices plugged into data center server slots and typically communicate with hosts and other nodes via PCIe. While flexible and high-speed NVLink (a bus and its communication protocol) is available for inter-GPU communication, this technology is limited to intra-node GPU communication and prevents GPUs from directly connecting to external data center networks. RoCE is a reliable transport protocol that leverages converged Ethernet networks to enable direct access to local and remote memory. It reduces the overhead on the host CPU during data movement, freeing the CPU to manage only the control plane.

[0080] In a specific embodiment, the slave device is directly connected to the PCIe slot of the master device via a PCIe link and an SMBUS (i.e., System Management Bus) bus. The master FPGA device has multiple PCIe rootcomplex mode PCIe HIP hard cores, out-of-band supervision modules, link initialization modules, address allocation and conversion modules, GDDR controllers (i.e., video memory controllers), DMA (i.e., direct data access) engines, RoCE protocol stacks (i.e., network modules), MAC controllers (i.e., media access controllers), and acceleration cores. The PCIe-based GPU slave device chip typically has a computing core, a GDDR controller, a PCIe HIP, a BAR (i.e., base address register, base address register), and a Copy (data movement) engine, etc. The board also has an out-of-band management I2C (i.e., Inter-Integrated Circuit, a bidirectional two-wire synchronous serial bus) channel. For example, see Figure 4, which is a schematic diagram of a specific slave device provided in an embodiment of the present application. See Figure 5, which is a schematic diagram of a specific master device provided in an embodiment of the present application.

[0081] Among them, the master device of the present application specifically includes the following modules: an out-of-band supervision module connects to the slave device through the I2C bus and reads and writes the slave device register to obtain the status data of the slave device to monitor and manage the slave device; two PCIe HIPs work in PCIe rootcomplex mode and connect to the slave device PCIe HIP. It should be pointed out that PCIe HIP0 (i.e. hard core intellectual property 0) and PCIe HIP1 (i.e. hard core intellectual property 1) are used as examples in the figure. The PCIe HIP can be expanded according to the number of slave devices actually in place; the link initialization module converts the configuration space register read and write commands into standard PCIe TLP (i.e. Transaction Layer Packet, transaction layer) package completes the enumeration of PCIe from the device and configuration space register configuration; the bus address allocation and conversion module connects the control status register interface of each module and the GDDR controller and DMA engine, and allocates registers, different memory address spaces and base addresses to each module; the network protocol module that supports RoCEv2 has the function of remote direct memory data movement with heterogeneous devices in other nodes, and ensures high-bandwidth and reliable network communication between the FPGA card and the remote management and control platform and other FPGA cards; the MAC controller module is mainly responsible for sending and receiving network data packets; the GDDR controller is a high-performance video memory controller, and the video memory it controls has a higher operating frequency, heat generation and smaller size; the DMA engine receives and processes the load data in the TLP packet from the slave device, caches it in the master device GDDR, or sends it to the acceleration core processing or sends it to other node devices through the RoCE network. Similarly, data from the master device's GDDR, acceleration core, or RoCE network can be sent to the slave device via the DMA engine and PCIe HIP. The acceleration core can be an algorithm core implemented in hardware using some FPGA logic resources, such as encryption and decryption, compression and decompression, and can process data from the slave device's DMA, the RoCE network, and local GDDR. Numbers 1 to 16 represent transmission paths. For example, number 1 represents the transmission path between the out-of-band supervision module and the link initialization module.

[0082] Referring to FIG6 , FIG6 is a schematic diagram of a mapping relationship of the hardware storage resources of a slave device GPU card on the 64-bit bus of a master device provided by an embodiment of the present application, wherein, starting from the base address 0x1000_0000_0000_0000 obtained on the master device bus, the configuration space register, the BAR register, and the GDDR memory resources are sequentially provided. Referring to FIG7 , FIG7 is a schematic diagram of a mapping relationship of the internal storage resources of a master FPGA device on the bus provided by an embodiment of the present application, wherein, starting from the base address 0x0, the configuration space register, the BAR register space, and the GDDR memory resources are sequentially provided. Referring to FIG8 , FIG8 is a schematic diagram of a mapping relationship of the storage resources of multiple slave devices on the master device FPGA bus provided by an embodiment of the present application, wherein, from low to high, the local resource mapping of the master device and the resource mapping of each slave device are sequentially provided.

[0083] Further, referring to Figure 9, Figure 9 is a device registration flow chart provided by an embodiment of the present application. Taking the GPU card of the slave device in the node as an example, the system power-on initialization, slave device registration and slave device PCIe configuration space initialization, and storage resource mapping process are as follows: power-on initialization of the master device, triggered by the master device, power-on initialization of the slave device, the slave device can be a GPU card or an FPGA card, and judge whether the link with the in-place slave device is successful, that is, whether a physical layer connection is established with the in-place slave device. If the physical layer connection with the in-place slave device fails, the number of failures is counted. If the physical layer connection with the in-place slave device is successful, the configuration space is scanned and the register is read and written. The memory size required for the BAR register can be obtained, and then the bus address space is registered. After that, the bus address space registered by the newly added slave device is broadcast, that is, the allocated bus address space, is written to the designated space of the mounted GDDR, and the in-place slave device and the remote platform update the bus address space.

[0084] Furthermore, the present application can implement sending an interrupt data packet to notify the first slave device to process the pending data. In a specific embodiment, the interrupt data packet can be written to a designated register of the first slave device based on a mapping relationship between registers in the first slave device and the master field programmable logic gate array device bus to notify the first slave device to process the pending data.

[0085] Step S12: Acquire result data sent by the first slave device.

[0086] Step S13: Determine the destination address of the result data. If the destination address points to a storage space of the second slave device, write the result data to the storage component of the second slave device via a second high-speed serial computer expansion bus standard link. The second slave device is a graphics processor accelerator card or a field programmable gate array accelerator card.

[0087] Furthermore, if the destination address points to the storage space of the local device, the result data is written into the local storage component.

[0088] In addition, if the destination address points to a local network module, the result data is sent to the network module and then sent to the network through the network module.

[0089] Furthermore, if the destination address points to a local acceleration core module, the result data is sent to the acceleration core module, and the acceleration core module calls a preset processing logic to process the result data.

[0090] Moreover, in a specific implementation, the data processing type can be determined based on the descriptor corresponding to the result data; accordingly, the result data is processed by calling the preset processing logic through the acceleration core module, including: processing the result data by calling the preset processing logic corresponding to the data processing type through the acceleration core module.

[0091] Among them, if the data processing type is encryption processing, the encryption processing logic is called by the acceleration core module to encrypt the result data; if the data processing type is compression processing, the compression processing logic is called by the acceleration core module to compress the result data; if the data processing type is compression processing first and then encryption processing, the compression processing logic is called by the acceleration core module to compress the result data to obtain compressed data, and the encryption processing logic is called to encrypt the compressed data.

[0092] That is, in the implementation of this application, the descriptor describes the next operation for the result data, and the result data can be forwarded and the next operation can be performed based on the descriptor and the destination address.

[0093] In one embodiment, after sending an interrupt data packet to notify the first slave device, the embodiment of the present application may further, upon receiving the notification sent by the first slave device, read result data from the storage component of the first slave device; wherein the result data is stored by the first slave device into the storage component of the first slave device. That is, the first slave device processes the data to be processed, obtains the result data, and then stores the result data from the first slave device into the storage component of the first slave device. wherein the result data is read from the storage component of the first slave device using a direct data access engine.

[0094] After reading the result data from the storage component of the first slave device, the result data can be cached in the storage component of the local device. Furthermore, the result data can be compressed using the acceleration core module to obtain compressed data, and the compressed data can be encrypted to obtain encrypted data. The encrypted data can then be encapsulated using the network module and sent to other nodes via the optical network.

[0095] That is, in a specific implementation, after obtaining the result data, the slave device may notify the master device to read from the slave device, or may send the result data to the master device.

[0096] It can be understood that in the embodiment of the present application, the PCIe slave device is initialized and registered in the master device to complete the address mapping of the storage resources. In addition, the out-of-band supervision module formed by the I2C channel in the master device can monitor and manage the slave device and the master device. Convert from the internal bus interface to a standard format TLP packet. In addition, a DMA controller is contained between the slave device and the master device. When one party performs a DMA operation, it does not affect the normal DMA operation of the other party; when the master device FPGA communicates with other node devices through the RoCE network, encryption and decryption, compression and decompression operations are performed locally to ensure data communication security, reduce communication volume, and reduce communication delays; the source or destination of the data processed by the master device DMA engine can be a slave device cache, a local cache, or it can be from or sent to the RoCE module and the acceleration core module for further processing, and different descriptors can be used to mark and distinguish. Further, in conjunction with Figure 5, the master device provided by the present application, wherein the DMA engine, the acceleration core, and the RoCE module support a variety of data stream processing combinations, and several achievable data processing flows are further listed below:

[0097] 1. After the data to be processed is parsed from the RoCE (network module), it is first decrypted by the acceleration core and stored in the master device's GDDR via path 12. It is then read from the GDDR and decompressed by the acceleration core. After decompression, it is sent to PCIe HIP0 via the DMA engine along paths 11 and 9. It is written to the GDDR of slave device 0 (GPU card) corresponding to PCIe HIP0, and an interrupt TLP packet is sent to notify the GPU card for processing. Specifically, the TLP packet sent by the DMA engine is sequentially packaged by the bus address allocation and conversion module and the link initialization module to obtain a write packet for the specified register. The packet is then written to the specified register of the GPU card, sequentially passing through paths 5, 4, and 2 in Figure 5.

[0098] 2. After the slave device 0 GPU card processes the data, it writes to the Doorbell register to notify the DMA engine in the master FPGA device to read the result in its GDDR (through paths 2, 4, and 5 in Figure 5). After receiving the data, the DMA engine first caches it in the master device GDDR, compresses it by the acceleration core, reads it to the acceleration core for encryption, and sends it to the RoCE module for encapsulation. It is then sent to other nodes via the optical network (through path 16 and the media access controller to other nodes).

[0099] 3. The DMA engine can perform the next operation based on the descriptor and destination address of the data packet sent from the GPU card of device 0. If the address points to the storage space of slave device 1, the TLP packet header related information is modified and forwarded to slave device 1 through the DMA engine. Specifically, the data is obtained through PCIE HIP0 and forwarded to slave device 1 through PCIE HIP0 (through paths 9 and 10); if the address points to the storage space of the local device, the local storage GDDR is written through the DMA engine (through paths 9 and 11); if the address points to RoCE or the acceleration core, the packet is sent to the RoCE module through the DMA engine and sent to the network (through paths 9, 13, and 16) or to the acceleration core for further processing (through paths 9 and 15).

[0100] It should be pointed out that in the embodiment of the present application, all slave devices can use FPGA acceleration cards, or some can use GPU acceleration cards and some can use FPGA acceleration cards, thereby forming a heterogeneous acceleration system; when using GPU cards or FPGA cards, the GPU cards or FPGA cards are independent of the traditional Host motherboard, and directly communicate with the master device FPGA as an endpoint (slave device) through the PCIe link to complete the enumeration, configuration and initialization of the GPU card or FPGA card as a slave device, which can reduce the coupling degree between the GPU card or FPGA card and the server; it does not rely on the CPU, memory and PCIe-related chipset of the HOST, reducing the indirect overhead cost of these resources when users use GPU or FPGA resources; the communication between devices in this application adopts mature and universal PCIe links and PCIe-based links. The supported protocol direct communication has high flexibility and lower communication delay; a single master device FPGA of the present application can support connection with multiple GPU cards or FPGA cards through PCIe, and all storage resources (in-band BAR registers, in-band cache) on each slave device are mapped to the internal interconnection bus of the master device, so that the master device can schedule and use the resources of the slave device; the master device FPGA of the present application can communicate with the slave device through the out-band I2C channel through the out-band supervision module to monitor and manage the status of the slave device; before being transmitted to the GPU card and after being output from the GPU card, the data can be secondary processed (such as encryption and decryption, compression and decompression) in the FPGA card, and then sent to the next-level processing module or sent out through the optical port, thereby improving data transmission security, reducing communication volume and communication delay; the DMA engine module of the present application can forward TLP packets to other slave devices according to the PCIe TLP packet address, or store them in the master device GDDR, or encapsulate them through the RoCE protocol and forward them to other node devices through the optical network.

[0101] In this way, slave devices are connected via multiple PCIe interfaces within a master device (which can be an FPGA accelerator card), reducing the coupling between PCIe-based slave devices and server motherboards. This allows for flexible slave device initialization, registration, and address mapping. The DMA engine connects multiple modules within the master and slave devices, enabling flexible data processing. This effectively reduces inter-device communication latency, significantly improves the ability to expand communication with adjacent nodes, significantly reduces the deployment cost of heterogeneous systems using PCIe-based devices, and provides a new computing acceleration platform for distributed applications. This addresses the issues of high latency in cross-node inter-GPU communication during GPU-based AI training in modern data centers, reliance on server CPUs, memory, and PCIe chipsets, and high hardware resource overhead during data transmission.

[0102] As shown in FIG10 , an embodiment of the present application discloses a data processing device, which is applied to a master field programmable gate array device, including:

[0103] The module 11 for writing data to be processed is used to write the data to be processed into the storage component of the first slave device based on the bus address space allocated to the first slave device and through the first high-speed serial computer expansion bus standard link, so that the first slave device processes the data to be processed and obtains result data;

[0104] A result data acquisition module 12, configured to acquire result data sent by the first slave device;

[0105] The result data forwarding module 13 is used to determine the destination address of the result data, and if the destination address points to the storage space of the second slave device, write the result data into the storage component of the second slave device through the second high-speed serial computer expansion bus standard link.

[0106] As can be seen, the embodiment of the present application is applied to a master field programmable logic gate array device, which, based on the bus address space allocated to the first slave device, writes the data to be processed into the storage component of the first slave device via a first high-speed serial computer expansion bus standard link, so that the first slave device processes the data to be processed and obtains result data, then obtains the result data sent by the first slave device, determines the destination address of the result data, and if the destination address points to the storage space of the second slave device, writes the result data into the storage component of the second slave device via a second high-speed serial computer expansion bus standard link. In other words, the master field programmable logic gate array device in the embodiment of the present application allocates bus address space to the slave device, writes the data to be processed into the storage component of the first slave device based on the bus address space allocated to the first slave device via a first high-speed serial computer expansion bus standard link, obtains the result data obtained by processing the data to be processed sent by the first slave device, and if the destination address of the result data points to the storage space of the second slave device, writes the result data into the storage component of the second slave device via a second high-speed serial computer expansion bus standard link. In this way, the bus address space is allocated to the slave device through the master field programmable logic gate array device to realize cross-node communication of the slave device. The slave device can be a graphics processor accelerator card or a field programmable logic gate array accelerator card, which reduces the coupling between the slave device and the server and can reduce cross-node communication delay and hardware resource overhead.

[0107] The apparatus further includes an interrupt notification module, which is used to send an interrupt data packet to notify the first slave device to process the data to be processed.

[0108] The interrupt notification module is specifically configured to write an interrupt data packet into a designated register of the first slave device based on a mapping relationship between registers in the first slave device and the master field programmable logic gate array device bus, so as to notify the first slave device to process the pending data.

[0109] The result data forwarding module 13 is further configured to write the result data to a local storage component if the destination address points to a storage space of a local device. If the destination address points to a local network module, the result data is sent to the network module and then transmitted to the network via the network module. If the destination address points to a local acceleration core module, the result data is sent to the acceleration core module, and the acceleration core module calls preset processing logic to process the result data.

[0110] Furthermore, the result data forwarding module 13 is further configured to determine a data processing type based on the descriptor corresponding to the result data; and to process the result data by invoking the preset processing logic corresponding to the data processing type via the acceleration core module. Specifically, if the data processing type is encryption, the acceleration core module invokes the encryption processing logic to encrypt the result data; if the data processing type is compression, the acceleration core module invokes the compression processing logic to compress the result data; and if the data processing type is compression first, then encryption, the acceleration core module invokes the compression processing logic to compress the result data to obtain compressed data, and then invokes the encryption processing logic to encrypt the compressed data.

[0111] Furthermore, the apparatus also includes a data reading module, which is specifically used to read result data from the storage component of the first slave device when a notification sent by the first slave device is obtained; wherein the result data is stored from the first slave device into the storage component of the first slave device.

[0112] In addition, the apparatus further includes a data cache module for caching the result data in the storage component of the local device after reading the result data from the storage component of the first slave device. Furthermore, the apparatus further includes an acceleration core module for compressing the result data to obtain compressed data and encrypting the compressed data to obtain encrypted data; and a network module for encapsulating the encrypted data and transmitting it to other nodes via an optical network.

[0113] The data reading module is specifically configured to read result data from the storage component of the first slave device using a direct data access engine.

[0114] In addition, the device also includes a slave device registration and bus address space allocation module, which is used to discover the slave devices in place and allocate bus address space to each slave device in place to complete the registration of the slave devices in place; and allocate bus address space to each local module.

[0115] The first slave device is a graphics processor accelerator card or a field programmable gate array accelerator card, and the second slave device is a graphics processor accelerator card or a field programmable gate array accelerator card.

[0116] In one embodiment, the module 11 for writing data to be processed is specifically used to obtain data to be processed from the network, and if the data to be processed is encrypted data, decrypt it to obtain decrypted data; based on the bus address space allocated to the first slave device, and through the first high-speed serial computer expansion bus standard link, the decrypted data is written into the storage component of the first slave device.

[0117] In another embodiment, the data to be processed writing module 11 is specifically used to obtain the data to be processed from the network, and if the data to be processed is compressed data, decompress it to obtain decompressed data; based on the bus address space allocated to the first slave device, and through the first high-speed serial computer expansion bus standard link, the decompressed data is written into the storage component of the first slave device.

[0118] As shown in Figure 11, an embodiment of the present application discloses an electronic device 20, including a processor 21 and a memory 22; wherein the memory 22 is used to store computer programs; the processor 21 is used to execute computer programs, and the data processing method disclosed in the above embodiment.

[0119] For the specific process of the above data processing method, please refer to the corresponding content disclosed in the above embodiments, which will not be repeated here.

[0120] Furthermore, the memory 22 as a carrier for resource storage may be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the storage method may be temporary storage or permanent storage.

[0121] In addition, the electronic device 20 also includes a power supply 23, a communication interface 24, an input / output interface 25 and a communication bus 26; wherein the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0122] Furthermore, an embodiment of the present application also discloses a computer non-volatile readable storage medium for storing a computer program, wherein the computer program implements the data processing method disclosed in the aforementioned embodiment when executed by a processor.

[0123] For the specific process of the above data processing method, please refer to the corresponding content disclosed in the above embodiments, which will not be repeated here.

[0124] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0125] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0126] The above is a detailed introduction to a data processing method, device, equipment and medium provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present application.

Claims

1. A data processing method, characterized in that: Applicable to main FPGA devices, including: Based on the bus address space allocated to the first slave device, the data to be processed is written into the storage component of the first slave device through a first high-speed serial computer expansion bus standard link, so that the first slave device processes the data to be processed to obtain result data; Acquire the result data sent by the first slave device; The destination address of the result data is determined, and if the destination address points to the storage space of the second slave device, the result data is written into the storage component of the second slave device through a second high-speed serial computer expansion bus standard link.

2. The data processing method according to claim 1, characterized in that: After the process writes the to-be-processed data into the storage component of the first slave device through the first high-speed serial computer expansion bus standard link based on the bus address space allocated to the first slave device, the process further includes: An interrupt data packet is sent to notify the first slave device to process the data to be processed.

3. The data processing method according to claim 2, characterized in that: The sending of the interruption data packet to notify the first slave device to process the data to be processed includes: The interrupt data packet is written into a designated register of the first slave device based on a mapping relationship between the register in the first slave device and the master field programmable logic gate array device bus, so as to notify the first slave device to process the data to be processed.

4. The data processing method according to claim 1, characterized in that: Also includes: If the destination address points to the storage space of the local device, the result data is written into the local storage component.

5. The data processing method according to claim 1, characterized in that: Also includes: If the destination address points to a local network module, the result data is sent to the network module, and then sent to the network through the network module.

6. The data processing method according to claim 1, characterized in that: Also includes: If the destination address points to a local acceleration core module, the result data is sent to the acceleration core module, and the acceleration core module calls a preset processing logic to process the result data.

7. The data processing method according to claim 6, characterized in that: Also includes: Determining a data processing type based on a descriptor corresponding to the result data; Correspondingly, the processing of the result data by calling the preset processing logic through the acceleration core module includes: processing the result data by calling the preset processing logic corresponding to the data processing type through the acceleration core module.

8. The data processing method according to claim 7, characterized in that: The processing of the result data by calling the preset processing logic corresponding to the data processing type through the acceleration core module includes: If the data processing type is encryption processing, the encryption processing logic is called by the acceleration core module to encrypt the result data; If the data processing type is compression processing, the compression processing logic is called by the acceleration core module to compress the result data; If the data processing type is compression processing first and encryption processing later, the acceleration core module calls the compression processing logic to compress the result data to obtain compressed data, and calls the encryption processing logic to encrypt the compressed data.

9. The data processing method according to claim 1, characterized in that: After sending the interrupt data packet to notify the first slave device, the method further includes: When the notification sent by the first slave device is obtained, reading the result data from the storage component of the first slave device; The result data is stored by the first slave device into a storage component of the first slave device.

10. The data processing method according to claim 9, characterized in that: After reading the result data from the storage component of the first slave device, the method further includes: The result data is cached in a storage component of a local device.

11. The data processing method according to claim 10, characterized in that: Also includes: The result data is compressed by using an acceleration core module to obtain compressed data, and the compressed data is encrypted to obtain encrypted data.

12. The data processing method according to claim 11, characterized in that: After the compressed data is encrypted to obtain the encrypted data, the following steps are also included: The encrypted data is encapsulated using the network module and sent to other nodes through the optical network.

13. The data processing method according to claim 9, characterized in that: The reading the result data from the storage component of the first slave device comprises: The result data is read from the storage component of the first slave device using a direct data access engine.

14. The data processing method according to claim 1, characterized in that: Also includes: Discover the slave devices in place and allocate bus address space to each slave device in place to complete the registration of the slave devices in place; Allocate bus address space for each local module.

15. The data processing method according to claim 1, characterized in that: The first slave device is a graphics processor accelerator card or a field programmable gate array accelerator card, and the second slave device is a graphics processor accelerator card or a field programmable gate array accelerator card.

16. The data processing method according to any one of claims 1 to 15, characterized in that: The method of writing the to-be-processed data into the storage component of the first slave device through a first high-speed serial computer expansion bus standard link based on the bus address space allocated to the first slave device comprises: Obtain the data to be processed from the network, and if the data to be processed is encrypted data, decrypt it to obtain the decrypted data; The decrypted data is written into the storage component of the first slave device based on the bus address space allocated to the first slave device and through a first high-speed serial computer expansion bus standard link.

17. The data processing method according to any one of claims 1 to 15, characterized in that: The method of writing the to-be-processed data into the storage component of the first slave device through a first high-speed serial computer expansion bus standard link based on the bus address space allocated to the first slave device comprises: Obtain the data to be processed from the network, and if the data to be processed is compressed data, decompress it to obtain the decompressed data; Based on the bus address space allocated for the first slave device, the decompressed data is written into the storage component of the first slave device via a first high-speed serial computer expansion bus standard link.

18. A data processing device, characterized in that: Applicable to main FPGA devices, including: a module for writing data to be processed, used for writing the data to be processed into the storage component of the first slave device based on the bus address space allocated to the first slave device and through the first high-speed serial computer expansion bus standard link, so that the first slave device processes the data to be processed and obtains result data; A result data acquisition module, used for acquiring the result data sent by the first slave device; The result data forwarding module is used to determine the destination address of the result data, and if the destination address points to the storage space of the second slave device, write the result data into the storage component of the second slave device through a second high-speed serial computer expansion bus standard link.

19. An electronic device, characterized in that: comprising a memory and a processor, wherein: The memory is used to store the computer program; The processor is used to execute the computer program to implement the data processing method according to any one of claims 1 to 17.

20. A computer non-volatile readable storage medium, characterized in that: Used to store a computer program, wherein when the computer program is executed by a processor, the data processing method according to any one of claims 1 to 17 is implemented.

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