High-speed serial computer expansion bus standard terminal equipment and its clock distribution circuit

Abstract

This invention discloses a high-speed serial computer extended bus standard terminal device and its clock distribution circuit, belonging to the field of integrated circuit design. When the level conversion circuit receives a "dual-port enable signal from the host", it can control the multiplexer to work in dual-port mode, thereby leading the two reference clocks of the host to the first physical medium sublayer and the second physical medium sublayer respectively. When the dual-port enable signal is not received, it can control the multiplexer to work in single-port mode, so that the reference clock provided by the host through the first output terminal can be synchronously output through the two output terminals of the multiplexer, thereby keeping the two reference clocks synchronized and not affecting the collaborative work of the two physical medium sublayers. Moreover, the forwarding processing performed by the multiplexer does not affect the reference clock quality. In addition, the host can accurately control the working mode of the PCIe terminal device through the dual-port enable signal.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to a high-speed serial computer extended bus standard terminal device and its clock distribution circuit. Background Technology

[0002] A dual-port PCIe (Peripheral Component Interconnect express) device has two independent PAMs (Physical Medium Attachment) within its PCIe controller. This allows the dual-port device to operate in both dual-port and single-port modes. In dual-port mode, a single PAM can be considered an independent PCIe terminal device, capable of independently receiving PCIe signals from the host. In single-port mode, the host provides a reference clock to one PAM within the PCIe controller. The processing unit within the PCIe controller then converts and distributes this reference clock to the other PAM. However, this "conversion and distribution" process by the processing unit not only introduces latency, affecting the coordinated operation of the two PAMs, but may also degrade the quality of the reference clock.

[0003] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a high-speed serial computer extended bus standard terminal device and its clock distribution circuit. In the single-port mode of the PCIe terminal device, the multiplexer can synchronously output the reference clock provided by the host through the first output terminal through the two output terminals of the multiplexer, thereby keeping the two reference clocks synchronized and not affecting the collaborative work of the two physical media sublayers. Furthermore, the forwarding processing performed by the multiplexer does not affect the quality of the reference clock. In addition, the host can accurately control the working mode of the PCIe terminal device through the dual-port enable signal.

[0005] To solve the above-mentioned technical problems, the present invention provides a clock distribution circuit, including a multi-channel clock selector and a level conversion circuit;

[0006] The first output of the multiplexer is connected to the clock input of the first physical medium sublayer, the second output of the multiplexer is connected to the clock input of the second physical medium sublayer, the first input of the multiplexer is connected to the first output of the host, the second input of the multiplexer is connected to the second output of the host, the control terminal of the multiplexer is connected to the output of the level conversion circuit, and the input of the level conversion circuit is connected to the third output of the host.

[0007] Among them, the first physical medium sublayer and the second physical medium sublayer belong to the same high-speed serial computer expansion bus standard controller, and the first output terminal and the second output terminal of the host are both used to output the reference clock.

[0008] A multiplexer clock selector is used to connect its first input terminal to its first output terminal and its second input terminal to its second output terminal when it receives a first level. When it receives a second level, it outputs the reference clock received by its first input terminal synchronously through its first output terminal and second output terminal.

[0009] The level conversion circuit is used to output a first level when a dual-port enable signal is received, and to output a second level when a dual-port enable signal is not received.

[0010] On the other hand, the multiple clock selector and the level conversion circuit are both located on the motherboard of the high-speed serial computer expansion bus standard terminal device.

[0011] The clock distribution circuit also includes first to twelfth connection terminals and four electrical connection devices disposed on the motherboard of the high-speed serial computer expansion bus standard terminal device;

[0012] The first connection terminal is used to connect to the first output terminal of the host, the second connection terminal is connected to the fifth connection terminal, the third connection terminal is connected to the first input terminal of the multiplexer, the fourth connection terminal is connected to the clock input terminal of the first physical media sublayer, the sixth connection terminal is connected to the first output terminal of the multiplexer, the seventh connection terminal is used to connect to the second output terminal of the host, the eighth connection terminal is connected to the eleventh connection terminal, the ninth connection terminal is connected to the second input terminal of the multiplexer, the tenth connection terminal is connected to the clock input terminal of the second physical media sublayer, and the twelfth connection terminal is connected to the second output terminal of the multiplexer.

[0013] Any one of the first, fourth, seventh, and tenth connection terminals is used to establish an electrical connection with an adjacent connection terminal via a corresponding electrical connection device.

[0014] On the other hand, the electrical connection device includes a zero-ohm resistor or a jumper cap.

[0015] On the other hand, the level conversion circuit includes a processor;

[0016] The clock distribution circuit also includes a prompter;

[0017] The processor is configured to output a first level when a dual-port enable signal is received, and output a second level when a dual-port enable signal is not received; the control prompt indicates whether a dual-port enable signal has been received.

[0018] On the other hand, the clock distribution circuit also includes a first voltage monitoring module;

[0019] The first voltage monitoring module is used to detect the first voltage value at the second input terminal of the multi-channel clock selector;

[0020] The processor is also configured to, when not receiving a dual-port enable signal, determine whether there is a reference clock at the second input terminal of the multiplexer based on the first voltage value; if there is, control the prompt to indicate a reference clock error.

[0021] On the other hand, the clock distribution circuit also includes a second voltage monitoring module:

[0022] The second voltage monitoring module is used to detect the second voltage value at the first input terminal of the multi-channel clock selector;

[0023] The processor is further configured to, upon receiving a dual-port enable signal, determine whether a reference clock exists at the second input terminal of the multiplexer based on the first voltage value, determine whether a reference clock exists at the first input terminal of the multiplexer based on the second voltage value, and, if no reference clock exists at any input terminal of the multiplexer, control the prompt to indicate a reference clock error.

[0024] On the other hand, the level conversion circuit includes a controllable switch, a power supply, a first resistor, and a second resistor;

[0025] The control terminal of the controllable switch is connected to the third output terminal of the host, the second terminal of the controllable switch is grounded, and the common terminal formed by the first terminal of the controllable switch, the first terminal of the first resistor, and the first terminal of the second resistor serves as the output terminal of the level conversion circuit. The second terminal of the first resistor is connected to the power supply, and the second terminal of the second resistor is grounded.

[0026] The controllable switch is used to turn off its first and second terminals when the control terminal receives a dual-port enable signal, and otherwise connect its first and second terminals.

[0027] On the other hand, the level conversion circuit also includes a filtering module;

[0028] The first terminal of the filter module is connected to a common terminal formed by the first terminal of the controllable switch, the first terminal of the first resistor, and the first terminal of the second resistor, and the second terminal of the filter module is grounded.

[0029] The filtering module is used to filter the voltage between the first resistor and the second resistor.

[0030] On the other hand, the dual-port enable signal is at a low level;

[0031] The controllable switch includes an N-channel metal-oxide-semiconductor field-effect transistor.

[0032] To solve the above-mentioned technical problems, the present invention also provides a high-speed serial computer expansion bus standard terminal device, including a circuit board and a dual-port high-speed serial computer expansion bus standard controller, and further including the clock distribution circuit as described above connected to the dual-port high-speed serial computer expansion bus standard controller;

[0033] The dual-port high-speed serial computer expansion bus standard controller and the clock distribution circuit are mounted on the circuit board.

[0034] Beneficial Effects: This invention provides a clock distribution circuit. Considering that in single-port mode, "leading a single reference clock to the same device and then outputting it synchronously through two ports" can output two synchronous reference clocks, the clock distribution circuit of this application includes a multi-channel clock selector and a level conversion circuit. When the level conversion circuit receives a "dual-port enable signal from the host," it can control the multi-channel clock selector to work in dual-port mode, thereby leading the two reference clocks of the host to the first physical medium sublayer and the second physical medium sublayer respectively. When the dual-port enable signal is not received, it can control the multi-channel clock selector to work in single-port mode, allowing the reference clock provided by the host through the first output terminal to be output synchronously through the two output terminals of the multi-channel clock selector, thus keeping the two reference clocks synchronized without affecting the collaborative work of the two physical medium sublayers. Furthermore, the forwarding processing performed by the multi-channel clock selector does not affect the reference clock quality. In addition, the host can accurately control the working mode of the PCIe terminal device through the dual-port enable signal.

[0035] The present invention also provides a high-speed serial computer extended bus standard terminal device, which has the same beneficial effects as the clock distribution circuit described above. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention, the relevant technologies and the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A schematic diagram of a clock distribution circuit provided by the present invention;

[0038] Figure 2 This is a schematic diagram of signal connection in the dual-port mode of related technologies;

[0039] Figure 3 This is a schematic diagram of signal connections in single-port mode in related technologies;

[0040] Figure 4 A schematic diagram of another clock distribution circuit provided by the present invention;

[0041] Figure 5 This is a schematic diagram of a level conversion circuit provided by the present invention. Detailed Implementation

[0042] The core of this invention is to provide a high-speed serial computer extended bus standard terminal device and its clock distribution circuit. In the single-port mode of the PCIe terminal device, the multiplexer can synchronously output the reference clock provided by the host through the first output terminal through the two output terminals of the multiplexer, thereby keeping the two reference clocks synchronized and not affecting the collaborative work of the two physical media sublayers. Furthermore, the forwarding processing performed by the multiplexer does not affect the quality of the reference clock. In addition, the host can accurately control the working mode of the PCIe terminal device through the dual-port enable signal.

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a clock distribution circuit provided by the present invention. The clock distribution circuit includes a multi-channel clock selector 1 and a level conversion circuit 2.

[0045] The first output terminal of the multiplexer 1 is connected to the clock input terminal of the first physical medium sublayer, the second output terminal of the multiplexer 1 is connected to the clock input terminal of the second physical medium sublayer, the first input terminal of the multiplexer 1 is connected to the first output terminal of the host, the second input terminal of the multiplexer 1 is connected to the second output terminal of the host, the control terminal of the multiplexer 1 is connected to the output terminal of the level conversion circuit 2, and the input terminal of the level conversion circuit 2 is connected to the third output terminal of the host.

[0046] Among them, the first physical medium sublayer and the second physical medium sublayer belong to the same high-speed serial computer expansion bus standard controller, and the first output terminal and the second output terminal of the host are both used to output the reference clock.

[0047] The multiplexer 1 is used to connect its first input terminal to its first output terminal and its second input terminal to its second output terminal when it receives a first level, and to output the reference clock received by its first input terminal synchronously through its first output terminal and second output terminal when it receives a second level.

[0048] Level conversion circuit 2 is used to output a first level when a dual-port enable signal is received, and to output a second level when a dual-port enable signal is not received.

[0049] For a better explanation of the embodiments of the present invention, please refer to Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of signal connection in a two-port mode in related technologies. Figure 3 This is a schematic diagram of signal connection in single-port mode in related technologies. Figure 2 In this configuration, the two PAMs operate independently. The reference clock of the first host is provided to the clock input of the first PAM. The first host and the first PAM transmit signals through the first and second channels. The reference clock of the second host is provided to the clock input of the second PAM. The second host and the second PAM transmit signals through the third and fourth channels. Figure 3 In this configuration, the two PAMs work as a whole. At this time, the first host provides a reference clock to the clock input of the first PAM. The processing unit in the PCIe controller converts and distributes the reference clock to the second PAM. The first host and the "first PAM and second PAM as a whole" transmit signals through the first to fourth channels.

[0050] Specifically, considering the technical problems mentioned in the background above, and considering that in single-port mode, "leading a single reference clock to the same device and then outputting it synchronously through two ports" can output two synchronous reference clocks, in this embodiment of the invention, it is intended to connect both outputs of the host to the two inputs of the multiplexer 1, and connect the two outputs of the multiplexer 1 to the clock inputs of the two physical media sublayers (i.e., PCIe modules) in the PCIe controller, thereby enabling the multiplexer 1 to forward the two reference clocks.

[0051] Specifically, based on the above structure, the dual-port enable signal sent by the host can be processed by the level conversion circuit 2 to control the multiplexer 1 to work in dual-port mode in conjunction with the PCIe controller of the PCIe terminal device. When the host does not send a dual-port enable signal, the level conversion circuit 2 can control the multiplexer 1 to work in single-port mode in conjunction with the PCIe controller of the PCIe terminal device through the output second level.

[0052] In dual-port mode, the multiplexer 1 can send the two received reference clocks one-to-one to the clock input of the physical medium sublayer. In single-port mode, the multiplexer 1 can receive the reference clock provided by the host through the first output through the first input and output the reference clock synchronously through its two outputs, so that the two physical medium sublayers can receive the reference clock synchronously. That is, in single-port mode, the two PAMs of the PCIe controller can receive one reference clock synchronously without any delay between the two PAMs, thereby improving the reliability of single-port mode. Moreover, the "copying and synchronous output" operation of the multiplexer for a single reference clock in single-port mode will not affect the signal quality of the reference clock, thus ensuring the quality of the reference clock.

[0053] Additionally, it is worth mentioning that the PCIe standard specifies that in single-port mode, the PCIe host provides a single reference clock through the output terminal with the smallest sequence number. Therefore, in this embodiment of the invention, the PCIe host can output the reference clock through the first output terminal in single-port mode.

[0054] The first level and the second level can be two levels with opposite high and low states, and this embodiment of the invention does not limit them.

[0055] Specifically, the multiplexer 1 can be of various types, such as a MUX (multiplexer), specifically the RC19202AGNT MUX, etc. This embodiment of the invention does not limit the specific type.

[0056] The clock distribution circuit of this application includes a multiplexer clock selector and a level conversion circuit. When the level conversion circuit receives a dual-port enable signal from the host, it can control the multiplexer clock selector to operate in dual-port mode, thereby directing the two reference clocks of the host to the first physical medium sublayer and the second physical medium sublayer respectively. When the dual-port enable signal is not received, it can control the multiplexer clock selector to operate in single-port mode, so that the reference clock provided by the host through the first output terminal can be synchronously output through the two output terminals of the multiplexer clock selector, thereby keeping the two reference clocks synchronized and not affecting the collaborative operation of the two physical medium sublayers. Moreover, the forwarding processing performed by the multiplexer clock selector does not affect the reference clock quality. In addition, the host can accurately control the operating mode of the PCIe terminal device through the dual-port enable signal.

[0057] Based on the above embodiments:

[0058] As an optional embodiment, both the multiplexer 1 and the level conversion circuit 2 are located on the motherboard of the high-speed serial computer expansion bus standard terminal device;

[0059] The clock distribution circuit also includes the first to twelfth connection terminals and four electrical connection devices located on the motherboard of the high-speed serial computer expansion bus standard terminal equipment;

[0060] The first connection terminal is used to connect to the first output terminal of the host, the second connection terminal is connected to the fifth connection terminal, the third connection terminal is connected to the first input terminal of the multiplexer 1, the fourth connection terminal is connected to the clock input terminal of the first physical media sublayer, the sixth connection terminal is connected to the first output terminal of the multiplexer 1, the seventh connection terminal is used to connect to the second output terminal of the host, the eighth connection terminal is connected to the eleventh connection terminal, the ninth connection terminal is connected to the second input terminal of the multiplexer 1, the tenth connection terminal is connected to the clock input terminal of the second physical media sublayer, and the twelfth connection terminal is connected to the second output terminal of the multiplexer 1.

[0061] Any one of the first, fourth, seventh, and tenth connecting terminals is used to establish an electrical connection between itself and an adjacent connecting terminal through a corresponding electrical connecting device.

[0062] Specifically, for a better explanation of the embodiments of the present invention, please refer to... Figure 4 , Figure 4 This is a schematic diagram of another clock distribution circuit provided by the present invention. Figure 4The 12 circular symbols containing the numbers 1 to 12 surrounding the multiplexer 1 represent the first to twelfth connection terminals. The serial numbers of the connection terminals (first to twelfth) are consistent with the numbers inside the circular symbols. The signal transmission scheme can be selected through these twelve connection terminals.

[0063] Specifically, in order to improve the simplicity of the connection between the PCIe terminal device and the PCIe host, the multi-channel clock selector 1 and the level conversion circuit 2 in this embodiment of the invention are both located on the motherboard of the PCIe terminal device.

[0064] Specifically, considering that some PCIe controllers have good design quality for the conversion and distribution of the reference clock, thus not increasing signal delay or reducing signal quality, theoretically, these PCIe controllers can forward the reference clock without using the multiplexer 1. Therefore, to meet this requirement, this embodiment of the invention also designs the first to twelfth connection terminals on the motherboard of the PCIe device. By connecting these terminals, two signal processing schemes can be selected. The first is the scheme described above that processes the signal using the multiplexer 1. The second is the traditional scheme that "directly connects the first output of the PCIe host to the clock input of the first PAM, and directly connects the second output of the PCIe host to the clock input of the second PAM, and the internal processing unit of the PCIe controller performs the conversion and distribution of the reference clock in single-port mode".

[0065] If the option "including multiple clock selector 1" is selected, the first connection terminal can be connected to the third connection terminal, the fourth connection terminal to the sixth connection terminal, the seventh connection terminal to the ninth connection terminal, and the tenth connection terminal to the twelfth connection terminal. If the option "excluding multiple clock selector 1" is selected, the first connection terminal can be connected to the second connection terminal, the fourth connection terminal to the fifth connection terminal, the seventh connection terminal to the eighth connection terminal, and the tenth connection terminal to the eleventh connection terminal.

[0066] As an alternative embodiment, the electrical connection device includes a zero-ohm resistor or a jumper cap.

[0067] Specifically, electrical connections to the terminals can be made using either zero-ohm resistors or jumper caps without affecting the transmission of the reference clock, and both methods offer advantages such as small size and low cost.

[0068] Of course, in addition to zero-ohm resistors and jumper caps, electrical connection devices can be of many other types, and this embodiment of the invention does not limit them.

[0069] As an optional embodiment, the level conversion circuit 2 includes a processor;

[0070] The clock distribution circuit also includes a prompter;

[0071] The processor is configured to output a first level when a dual-port enable signal is received, and output a second level when a dual-port enable signal is not received; the control indicator indicates whether a dual-port enable signal has been received.

[0072] Specifically, considering that the processor has level processing capabilities and is small and simple, the level conversion circuit 2 in this embodiment of the invention includes a processor. Furthermore, considering that in some situations staff need to know in real time whether the level conversion circuit 2 can normally receive the dual-port enable signal, the processor in this embodiment of the invention can also control a prompt to indicate whether the dual-port enable signal is currently received, so that staff can use the information prompted by the prompt to determine whether the processor can normally receive the dual-port enable signal and analyze the signal transmission path or whether the processor has a fault.

[0073] The prompter can be of various types, such as a display or a voice announcer, or the PCIe host can be used directly as the prompter. This embodiment of the invention does not limit the types of prompters.

[0074] As an optional embodiment, the clock distribution circuit further includes a first voltage monitoring module;

[0075] The first voltage monitoring module is used to detect the first voltage value at the second input terminal of the multiplex clock selector 1;

[0076] The processor is also used to determine whether there is a reference clock at the second input of the multiplexer 1 by using the first voltage value when no dual-port enable signal is received. If there is a reference clock, the processor will control the indicator to indicate that there is a reference clock error.

[0077] Specifically, considering that the PCIe host may incorrectly send a reference clock to the second input of the clock selector in single-port mode, in order to detect this situation in a timely manner, in this embodiment of the invention, in the case of single-port mode (that is, when the processor does not receive the dual-port enable signal), the first voltage value of the second input of the multiplexer 1 is used to determine whether there is a reference clock at the second input of the multiplexer 1. Under normal circumstances, it should not exist. If it exists, it means that the PCIe host is incorrectly outputting a reference clock, so the indicator can be controlled to indicate that the reference clock is incorrect.

[0078] The first voltage monitoring module can be of various types, such as a voltage divider circuit, etc., and this embodiment of the invention does not limit it.

[0079] As an optional embodiment, the clock distribution circuit also includes a second voltage monitoring module:

[0080] The second voltage monitoring module is used to detect the second voltage value at the first input terminal of the multiplex clock selector 1.

[0081] The processor is also configured to, upon receiving a dual-port enable signal, determine whether a reference clock exists at the second input of the multiplexer 1 based on a first voltage value, determine whether a reference clock exists at the first input of the multiplexer 1 based on a second voltage value, and, if no reference clock exists at any input of the multiplexer 1, control the prompt to indicate a reference clock error.

[0082] Specifically, considering that if the PCIe host malfunctions in dual-port mode, it may be unable to output a reference clock through either of its output terminals, in order to detect this malfunction in a timely manner, the processor in this embodiment of the invention can, upon receiving the dual-port enable signal, determine whether a reference clock exists at the second input terminal of the multiplexer 1 by using the first voltage value of the second input terminal of the multiplexer 1, and determine whether a reference clock exists at the first input terminal of the multiplexer 1 by using the second voltage value of the first input terminal of the multiplexer 1. If a reference clock does not exist at any input terminal of the multiplexer 1, the processor can control the indicator to indicate a reference clock error, so that staff can promptly detect the error in the PCIe host's reference clock output.

[0083] The specific methods for determining whether a reference clock exists at the second input terminal of the multiplexer 1 by using the first voltage value and the method for determining whether a reference clock exists at the first input terminal of the multiplexer 1 by using the second voltage value can be varied. For example, they can all be "when the voltage value fluctuates periodically, it can be determined that a reference clock exists; otherwise, it can be determined that a reference clock does not exist." This embodiment of the invention does not limit these methods.

[0084] Furthermore, considering the possibility of abnormal transmission of the reference clock and the possibility of failure of the multiplexer 1, this embodiment of the invention may also include a third voltage monitoring module and a fourth voltage monitoring module to analyze faults at the multiplexer 1. The third voltage monitoring module can detect the third voltage value at the first output terminal of the multiplexer 1, and the fourth voltage monitoring module can detect the fourth voltage value at the second output terminal of the multiplexer 1. In this case, the processor can control the prompt to display the "signal waveform from the first voltage value to the fourth voltage value" and "whether a dual-port enable signal is currently received" in real time. Based on the prompt information, the operator can analyze whether the reference clocks of the two inputs and two outputs of the multiplexer 1 match the signals received at the control terminal of the multiplexer 1. If they match, it means that "the multiplexer 1 has no problem", thus efficiently realizing the fault analysis of the multiplexer 1.

[0085] As an optional embodiment, the level conversion circuit 2 includes a controllable switch, a power supply, a first resistor, and a second resistor;

[0086] The control terminal of the controllable switch is connected to the third output terminal of the host, the second terminal of the controllable switch is grounded, and the common terminal composed of the first terminal of the controllable switch, the first terminal of the first resistor, and the first terminal of the second resistor serves as the output terminal of the level conversion circuit 2. The second terminal of the first resistor is connected to the power supply, and the second terminal of the second resistor is grounded.

[0087] A controllable switch is used to turn off its first and second terminals when a dual-port enable signal is received at the control terminal, and otherwise connect its first and second terminals.

[0088] Specifically, for a better explanation of the embodiments of the present invention, please refer to... Figure 5 , Figure 5 This is a schematic diagram of the structure of a level conversion circuit 2 provided by the present invention. Figure 5 Q1 in the diagram represents a controllable switch (which can be NMOS). The control terminal of the controllable switch can also be connected to a current-limiting resistor R3. R1 is the first resistor, and R2 is the second resistor. The filter circuit is implemented by capacitor C1. When the PCIe host outputs a low level (i.e., a dual-port enable signal) through the third output terminal, Q1 is not turned on. The voltage signal between R1 and R2 (e.g., 1.65V) is used as the output of level conversion circuit 2. When the PCIe host outputs a high level through the third output terminal, Q1 is turned on, and level conversion circuit 2 outputs a low level.

[0089] Please refer to Table 1 below. Table 1 is a table showing the relationship between the output of level conversion circuit 2 and the output of multiplexer 1. As can be seen from the table, when the output signal CLKSEL_MUX of level conversion circuit 2 is 0 (low level), corresponding to the single-port mode of PCIe terminal device, both the first output terminal and the second output terminal of MUX output the reference clock received by the first input terminal of MUX. When the output signal CLKSEL_MUX of level conversion circuit 2 is 1 (high level), corresponding to the dual-port mode of PCIe terminal device, the first output terminal of MUX outputs the reference clock received by the first input terminal of MUX, and the second output terminal of MUX outputs the reference clock received by the second input terminal of MUX.

[0090] Table 1

[0091]

[0092] Specifically, considering that the level conversion circuit 2 can also be constructed using circuit components, and has the advantages of small size and low cost, the level conversion circuit 2 in this embodiment of the invention can be constructed using a controllable switch, a power supply, a first resistor, and a second resistor. The controllable switch can turn off its first and second terminals when it receives a dual-port enable signal at the control terminal; otherwise, it can connect its first and second terminals. After turning off its first and second terminals, the level output by the level conversion circuit 2 is the voltage between the first and second resistors (first level). When its first and second terminals are connected, since the output terminal is grounded, the level output by the level conversion circuit 2 is a low level (second level).

[0093] Of course, in addition to this specific construction, the level conversion circuit 2 constructed by circuit elements can also take many other forms, and the embodiments of the present invention are not limited here.

[0094] As an optional embodiment, the level conversion circuit 2 also includes a filtering module;

[0095] The first terminal of the filter module is connected to the common terminal formed by the first terminal of the controllable switch, the first terminal of the first resistor, and the first terminal of the second resistor, and the second terminal of the filter module is grounded.

[0096] The filtering module is used to filter the voltage between the first resistor and the second resistor.

[0097] Specifically, considering that the output signal of the level conversion circuit 2 may be mixed with noise, and that the stability of the output signal of the level conversion circuit 2 is related to the stability of the multiplex clock selector 1, the level conversion circuit 2 in this embodiment of the invention also includes a filtering module, which can filter the voltage between the first resistor and the second resistor, thereby improving the stability of the output signal of the level conversion circuit 2.

[0098] The filtering module can be of various types, such as a capacitor, and this embodiment of the invention does not limit it.

[0099] As an optional implementation, the dual-port enable signal is low;

[0100] Controllable switches include N-channel metal-oxide-semiconductor field-effect transistors.

[0101] Specifically, the dual-port enable signal can be low, while when the dual-port enable signal is not issued, the PCIe host can output a high level through the third output terminal, thereby causing the level conversion circuit 2 to output a second level.

[0102] Among them, NMOS (N-Metal-Oxide-Semiconductor Field Effect Transistor) has advantages such as small size, fast response and low cost.

[0103] Of course, besides NMOS, controllable switches can be of many other types, and this embodiment of the invention does not limit them.

[0104] The present invention also provides a high-speed serial computer expansion bus standard terminal device, including a circuit board and a dual-port high-speed serial computer expansion bus standard controller, and further including the above-mentioned clock distribution circuit connected to the dual-port high-speed serial computer expansion bus standard controller.

[0105] Among them, the dual-port high-speed serial computer expansion bus standard controller and clock distribution circuit are set up on the circuit board.

[0106] For a description of the embodiments of the present invention, please refer to the aforementioned embodiments of the clock distribution circuit; the embodiments of the present invention will not be repeated here.

[0107] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should also be noted that in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0108] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A clock distribution circuit, characterized in that, Includes a multiplex clock selector and a level conversion circuit; The first output of the multiplexer is connected to the clock input of the first physical medium sublayer, the second output of the multiplexer is connected to the clock input of the second physical medium sublayer, the first input of the multiplexer is connected to the first output of the host, the second input of the multiplexer is connected to the second output of the host, the control terminal of the multiplexer is connected to the output of the level conversion circuit, and the input of the level conversion circuit is connected to the third output of the host. Among them, the first physical medium sublayer and the second physical medium sublayer belong to the same high-speed serial computer extended bus standard controller, and the first output terminal and the second output terminal of the host are both used to output the reference clock. A multiplexer clock selector is used to connect its first input terminal to its first output terminal and its second input terminal to its second output terminal when it receives a first level. When it receives a second level, it outputs the reference clock received by its first input terminal synchronously through its first output terminal and second output terminal. The level conversion circuit is used to output a first level when a dual-port enable signal is received, and to output a second level when a dual-port enable signal is not received.

2. The clock distribution circuit according to claim 1, characterized in that, The multiplex clock selector and the level conversion circuit are both located on the motherboard of the high-speed serial computer expansion bus standard terminal device. The clock distribution circuit also includes first to twelfth connection terminals and four electrical connection devices disposed on the motherboard of the high-speed serial computer expansion bus standard terminal device; The first connection terminal is used to connect to the first output terminal of the host, the second connection terminal is connected to the fifth connection terminal, the third connection terminal is connected to the first input terminal of the multiplexer, the fourth connection terminal is connected to the clock input terminal of the first physical media sublayer, the sixth connection terminal is connected to the first output terminal of the multiplexer, the seventh connection terminal is used to connect to the second output terminal of the host, the eighth connection terminal is connected to the eleventh connection terminal, the ninth connection terminal is connected to the second input terminal of the multiplexer, the tenth connection terminal is connected to the clock input terminal of the second physical media sublayer, and the twelfth connection terminal is connected to the second output terminal of the multiplexer. Any one of the first, fourth, seventh, and tenth connection terminals is used to establish an electrical connection with an adjacent connection terminal via a corresponding electrical connection device.

3. The clock distribution circuit according to claim 2, characterized in that, The electrical connection device includes a zero-ohm resistor or a jumper cap.

4. The clock distribution circuit according to claim 1, characterized in that, The level conversion circuit includes a processor; The clock distribution circuit also includes a prompter; The processor is configured to output a first level when a dual-port enable signal is received, and output a second level when a dual-port enable signal is not received; the control prompt indicates whether a dual-port enable signal has been received.

5. The clock distribution circuit according to claim 4, characterized in that, The clock distribution circuit also includes a first voltage monitoring module; The first voltage monitoring module is used to detect the first voltage value at the second input terminal of the multi-channel clock selector; The processor is also configured to, when not receiving a dual-port enable signal, determine whether there is a reference clock at the second input terminal of the multiplexer based on the first voltage value; if there is, control the prompt to indicate a reference clock error.

6. The clock distribution circuit according to claim 5, characterized in that, The clock distribution circuit also includes a second voltage monitoring module: The second voltage monitoring module is used to detect the second voltage value at the first input terminal of the multi-channel clock selector; The processor is further configured to, upon receiving a dual-port enable signal, determine whether a reference clock exists at the second input terminal of the multiplexer based on the first voltage value, determine whether a reference clock exists at the first input terminal of the multiplexer based on the second voltage value, and, if no reference clock exists at any input terminal of the multiplexer, control the prompt to indicate a reference clock error.

7. The clock distribution circuit according to any one of claims 1 to 6, characterized in that, The level conversion circuit includes a controllable switch, a power supply, a first resistor, and a second resistor; The control terminal of the controllable switch is connected to the third output terminal of the host, the second terminal of the controllable switch is grounded, and the common terminal formed by the first terminal of the controllable switch, the first terminal of the first resistor, and the first terminal of the second resistor serves as the output terminal of the level conversion circuit. The second terminal of the first resistor is connected to the power supply, and the second terminal of the second resistor is grounded. The controllable switch is used to turn off its first and second terminals when it receives a dual-port enable signal at its control terminal, and otherwise connect its first and second terminals.

8. The clock distribution circuit according to claim 7, characterized in that, The level conversion circuit also includes a filtering module; The first terminal of the filter module is connected to a common terminal formed by the first terminal of the controllable switch, the first terminal of the first resistor, and the first terminal of the second resistor, and the second terminal of the filter module is grounded. The filtering module is used to filter the voltage between the first resistor and the second resistor.

9. The clock distribution circuit according to claim 7, characterized in that, The dual-port enable signal is low. The controllable switch includes an N-channel metal-oxide-semiconductor field-effect transistor.

10. A high-speed serial computer expansion bus standard terminal device, characterized in that, The system includes a circuit board and a dual-port high-speed serial computer expansion bus standard controller, and also includes a clock distribution circuit as described in any one of claims 1 to 9 connected to the dual-port high-speed serial computer expansion bus standard controller. The dual-port high-speed serial computer expansion bus standard controller and the clock distribution circuit are disposed on the circuit board.

Images