Display panel and test method therefor, and display device

Abstract

A display panel and a test method therefor, and a display device. The display panel comprises a plurality of pixel units (110), a plurality of data lines (DA) and a plurality of first fan-out lines (F1) located in a display area (AA), and a plurality of second fan-out lines (F2), a plurality of test circuit units (120) and at least two test signal lines (TES) located in a non-display area (NAA), wherein the first fan-out lines (F1) are electrically connected to corresponding first data lines (DA1); each test circuit unit (120) comprises a plurality of first switches (121) and a plurality of second switches (122); first ends of the plurality of first switches (121) are electrically connected to the corresponding first fan-out lines (F1) by means of the corresponding second fan-out lines (F2); first ends of the plurality of second switches (122) are electrically connected to corresponding second data lines (DA2) by means of the corresponding second fan-out lines (F2); second ends of the switches correspondingly electrically connected to the pixel units (110) in a same column are electrically connected to a same test signal line (TES); second ends of the switches correspondingly electrically connected to the pixel units (110) in two adjacent columns are electrically connected to different test signal lines (TES). When the display panel is abnormal, defect detection for the display panel can be realized.

Description

Display panel, testing method thereof, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 13, 2023, with application number 202310706955.8, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of display technology, for example, to a display panel and a testing method thereof, and a display device. Background Art

[0003] After all the film layers of the display panel are manufactured, a test signal can be provided to the display panel through the test terminal to implement the detection of the display panel, so as to screen out defective display panels and avoid waste of subsequent processes caused by subsequent defective display panels.

[0004] Summary of the Invention

[0005] The present application provides a display panel, a testing method thereof, and a display device to implement defect detection of the display panel.

[0006] In a first aspect, an embodiment of the present application provides a display panel, the display panel including a display area and a non-display area, and the display panel further including:

[0007] A plurality of pixel units arranged in an array are located in the display area;

[0008] a plurality of data lines located in the display area and electrically connected to the pixel units of corresponding columns; the plurality of data lines extend along the column direction and are arranged along the row direction; the plurality of data lines include at least two first data lines and at least two second data lines;

[0009] A plurality of first fan-out lines are located in the display area, and the first fan-out lines are electrically connected to corresponding first data lines;

[0010] A plurality of second fan-out lines, a plurality of test circuit units and at least two test signal lines are located in a non-display area, each test circuit unit includes a plurality of first switches and a plurality of second switches, the first ends of the plurality of first switches are electrically connected to the corresponding first fan-out lines via the corresponding second fan-out lines; the first ends of the plurality of second switches are electrically connected to the corresponding second data lines via the corresponding second fan-out lines; the second ends of the switches electrically connected to the corresponding pixel units in the same column are electrically connected to the same test signal line; the second ends of the switches electrically connected to the corresponding pixel units in two adjacent columns are electrically connected to different test signal lines.

[0011] In a second aspect, an embodiment of the present application further provides a display device, comprising a driver chip and the display panel of the first aspect, wherein the driver chip is electrically connected to the second fan-out line.

[0012] In a third aspect, an embodiment of the present application further provides a method for testing the display panel according to the first aspect, the method comprising:

[0013] During a first period, the first switch and the second switch are controlled to be turned on, the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the odd columns is connected to a lighting voltage, and the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the even columns is connected to an extinguishing voltage;

[0014] And / or, in the second time period, the first switch and the second switch are controlled to be turned on, the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the odd columns is connected to the extinguishing voltage, and the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the even columns is connected to the lighting voltage.

[0015] The technical solution of the embodiment of the present application is as follows: by setting the first end of the first switch in the test circuit unit to be electrically connected to the corresponding first data line via the corresponding second fan-out line and the first fan-out line; the first end of the second switch to be electrically connected to the corresponding second data line via the corresponding second fan-out line; the second end of the switch electrically connected to the same column of pixel units is electrically connected to the same test signal line; the second end of the switch electrically connected to the two adjacent columns of pixel units is electrically connected to different test signal lines. When performing display panel testing, different test signals can be provided to different test signal lines so that the test signals obtained by the two adjacent columns of pixel units are different. When the display panel is normal, a test screen can be achieved in which the pixel units are lit at least one column apart. When the display panel is abnormal, the display panel cannot achieve a test screen in which the pixel units are lit at least one column apart. Therefore, it is possible to judge whether the display panel is abnormal based on the test screen, thereby achieving a defect detection of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG1 is a schematic diagram of a partial structure of a display panel provided by the related art;

[0017] FIG2 is a schematic diagram of a partial structure of a display panel provided in an embodiment of the present application;

[0018] FIG3 is a schematic diagram of a partially enlarged structure of a display panel provided in an embodiment of the present application;

[0019] FIG4 is a schematic diagram of a partially enlarged structure of another display panel provided in an embodiment of the present application;

[0020] FIG5 is a schematic diagram of a partially enlarged structure of another display panel provided in an embodiment of the present application;

[0021] FIG6 is a schematic diagram of a partially enlarged structure of another display panel provided in an embodiment of the present application;

[0022] FIG7 is a schematic structural diagram of a pad provided in an embodiment of the present application;

[0023] FIG8 is a schematic diagram of a partially enlarged structure of another display panel provided in an embodiment of the present application;

[0024] FIG9 is a schematic diagram of a partially enlarged structure of another display panel provided in an embodiment of the present application;

[0025] FIG10 is a schematic diagram of a partially enlarged structure of another display panel provided in an embodiment of the present application;

[0026] FIG11 is a schematic diagram of a partially enlarged structure of another display panel provided in an embodiment of the present application;

[0027] FIG12 is a schematic diagram of a partial cross-sectional structure of a display panel provided in an embodiment of the present application;

[0028] FIG13 is a schematic structural diagram of another display panel provided in an embodiment of the present application;

[0029] FIG14 is a schematic structural diagram of a display device provided in an embodiment of the present application;

[0030] FIG15 is a flow chart of a method for testing a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] When a display panel adopts a fan-out in active area (FIAA) structure to reduce the bezel of the display panel, the fan-out lines of the display panel are out of order. At this time, it is impossible to detect defective display panels, which easily leads to defective display panels and waste of subsequent processes.

[0032] Figure 1 is a schematic diagram of a partial structure of a display panel provided by related art. As shown in Figure 1, the display panel includes a display area 101 and a non-display area 102. The display area 101 is provided with pixels A, data lines D, and connecting lines M1. A data line D is electrically connected to a column of pixels A. Some data lines D are connected to fan-out lines M2 in the non-display area 102 via connecting lines M1, while some data lines D are directly connected to fan-out lines M2. Specifically, when the display panel adopts an FIAA structure to reduce the display panel's bezel, the arrangement order of the fan-out lines M2 in the non-display area 102 of the display panel differs from the arrangement order of the data lines D, resulting in a phenomenon in which the fan-out lines M2 in the non-display area 102 are out of order. The non-display area 102 is also provided with a detection circuit 103. The detection circuit 103 includes multiple switches K, each connected to a data line D via a fan-out line M2. The display panel also includes a control line SW, a first detection line D_1, and a second detection line D_2. In related art, two adjacent switches K alternately connect the first detection line D_1 and the second detection line D_2. During the display panel testing process, different voltages can be provided to the first detection line D_1 and the second detection line D_2. If the fan-out lines M2 in the non-display area 102 are out of sequence, even if the display panel is functioning properly, the alternate-column test screen cannot be achieved, making it impossible to detect whether the display panel is abnormal.

[0033] For example, when the fan-out lines M2 of the non-display area 102 are out of order, along the row direction, the first switch K is connected to the fourth data line D through the first fan-out line M2, the second switch K is connected to the fifth data line D through the second fan-out line M2, the third switch K is connected to the sixth data line D through the third fan-out line M2, the fourth switch K is connected to the third data line D through the fourth fan-out line M2, the fifth switch K is connected to the seventh data line D through the fifth fan-out line M2, and the sixth switch K is connected to the sixth data line D through the sixth fan-out line M2. 2 is connected to the 8th data line D, the 7th switch K is connected to the 2nd data line D through the 7th fan-out line M2, the 8th switch K is connected to the 9th data line D through the 8th fan-out line M2, the 9th switch K is connected to the 10th data line D through the 9th fan-out line M2, the 10th switch K is connected to the 1st data line D through the 10th fan-out line M2, the 11th switch K is connected to the 11th data line D through the 11th fan-out line M2, and the 12th switch K is connected to the 12th data line D through the 12th fan-out line M2. When testing the display panel, the control line SW can be set to provide a low level, for example, -7.5V, the first detection line D_1 provides a lighting voltage, for example, 4V, and the second detection line D_2 provides an extinguishing voltage, for example, 7.5V. At this time, the pixels corresponding to the data lines D connected to the 1st switch K, the 2nd switch K, the 5th switch K, the 6th switch K, the 9th switch K and the 10th switch K are lit, that is, the pixels corresponding to the 4th, 5th, 7th, 8th, 10th and 1st data lines D are lit; the pixels corresponding to the data lines D connected to the 3rd switch K, the 4th switch K, the 7th switch K, the 8th switch K, the 11th switch K and the 12th switch K are extinguished, that is, the pixels corresponding to the 6th, 3rd, 2nd, 9th, 11th and 12th data lines D are extinguished. When the display panel is normal, it is impossible to achieve a detection screen in which two columns are lit every other two columns. Therefore, it is impossible to determine whether the display panel is abnormal based on the detection image.

[0034] When a display panel uses the FIAA structure to reduce the bezel of the display panel, the arrangement order of the fan-out lines in the non-display area of ​​the display panel is different from the arrangement order of the data lines, which is equivalent to the fan-out lines in the non-display area being out of order. In this case, when using the detection circuit provided by the related art for detection, even if there is no abnormality in the display panel, it will still cause the display panel to be unable to achieve the detection image of lighting up every other column, and it is impossible to detect the display panel failure, which is likely to cause the waste of subsequent processes due to the occurrence of defective display panels.

[0035] The present invention provides a display panel. FIG2 is a schematic diagram of a partial structure of a display panel provided in the present invention, and FIG3 is a schematic diagram of an enlarged partial structure of a display panel provided in the present invention. As shown in FIG2 and FIG3, the display panel includes a display area AA and a non-display area NAA. The display panel also includes:

[0036] A plurality of pixel units 110 arranged in an array are located in the display area AA. Exemplarily, any pixel unit 110 includes at least two sub-pixels P.

[0037] Multiple data lines DA are located in the display area AA and are electrically connected to the pixel units 110 of the corresponding columns; the multiple data lines DA extend along the column direction Y and are arranged along the row direction X; the multiple data lines DA include at least two first data lines DA1 (for example, DA11 to DA14) and at least two second data lines DA2 (for example, DA21 to DA28); the column direction Y may intersect with the row direction X, and illustratively, the column direction Y may be perpendicular to the row direction X.

[0038] A plurality of first fan-out lines F1 are located in the display area AA, and the first fan-out lines F1 are electrically connected to corresponding first data lines DA1;

[0039] Multiple second fan-out lines F2, multiple test circuit units 120 and at least two test signal lines TES are located in the non-display area NAA, each test circuit unit 120 includes multiple first switches 121 and multiple second switches 122, the first ends of the multiple first switches 121 are electrically connected to the corresponding first fan-out line F1 via the corresponding second fan-out line F2; the first ends of the multiple second switches 122 are electrically connected to the corresponding second data line DA2 via the corresponding second fan-out line F2; the second ends of the switches electrically connected to the same column of pixel units 110 are electrically connected to the same test signal line TES; the second ends of the switches electrically connected to the two adjacent columns of pixel units 110 are electrically connected to different test signal lines TES.

[0040] Exemplarily, in the same pixel unit 110, at least two sub-pixels may be located in different columns. Exemplarily, all sub-pixels in the same pixel unit 110 are located in different columns, and are located in the same row and adjacent to each other. Exemplarily, when the pixel arrangement of the display panel is an RGBG arrangement, the red sub-pixel and the blue sub-pixel are arranged in the same column and serve as the first column sub-pixel. The green sub-pixel is arranged in the same column and serves as the second column sub-pixel. The first column sub-pixels and the second column sub-pixel are arranged alternately. And in the two adjacent columns of the first column sub-pixels, the arrangement order of the red sub-pixels and the blue sub-pixels is different. At this time, the pixel unit 110 may include sub-pixels in adjacent columns of the same row, for example, it may include red sub-pixels and green sub-pixels in the same row, or blue sub-pixels and green sub-pixels in the same row, corresponding to two data lines DA. When the pixel arrangement of the display panel is an RGB arrangement, the red sub-pixels, blue sub-pixels and green sub-pixels are respectively arranged in one column, and the sub-pixel columns of different colors are arranged alternately. At this time, the pixel unit 110 may include three sub-pixels in adjacent columns of the same row, namely a red sub-pixel, a blue sub-pixel, and a green sub-pixel, which are correspondingly connected to three data lines DA.

[0041] The display area AA is also provided with a first fan-out line F1, which is connected to the corresponding first data line DA1. The non-display area NAA is provided with a second fan-out line F2 and a test circuit unit 120. The first end of a first switch 121 in the test circuit unit 120 is connected to one end of the corresponding second fan-out line F2, and the other end of the corresponding second fan-out line F2 is connected to the corresponding first fan-out line F1. This allows the first end of the first switch 121 to be connected to the corresponding first data line DA1 via the corresponding second fan-out line F2 and the first fan-out line F1, thereby providing a test signal to the sub-pixel connected to the first data line DA1. The first end of a second switch 122 in the test circuit unit 120 is connected to one end of the corresponding second fan-out line F2, and the other end of the corresponding second fan-out line F2 is connected to the corresponding second data line DA2, thereby providing a test signal to the sub-pixel connected to the second data line DA2. To reduce the size of the lower frame, when the first fan-out line F1 is set in the display area AA, one end of the first fan-out line F1 is electrically connected to the first data line DA1, and the other end is inserted between the second data line DA2 and extends from the display area AA to the non-display area NAA. Therefore, the arrangement order of the second fan-out lines F2 of the display panel is different from the arrangement order of the corresponding connected data lines, and the second fan-out lines F2 are out of order. For example, with reference to Figure 3 again, the first data lines DA1 and the second data lines DA2 can be arranged in sequence along the row direction X. Figure 3 exemplarily shows a group of data lines DA corresponding to a test circuit unit 120, wherein there are four first data lines DA1, which can be the first first data line DA11, the second first data line DA12, the third first data line DA13, and the fourth first data line DA14, respectively. It is also shown that there are eight second data lines DA2, which may be the first second data line DA21, the second second data line DA22, the third second data line DA23, the fourth second data line DA24, the fifth second data line DA25, the sixth second data line DA26, the seventh second data line DA27, and the eighth second data line DA28. Along the row direction X, the arrangement order of the first to the twelfth data lines from left to right is the first first data line DA11, the second first data line DA12, the third first data line DA13, the fourth first data line DA14, the first second data line DA21, the second second data line DA22, the third second data line DA23, the fourth second data line DA24, the fifth second data line DA25, the sixth second data line DA26, the seventh second data line DA27, and the eighth second data line DA28. Four first fan-out lines F1 and twelve second fan-out lines F2 are connected to one test circuit unit 120 .Each first fan-out line F1 can be electrically connected to a first data line DA1 in a one-to-one correspondence, and each second fan-out line F2 can be electrically connected to one first fan-out line F1 or one second data line DA2. For example, the four first fan-out lines F1 and 12 second fan-out lines F2 corresponding to a test circuit unit 120 are arranged from left to right in FIG3 , with the first fan-out lines F1 arranged from the first first fan-out line F1 to the fourth first fan-out line F1, and the second fan-out lines F2 arranged from the first second fan-out line F2 to the twelfth second fan-out line F2. At this time, the first second fan-out line F2 can be set to be electrically connected to the fourth first data line DA14 (the fifth data line on the left) through the first first fan-out line F1, which is equivalent to the second fan-out line F2 located on the far left not being electrically connected to the corresponding data line DA located on the far left, that is, the order of the second fan-out line F2 is different from the order of the data line DA electrically connected thereto, the second second fan-out line F2 and the third second fan-out line F2 are electrically connected to the first second data line DA21 (the fifth data line on the left) and the second second data line DA22 (the sixth data line on the left) respectively, the fourth second fan-out line F2 is electrically connected to the third first data line DA13 (the third data line on the left) through the second first fan-out line F1, the fifth second fan-out line F2 and the sixth second fan-out line F2 are electrically connected to the third second data line DA23 (the sixth data line on the left) respectively. The 7th second fan-out line F2 is electrically connected to the 2nd first data line DA12 (the 2nd data line on the left) through the 3rd first fan-out line F1, the 8th second fan-out line F2 and the 9th second fan-out line F2 are electrically connected to the 5th second data line DA25 (the 9th data line on the left) and the 6th second data line DA26 (the 10th data line on the left), respectively, the 10th second fan-out line F2 is electrically connected to the 1st first data line DA11 (the 1st data line on the left) through the 4th first fan-out line F1, the 11th second fan-out line F2 and the 12th second fan-out line F2 are electrically connected to the 7th second data line DA27 (the 11th data line on the left) and the 8th second data line DA28 (the 12th data line on the left), respectively. At this time, according to Figure 3 from left to right, the correspondence between the arrangement order of the second fan-out lines F2 and the data lines is that the 1st second fan-out line F2 to the 12th second fan-out line F2 correspond to the 4th data line, the 5th data line, the 6th data line, the 3rd data line, the 7th data line, the 8th data line, the 2nd data line, the 9th data line, the 10th data line, the 1st data line, the 11th data line and the 12th data line, that is, the arrangement order of the second fan-out lines F2 is different from the arrangement order of the corresponding electrically connected data lines, and the second fan-out lines F2 are out of order.

[0042] The number of first switches 121 is equal to the number of first data lines DA1, and the number of second switches 122 is equal to the number of second data lines DA2. When a pixel unit 110 includes sub-pixels P arranged in at least two different columns, at least two switches may be provided for the same pixel unit 110. In pixel units electrically connected to the same test circuit unit, all sub-pixels in the same column of pixel units 110 may be electrically connected to the first switch, or all sub-pixels in the same column of pixel units 110 may be electrically connected to the second switch. The first end of the first switch 121 is electrically connected to the corresponding first fan-out line F1 via the corresponding second fan-out line F2, and the first end of the second switch 122 is electrically connected to the corresponding second data line DA2 via the corresponding second fan-out line F2. When the second fan-out lines F2 are out of order, the corresponding electrically connected switches in the same column of pixel units 110 may include the first switch 121 and / or the second switch 122. At this time, the second ends of the first switches 121 and / or the second switches 122 electrically connected to the same column of pixel units 110 can be set to be electrically connected to the same test signal line TES, and the second ends of the switches electrically connected to the two adjacent columns of pixel units 110 can be electrically connected to different test signal lines TES. When performing display panel testing, different test signals can be provided to different test signal lines TES so that the test signals obtained by the two adjacent columns of pixel units 110 are different. When the display panel is normal, a detection screen in which the pixel units 110 are lit at intervals of x columns can be achieved, for example, the detection screen is a white screen. Wherein, when the display panel includes p test signal lines TES, x is an integer greater than or equal to 1 and less than or equal to p-1, and p is an integer greater than or equal to 2. When the display panel is abnormal, the display panel cannot achieve a detection screen in which the pixel units 110 are lit at intervals of x columns, so that it can be judged whether the display panel is abnormal based on the detection screen, thereby achieving poor detection of the display panel. For example, at least two second fan-out lines F2 electrically connected to the same column of pixel units 110 are arranged in different layers, and at least two second fan-out lines F2 electrically connected to different columns of pixel units 110 are arranged in the same layer, with no second fan-out lines F2 on the same layer between them. When the second fan-out lines F2 on the same layer are short-circuited, the display panel cannot achieve a detection image in which every other x columns of pixel units 110 are lit. For example, two adjacent columns of pixel units 110 may be lit simultaneously, and the brightness of at least two columns of pixel units 110 is between maximum brightness and off, thereby enabling display panel failure detection.

[0043] Exemplarily, the number of sub-pixels in each pixel unit in the same column of pixel units 110 is equal. Exemplarily, the number of sub-pixels in each pixel unit in different columns of pixel units 110 is equal or unequal. Exemplarily, referring to FIG3 , when the pixel unit 110 includes two sub-pixels P, and different sub-pixels P are arranged in different columns, the display panel may include four first data lines DA1 and eight second data lines DA2, and the connection relationship with the second fan-out line F2 is shown in FIG3 . At this time, the two sub-pixels P in the first column of pixel units 110 can be correspondingly connected to the first first data line DA11 and the second first data line DA12, the two sub-pixels P in the second column of pixel units 110 can be correspondingly connected to the third first data line DA13 and the fourth first data line DA14, the two sub-pixels P in the third column of pixel units 110 can be correspondingly connected to the first second data line DA21 and the second second data line DA22, the two sub-pixels P in the fourth column of pixel units 110 can be correspondingly connected to the third second data line DA23 and the fourth second data line DA24, the two sub-pixels P in the fifth column of pixel units 110 can be correspondingly connected to the fifth second data line DA25 and the sixth second data line DA26, and the two sub-pixels P in the sixth column of pixel units 110 can be correspondingly connected to the seventh second data line DA27 and the eighth second data line DA28. When there are two test signal lines TES, based on the correspondence between the data lines and the second fan-out lines F2, it can be determined that the second ends of the switches electrically connected to the first, third, fifth, and seventh columns of pixel units 110 are electrically connected to one test signal line TES, while the second ends of the switches electrically connected to the second, fourth, sixth, and eighth columns of pixel units 110 are electrically connected to the other test signal line TES. This allows the sub-pixels P in adjacent columns of pixel units 110 to receive different test signals. When the display panel is functioning normally, a test image can be achieved in which alternate columns of pixel units 110 are illuminated. For example, one column of pixel units 110 can be illuminated while the other column of pixel units 110 is not illuminated, i.e., off. For example, the light emitted by the multiple sub-pixels in each illuminated pixel unit can be mixed to form white light, resulting in a white test image. At the same time, the two second fan-out lines F2 corresponding to the same column of pixel units 110 can be set in different layers, two of the four second fan-out lines F2 corresponding to two adjacent columns of pixel units 110 can be set in the same layer, and the other two second fan-out lines F2 can be set in the same layer.For example, the two second fan-out lines F2 corresponding to the first column of pixel units 110 are respectively arranged in two conductive layers, the first second fan-out line F2 corresponding to the second column of pixel units 110 and the first second fan-out line F2 corresponding to the first column of pixel units 110 are arranged in the same conductive layer, and the second second fan-out line F2 corresponding to the second column of pixel units 110 and the second second fan-out line F2 corresponding to the first column of pixel units 110 are arranged in the same conductive layer. When the second fan-out lines F2 in the same layer are short-circuited, the display panel cannot achieve a detection image in which alternate columns of adjacent pixel units 110 are illuminated. Therefore, it is possible to determine whether the display panel is abnormal based on the detection image, thereby achieving short-circuit detection of the display panel.

[0044] The technical solution of this embodiment is to electrically connect the first end of the first switch in the test circuit unit to the corresponding first fan-out line via the corresponding second fan-out line; the first end of the second switch to the corresponding second data line via the corresponding second fan-out line; the second end of the switch electrically connected to the same column of pixel units is electrically connected to the same test signal line; and the second ends of the switches electrically connected to two adjacent columns of pixel units are electrically connected to different test signal lines. When performing display panel testing, different test signals can be provided to different test signal lines so that the test signals obtained by the two adjacent columns of pixel units are different. When the display panel is normal, a test screen can be achieved in which at least one column of pixel units are lit. When the display panel is abnormal, the display panel cannot achieve a test screen in which at least one column of pixel units are lit. Therefore, it is possible to determine whether the display panel is abnormal based on the test screen, thereby achieving a defect detection of the display panel.

[0045] Continuing to refer to Figure 3, the at least two test signal lines TES include: a first test signal line TES1 and a second test signal line TES2. The second ends of the switches electrically connected to the odd-numbered pixel units 110 are electrically connected to the first test signal line TES1, and the second ends of the switches electrically connected to the even-numbered pixel units 110 are electrically connected to the second test signal line TES2.

[0046] When testing the display panel, one of the first test signal line TES1 and the second test signal line TES2 can be used to input a lighting voltage and the other to input an extinguishing voltage. When the display panel is normal, a test image in which two adjacent columns of pixel units 110 are lit up in alternate columns can be achieved. When the display panel is abnormal, the display panel cannot achieve a test image in which two adjacent columns of pixel units 110 are lit up in alternate columns. Therefore, whether the display panel is abnormal can be determined based on the test image, thereby achieving display panel failure detection.

[0047] Exemplarily, when the pixel unit 110 includes two adjacent sub-pixels P located in the same row, and different sub-pixels P are arranged in different columns, the display panel may include two conductive layers, and the second fan-out lines F2 may be alternately arranged in different layers in the two conductive layers from left to right along the row direction X. In this case, the two second fan-out lines F2 corresponding to the same column of pixel units 110 are arranged in different layers, two of the four second fan-out lines F2 corresponding to the two adjacent columns of pixel units 110 can be arranged in the same layer, and the other two second fan-out lines F2 can be arranged in the same layer. For example, the first second fan-out line F2 corresponding to an odd-numbered column of pixel units 110 and the first second fan-out line F2 corresponding to an even-numbered column of pixel units 110 are arranged in the same layer, and the distance between them is relatively close, for example, there is no other second fan-out line in the same layer between them, and there is only one second fan-out line arranged in a different layer between them. During the detection process of the display panel, the first test signal line TES1 can input a lighting voltage, and the second test signal line TES2 can input an off voltage. When the second fan-out line F2 of the same layer is short-circuited, the pixel units 110 of the odd columns and the even columns are both input with a lighting voltage or an off voltage, so that the display panel cannot realize the detection screen in which the two adjacent columns of pixel units 110 are lit every other column. Therefore, it is possible to judge whether the display panel is abnormal based on the detection screen, thereby realizing the detection of the display panel.

[0048] Figure 4 is a partial enlarged structural diagram of another display panel provided in an embodiment of the present application. As shown in Figure 3, the display panel further includes a control signal line CTRL, to which the control terminals of the first switch 121 and the second switch 122 are electrically connected.

[0049] For example, the same control signal line CTRL can provide control signals for the first switch 121 and the second switch 122. When the display panel is not being tested, the control signal provided by the control signal line CTRL can control the first switch 121 and the second switch 122 to be turned off. When the display panel is being tested, the control signal provided by the control signal line CTRL can control the first switch 121 and the second switch 122 to be turned on, so that the test signals provided by the test signal line TES connected to the second ends of the first switch 121 and the second switch 122 are output to the corresponding electrically connected pixel units 110 through the first switch 121 and the second switch 122, respectively, to achieve defect detection of the display panel.

[0050] Continuing with reference to Figure 4, the first switch 121 includes a first transistor S1, the first electrode of the first transistor S1 serves as the first end of the first switch 121, the second electrode of the first transistor S1 serves as the second end of the first switch 121, and the control electrode of the first transistor S1 serves as the control end of the first switch 121; and / or, the second switch 122 includes a second transistor S2, the first electrode of the second transistor S2 serves as the first end of the second switch 122, the second electrode of the second transistor S2 serves as the second end of the second switch 122, and the control electrode of the second transistor S2 serves as the control end of the second switch 122.

[0051] For example, FIG4 exemplarily illustrates that the first switch 121 includes a first transistor S1, while the second switch 122 includes a second transistor S2. The channel types of the first transistor S1 and the second transistor S2 can be the same. FIG4 merely exemplarily illustrates that the first transistor S1 and the second transistor S2 are N-type transistors. In other embodiments, the first transistor S1 and the second transistor S2 can also be P-type transistors. During the detection process of the display panel, the timing of the control signal can be adaptively adjusted, which is not limited here.

[0052] For example, the first transistor S1 and the second transistor S2 can be P-type transistors. When the display panel is not being tested, the control signal provided by the control signal line CTRL can be a high level, for example, 8.5V, at which point the first transistor S1 and the second transistor S2 are in an off state. When the display panel is being tested, the control signal provided by the control signal line CTRL can be a low level, for example, -7.5V, and the first transistor S1 and the second transistor S2 are in an on state. The voltage provided by the first test signal line TES1 is a lighting voltage, for example, 4V, and the voltage provided by the second test signal line TES2 is an off voltage, for example, 7.5V. This causes the pixel unit 110 connected to the transistor connected to the first test signal line TES1 to light up, and the pixel unit 110 connected to the transistor connected to the second test signal line TES2 to turn off. When the display panel is normal, a test screen in which alternate columns of pixel units 110 are lit can be achieved. When the display panel is abnormal, the display panel cannot achieve a test screen in which alternate columns of pixel units 110 are lit. Therefore, it is possible to determine whether the display panel is abnormal based on the test screen, thereby achieving a defect detection of the display panel.

[0053] On the basis of the above technical solution, the arrangement order of the plurality of second fan-out lines F2 along the row direction X is different from the arrangement order of the data lines DA electrically connected to the second fan-out lines F2 .

[0054] Exemplarily, the arrangement order of the data lines DA along the positive direction of the row direction X is the overall arrangement order of the first data lines DA1 and the second data lines DA2 along the row direction X. When the arrangement order of the plurality of second fan-out lines F2 along the positive direction of the row direction X is different from the arrangement order of the data lines DA to which the second fan-out lines F2 are electrically connected, the second fan-out lines F2 are out of order. When the display area AA has rounded corners on both sides of one end near the test circuit unit 120, the second fan-out lines F2 corresponding to the pixel units 110 in the corresponding columns of the rounded corners can be moved to the middle area and then connected to the data lines DA corresponding to the pixel units 110 via the first fan-out lines F1. This avoids the need to position the second fan-out lines F2 in the rounded corners and reduces the width of the non-display area NAA.

[0055] In other embodiments, illustratively, the first end of the first fan-out line F1 electrically connected to the second fan-out line F2 is closer to the second data line DA2 located in the middle of the display area AA than the second end of the first fan-out line F1 electrically connected to the first data line DA1.

[0056] With this arrangement, compared to connecting all data lines DA to the driver chip in the binding area via the fan-out lines of the non-display area NAA, leading the first data line DA1 at the edge of the display area AA out from the middle of the display area AA via the first fan-out line F1 can reduce the space occupied by the fan-out lines in the non-display area NAA, which is conducive to achieving a narrow bezel. For example, the first first data line DA11 is connected to the fourth first fan-out line F1, which is correspondingly connected to the tenth second fan-out line F2. The first end A where the fourth first fan-out line F1 is electrically connected to the tenth second fan-out line F2 is closer to the second data line DA2 located in the middle of the display area AA than the second end B where the fourth first fan-out line F1 is electrically connected to the first first data line DA1. This allows the second fan-out line F2 corresponding to the first first data line DA11 to be closer to the middle area of ​​the non-display area NAA, thereby reducing the width of the non-display area NAA.

[0057] In other embodiments, illustratively, a plurality of second fan-out lines F2 may be arranged along the row direction X. Exemplarily, the outermost second fan-out line F2 is electrically connected to the first end of the first switch 121 . Exemplarily, the outermost second fan-out line F2 is electrically connected to the first end of the second switch 122 .

[0058] Figure 5 is a partially enlarged schematic diagram of another display panel structure provided by an embodiment of the present application. As shown in Figure 5, the first fan-out line F1 includes electrically connected first connection lines F11 and second connection lines F12. The second connection lines F12 are electrically connected to the corresponding first data lines DA1 via the first connection lines F11. The plurality of second connection lines F12 extend along the column direction Y and are arranged along the row direction X.

[0059] Exemplarily, among the plurality of second connection lines F12 electrically connected to the same test circuit unit 120, N data lines DA are arranged between two adjacent second connection lines F12; where N is an integer greater than or equal to 2. This is equivalent to inserting a second connection line F12 every N data lines DA among the plurality of second connection lines F12 electrically connected to the same test circuit unit 120. Exemplarily, among the plurality of second connection lines F12 electrically connected to the same test circuit unit 120, the N data lines DA between two adjacent second connection lines F12 are N second data lines DA2. The N second data lines DA2 arranged between two adjacent second connection lines F12 are electrically connected to the same column of pixel units; among the 2N second data lines DA2 arranged between three adjacent second connection lines F12, the N data lines DA and the other N data lines DA are electrically connected to pixel units in different columns, for example, two adjacent columns of pixel units. The plurality of second connection lines F12 electrically connected to the same test circuit unit 120 are electrically connected to the same column of pixel units or at least two adjacent columns of pixel units.

[0060] Exemplarily, any pixel unit 110 includes M sub-pixels P, or any pixel unit 110 is electrically connected to M data lines DA, where M is an integer greater than or equal to 2; any test circuit unit 120 includes K*M first switches 121 and N*K*M second switches 122, where K is an integer greater than or equal to 1.

[0061] Exemplarily, the extension direction of the first connection line F11 intersects the extension direction of the second connection line F12, so that the first fan-out line F1 has a projection along the row direction X. Exemplarily, as shown in FIG5 , the first connection line F11 may extend along the row direction X. Exemplarily, the pixel unit 110 includes M sub-pixels P located in different columns. Exemplarily, the M sub-pixels P in the pixel unit 110 are arranged along the row direction X and are respectively electrically connected to M data lines DA. Alternatively, the pixel unit 110 includes at least two sub-pixels P, and the at least two sub-pixels P are arranged in M ​​columns. In this case, the pixel unit 110 is electrically connected to M data lines DA. The second connection lines F12 corresponding to the same test circuit unit 120 may include K*M lines, each connected to the data lines DA corresponding to the K pixel units 110. In this case, the data lines DA corresponding to the K pixel units 110 may be the first data lines DA1. The second connection lines F12 are inserted between different second data lines DA2, so that N second data lines DA2 are provided between two adjacent second connection lines F12. When the number of second connection lines F12 corresponding to the same test circuit unit 120 is K*M, K*M*(N+1) second fan-out lines F2 can be provided corresponding to the same test circuit unit 120, respectively used to provide test signals to the corresponding second connection lines F12 and the data lines DA between the corresponding second connection lines F12. At the same time, any test circuit unit 120 can include K*M first switches 121 and N*K*M second switches 122. The K*M first switches 121 are electrically connected to the first fan-out line F1 via the second fan-out lines F2, thereby providing test signals to the first data lines DA1 corresponding to the first fan-out lines F1. The number and arrangement of the first switches 121 and the second switches 122 in the test circuit unit 120 are the same or similar, equivalent to a test circuit repeating unit. At the same time, the N*K*M second switches 122 are electrically connected to the second data lines DA2 via the second fan-out lines F2, thereby providing test signals to the second data lines DA2 corresponding to the second fan-out lines F2. When the second ends of the switches electrically connected to the pixel units 110 in the same column are electrically connected to the same test signal line TES; and the second ends of the switches electrically connected to the pixel units 110 in two adjacent columns are electrically connected to different test signal lines TES, different test signals can be provided to different test signal lines TES during the detection process of the display panel, so that the test signals obtained by the two adjacent columns of pixel units 110 are different. When the display panel is normal, a detection screen in which the pixel units 110 are lit at intervals of x columns can be achieved. When the display panel includes p test signal lines TES, x is an integer greater than or equal to 1 and less than or equal to p-1. When the display panel is abnormal, the display panel cannot achieve a detection screen in which the pixel units 110 are lit at intervals of x columns, so that it can be judged whether the display panel has an abnormality based on the detection screen, thereby achieving detection of the display panel.

[0062] For example, when M is 2, N is 2, and K is 2, each pixel unit 110 is electrically connected to two data lines DA, and two data lines DA are provided between two adjacent second connection lines F12. The pixel repeating unit 10 includes two pixel units 110. In this case, four first fan-out lines F14 can be provided corresponding to the same test circuit unit 120, i.e., the number of second connection lines F12 is four, corresponding to twelve second fan-out lines F2. The test circuit unit 120 can also include four first switches 121 and eight second switches 122. Each of the four first switches 121 is electrically connected to the first fan-out line F1 via a second fan-out line F2, thereby providing a test signal to the first data line DA1 corresponding to the first fan-out line F1. Each of the eight second switches 122 is electrically connected to the second data line DA2 via a second fan-out line F2, thereby providing a test signal to the second data line DA2 corresponding to the second fan-out line F2. When there are two test signal lines TES, the second ends of the switches electrically connected to the pixel units 110 in the same column are electrically connected to the same test signal line TES; the second ends of the switches electrically connected to the pixel units 110 in two adjacent columns are electrically connected to different test signal lines TES. During the display panel inspection process, different test signals can be provided to different test signal lines TES so that the two adjacent columns of pixel units 110 receive different test signals. When the display panel is normal, a test image in which every other column of pixel units 110 is illuminated can be achieved. When the display panel is abnormal, the display panel cannot achieve a test image in which every other column of pixel units 110 is illuminated. Therefore, it is possible to determine whether the display panel is abnormal based on the test image, thereby achieving display panel failure detection.

[0063] 5 , multiple pixel units 110 are divided into at least two pixel repeating units 10, and each pixel repeating unit 10 includes K pixel units 110. For example, when K is an integer greater than or equal to 2, each pixel repeating unit 10 may include K adjacent pixel units 110 arranged along a row direction X. K adjacent pixel units 110 in the same row may be considered as one pixel repeating unit 10.

[0064] For example, the pixel repeating unit 10 may be an integer multiple of the pixel units 110 included in the repeated pixel arrangement, that is, the pixel repeating unit 10 includes K pixel units 110, where K is an integer greater than or equal to 1. For example, when the pixel arrangement of the display panel is an RGBG arrangement, two pixel units 110 along the row direction X form one pixel repeating unit.

[0065] On the basis of the above technical solution, referring to FIG5 , the first connection line F11 extends along the row direction X. For example, among the multiple first connection lines F11 arranged along the column direction Y, the longer the first connection line F11 is, the closer the corresponding electrically connected first data line DA1 is to the frame of the display panel, and the longer the length of the corresponding electrically connected second connection line F12 is.

[0066] For example, the display area of ​​the display panel can be a rounded rectangle. The closer the first data line DA1 is to the display panel frame, the shorter it is, and the longer the first and second connection lines F11 and F12 it connects, which helps reduce line impedance differences. This arrangement also prevents the first connection line F11 from intersecting with the non-electrically connected second connection line F12, simplifying the layout of the first fan-out line F1.

[0067] 5 , the plurality of second fan-out lines F2 include at least two third fan-out lines F21 and at least two fourth fan-out lines F22 ; the third fan-out line F21 is electrically connected to the first end of the first switch 121 ; and the fourth fan-out line F22 is electrically connected to the first end of the second switch 122 .

[0068] Exemplarily, at least two third fan-out lines F21 can be electrically connected to the first data line DA1 via the first fan-out line F1. The third fan-out lines F21 are also electrically connected to the first end of the first switch 121, so that when the first switch 121 is turned on, the first data line DA1 is provided with a detection signal via the third fan-out lines F21 and the first fan-out line F1. At least two fourth fan-out lines F22 can be electrically connected to the second data line DA2. The fourth fan-out lines F22 are also electrically connected to the first end of the second switch 122, so that when the second switch 122 is turned on, the second data line DA2 is provided with a detection signal via the fourth fan-out lines F22. When the display panel employs an FIAA structure, the arrangement order of the third fan-out lines F21 along the row direction X differs from the arrangement order of the corresponding electrically connected first data lines DA1. In this case, the drive signals for the third fan-out lines F21 can be provided via the reverse sequence channel of the reverse sequence driver chip. The reverse sequence driver chip can also include a positive sequence channel to provide a drive signal for the fourth fan-out line F22.

[0069] 5 , multiple second fan-out lines F2 are arranged along the row direction X. The arrangement order of the third fan-out lines F21 is opposite to the arrangement order of the corresponding electrically connected first data lines DA1. This arrangement simplifies the corresponding connection relationship between the third fan-out lines F21 and the first data lines DA1.

[0070] For example, the arrangement order of the fourth fan-out lines F22 is the same as the arrangement order of the corresponding electrically connected second data lines DA2. This configuration simplifies the corresponding connection relationship between the fourth fan-out lines F22 and the second data lines DA2.

[0071] Based on the above technical solution, illustratively, among the plurality of second fan-out lines F2 electrically connected to the same test circuit unit 120, N fourth fan-out lines F22 are provided between two adjacent third fan-out lines F21, which is equivalent to inserting a third fan-out line F21 for every fourth fan-out line F22.

[0072] Exemplarily, among the multiple second fan-out lines F2 electrically connected to the same test circuit unit 120, the N fourth fan-out lines F22 arranged between two adjacent third fan-out lines F21 are electrically connected to the same column of pixel units 110; among the 2N fourth fan-out lines F22 arranged between three adjacent third fan-out lines F21, the N fourth fan-out lines F22 and the other N fourth fan-out lines F22 are electrically connected to different columns of pixel units 110, for example, they can be two adjacent columns of pixel units; and / or, in each test circuit unit 120, the multiple first switches 121 and the multiple second switches 122 are arranged along the row direction X; and N second switches 122 are arranged between two adjacent first switches 121.

[0073] Exemplarily, the number of third fan-out lines F21 is equal to the number of second connection lines F12, and they are electrically connected to the second connection lines F12 in a one-to-one correspondence. When the second connection lines F12 corresponding to the same test circuit unit 120 include K*M lines, and are respectively connected to the first data lines DA1 corresponding to K pixel units 110, the third fan-out lines F21 are electrically connected to the corresponding K pixel units 110. The fourth fan-out line F22 is electrically connected to the second data line DA2 and is electrically connected to the corresponding K*N pixel units 110. When N fourth fan-out lines F22 are provided between two adjacent third fan-out lines F21, the repeating unit of the third fan-out lines F21 and the fourth fan-out lines F22 has a total of K*M*(N+1) second fan-out lines F2.

[0074] When N data lines DA are set between two adjacent second connection lines F12, N fourth fan-out lines F22 can be set between two adjacent third fan-out lines F21, so that the third fan-out line F21 can be connected to the corresponding second connection line F12. At the same time, the N fourth fan-out lines F22 between two adjacent third fan-out lines F21 are electrically connected to the same column of pixel units 110, so that the N fourth fan-out lines F22 between two adjacent third fan-out lines F21 can be connected to the N data lines DA between the corresponding two adjacent second connection lines F12, which can simplify the line arrangement of the non-display area NAA. At the same time, the N fourth fan-out lines F22 arranged between two adjacent third fan-out lines F21 are electrically connected to the same column of pixel units 110. Among the 2N fourth fan-out lines F22 arranged between three adjacent third fan-out lines F21, N fourth fan-out lines F22 and another N fourth fan-out lines F22 are electrically connected to different columns of pixel units 110. This allows K*M*(N+1) second fan-out lines F2 to be electrically connected to K pixel units 110 in the same pixel repeating unit 10. In this way, the K*M*(N+1) second fan-out lines F2 can be electrically connected to the pixel units 110 in multiple pixel repeating units 10 through switches in a test circuit unit 120, thereby implementing defect detection of the display panel.

[0075] Exemplarily, N is an integer multiple of M. N can be greater than or equal to M. The larger N is, the more second fan-out lines a test circuit unit 120 corresponds to. Since the test circuit unit 120 acts as a circuit duplication unit, the greater the number of second fan-out lines corresponding to the test circuit unit 120, the higher the labor cost and lower the efficiency of sorting and checking the third and fourth fan-out lines. The larger N is, the fewer first data lines there are, which is not conducive to reducing the frame size. The larger N is, the more likely it is to increase the probability of short circuit detection.

[0076] In addition, in other embodiments, it is possible to arrange in each test circuit unit 120 a plurality of first switches 121 and a plurality of second switches 122 along the row direction X; and N second switches 122 are arranged between two adjacent first switches 121, so that the first switch 121 can be electrically connected to the corresponding third fan-out line F21 in sequence, and the second switch 122 can be electrically connected to the corresponding fourth fan-out line F22 in sequence, thereby further simplifying the wiring design of the non-display area NAA.

[0077] Based on the above technical solution, illustratively, in each test circuit unit 120, the second ends of the N second switches 122 located between two adjacent first switches 121 are electrically connected to the same test signal line TES; among the 2N second switches 122 between three adjacent first switches 121, the second ends of N second switches 122 and the second ends of another N second switches 122 are electrically connected to different test signal lines TES.

[0078] For example, when the second ends of the N second switches 122 located between two adjacent first switches 121 are electrically connected to the same test signal line TES, when the N second switches 122 located between the two adjacent first switches 121 are electrically connected to the same column of pixel units 110, the second ends of the switches electrically connected to the pixel units 110 in the same column can be electrically connected to the same test signal line TES. When the second ends of N of the 2N second switches 122 located between three adjacent first switches 121 are electrically connected to different test signal lines TES, when the N fourth fan-out lines F22 and the N other fourth fan-out lines F22 are electrically connected to different columns of pixel units 110, the second ends of the switches electrically connected to the pixel units 110 in two adjacent columns can be electrically connected to different test signal lines TES, thereby enabling detection of alternating lighting along the column direction Y of the display panel.

[0079] Based on the above technical solution, the multiple first switches in each test circuit unit are electrically connected to a column of pixel units or at least two adjacent columns of pixel units; the multiple second switches in each test circuit unit are electrically connected to multiple adjacent columns of pixel units.

[0080] Exemplarily, the test circuit unit includes K*M first switches and N*K*M second switches. When K is 1, the test circuit unit may include M first switches and N*M second switches. In this case, the M first switches can be electrically connected to a column of pixel cells, and the N*M second switches can be electrically connected to N adjacent columns of pixel cells. When K is greater than 1, the test circuit unit may include K*M first switches and K*N*M second switches. In this case, the K*M first switches can be electrically connected to K adjacent columns of pixel cells, and the K*N*M second switches can be electrically connected to K adjacent columns of pixel cells. At the same time, N data lines are arranged between two adjacent second connection lines F12, so that the pixel cells electrically connected to the first switches 121 are arranged adjacent to each other, and the pixel cells electrically connected to the second switches are arranged adjacent to each other. In this case, the test circuit unit can be electrically connected to at least some of the adjacent K*(N+1) columns of pixel cells. When the second fan-out lines and the corresponding electrically connected data lines are arranged in a different order, this helps to simplify the wiring layout between the test circuit and the corresponding electrically connected pixel cells.

[0081] Exemplarily, M is equal to N.

[0082] For example, when a pixel unit is electrically connected to M data lines, K*M second connection lines may be provided corresponding to the same test circuit unit 120, for electrically connecting to the data lines corresponding to K columns of pixel units. M data lines may also be provided between two adjacent second connection lines, so that the data lines between the two adjacent second connection lines can be electrically connected to the pixel units in the same column. This facilitates simplifying the wiring design of the data lines and the corresponding second fan-out lines when the second fan-out lines and the corresponding electrically connected data lines are arranged in a different order.

[0083] Figure 6 is a partially enlarged schematic diagram of another display panel provided in an embodiment of the present application. As shown in Figure 6, the display panel further includes N+1 rows of pads 130 located in the non-display area NAA. Each row of pads 130 includes multiple pads 130 arranged along the row direction X. One row of pads 130 is electrically connected to the third fan-out line F21 electrically connected to the first switch 121, and is arranged in the opposite order to the corresponding data line DA. The remaining N rows of pads 130 are electrically connected to the fourth fan-out line F22 electrically connected to the second switch 122, and are arranged in the same order as the corresponding data line DA.

[0084] Exemplarily, the pads 130 are arranged in the non-display area NAA, for receiving a driving signal input from the outside, and transmitting it to the data line DA through the first fan-out line F1 and the second fan-out line F2, for providing a driving signal to the pixel unit 110 electrically connected to the data line DA, thereby driving the display panel. The arrangement order of the pads 130 can be set according to the port sequence of the driver chip that provides the driving signal. Exemplarily, along the row direction X, when the arrangement order of the ports of the driver chip corresponding to a row of pads 130 is in positive sequence, the arrangement order of the pads 130 in a row is in positive sequence, which is the same as the arrangement order of the corresponding electrically connected data lines DA. When the arrangement order of the ports of the driver chip corresponding to a row of pads 130 is in reverse sequence, the arrangement order of the pads 130 in a row is in reverse sequence, which is opposite to the arrangement order of the corresponding electrically connected data lines DA. For example, along the row direction X, the sequence numbering of the positive-sequence ports in one row is odd-numbered ports and can be increased from 361-363-365-367..., and the sequence numbering of the positive-sequence ports in another row is even-numbered ports and can be increased from 362-364-366-368... In this case, the pads corresponding to the two rows of positive-sequence ports are arranged in positive sequence. The sequence numbering of the reverse-sequence ports is decreased from 360-359-358-357..., and the pads corresponding to the reverse-sequence ports are arranged in reverse sequence, and the sequence numbering of the pad 130 can be consistent with the data numbering of the port.

[0085] The arrangement order of the third fan-out lines F21 is opposite to the arrangement order of the corresponding electrically connected first data lines DA1, and the third fan-out lines F21 are electrically connected to the first end of the first switch 121. In this case, a row of pads 130 is provided that is electrically connected to the third fan-out lines F21 electrically connected to the first switch 121, and the arrangement order is opposite to the arrangement order of the corresponding electrically connected data lines DA. This allows the arrangement order of the row of pads 130 and the third fan-out lines F21 to be the same, which helps simplify the connection between the pads 130 and the third fan-out lines F21 and also simplifies the port layout of the driver chip used to provide the drive signal. Similarly, the arrangement order of the fourth fan-out line F22 is the same as the arrangement order of the corresponding electrically connected second data line DA2. At the same time, the fourth fan-out line F22 is electrically connected to the first end of the second switch 121. At this time, N rows of pads 130 are set to be electrically connected to the fourth fan-out line F22 electrically connected to the second switch 122, and the arrangement order is the same as the corresponding electrically connected data line DA. This can make the arrangement order of the N rows of pads 130 and the fourth fan-out line F22 the same, which is conducive to simplifying the connection between the pads 130 and the fourth fan-out line F22, and at the same time can simplify the port layout of the driver chip used to provide the drive signal.

[0086] For example, FIG7 is a schematic diagram of the structure of a pad provided in an embodiment of the present application, and FIG8 is a schematic diagram of a partially enlarged structure of another display panel provided in an embodiment of the present application. As shown in FIG7 and FIG8, when N is 2, two adjacent second connection lines F12 are separated by two second data lines DA2. At this time, the display panel is provided with three rows of pads 130, one of which is a reverse sequence pad, and the other two rows of pads 130 are positive sequence pads. For example, as shown in FIG8, the sequence numbering of the reverse sequence pads decreases from 360-359-358-357..., wherein the sequence numbering of one row of positive sequence pads is an odd-numbered port, which can be increased from 361-363-365-367..., and the sequence numbering of another row of positive sequence pads is an even-numbered port, which can be increased from 362-364-366-368... Each row exemplarily shows four pads 130. The reverse-sequence pads can be sequentially electrically connected to the third fan-out line F21 electrically connected to the first switch 121, with the reverse-sequence pads being numbered in the opposite order to the corresponding data lines DA. This matches the port layout of the driver chip, allowing the driver chip to provide a drive signal to the data line electrically connected to the third fan-out line F21. Simultaneously, the positive-sequence pads can be sequentially electrically connected to the fourth fan-out line F22 electrically connected to the second switch 122, with the positive-sequence pads being numbered in the same order to the corresponding data lines DA. This matches the port layout of the driver chip, allowing the driver chip to provide a drive signal to the data line electrically connected to the fourth fan-out line F22, thereby enabling display on the display panel.

[0087] Continuing with reference to Figures 2 to 6 , based on the above technical solution, when N is 2, M is 2, and K is 2, each pixel unit 110 is electrically connected to two data lines DA, and two data lines DA are provided between two adjacent second connection lines F12. The pixel repeating unit 10 includes two adjacent pixel units 110 in the same row. The test circuit unit 120 may include four first switches 121 and eight second switches 122. Four first fan-out lines F1 and twelve second fan-out lines F2 may be provided corresponding to the same test circuit unit 120. The twelve second fan-out lines F2 are arranged to electrically connect six columns of pixel units 10, at least partially adjacent to each other. The four first fan-out lines F1 are arranged to electrically connect two columns of pixel units 10, four third fan-out lines of the twelve second fan-out lines F2 are arranged to electrically connect two columns of pixel units 10, and eight third fan-out lines are arranged to electrically connect four columns of pixel units 10. When the second ends of the switches electrically connected to the pixel units 110 in the same column are electrically connected to the same test signal line TES; and the second ends of the switches electrically connected to the pixel units 110 in two adjacent columns are electrically connected to different test signal lines TES, different test signals can be provided to different test signal lines TES during the detection process of the display panel, so that the test signals obtained by the two adjacent columns of pixel units 110 are different. When the display panel is normal, a detection screen in which the pixel units 110 are lit at intervals of x columns can be achieved. When the display panel includes p test signal lines TES, x is an integer greater than or equal to 1 and less than or equal to p-1. When the display panel is abnormal, the display panel cannot achieve a detection screen in which the pixel units 110 are lit at intervals of x columns, so that it is possible to judge whether the display panel is abnormal based on the detection screen, thereby achieving a defect detection of the display panel.

[0088] For example, adjacent second fan-out lines F2 can be arranged alternately in different layers, such that two second fan-out lines F2 electrically connected to the same column of pixel units 110 are arranged in different layers, two of the four second fan-out lines F2 electrically connected to two adjacent columns of pixel units 110 are arranged in the same layer, and the remaining two second fan-out lines F2 are arranged in the same layer. For example, the display panel includes a first conductive layer and a second conductive layer. The three pixel repeating units 10 electrically connected to the test circuit unit 120 can be arranged in the same row and adjacent to each other or partially non-adjacent to each other. The four first switches 121 electrically connected to one pixel repeating unit 10 are located on one side of the display area AA relative to the two pixel repeating units 10 electrically connected to the eight second switches 122. The second fan-out lines F2 are arranged in the opposite order to the first data lines DA1 to which they are electrically connected, and the second fan-out lines F2 are arranged in the same order as the second data lines DA2 to which they are electrically connected. In the same test circuit unit 120, the four first switches 121 electrically connected to one pixel repeating unit 10 and the eight second switches 122 electrically connected to two pixel repeating units 10 are in the same row and may be adjacent or non-adjacent. The eight second switches 122 electrically connected to two pixel repeating units 10 are in the same row and adjacent. For example, a test circuit unit 120 may be configured with 12 second fan-out lines F2 arranged along the positive direction of the row direction X, respectively located at the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer, the first conductive layer, the second conductive layer. The second fan-out lines F2 electrically connected to the same column of pixel units 110 are arranged in different layers. The second fan-out lines F2 electrically connected to adjacent columns of pixel units 110 are at least partially arranged in the same layer, with no second fan-out lines in the same layer between them. When a short circuit occurs, it can be detected. The second fan-out lines F2 electrically connected to the pixel units 110 in odd columns and the second fan-out lines F2 electrically connected to the pixel units 110 in even columns are at least partially arranged in the same layer, and there is no second fan-out line in the same layer between them. When a short circuit occurs, it can be detected. When the second end of the switch electrically connected to the pixel units 110 in the same column is electrically connected to a test signal line TES; and the second end of the switch electrically connected to the pixel units 110 in two adjacent columns is electrically connected to another test signal line TES, during the detection process of the display panel, different test signals can be provided to different test signal lines TES, so that the test signals obtained by the pixel units 110 in the two adjacent columns are different. When the display panel is normal, a detection screen in which alternate columns are lit can be achieved. When the second fan-out lines F2 are short-circuited in the same layer, the pixel units 110 in two adjacent columns or two non-adjacent columns can be lit at the same time, and the brightness is between the maximum brightness and off, making it impossible to achieve a detection screen in which alternate columns of the display panel are lit, thereby achieving fault detection of the display panel.

[0089] Exemplarily, the plurality of pixel units 110 include at least two first pixel units 110A and at least two second pixel units 110B. The first pixel unit 110A includes a first color sub-pixel P1 and a second color sub-pixel P2; the second pixel unit 110B includes a third color sub-pixel P3 and a second color sub-pixel P2. In the same row of pixel units 110, the first pixel units 110A and the second pixel units 110B are alternately arranged along the row direction X. The first pixel unit 110A includes a first color sub-pixel P1 and a second color sub-pixel P2 located in different columns; the second pixel unit 110B includes a third color sub-pixel P3 and a second color sub-pixel P2 located in different columns.

[0090] Continuing with reference to Figures 2 to 6, the pixel unit 110 can be divided into a first pixel unit 110A and a second pixel unit 110B based on the colors of the sub-pixels included. The first pixel unit 110A can include a first color sub-pixel P1 and a second color sub-pixel P2 arranged along the row direction X, such that the first pixel unit 110A has two columns of sub-pixels P, correspondingly connected to two data lines DA. The second pixel unit 110B can include a third color sub-pixel P3 and a second color sub-pixel P2 arranged along the row direction X, such that the second pixel unit 110B also has two columns of sub-pixels P, correspondingly connected to two data lines DA. Within the same row of pixel units 110, the first pixel units 110A and the second pixel units 110B are alternately arranged along the row direction X, such that two adjacent first pixel units 110A and second pixel units 110B in the same row along the row direction X constitute the minimum repeating unit of the pixel arrangement. In addition, two adjacent columns of pixel units 110 include a first pixel unit 110A and a second pixel unit 110B, that is, two adjacent columns of pixel units 110 simultaneously include a first color sub-pixel P1, a second color sub-pixel P2 and a third color sub-pixel P3, which is beneficial to ensure the uniformity of the mixed color light of the display panel.

[0091] Exemplarily, in the same column of pixel units 110 , the first pixel units 110A and the second pixel units 110B are alternately arranged along the column direction Y.

[0092] Continuing with reference to Figures 2 to 6 , within the same column of pixel units 110, first pixel units 110A and second pixel units 110B are alternately arranged along the column direction Y, such that two adjacent first pixel units 110A and second pixel units 110B in the same row along the column direction Y constitute the minimum repeating unit of the pixel arrangement. Furthermore, two adjacent rows of pixel units 110 include the first pixel unit 110A and the second pixel unit 110B, i.e., the pixel units 110 in two adjacent rows simultaneously include the first color sub-pixel P1, the second color sub-pixel P2, and the third color sub-pixel P3, which also helps ensure uniformity of the mixed color light of the display panel.

[0093] For example, Figure 9 is a partially enlarged schematic diagram of another display panel provided in an embodiment of the present application. As shown in Figure 9, in two adjacent columns of sub-pixels P, the first color sub-pixels P1 and the third color sub-pixels P3 in one column of sub-pixels P are alternately arranged along the column direction Y; the sub-pixels 110 in the other column are all second color sub-pixels P2.

[0094] Exemplarily, the first pixel unit 110A and the second pixel unit 110B both include a second color sub-pixel P2. When the first pixel unit 110A and the second pixel unit 110B are alternately arranged along the column direction Y in the same column of pixel units 110, the second color sub-pixels P2 in the first pixel unit 110A and the second pixel unit 110B can be arranged in the same column, the first color sub-pixel P1 and the third color sub-pixel P3 can be arranged in the same column, and the first color sub-pixel P1 and the third color sub-pixel P3 are alternately arranged along the column direction Y, which is beneficial to ensure the uniformity of the mixed color light of the display panel.

[0095] For example, the first color subpixel P1 is a red subpixel, the second color subpixel P2 is a green subpixel, and the third color subpixel P3 is a blue subpixel. In this case, the pixel arrangement of the display panel is an RGBG arrangement. That is, the red subpixels and blue subpixels are arranged in the same column, and the green subpixels are arranged in the same column. In two adjacent columns of subpixels, the red and blue subpixels are arranged alternately in one column, while the subpixels in the other column are all green subpixels. In the same row of subpixels, the red subpixels, green subpixels, blue subpixels, and green subpixels are arranged in a cyclical sequence.

[0096] Exemplarily, each test circuit unit 120 includes 4 first switches 121 and 8 second switches 122, and 2 data lines DA are set between two adjacent second connection lines F12; the 4 first switches 121 in each test circuit unit 120 are electrically connected to two adjacent columns of pixel units 110; and the 8 second switches 122 in each test circuit unit 120 are electrically connected to 4 adjacent columns of pixel units 110.

[0097] For example, when N is 2, M is 2, and K is 2, the pixel repeating unit 10 includes two pixel units 110. In this case, the pixel repeating unit 10 is electrically connected to four data lines DA. In this case, the test circuit unit 120 can be configured to include four first switches 121 and eight second switches 122, corresponding to four first fan-out lines F1 and twelve second fan-out lines F2. Among them, the first fan-out line F1 includes a first connection line F11 and a second connection line F12. The four first switches 121 are respectively electrically connected to the four first data lines DA1 electrically connected to a pixel repeating unit 10 through the second connection line F12. Among the eight second switches 122, two adjacent second switches 122 are respectively electrically connected to the two data lines DA between two adjacent second connection lines F12. The eight second switches 122 are electrically connected to the eight first data lines DA1 electrically connected to two adjacent pixel repeating units 10 in the same row, so that the test circuit unit 120 can be electrically connected to the three pixel repeating units 10 in the same row through the first fan-out line F1 and the second fan-out line F2. The corresponding connection relationship between the three pixel repetition units 10 and the test circuit unit 120 in the same row can serve as the minimum repetition unit of the corresponding connection relationship between the test circuit unit 120 and the pixel unit 110. When the display panel includes multiple rows and columns of pixel units 110, the corresponding connection between all the test circuit units 120 and the pixel units 110 in the display panel is realized according to the minimum repetition unit of the corresponding connection relationship between the test circuit unit 120 and the pixel unit 110.

[0098] For example, of the four first switches 121 in each test circuit unit 120, two adjacent first switches 121 on one side are electrically connected to the same column of pixel units 110, and the other two adjacent first switches 121 on the other side are electrically connected to the same column of pixel units 110. By electrically connecting two adjacent first switches 121 to two data lines DA of the same column of pixel units 110, the probability of spatial overlap between the first switches 121 and the correspondingly electrically connected pixel units 110 can be reduced, thereby simplifying wiring design.

[0099] Figure 10 is a schematic diagram of a partial structure of another display panel provided in an embodiment of the present application. Figure 11 is a schematic diagram of an enlarged partial structure of another display panel provided in an embodiment of the present application. As shown in Figures 10 and 11, N is 3, M is 3, and K is 1. In this case, each pixel unit 110 is electrically connected to three data lines DA, and three data lines DA are arranged between two adjacent second connection lines F12. The pixel repeating unit 10 includes one pixel unit 110. The test circuit unit 120 may include three first switches 121 and nine second switches 122. The display panel also includes three first fan-out lines F1 and twelve second fan-out lines F2. The three first switches 121 are each electrically connected to the first fan-out line F1 via a second fan-out line F2, thereby providing a test signal to the first data line DA1 corresponding to the first fan-out line F1. Simultaneously, the nine second switches 122 are each electrically connected to the second data line DA2 between the second fan-out line F2 and the second connection line F12, thereby providing a test signal to the second data line DA2 corresponding to the second fan-out line F2. When there are two test signal lines TES, the second ends of the switches electrically connected to the pixel units 110 in the same column are electrically connected to the same test signal line TES; the second ends of the switches electrically connected to the pixel units 110 in two adjacent columns are electrically connected to different test signal lines TES. During the display panel inspection process, different test signals can be provided to different test signal lines TES so that the two adjacent columns of pixel units 110 receive different test signals. When the display panel is normal, a test screen in which the pixel units 110 are lit up in alternate columns can be achieved. When the display panel is abnormal, the display panel cannot achieve a test screen in which the pixel units 110 are lit up in alternate columns. Therefore, it is possible to determine whether the display panel is abnormal based on the test screen, thereby achieving display panel failure detection.

[0100] For example, adjacent second fan-out lines F2 may be arranged alternately in different layers. For example, the display panel includes a first conductive layer and a second conductive layer. The pixel repeating unit 10 electrically connected to the three first switches 121 is located on one side of the display area AA (e.g., the first display area) relative to the three pixel repeating units 10 electrically connected to the nine second switches 122. The second fan-out lines F2 are arranged in the opposite order to the first data lines DA1 to which they are electrically connected, and the second fan-out lines F2 are arranged in the same order as the second data lines DA2 to which they are electrically connected. For example, the twelve second fan-out lines F2 arranged along the positive direction of the row direction X and corresponding to the same test circuit unit are located in the first conductive layer, the second conductive layer, ... For example, the second fan-out lines F2 electrically connected to the pixel units 110 in odd columns and the second fan-out lines F2 electrically connected to the pixel units 110 in even columns are at least partially arranged in the same layer, and there is no second fan-out line in the same layer between them. When a short circuit occurs, it can be detected. When the second end of the switch electrically connected to the pixel units 110 in the same column is electrically connected to a test signal line TES; and the second end of the switch electrically connected to the pixel units 110 in two adjacent columns is electrically connected to another test signal line TES, during the detection process of the display panel, different test signals can be provided to different test signal lines TES, so that the test signals obtained by the two adjacent columns of pixel units 110 are different. When the display panel is normal, a detection screen in which alternate columns are lit can be achieved. When the second fan-out lines F2 are short-circuited in the same layer, the pixel units 110 in the two adjacent columns can be lit at the same time, and the brightness is between the maximum brightness and off. It is impossible to achieve a detection screen in which alternate columns of the display panel are lit, thereby achieving a defect detection of the display panel.

[0101] Alternatively, the display panel may include a first conductive layer, a second conductive layer, and a third conductive layer. The four pixel repeating units 10 electrically connected to the test circuit unit 120 may be arranged adjacently or partially adjacently. The one pixel repeating unit 10 electrically connected to the three first switches 121 may be located on one side of the display area AA (e.g., the first display area) relative to the three pixel repeating units 10 electrically connected to the nine second switches 122. The second fan-out lines F2 and the corresponding first data lines DA1 may be arranged in the opposite order, while the second fan-out lines F2 and the corresponding second data lines DA2 may be arranged in the same order. In this case, the twelve second fan-out lines F2 arranged along the positive direction of the row direction X are respectively located in the first conductive layer, the second conductive layer, the third conductive layer, the first conductive layer, the second conductive layer, the third conductive layer, the first conductive layer, the second conductive layer, the third conductive layer, the first conductive layer, the second conductive layer, the third conductive layer, the first conductive layer, the second conductive layer, and the third conductive layer. The second fan-out lines F2 electrically connected to adjacent columns of pixel units 110 may be at least partially arranged in the same layer, with no second fan-out lines in the same layer between them. Short circuits can be detected. For example, the second fan-out lines F2 electrically connected to the pixel units 110 in odd columns and the second fan-out lines F2 electrically connected to the pixel units 110 in even columns are at least partially arranged in the same layer, and there is no second fan-out line in the same layer between them. When a short circuit occurs, it can be detected. When the second end of the switch electrically connected to the pixel units 110 in the same column is electrically connected to a test signal line TES; and the second end of the switch electrically connected to the pixel units 110 in two adjacent columns is electrically connected to another test signal line TES, during the detection process of the display panel, different test signals can be provided to different test signal lines TES, so that the test signals obtained by the two adjacent columns of pixel units 110 are different. When the display panel is normal, a detection screen in which alternate columns are lit can be achieved. When the second fan-out lines F2 are short-circuited in the same layer, the pixel units 110 in the two adjacent columns can be lit at the same time, and the brightness is between the maximum brightness and off. It is impossible to achieve a detection screen in which alternate columns of the display panel are lit, thereby achieving a defect detection of the display panel.

[0102] In addition, the display panel may be provided with four rows of pads 130 in the non-display area NAA, each row of pads 130 including a plurality of pads 130 arranged along the row direction X. One row of pads 130 is electrically connected to the third fan-out line F21 electrically connected to the first switch 121, and is arranged in the opposite order to the corresponding electrically connected data line DA; the remaining three rows of pads 130 are electrically connected to the fourth fan-out line F22 electrically connected to the second switch 122, and are arranged in the same order as the corresponding electrically connected data line DA. Continuing with reference to FIG. 11 , for example, the reverse order pads are sequentially numbered from 180-179-178, etc., while the sequence of the positive order pads in one row may be sequentially numbered from 181-184-187, etc., and the sequence of the positive order pads in another row may be sequentially numbered from 182-185-188, etc., and the sequence of the positive order pads in another row may be sequentially numbered from 183-186-189, etc. 11 , three pads are shown in each row. The reverse-sequence pads can be sequentially electrically connected to the third fan-out line F21 electrically connected to the first switch 121, such that the sequence of the reverse-sequence pads is opposite to the order of the corresponding data lines DA electrically connected thereto, to match the port layout of the driver chip. This allows the driver chip to provide a drive signal to the data line electrically connected to the third fan-out line F21. Simultaneously, the positive-sequence pads can be sequentially electrically connected to the fourth fan-out line F22 electrically connected to the second switch 122, such that the sequence of the positive-sequence pads is the same as the order of the corresponding data lines DA electrically connected thereto, to match the port layout of the driver chip. This allows the driver chip to provide a drive signal to the data line electrically connected to the fourth fan-out line F22, thereby enabling display on the display panel.

[0103] Exemplarily, any pixel unit 110 includes a first color subpixel P1, a second color subpixel P2, and a third color subpixel P3; each row of subpixels P is arranged cyclically in the order of first color subpixel P1, second color subpixel P2, and third color subpixel P3; each column of subpixels P is a subpixel of the same color. Exemplarily, any pixel unit 110 includes a first color subpixel P1, a second color subpixel P2, and a third color subpixel P3 located in different columns.

[0104] Continuing with reference to FIG. 10 , the pixel unit 110 includes, for example, a first color sub-pixel P1, a second color sub-pixel P2, and a third color sub-pixel P3 arranged along a row direction X. This allows the pixel unit 110 to have three columns of sub-pixels P, correspondingly connected to three data lines DA. For example, each pixel unit 110 includes a first color sub-pixel P1, a second color sub-pixel P2, and a third color sub-pixel P3, which helps ensure uniform color mixing on the display panel. Each row of sub-pixels P is arranged cyclically in the order of the first color sub-pixel P1, the second color sub-pixel P2, and the third color sub-pixel P3, such that, along the row direction X, one pixel unit 110 represents the minimum repeating unit of the pixel arrangement.

[0105] For example, the first color subpixel P1 is a red subpixel, the second color subpixel P2 is a green subpixel, and the third color subpixel P3 is a blue subpixel. In this case, the pixel arrangement of the display panel is an RGB arrangement. That is, the subpixels P in each row are arranged cyclically in the order of red subpixels, blue subpixels, and green subpixels, and the red subpixels, blue subpixels, and green subpixels are arranged in the same column.

[0106] Exemplarily, each test circuit unit 120 includes 3 first switches 121 and 9 second switches 122, and 3 data lines DA are set between two adjacent second connection lines F12; the 3 first switches 121 in each test circuit unit 120 are electrically connected to the pixel units 110 in the same column; and the 9 second switches 122 in each test circuit unit 120 are electrically connected to the 3 adjacent columns of pixel units 110.

[0107] For example, when N is 3, M is 3, and K is 1, the pixel repeating unit 10 includes one pixel unit 110. In this case, the pixel repeating unit 10 is electrically connected to three data lines DA. In this case, the test circuit unit 120 can be configured to include three first switches 121 and nine second switches 122, corresponding to three first fan-out lines F1 and twelve second fan-out lines F2. The first fan-out lines F1 include first connection lines F11 and second connection lines F12. The three first switches 121 are each electrically connected to the three first data lines DA1 electrically connected to one pixel repeating unit 10 via the second connection lines F12. Of the nine second switches 122, three adjacent second switches 122 are each electrically connected to the three data lines DA between two adjacent second connection lines F12. This allows the test circuit unit 120 to be electrically connected to four pixel repeating units 10 via the first fan-out lines F1 and the second fan-out lines F2. Moreover, the corresponding connection relationship between the four pixel repetition units 10 and the test circuit unit 120 can serve as the minimum repetition unit of the corresponding connection relationship between the test circuit unit 120 and the pixel unit 110. When the display panel includes multiple rows and columns of pixel units 110, the corresponding connection between all the test circuit units 120 and the pixel units 110 in the display panel is realized according to the minimum repetition unit of the corresponding connection relationship between the test circuit unit 120 and the pixel unit 110.

[0108] Based on the above technical solution, referring to Figure 12, at least part of the second fan-out lines F2 are located in the same conductive layer. Figure 12 is a schematic cross-sectional view taken along the C1C2 direction in Figure 9. Figure 12 is a schematic cross-sectional view taken along the D1D2 direction in Figure 11.

[0109] Exemplarily, when at least some of the second fan-out lines are located in the same conductive layer and electrically connected to corresponding columns of pixel units, with no second fan-out lines in the same layer between them, if the second ends of the switches electrically connected to corresponding columns of pixel units in the same column are electrically connected to one test signal line, and the second ends of the switches electrically connected to corresponding columns of pixel units in adjacent columns are electrically connected to another test signal line, during display panel testing, if the second fan-out lines located in the same conductive layer are short-circuited, the display panel will not be able to achieve a test image in which alternate columns of pixel units in adjacent columns are illuminated. Therefore, it is possible to determine whether the display panel is abnormal based on the test image, thereby achieving display panel failure detection.

[0110] For example, referring to FIG11 , multiple second fan-out lines F2 are arranged in a row direction, and two adjacent second fan-out lines F2 are located on different conductive layers (e.g., a first conductive layer 301 and a second conductive layer 302 on a substrate 300, which may be metal layers). Of three adjacent second fan-out lines F2, two second fan-out lines F2 located on opposite sides are located on the same conductive layer. An insulating layer may be provided between adjacent conductive layers.

[0111] Exemplarily, the number of second fan-out lines is relatively large. By arranging at least some of the adjacent second fan-out lines in different conductive layers, it is beneficial to ensure the spacing between the second fan-out lines and simplify the arrangement of the second fan-out lines. At the same time, two adjacent second fan-out lines are located in different conductive layers; among the three adjacent second fan-out lines, the two second fan-out lines located on both sides are located in the same conductive layer. When arranged along the row direction, the second fan-out lines can be alternately arranged in different conductive layers, which can further ensure the spacing between the second fan-out lines. Based on the above technical solution, some or all of the second fan-out lines corresponding to the same column of pixel units can be arranged in different layers, and at least some of the second fan-out lines corresponding to adjacent columns of pixel units can be arranged in the same layer.

[0112] Based on the above technical solution, Figure 13 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. As shown in Figure 13, the display area AA includes a first display area AA1, a second display area AA2, and a third display area AA3 arranged in sequence along the row direction X. The first data line DA1 is located in the first display area AA1 and the third display area AA3, and the second data line DA2 is located in the second display area AA2.

[0113] Exemplarily, along the row direction X, the first display area AA1 and the third display area AA3 are located on either side of the display area AA, and the second display area AA2 is located in the middle of the display area AA. The first display area AA1 and the third display area AA3 may be located on opposite sides of the second display area AA2 along the row direction X. Exemplarily, all second connection lines F12 are located in the second display area AA2. Longer second connection lines F12 may be closer to the data lines in the middle of the second display area AA2.

[0114] Exemplarily, the number of first data lines DA1 corresponding to the first display area AA1 can be equal to the number of first data lines DA1 corresponding to the third display area AA3. Exemplarily, when the first display area AA1 corresponds to 360 first data lines DA1, the third display area AA3 also corresponds to 360 first data lines DA1. Furthermore, if the display area AA includes 2560 data lines DA, then the second display area AA2 corresponds to 1840 second data lines DA2, and the first first data line DA1 corresponding to the third display area AA3 is the 2201st data line DA. Exemplarily, the data lines DA are numbered in a direction from the first display area AA1 to the second display area AA2: the data lines DA in the first display area AA1 are numbered 1 to 360, the data lines DA in the second display area AA2 are numbered 361 to 2200, and the data lines DA in the third display area AA3 are numbered 2201 to 2560. The multiple test circuit units 120 connected to the first data line DA1 of the first display area AA1 and the multiple test circuit units 120 connected to the first data line DA1 of the third display area AA3 can be symmetrically arranged, with the axis of symmetry parallel to the column direction. The multiple first fan-out lines F1 connected to the first data line DA1 of the first display area AA1 and the multiple first fan-out lines F1 connected to the first data line DA1 of the third display area AA3 can be symmetrically arranged, with the axis of symmetry parallel to the column direction. The multiple second fan-out lines F2 connected to the first data line DA1 of the first display area AA1 and the multiple second fan-out lines F2 connected to the first data line DA1 of the third display area AA2 can be symmetrically arranged, with the axis of symmetry parallel to the column direction. Exemplarily, the display panel may further include a third switch 140. The first end of the third switch 140 may be electrically connected to the second data line DA2 via the corresponding second fan-out line F2. The second end of the third switch 140 may be electrically connected to the corresponding test signal line. The test circuit unit 120 may be located on opposite sides of the third switch 140 along direction X. The control end of the third switch 140 can be electrically connected to the control signal line CTRL. The same column of pixel units electrically connected to the third switch 140 is electrically connected to the same test signal line. The two adjacent columns of pixel units electrically connected to the third switch 140 are electrically connected to different test signal lines via the third switch 140. For example, the odd-numbered column of pixel units 110 electrically connected to the third switch 140 is electrically connected to the first test signal line TES1 via the third switch 140; the even-numbered column of pixel units 110 electrically connected to the third switch 140 is electrically connected to the second test signal line TES2 via the third switch 140. When performing display panel testing, the first test signal line TES1 and the second test signal line TES2 can be used to input a lighting voltage and an off voltage, respectively. When the display panel is normal, a test screen in which two adjacent columns of pixel units 110 are lit every other column can be achieved.When the display panel is abnormal, the display panel cannot achieve a detection image in which two adjacent columns of pixel units 110 are lit in alternate columns. Therefore, it is possible to determine whether the display panel is abnormal based on the detection image, thereby achieving display panel failure detection. Exemplarily, the third switch 140 includes a third transistor, the first electrode of the third transistor serving as the first end of the third switch 140, the second electrode of the third transistor serving as the second end of the third switch 140, and the control electrode of the third transistor serving as the control end of the third switch 140.

[0115] The present application also provides a display device. Figure 14 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. As shown in Figure 14, the display device 00 includes a driver chip 20 and a display panel 21 provided in any embodiment of the present application. The driver chip 20 is electrically connected to the second fan-out line.

[0116] Exemplarily, the driver chip 20 is electrically connected to the second fan-out line, and a drive signal can be provided to the display panel through the second fan-out line. Exemplarily, the display panel may further include a pad located in the binding area, and the driver chip 20 may be connected by binding with the pad, and then electrically connected to the second fan-out line. Since the display device 00 includes the display panel provided by any embodiment of the present application, it has the same beneficial effects as the display panel provided by any embodiment of the present application, and will not be described in detail here. The display device 00 can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, etc.

[0117] The present application also provides a display panel testing method, applicable to the display panel provided in any embodiment of the present application. FIG15 is a flow chart of a display panel testing method provided in an embodiment of the present application. As shown in FIG15 , the testing method includes: step S101 and / or step S102.

[0118] S101. In the first time period, the first switch and the second switch are controlled to be turned on, the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the odd columns is connected to the lighting voltage, and the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the even columns is connected to the extinguishing voltage.

[0119] Among them, when the display panel is normal, when the first switch and the second switch are turned on, the lighting voltage is transmitted to the odd-numbered column pixel unit through the first switch and / or the second switch, so that the odd-numbered column pixel unit can be lit. When the display panel is normal, the extinguishing voltage is transmitted to the even-numbered column pixel unit through the first switch and / or the second switch, so that the even-numbered column pixel unit can be extinguished. When the display panel is normal, the odd-numbered column pixel unit is lit and the even-numbered column pixel unit is extinguished. When the display panel is abnormal, at least one odd-numbered column pixel unit is extinguished, and / or at least one even-numbered column pixel unit is lit, and / or the brightness of at least two columns of pixel units is between the brightness of the normally lit pixel unit and the extinguished pixel unit. Therefore, it is possible to judge whether the display panel is abnormal based on the luminescence of the odd-numbered column pixel unit and the even-numbered column pixel unit, and realize the defect detection of the display panel. Exemplarily, the display panel may also include a third switch 140, which controls the first switch, the second switch and the third switch to be turned on in the first time period.

[0120] S102. In the second time period, the first switch and the second switch are controlled to be turned on, the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the odd columns is connected to the extinguishing voltage, and the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the even columns is connected to the lighting voltage.

[0121] Among them, when the display panel is normal, when the first switch and the second switch are turned on, the extinguishing voltage is transmitted to the odd-numbered column pixel unit through the first switch and / or the second switch, so that the odd-numbered column pixel unit can be extinguished. When the display panel is normal, the lighting voltage is transmitted to the even-numbered column pixel unit through the first switch and / or the second switch, so that the even-numbered column pixel unit can be lit. When the display panel is normal, the odd-numbered column pixel unit is extinguished and the even-numbered column pixel unit is lit. When the display panel is abnormal, at least one odd-numbered column pixel unit is lit, and / or at least one even-numbered column pixel unit is extinguished, and / or the brightness of at least two columns of pixel units is between the brightness of the normally lit pixel unit and the brightness of the extinguished pixel unit. Therefore, it is possible to judge whether the display panel is abnormal based on the luminescence of the odd-numbered column pixel unit and the even-numbered column pixel unit, and realize the defect detection of the display panel. Exemplarily, the display panel may also include a third switch 140, which controls the first switch, the second switch and the third switch to be turned on in the second time period.

[0122] The order of the first time period and the second time period is not limited. For example, the first time period is before the second time period, or the first time period is after the second time period.

[0123] The technical solution of the embodiment of the present application is to control the first switch and the second switch to be turned on in the first time period, so that the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the odd columns is connected to the lighting voltage, and the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the even columns is connected to the extinguishing voltage. And / or, in the second time period, the first switch and the second switch are controlled to be turned on, so that the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the odd columns is connected to the extinguishing voltage, and the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the even columns is connected to the lighting voltage, so that the test signals obtained by the two adjacent columns of pixel units are different, and when the display panel is normal, a detection screen in which the pixel units are lit in alternate columns can be realized. When the display panel is abnormal, the display panel cannot realize the detection screen in which the pixel units are lit in alternate columns, so that it can be judged whether the display panel is abnormal based on the detection screen, and a defect detection of the display panel can be realized.

Claims

1. A display panel, comprising a display area and a non-display area, and further comprising: A plurality of pixel units arranged in an array are located in the display area; A plurality of data lines, located in the display area and electrically connected to the pixel units of corresponding columns; the plurality of data lines extend along the column direction and are arranged along the row direction; the plurality of data lines include at least two first data lines and at least two second data lines; A plurality of first fan-out lines are located in the display area, and the first fan-out lines are electrically connected to corresponding first data lines; A plurality of second fan-out lines, a plurality of test circuit units and at least two test signal lines are located in the non-display area, each of the test circuit units comprises a plurality of first switches and a plurality of second switches, the first ends of the plurality of first switches are electrically connected to the corresponding first fan-out lines via the corresponding second fan-out lines; the first ends of the plurality of second switches are electrically connected to the corresponding second data lines via the corresponding second fan-out lines; the second ends of the switches electrically connected to the corresponding pixel units in the same column are electrically connected to the same test signal line; the second ends of the switches electrically connected to the corresponding pixel units in two adjacent columns are electrically connected to different test signal lines.

2. The display panel according to claim 1, wherein: The at least two test signal lines include: a first test signal line and a second test signal line, The second ends of the switches electrically connected to the pixel units in the odd columns are electrically connected to the first test signal line, and the second ends of the switches electrically connected to the pixel units in the even columns are electrically connected to the second test signal line.

3. The display panel according to claim 1, further comprising: A control signal line, to which the control end of the first switch and the control end of the second switch are electrically connected.

4. The display panel according to claim 3, wherein: The first switch includes a first transistor, the first electrode of the first transistor serves as the first end of the first switch, the second electrode of the first transistor serves as the second end of the first switch, and the control electrode of the first transistor serves as the control end of the first switch; And / or, the second switch includes a second transistor, a first electrode of the second transistor serves as the first end of the second switch, a second electrode of the second transistor serves as the second end of the second switch, and a control electrode of the second transistor serves as the control end of the second switch.

5. The display panel according to claim 1, wherein: The arrangement order of the plurality of second fan-out lines along the row direction is different from the arrangement order of the data lines electrically connected to the second fan-out lines; and / or, The first end of the first fan-out line electrically connected to the second fan-out line is closer to the second data line located in the middle of the display area than the second end of the first fan-out line electrically connected to the first data line; and / or, The plurality of second fan-out lines are arranged along a row direction, and the second fan-out line located at the outermost side is electrically connected to the first end of the first switch.

6. The display panel according to claim 1, wherein: The first fan-out line includes a first connection line and a second connection line that are electrically connected, and the second connection line is electrically connected to the corresponding first data line via the first connection line; a plurality of the second connection lines extend along the column direction and are arranged along the row direction; N data lines are arranged between two adjacent second connection lines; wherein N is an integer greater than or equal to 2; Any of the pixel units includes M sub-pixels, or any of the pixel units is electrically connected to M data lines, wherein M is an integer greater than or equal to 2; any of the test circuit units includes K*M first switches and N*K*M second switches, and K is an integer greater than or equal to 1; The plurality of pixel units are divided into at least two pixel repeating units, and any of the pixel repeating units includes K pixel units.

7. The display panel according to claim 6, wherein: The plurality of second fan-out lines include at least two third fan-out lines and at least two fourth fan-out lines; the third fan-out line is electrically connected to the first end of the first switch; the fourth fan-out line is electrically connected to the first end of the second switch; The plurality of second fan-out lines are arranged in a row direction; the arrangement order of the third fan-out lines is opposite to the arrangement order of the corresponding electrically connected first data lines, and the arrangement order of the fourth fan-out lines is the same as the arrangement order of the corresponding electrically connected second data lines.

8. The display panel according to claim 7, wherein: N fourth fan-out lines are arranged between two adjacent third fan-out lines; the N fourth fan-out lines arranged between two adjacent third fan-out lines are electrically connected to the pixel units in the same column; among the 2N fourth fan-out lines arranged between three adjacent third fan-out lines, the N fourth fan-out lines and the other N fourth fan-out lines are electrically connected to the pixel units in different columns; and / or, In each of the test circuit units, a plurality of first switches and a plurality of second switches are arranged along a row direction; and N second switches are arranged between two adjacent first switches.

9. The display panel according to claim 7, wherein: In each of the test circuit units, the second ends of the N second switches located between two adjacent first switches are electrically connected to the same test signal line; among the 2N second switches between three adjacent first switches, the second ends of N second switches and the second ends of another N second switches are electrically connected to different test signal lines.

10. The display panel according to claim 6, wherein: The plurality of first switches in each of the test circuit units are electrically connected to a column of the pixel units or at least two adjacent columns of the pixel units; the plurality of second switches in each of the test circuit units are electrically connected to adjacent columns of the pixel units; M equals N.

11. The display panel according to claim 7, wherein: The display panel also includes N+1 rows of solder pads located in the non-display area, each row of the solder pads including a plurality of solder pads arranged along the row direction, a row of the solder pads being electrically connected to the third fan-out line electrically connected to the first switch, and having an arrangement order opposite to that of the corresponding electrically connected data lines; the remaining N rows of the solder pads being electrically connected to the fourth fan-out line electrically connected to the second switch, and having an arrangement order the same as that of the corresponding electrically connected data lines.

12. The display panel according to claim 6, wherein: N is 2, M is 2, K is 2; The plurality of pixel units include at least two first pixel units and at least two second pixel units, the first pixel unit includes a first color sub-pixel and a second color sub-pixel; the second pixel unit includes a third color sub-pixel and a second color sub-pixel; in the same row of the pixel units, the first pixel units and the second pixel units are alternately arranged along the row direction; In the same column of pixel units, the first pixel units and the second pixel units are alternately arranged along the column direction; In two adjacent columns of sub-pixels, the first color sub-pixels and the third color sub-pixels in one column of the sub-pixels are alternately arranged along the column direction; and the sub-pixels in the other column are all second color sub-pixels; The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

13. The display panel according to claim 12, wherein: Each of the test circuit units includes 4 first switches and 8 second switches, and 2 data lines are arranged between two adjacent second connection lines; the 4 first switches in each of the test circuit units are electrically connected to two adjacent columns of pixel units; the 8 second switches in each of the test circuit units are electrically connected to four adjacent columns of pixel units; Among the four first switches in each of the test circuit units, two adjacent first switches on one side are electrically connected to the pixel units in the same column, and the other two adjacent first switches on the other side are electrically connected to the pixel units in the same column.

14. The display panel according to claim 6, wherein: N is 3, M is 3, K is 1; Any of the pixel units comprises a first color sub-pixel, a second color sub-pixel and a third color sub-pixel; the sub-pixels in each row are arranged cyclically in the order of the first color sub-pixel, the second color sub-pixel and the third color sub-pixel; the sub-pixels in each column are sub-pixels of the same color; The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a green sub-pixel, and the third color sub-pixel is a blue sub-pixel.

15. The display panel according to claim 14, wherein: Each of the test circuit units includes three first switches and nine second switches, and three data lines are arranged between two adjacent second connection lines; The three first switches in each of the test circuit units are electrically connected to the pixel units in the same column; and the nine second switches in each of the test circuit units are electrically connected to the pixel units in three adjacent columns.

16. The display panel according to claim 6, wherein: The first connection line extends along the row direction; among the multiple first connection lines arranged along the column direction, the longer the first connection line is, the closer the corresponding electrically connected first data line is to the frame of the display panel, and the longer the length of the corresponding electrically connected second connection line is.

17. The display panel according to claim 1, wherein: At least part of the second fan-out lines are located in the same conductive layer; A plurality of second fan-out lines are arranged along the row direction, and two adjacent second fan-out lines are located in different conductive layers; among three adjacent second fan-out lines, two second fan-out lines located on both sides are located in the same conductive layer.

18. The display panel according to claim 1, wherein: The display area includes a first display area, a second display area and a third display area sequentially arranged along a row direction, the first data line is located in the first display area and the third display area, and the second data line is located in the second display area.

19. A display device, comprising a driving chip and the display panel according to any one of claims 1 to 18, wherein the driving chip is electrically connected to the second fan-out line.

20. A method for testing a display panel according to any one of claims 1 to 18, comprising: In a first time period, the first switch and the second switch are controlled to be turned on, the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the odd columns is connected to a lighting voltage, and the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the even columns is connected to an extinguishing voltage; and / or, In the second time period, the first switch and the second switch are controlled to be turned on, the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the odd columns is connected to the extinguishing voltage, and the test signal line electrically connected to the second end of the switch electrically connected to the pixel units in the even columns is connected to the lighting voltage.

Images