Device, system and method for preparing heterojunction solar cell

Abstract

The present application belongs to the technical field of solar cell preparation. Disclosed are a device, system and method for preparing a heterojunction solar cell. With regard to the device for preparing a heterojunction solar cell , the heterojunction solar cell comprises a silicon substrate, a first intrinsic passivation layer arranged on a first surface of the silicon substrate, and a second intrinsic passivation layer arranged on a second surface of the silicon substrate, wherein the first intrinsic passivation layer comprises a first intrinsic sub-layer and a second intrinsic sub-layer, and the second intrinsic passivation layer comprises a third intrinsic sub-layer and a fourth intrinsic sub-layer. The device comprises a first process cavity, which is used for preparing the first intrinsic sub-layer or the third intrinsic sub-layer; and a second process cavity, which is in communication with the first process cavity and is used for preparing the second intrinsic sub-layer or the fourth intrinsic sub-layer, wherein a process temperature in the first process cavity is different from a process temperature in the second process cavity. The present application can meet multiple requirements of a heterojunction cell for an intrinsic amorphous-silicon-based thin film, facilitating the improvement in the photoelectric conversion efficiency of the cell.

Description

Device, system and method for preparing heterojunction solar cells Technical Field

[0001] The present application belongs to the technical field of solar cell preparation, and specifically relates to an apparatus, system, and method for preparing heterojunction solar cells. Background Art

[0002] Heterojunction solar cells are a relatively efficient type of crystalline silicon solar cell. Due to their simple manufacturing process, low processing temperature, high photoelectric conversion efficiency, ease of thinning, and lack of PID (Protection Factor) (PID), they have become a major development direction for high-efficiency cells and have been widely adopted. Existing heterojunction solar cell structures include a silicon substrate; a first intrinsic layer, an N-type doped layer, a first transparent conductive film layer, and a first electrode located on the light-receiving side of the silicon substrate; and a second intrinsic layer, a P-type doped layer, a second transparent conductive film layer, and a second electrode located on the backlight side of the silicon substrate. To optimize passivation at the silicon substrate interface and increase open-circuit voltage and fill factor, both the first and second intrinsic layers typically comprise two or more (multiple) sub-intrinsic layers.

[0003] However, in the related art, the heterojunction solar cell used to prepare the intrinsic layer containing multiple sub-intrinsic layers is carried out in the same process chamber, which cannot meet the different process requirements of different sub-intrinsic layers and cannot optimize the film layer combination. It may result in the prepared sub-intrinsic layer having poor film quality and more defects, which in turn limits the further improvement of the conversion efficiency of the heterojunction solar cell and needs further improvement. Summary of the Invention

[0004] In view of the above-mentioned problems, the present invention aims to at least partially solve one of the technical problems in the related art. To this end, the present invention provides an apparatus and method for preparing heterojunction solar cells, which can meet the different preparation requirements of multiple sub-film layers, help improve the quality of the film layers, and thus improve the photoelectric conversion efficiency of the solar cell.

[0005] In order to solve the above technical problems, this application is implemented as follows:

[0006] According to one aspect of the present application, an embodiment of the present application provides an apparatus for preparing a heterojunction solar cell, wherein the heterojunction solar cell includes a silicon substrate, a first intrinsic passivation layer and a first doping layer sequentially stacked on a first surface of the silicon substrate, and a second intrinsic passivation layer and a second doping layer sequentially stacked on a second surface of the silicon substrate, wherein the first intrinsic passivation layer includes a first sub-intrinsic layer and a second sub-intrinsic layer, and the second intrinsic passivation layer includes a third sub-intrinsic layer and a fourth sub-intrinsic layer; the apparatus includes:

[0007] a first process chamber, for preparing the first sub-intrinsic layer;

[0008] a second process chamber, the second process chamber being connected to the first process chamber, and the second process chamber being used for preparing the second sub-intrinsic layer;

[0009] Alternatively, the first process chamber is used to prepare the third sub-intrinsic layer;

[0010] a second process chamber, the second process chamber being connected to the first process chamber, and the second process chamber being used for preparing the fourth sub-intrinsic layer;

[0011] The process temperature in the first process chamber is at least 25° C. lower than the process temperature in the second process chamber.

[0012] In addition, the device for preparing a heterojunction solar cell according to the present application may also have the following additional technical features:

[0013] In some embodiments, the process temperature in the first process chamber ranges from 130°C to 200°C, and the process temperature in the second process chamber ranges from 180°C to 250°C.

[0014] In some embodiments, the first process chamber is connected to the second process chamber through a first gate valve, and a first heating device and a second heating device are respectively provided in the first process chamber and the second process chamber, and a first transmission mechanism and a second transmission mechanism are also respectively provided in the first process chamber and the second process chamber; after completing the preparation of the first sub-intrinsic layer or the third sub-intrinsic layer in the first process chamber, the first gate valve is opened, and the process enters the second process chamber, and the temperature of the second heating device is adjusted to prepare the corresponding second sub-intrinsic layer or the fourth sub-intrinsic layer.

[0015] In some embodiments, the device further includes a heating chamber, which is located between the first process chamber and the second process chamber; the outlet end of the first process chamber is connected to the inlet end of the heating chamber through a second gate valve, and the outlet end of the heating chamber is connected to the inlet end of the second process chamber through a third gate valve.

[0016] In some embodiments, the device further includes a third process chamber, which is located between the first process chamber and the second process chamber; the outlet end of the first process chamber is connected to the inlet end of the third process chamber through a fourth gate valve, and the outlet end of the third process chamber is connected to the inlet end of the second process chamber through a fifth gate valve.

[0017] In some embodiments, the first intrinsic passivation layer further includes a fifth sub-intrinsic layer, wherein the first sub-intrinsic layer, the fifth sub-intrinsic layer and the second sub-intrinsic layer are stacked in sequence; and / or the second intrinsic passivation layer further includes a sixth sub-intrinsic layer, wherein the third sub-intrinsic layer, the sixth sub-intrinsic layer and the fourth sub-intrinsic layer are stacked in sequence; the third process chamber is used to prepare the fifth sub-intrinsic layer or the sixth sub-intrinsic layer, and the process temperature in the third process chamber is greater than or equal to the process temperature in the first process chamber, and the process temperature in the third process chamber is less than or equal to the process temperature in the second process chamber.

[0018] In some embodiments, the device further includes a buffer chamber, in which a transmission mechanism is provided; the first process chamber is connected to the first end of the buffer chamber through a sixth gate valve, and the second process chamber is connected to the second end of the buffer chamber through a seventh gate valve, and the first end and the second end are arranged at an angle.

[0019] According to another aspect of the present application, an embodiment of the present application provides a system for preparing a heterojunction solar cell, the heterojunction solar cell comprising a silicon substrate, a first intrinsic passivation layer and a first doping layer sequentially stacked on a first surface of the silicon substrate, and a second intrinsic passivation layer and a second doping layer sequentially stacked on a second surface of the silicon substrate, the first intrinsic passivation layer comprising a first sub-intrinsic layer and a second sub-intrinsic layer, and the second intrinsic passivation layer comprising a third sub-intrinsic layer and a fourth sub-intrinsic layer; the system sequentially comprising: a first coating device and a second coating device;

[0020] The first coating equipment at least includes:

[0021] a first process chamber, for preparing the first sub-intrinsic layer;

[0022] a second process chamber, the second process chamber being connected to the first process chamber, and the second process chamber being used for preparing the second sub-intrinsic layer;

[0023] A first process doping cavity, used for preparing the first doping layer;

[0024] The second coating equipment at least includes:

[0025] A first process chamber, used for preparing the third sub-intrinsic layer;

[0026] a second process chamber, the second process chamber being connected to the first process chamber, and the second process chamber being used for preparing the fourth sub-intrinsic layer;

[0027] A second process doping cavity, used for preparing the second doping layer;

[0028] The process temperature in the first process chamber is at least 25° C. lower than the process temperature in the second process chamber.

[0029] According to another aspect of the present application, an embodiment of the present application provides a system for preparing a heterojunction solar cell, the heterojunction solar cell comprising a silicon substrate, a first intrinsic passivation layer and a first doping layer sequentially stacked on a first surface of the silicon substrate, and a second intrinsic passivation layer and a second doping layer sequentially stacked on a second surface of the silicon substrate, the first intrinsic passivation layer comprising a first sub-intrinsic layer and a second sub-intrinsic layer, and the second intrinsic passivation layer comprising a third sub-intrinsic layer and a fourth sub-intrinsic layer; the system sequentially comprising: a first coating device, a second coating device, and a third coating device;

[0030] The first coating equipment at least includes:

[0031] a first process chamber, for preparing the first sub-intrinsic layer;

[0032] a second process chamber, the second process chamber being connected to the first process chamber, and the second process chamber being used for preparing the second sub-intrinsic layer;

[0033] The second coating equipment at least includes:

[0034] A first process chamber, used for preparing the third sub-intrinsic layer;

[0035] a second process chamber, the second process chamber being connected to the first process chamber, and the second process chamber being used for preparing the fourth sub-intrinsic layer;

[0036] A second process doping cavity, used for preparing the second doping layer;

[0037] The third coating equipment at least includes:

[0038] A first process doping cavity, used for preparing the first doping layer;

[0039] The process temperature in the first process chamber is at least 25° C. lower than the process temperature in the second process chamber.

[0040] In some embodiments, a heating chamber is further provided between the first process chamber and the second process chamber.

[0041] In some embodiments, a third process chamber is further provided between the first process chamber and the second process chamber, which is used to prepare a fifth sub-intrinsic layer between the first sub-intrinsic layer and the second sub-intrinsic layer, or to prepare a sixth sub-intrinsic layer between the third sub-intrinsic layer and the fourth sub-intrinsic layer.

[0042] According to another aspect of the present application, an embodiment of the present application provides a method for preparing a heterojunction solar cell, wherein the method uses at least two devices for preparing a heterojunction solar cell as described above; the method comprises:

[0043] Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface disposed opposite to each other;

[0044] In a first process chamber of one of the apparatuses, a first sub-intrinsic layer is deposited on a first surface of a silicon substrate under conditions of a first process temperature and a first deposition rate; and in a second process chamber, a second sub-intrinsic layer is deposited on a surface of the first sub-intrinsic layer under conditions of a second process temperature and a second deposition rate;

[0045] In a first process chamber of another of the devices, a third sub-intrinsic layer is deposited on the second surface of the silicon substrate under conditions of a first process temperature and a first deposition rate; and in a second process chamber, a fourth sub-intrinsic layer is deposited on the surface of the third sub-intrinsic layer under conditions of a second process temperature and a second deposition rate;

[0046] The first process temperature is at least 25° C. lower than the second process temperature.

[0047] In some embodiments, the first process temperature ranges from 130 to 200°C, and the second process temperature ranges from 180 to 250°C.

[0048] The implementation of the technical solution of the present invention has at least the following beneficial effects:

[0049] In an embodiment of the present application, an apparatus for preparing a heterojunction solar cell is provided, comprising a first process chamber and a second process chamber. Different film layers can be prepared in the first process chamber and the second process chamber. For example, a first sub-intrinsic layer or a third sub-intrinsic layer close to the surface of a silicon substrate is prepared in the first process chamber, and a second sub-intrinsic layer or a fourth sub-intrinsic layer away from the surface of the silicon substrate is prepared in the second process chamber. The process temperatures of the first process chamber and the second process chamber are different, that is, differentiated process temperatures of the two process chambers are used to complete the preparation of each sub-intrinsic layer, thereby meeting the different preparation requirements of multiple sub-film layers and helping to improve the quality of the film layers.

[0050] Compared with the existing battery preparation which is limited by the single-chamber design of the thin-film deposition equipment and uses a single process condition to complete the deposition of each sub-intrinsic layer, this application uses multiple process chambers with differentiated process temperatures to complete the preparation of each sub-intrinsic layer, which can meet the passivation requirements of heterojunction batteries and the multiple requirements of heterojunction solar cell products for intrinsic amorphous silicon-based thin films, thereby achieving the effect of improving the photoelectric conversion efficiency of the battery.

[0051] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] FIG1 is a schematic structural diagram of an apparatus for preparing a heterojunction solar cell according to some exemplary embodiments of the present application;

[0053] FIG2 is a schematic structural diagram of a heterojunction solar cell provided by some exemplary embodiments of the present application;

[0054] FIG3 is a schematic structural diagram of an apparatus for preparing a heterojunction solar cell provided in some other exemplary embodiments of the present application;

[0055] FIG4 is a schematic structural diagram of an apparatus for preparing a heterojunction solar cell according to some further exemplary embodiments of the present application;

[0056] FIG5 is a schematic structural diagram of an apparatus for preparing a heterojunction solar cell according to some further exemplary embodiments of the present application;

[0057] FIG6 is a schematic structural diagram of a heterojunction solar cell provided by some other exemplary embodiments of the present application;

[0058] FIG7 is a schematic structural diagram of a heterojunction solar cell provided in some further exemplary embodiments of the present application;

[0059] FIG8 is a schematic structural diagram of a system for preparing a heterojunction solar cell according to some exemplary embodiments of the present application;

[0060] FIG9 is a schematic structural diagram of a system for preparing a heterojunction solar cell provided by some other exemplary embodiments of the present application;

[0061] FIG10 is a schematic structural diagram of a system for preparing a heterojunction solar cell provided by some other exemplary embodiments of the present application;

[0062] FIG11 is a schematic structural diagram of a system for preparing a heterojunction solar cell provided in accordance with some further exemplary embodiments of the present application.

[0063] Description of reference numerals:

[0064] 100 - first process chamber; 110 - first heating device;

[0065] 200 - second process chamber; 210 - second heating device;

[0066] 300-heating cavity; 310-third heating device;

[0067] 400-third process chamber;

[0068] 500-buffer cavity; 510-carrier board;

[0069] 610 - first gate valve; 620 - second gate valve; 630 - third gate valve; 640 - fourth gate valve; 650 - fifth gate valve; 660 - sixth gate valve; 670 - seventh gate valve;

[0070] 710 - first loading chamber; 720 - second loading chamber; 730 - third loading chamber;

[0071] 810-first unloading chamber; 820-second unloading chamber; 830-third unloading chamber;

[0072] 910-first process doping chamber; 920-second process doping chamber;

[0073] 1001-first coating equipment; 1002-second coating equipment; 1003-third coating equipment;

[0074] 10-silicon substrate;

[0075] 20-first intrinsic passivation layer; 21-first sub-intrinsic layer; 22-second sub-intrinsic layer; 23-fifth sub-intrinsic layer;

[0076] 30 - second intrinsic passivation layer; 31 - third sub-intrinsic layer; 32 - fourth sub-intrinsic layer; 33 - sixth sub-intrinsic layer;

[0077] 41-first doping layer; 42-second doping layer;

[0078] 51-first transparent conductive layer; 52-second transparent conductive layer;

[0079] 61-first electrode; 62-second electrode. Implementation Method

[0080] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0081] Heterojunction solar cells are a type of cell technology that forms a silicon heterojunction by depositing an amorphous silicon thin film on a crystalline silicon surface. This type of solar cell combines the characteristics of crystalline silicon cells and silicon-based thin-film cells, and has many advantages, such as high conversion efficiency, simple manufacturing process steps, low process temperature, good product stability, and low degradation. In the related art, in the production process of heterojunction solar cells, the deposition of silicon-based thin films is usually achieved by PECVD. Usually, an amorphous silicon intrinsic layer is deposited as a passivation layer on both sides of the crystalline silicon substrate to form an a-Si / c-Si interface, which plays the role of passivating silicon dangling bonds. However, the cells of the prior art are usually limited by the single-chamber design of the thin film deposition equipment. The deposition of the intrinsic passivation layer is completed using a single process condition, which cannot further optimize the conversion efficiency and production cycle of the heterojunction solar cell. Therefore, it is necessary to provide an improved technical solution to alleviate the problem that the existing single process chamber is used to deposit the amorphous film layer, which cannot optimize the film layer combination and cannot further improve the conversion efficiency of the heterojunction solar cell. The specific technical solution is described below.

[0082] As shown in FIG1 , in some embodiments, an apparatus for preparing a heterojunction solar cell is provided. The apparatus includes at least a first process chamber 100 and a second process chamber 200 that are connected to each other. The process temperature in the first process chamber 100 is different from the process temperature in the second process chamber 200. The first process chamber 100 and the second process chamber 200 can be used to prepare different sub-intrinsic film layers, especially to prepare sub-intrinsic film layers with different process temperature requirements.

[0083] According to this embodiment, the equipment used can be a plasma-phase chemical vapor deposition (PECVD) device, or a catalytic chemical vapor deposition (CAT-CVD) device. For example, the equipment used can be RF-PECVD, VHF-PECVD, CAT-CVD, or other equipment. This embodiment is mainly described using a PECVD coating device as an example. The PECVD coating device can be used to prepare heterojunction solar cells, especially heterojunction solar cells with multiple sub-intrinsic layers. The PECVD coating device has multiple process chambers, such as a first process chamber 100 and a second process chamber 200 with different process temperatures.

[0084] The heterojunction solar cell fabricated using the aforementioned coating apparatus includes an intrinsic passivation layer, which may comprise multiple (e.g., two or more) sub-intrinsic passivation layers. As shown in FIG2 , in some embodiments, the heterojunction solar cell includes a silicon substrate 10 having two opposing surfaces, namely, a first surface and a second surface. The first surface may be the front or light-receiving surface (N-side), i.e., the surface facing the sun; the second surface may be the back or backlight surface (P-side), i.e., the surface facing away from the sun.

[0085] A first intrinsic passivation layer 20 and a first doped layer 41 are sequentially stacked on a first surface of the silicon substrate 10, and a second intrinsic passivation layer 30 and a second doped layer 42 are sequentially stacked on a second surface of the silicon substrate 10. The first intrinsic passivation layer 20 and the second intrinsic passivation layer 30 each include multiple (e.g., two or more) sub-intrinsic passivation layers. For example, the first intrinsic passivation layer 20 includes a first sub-intrinsic layer 21 and a second sub-intrinsic layer 22, and the second intrinsic passivation layer 30 includes a third sub-intrinsic layer 31 and a fourth sub-intrinsic layer 32. The first sub-intrinsic layer 21 is located near the first surface of the silicon substrate 10, i.e., the first sub-intrinsic layer 21 directly contacts the first surface of the silicon substrate 10, while the second sub-intrinsic layer 22 is located on a surface of the first sub-intrinsic layer 21 that is away from the first surface of the silicon substrate 10, i.e., the second sub-intrinsic layer 22 is away from the first surface of the silicon substrate 10. Similarly, the above-mentioned third sub-intrinsic layer 31 is close to the second surface of the silicon substrate 10, that is, the third sub-intrinsic layer 31 is directly in contact with the second surface of the silicon substrate 10, and the fourth sub-intrinsic layer 32 is located on the side surface of the third sub-intrinsic layer 31 away from the second surface of the silicon substrate 10, that is, the fourth sub-intrinsic layer 32 is away from the second surface of the silicon substrate 10.

[0086] The above-mentioned first process chamber 100 is used to prepare one of the first sub-intrinsic layer 21 or the third sub-intrinsic layer 31; for example, in the first process chamber 100, under the first process temperature condition, the first sub-intrinsic layer 21 is deposited on the first surface of the silicon substrate 10 to form the first sub-intrinsic layer 21, or the third sub-intrinsic layer 31 is deposited on the second surface of the silicon substrate 10 to form the third sub-intrinsic layer 31.

[0087] The above-mentioned second process chamber 200 is connected to the first process chamber 100, and the second process chamber 200 is used to prepare one of the second sub-intrinsic layer 22 or the fourth sub-intrinsic layer 32; for example, in the second process chamber 200, under the second process temperature conditions, the second sub-intrinsic layer 22 is deposited on the surface of the first sub-intrinsic layer 21, or the fourth sub-intrinsic layer 32 is deposited on the surface of the third sub-intrinsic layer 31.

[0088] Preferably, the first process temperature is lower than the second process temperature.

[0089] The first sub-intrinsic layer 21 is deposited at low temperature and the second sub-intrinsic layer 22 is deposited at high temperature by a chamber coating method, or the third sub-intrinsic layer 31 is deposited at low temperature and the fourth sub-intrinsic layer 32 is deposited at high temperature by a chamber coating method, which is beneficial to the control of the deposition temperature of each film layer, convenient to adjust, easy to implement, and highly feasible.

[0090] Therefore, based on the above configuration, the technical solution of the equipment for preparing heterojunction solar cells provided by this embodiment can meet the different preparation requirements of different sub-film layers by setting multiple process chambers and making the process temperatures of each process chamber different, which helps to improve the quality of the film layer. For example, the film layer of the first sub-intrinsic layer deposited at low temperature is loose, the passivation effect is better, and the hydrogen content is higher. Compared with the first sub-intrinsic layer deposited at high temperature, the parallel resistance and open circuit voltage of the heterojunction cell terminal are significantly improved. Compared with the existing battery preparation being limited by the single chamber design of the thin film deposition equipment, the deposition of each sub-intrinsic layer is completed using a single process condition. The present application uses multiple process chambers with differentiated process temperatures to complete the preparation of each sub-intrinsic layer, which can meet the passivation requirements of the heterojunction battery and meet the multiple requirements of heterojunction solar cell products for intrinsic amorphous silicon-based thin films, thereby achieving the effect of improving the photoelectric conversion efficiency of the battery.

[0091] In some embodiments, the process temperature in the first process chamber 100 is at least 25° C. lower than the process temperature in the second process chamber 200 . Furthermore, the process temperature in the first process chamber 100 is at least 20° C. or 30° C. lower than the process temperature in the second process chamber 200 .

[0092] In a specific implementation process, the process temperatures in the first process chamber 100 and the second process chamber 200 may be adjusted by controlling the heating devices in the first process chamber 100 and the second process chamber 200 respectively.

[0093] In some embodiments, the process temperature in the first process chamber 100 ranges from 130° C. to 200° C., and the process temperature in the second process chamber 200 ranges from 180° C. to 250° C. In some embodiments, the process temperature in the first process chamber 100 ranges from 150° C. to 180° C., and the process temperature in the second process chamber 200 ranges from 200° C. to 240° C. For example, the process temperature in the first process chamber 100, i.e., the deposition temperature, may be 130° C., 150° C., 160° C., 170° C., 180° C., 190° C., etc., and the process temperature in the second process chamber 200, i.e., the deposition temperature, may be 180° C., 200° C., 205° C., 210° C., 220° C., 230° C., 240° C., 250° C., etc.

[0094] Thus, within the range of the first process temperature within the first process chamber 100 and the second process temperature within the second process chamber 200, the low-temperature process described above can be used to prepare the first sub-intrinsic layer 21 or the third sub-intrinsic layer 31. Specifically, under the low-temperature deposition conditions of 130-200°C or 150-180°C, the hydrogen content of the prepared first sub-intrinsic layer 21 can be higher than that of a conventional high-temperature deposited first sub-intrinsic layer 21. Similarly, the hydrogen content of the prepared third sub-intrinsic layer 31 can be higher than that of a conventional high-temperature deposited third sub-intrinsic layer 31. This higher hydrogen content can improve the surface passivation of the heterojunction solar cell. Furthermore, the first sub-intrinsic layer 21 and the third sub-intrinsic layer 31 with higher hydrogen content have a larger electronic band gap, resulting in better light transmittance. Furthermore, the low-temperature deposited first sub-intrinsic layer 21 and the third sub-intrinsic layer 31 have a more porous film structure, which can increase the parallel resistance of the heterojunction solar cell, thereby improving the open-circuit voltage of the solar cell.

[0095] Continuing with reference to FIG. 1 , in some embodiments, in an apparatus for fabricating heterojunction solar cells, a first process chamber 100 and a second process chamber 200 are connected via a first gate valve 610 . A first heating device 110 and a second heating device 210 are respectively provided in the first process chamber 100 and the second process chamber 200. A first conveying mechanism (not shown) and a second conveying mechanism (not shown) are also respectively provided in the first process chamber 100 and the second process chamber 200. Optionally, temperature monitoring mechanisms, such as temperature sensors, may also be provided in the first process chamber 100 and the second process chamber 200 to monitor the deposition temperature in real time within each process chamber. The first and second conveying mechanisms may be used to transport a carrier loaded with silicon wafers. These first and second conveying mechanisms may employ conveyor belts, roller conveyors, or the like, without limitation.

[0096] The process temperatures in the first process chamber 100 and the second process chamber 200 are adjusted by controlling the first heating device 110 in the first process chamber 100 and the second heating device 210 in the second process chamber 200 respectively.

[0097] After the preparation of the first sub-intrinsic layer 21 or the third sub-intrinsic layer 31 is completed in the first process chamber 100, the first gate valve 610 is opened and the process enters the second process chamber 200. That is, the carrier loaded with the silicon wafer is transferred into the second process chamber 200, and the temperature of the second heating device 210 is adjusted. For example, the second heating device 210 in the second process chamber 200 is used to quickly increase the temperature of the silicon substrate to at least 25°C higher than the temperature of the first process chamber 100. Then, the second sub-intrinsic layer 22 or the fourth sub-intrinsic layer 32 is prepared.

[0098] In this embodiment, the first process chamber 100 is connected to the second process chamber 200 through the first gate valve 610, that is, the two adjacent process chambers are connected through the gate valve. The gate valve can connect or isolate the transmission module and the process module. Through the setting of the gate valve, when silicon wafers are transmitted, the gate valve can be opened to allow the silicon wafers to enter or leave each chamber. When performing vacuum or coating operations, the gate valve can be closed to keep each process chamber in a closed state.

[0099] As shown in Figure 3, in some embodiments, the apparatus for manufacturing heterojunction solar cells may further include at least one heating chamber 300, located between the first process chamber 100 and the second process chamber 200. That is, the first process chamber 100, the heating chamber 300, and the second process chamber 200 are sequentially connected. Optionally, a third heating device 310 and a third transmission mechanism (not shown) may be provided within the heating chamber 300. Optionally, a temperature monitoring mechanism, such as a temperature sensor, may also be provided within the heating chamber 300.

[0100] The outlet of the first process chamber 100 can be connected to the inlet of the heating chamber 300 through the second gate valve 620 , and the outlet of the heating chamber 300 can be connected to the inlet of the second process chamber 200 through the third gate valve 630 .

[0101] By disposing at least one heating chamber 300 with a heating function between the first process chamber 100 and the second process chamber 200, after the first sub-intrinsic layer 21 (e.g., the amorphous silicon first sub-film layer) or the third sub-intrinsic layer 31 is formed on the coated substrate in the first process chamber 100, the substrate is then transferred to the heating chamber 300. This allows the temperature of the coated substrate to be rapidly raised to the process temperature within the second process chamber 200. The substrate is then transferred to the second process chamber 200 to form the second sub-intrinsic layer 22 (e.g., the amorphous silicon second sub-film layer) or the fourth sub-intrinsic layer 32. Optionally, the coated substrate may be a silicon wafer.

[0102] The arrangement of the heating cavity 300 can play a buffering role, making it easier to control the temperatures of different cavities, thereby helping to improve heating efficiency and further helping to improve production efficiency.

[0103] As shown in Figure 4, in some other embodiments, the apparatus for manufacturing heterojunction solar cells may further include a third process chamber 400, which is located between the first process chamber 100 and the second process chamber 200; that is, the first process chamber 100, the third process chamber 400, and the second process chamber 200 are sequentially connected. Optionally, a third heating device and a third transmission mechanism may be provided within the third process chamber 400. Optionally, a temperature monitoring mechanism, such as a temperature sensor, may also be provided within the third process chamber 400.

[0104] The outlet of the first process chamber 100 is connected to the inlet of the third process chamber 400 through the fourth gate valve 640 , and the outlet of the third process chamber 400 is connected to the inlet of the second process chamber 200 through the fifth gate valve 650 .

[0105] At least one third process chamber 400 capable of thin film deposition may be located between the first process chamber 100 and the second process chamber 200. After the first sub-intrinsic layer 21 (e.g., the amorphous silicon first sub-film layer) or the third sub-intrinsic layer 31 is formed on the coated substrate in the first process chamber 100, the substrate is transferred to the third process chamber 400, where a fifth sub-intrinsic layer 23 is deposited on the first sub-intrinsic layer 21 of the coated substrate, or a sixth sub-intrinsic layer 33 is deposited on the third sub-intrinsic layer 31. The substrate is then transferred to the second process chamber 200 to form the second sub-intrinsic layer 22 (e.g., the amorphous silicon second sub-film layer) or the fourth sub-intrinsic layer 32. Optionally, the process temperature of the silicon substrate in the third process chamber 400 is greater than or equal to the process temperature in the first process chamber 100, and less than or equal to the process temperature in the second process chamber 200.

[0106] 4 and 6 , in some embodiments, the first intrinsic passivation layer 20 further includes a fifth sub-intrinsic layer 23, wherein the first sub-intrinsic layer 21, the fifth sub-intrinsic layer 23, and the second sub-intrinsic layer 22 are stacked in sequence; the second intrinsic passivation layer 30 further includes a sixth sub-intrinsic layer 33, wherein the third sub-intrinsic layer 31, the sixth sub-intrinsic layer 33, and the fourth sub-intrinsic layer 32 are stacked in sequence.

[0107] In some specific embodiments, the first intrinsic passivation layer 20 may include two sub-intrinsic layers, such as a first sub-intrinsic layer 21 and a second sub-intrinsic layer 22. In other specific embodiments, the first intrinsic passivation layer 20 may include three sub-intrinsic layers, such as a first sub-intrinsic layer 21, a fifth sub-intrinsic layer 23, and a second sub-intrinsic layer 22. Of course, in other embodiments, the first intrinsic passivation layer 20 may also include more than three sub-intrinsic layers, which will not be described in detail here. Similarly, in some specific embodiments, the second intrinsic passivation layer 30 may include two sub-intrinsic layers, such as a third sub-intrinsic layer 31 and a fourth sub-intrinsic layer 32. In other specific embodiments, the second intrinsic passivation layer 30 may include three sub-intrinsic layers, such as a third sub-intrinsic layer 31, a sixth sub-intrinsic layer 33, and a fourth sub-intrinsic layer 32. Of course, in other embodiments, the second intrinsic passivation layer 30 may also include more than three sub-intrinsic layers, which will not be described in detail here.

[0108] Optionally, the third process chamber 400 can be used to prepare the fifth sub-intrinsic layer 23 or the sixth sub-intrinsic layer 33, and the process temperature in the third process chamber 400 is greater than or equal to the process temperature in the first process chamber 100, and the process temperature in the third process chamber 400 is less than or equal to the process temperature in the second process chamber 200.

[0109] Thus, the apparatus includes multiple, for example, two or more, process chambers, enabling independent control of process parameters, such as process temperature, in each process chamber. Furthermore, there are various methods for independently controlling the temperature of each process chamber. Optionally, the number of process chambers is at least two, such as the number of process sub-chambers, which may be two, three, four, or more.

[0110] In this embodiment, by providing multiple process chambers, process parameters such as process temperatures of different process chambers can be made different according to situation needs, thereby meeting different process requirements, with better flexibility and stronger adaptability.

[0111] As shown in Figure 5, in some other embodiments, the equipment for preparing heterojunction solar cells may also include a buffer chamber 500, in which a carrier plate 510 is provided; the first process chamber 100 is connected to the first end of the buffer chamber 500 through the sixth gate valve 660, and the second process chamber 200 is connected to the second end of the buffer chamber 500 through the seventh gate valve 670, and the first end and the second end are arranged at an angle.

[0112] Optionally, a carrier plate 510 is provided in the buffer cavity 500 , and the carrier plate 510 is disposed on a transmission mechanism. The carrier plate 510 can be rotated in the buffer cavity 500 and transferred into and out of the corresponding chamber via the transmission mechanism.

[0113] Compared with the linear layout of the above-mentioned multiple process chambers, the equipment including the buffer chamber 500 adopts a cluster coating chamber design, which can save floor space and make the equipment more compact.

[0114] In this way, the carrier plate can be rotated and transported within the buffer chamber 500 to transfer the coated substrate into the first process chamber 100. After the coating is completed in the first process chamber 100, it can be returned to the buffer chamber 500. The carrier plate 510 is then rotated and transported again to transfer the coated substrate into the second process chamber 200 for coating in the second process chamber 200. Alternatively, after the coating is completed in the first process chamber 100 and the substrate is returned to the buffer chamber 500, the carrier plate is then rotated and transported again to transfer the coated electrode into the heating chamber 300 or the third process chamber 400, and then returns to the buffer chamber 500 and enters the second process chamber 200 for coating in the second process chamber 200.

[0115] In addition, as shown in Figure 8, in some embodiments, a system for preparing a heterojunction solar cell is also provided. The heterojunction solar cell includes a silicon substrate 10, a first intrinsic passivation layer 20 and a first doping layer 41 stacked in sequence on the first surface of the silicon substrate 10, and a second intrinsic passivation layer 30 and a second doping layer 42 stacked in sequence on the second surface of the silicon substrate 10, the first intrinsic passivation layer 20 includes a first sub-intrinsic layer 21 and a second sub-intrinsic layer 22, and the second intrinsic passivation layer 30 includes a third sub-intrinsic layer 31 and a fourth sub-intrinsic layer 32.

[0116] The aforementioned apparatus for preparing a heterojunction solar cell can be used in a system for preparing a heterojunction solar cell. That is, the system for preparing a heterojunction solar cell can include the aforementioned apparatus. When using the system to prepare a heterojunction solar cell, the heterojunction solar cell can refer to the cell structure described in FIG. 2 , FIG. 6 , or FIG. 7 of the aforementioned apparatus for preparing a heterojunction solar cell, and no further details are given here.

[0117] As shown in FIG8 , the system for preparing a heterojunction solar cell includes: a first coating device 1001 and a second coating device 1002 , specifically:

[0118] The first coating device 1001 at least includes:

[0119] The first process chamber 100 is used to prepare the first sub-intrinsic layer 21;

[0120] A second process chamber 200 , which is connected to the first process chamber 100 , and is used to prepare the second sub-intrinsic layer 22 ;

[0121] A first process doping cavity 910 is used to prepare a first doping layer 41;

[0122] The second coating equipment 1002 at least includes:

[0123] The first process chamber 100 is used to prepare the third sub-intrinsic layer 31;

[0124] A second process chamber 200 , which is connected to the first process chamber 100 , and is used to prepare the fourth sub-intrinsic layer 32 ;

[0125] The second process doping cavity 920 is used to prepare the second doping layer 42 .

[0126] In the above-mentioned coating system, that is, the above-mentioned system for preparing heterojunction solar cells, it also includes conventional cavities such as a loading chamber, a flipping mechanism, and an unloading chamber, which will not be further described here. For example, in this system, the first coating device 1001 may include a first loading chamber 710, a first process chamber 100, a second process chamber 200, a first process doping chamber 910, and a first unloading chamber 810 arranged in sequence; the second coating device 1002 may include a second loading chamber 720, a first process chamber 100, a second process chamber 200, a second process doping chamber 920, and a second unloading chamber 820 arranged in sequence; a flipping mechanism for flipping the silicon wafer may be provided between the first coating device 1001 and the second coating device 1002.

[0127] The process temperature in the first process chamber 100 is at least 25°C lower than the process temperature in the second process chamber 200. Furthermore, the process temperature range in the first process chamber 100 can be 130-200°C, and the process temperature range in the second process chamber 200 can be 180-250°C. Relatively speaking, the first process chamber is a low-temperature process chamber, and the second process chamber is a high-temperature process chamber. The first process chamber 100 in the first coating apparatus 1001 is used to prepare the first sub-intrinsic layer 21, and the second process chamber 200 in the first coating apparatus 1001 is used to prepare the second sub-intrinsic layer 22; the first process chamber 100 in the second coating apparatus 1002 is used to prepare the third sub-intrinsic layer 31, and the second process chamber 200 in the second coating apparatus 1002 is used to prepare the fourth sub-intrinsic layer 32.

[0128] Thus, when applying the above-mentioned system for preparing heterojunction solar cells to prepare heterojunction solar cells, in the first coating device 1001, the silicon wafer is first loaded in the loading chamber, and then in the first process chamber 100, a relatively low process temperature such as 130-200°C is used to deposit and form a first sub-intrinsic layer 21 on the first surface of the silicon substrate, and then in the second process chamber 200, a relatively high process temperature such as 150-250°C is used to deposit and form a second sub-intrinsic layer 22 on the first sub-intrinsic layer 21; then, in the first process doping chamber 910, a first doping layer 41 is deposited and formed on the second sub-intrinsic layer 22. After the silicon wafer is flipped, that is, after the first and second surfaces of the silicon substrate are reversed, a third sub-intrinsic layer 31 is deposited on the second surface of the silicon substrate in the first process chamber 100 in the second coating apparatus 1002 at a relatively low process temperature, such as 130-200°C. A fourth sub-intrinsic layer 32 is then deposited on the third sub-intrinsic layer 31 in the second process chamber 200 at a relatively high process temperature, such as 150-250°C. Finally, a second doped layer 42 is deposited on the fourth sub-intrinsic layer 32 in the second process doping chamber 920. During the fabrication of heterojunction solar cells using this system, a single flipping process is performed.

[0129] In addition, optionally, as shown in Figure 9, in the above-mentioned system for preparing heterojunction solar cells, a heating chamber 300 can also be set between the first process chamber 100 and the second process chamber 200, that is, the first low-temperature process chamber and the second high-temperature process chamber. For the setting of the heating chamber 300, please refer to the technical content in Figure 3 and no further explanation will be given here.

[0130] A heating chamber 300 may be provided between the first process chamber 100 and the second process chamber 200 in the first coating device 1001; or a heating chamber 300 may be provided between the first process chamber 100 and the second process chamber 200 in the second coating device 1002; or a heating chamber 300 may be provided between the first process chamber 100 and the second process chamber 200 in both the first coating device 1001 and the second coating device 1002.

[0131] Furthermore, optionally, when the first intrinsic passivation layer 20 further includes a fifth sub-intrinsic layer 23, wherein the first sub-intrinsic layer 21, the fifth sub-intrinsic layer 23, and the second sub-intrinsic layer 22 are sequentially stacked, and the second intrinsic passivation layer 30 further includes a sixth sub-intrinsic layer 33, wherein the third sub-intrinsic layer 31, the sixth sub-intrinsic layer 33, and the fourth sub-intrinsic layer 32 are sequentially stacked, in the above-described film coating system, a third process chamber 400 may be further disposed between the first process chamber 100 and the second process chamber 200. The third process chamber 400 is used to prepare the fifth sub-intrinsic layer 23 and the sixth sub-intrinsic layer 33. For the configuration of the third process chamber 400 and related processes, please refer to the technical content in Figure 4 and will not be further described here.

[0132] Optionally, the above-mentioned system for preparing heterojunction solar cells may also include equipment for preparing a transparent conductive layer in a heterojunction solar cell, equipment for preparing electrodes, etc. These equipments can refer to relevant technologies and are not further described here.

[0133] In addition, as shown in Figure 10, in other embodiments, a system for preparing a heterojunction solar cell is also provided. The heterojunction solar cell includes a silicon substrate 10, a first intrinsic passivation layer 20 and a first doping layer 41 stacked in sequence on the first surface of the silicon substrate 10, and a second intrinsic passivation layer 30 and a second doping layer 42 stacked in sequence on the second surface of the silicon substrate 10, the first intrinsic passivation layer 20 includes a first sub-intrinsic layer 21 and a second sub-intrinsic layer 22, and the second intrinsic passivation layer 30 includes a third sub-intrinsic layer 31 and a fourth sub-intrinsic layer 32.

[0134] The aforementioned apparatus for preparing a heterojunction solar cell can be used in a system for preparing a heterojunction solar cell. That is, the system for preparing a heterojunction solar cell can include the aforementioned apparatus. When using the system to prepare a heterojunction solar cell, the heterojunction solar cell can refer to the cell structure described in FIG. 2 , FIG. 6 , or FIG. 7 of the aforementioned apparatus for preparing a heterojunction solar cell, and no further details are given here.

[0135] As shown in FIG10 , the system for preparing a heterojunction solar cell includes: a first coating device 1001 , a second coating device 1002 , and a third coating device 1003 . Specifically:

[0136] The first coating device 1001 at least includes:

[0137] The first process chamber 100 is used to prepare the first sub-intrinsic layer 21;

[0138] A second process chamber 200 , which is connected to the first process chamber 100 , and is used to prepare the second sub-intrinsic layer 22 ;

[0139] The second coating equipment 1002 at least includes:

[0140] The first process chamber 100 is used to prepare the third sub-intrinsic layer 31;

[0141] A second process chamber 200 , which is connected to the first process chamber 100 , and is used to prepare the fourth sub-intrinsic layer 32 ;

[0142] The second process doping cavity 920 is used to prepare the second doping layer 42;

[0143] The third coating equipment 1003 at least includes:

[0144] The first process doping chamber 910 is used to prepare the first doping layer 41 .

[0145] The above-mentioned coating system, i.e., the system for preparing heterojunction solar cells, also includes conventional chambers such as a loading chamber, a flipping mechanism, and an unloading chamber, which will not be further described here. For example, in this system, the first coating apparatus 1001 may include a first loading chamber 710, a first process chamber 100, a second process chamber 200, and a first unloading chamber 810, which are arranged in sequence; the second coating apparatus 1002 may include a second loading chamber 720, a first process chamber 100, a second process chamber 200, a second process doping chamber 920, and a second unloading chamber 820, which are arranged in sequence. The third coating apparatus may include a third loading chamber 730, a first process doping chamber 910, and a third unloading chamber 830, which are arranged in sequence. In addition, a flipping mechanism for flipping the silicon wafer may be provided between the first coating apparatus 1001 and the second coating apparatus 1002, and a flipping mechanism for flipping the silicon wafer may be provided between the second coating apparatus 1002 and the third coating apparatus 1003.

[0146] The process temperature in the first process chamber 100 is at least 25°C lower than the process temperature in the second process chamber 200. Furthermore, the process temperature in the first process chamber 100 may range from 130°C to 200°C, and the process temperature in the second process chamber 200 may range from 180°C to 250°C. Relatively speaking, the first process chamber is a low-temperature process chamber, and the second process chamber is a high-temperature process chamber.

[0147] Thus, when applying the above-mentioned system for preparing heterojunction solar cells to prepare heterojunction solar cells, in the first coating device 1001, the silicon wafer is first loaded into the loading chamber, and then in the first process chamber 100, a relatively low process temperature such as 130-200°C is used to deposit and form a first sub-intrinsic layer 21 on the first surface of the silicon substrate, and then in the second process chamber 200, a relatively high process temperature such as 150-250°C is used to deposit and form a second sub-intrinsic layer 22 on the first sub-intrinsic layer 21. After the silicon wafer is flipped, that is, after the first and second surfaces of the silicon substrate are reversed, a third sub-intrinsic layer 31 is deposited on the second surface of the silicon substrate in the first process chamber 100 in the second coating apparatus 100 using a relatively low process temperature, such as 130-200°C. A fourth sub-intrinsic layer 32 is then deposited on the third sub-intrinsic layer 31 in the second process chamber 200 using a relatively high process temperature, such as 150-250°C. Then, a second doped layer 42 is deposited on the fourth sub-intrinsic layer 32 in the second process doping chamber 920. After the silicon wafer is flipped, that is, after the second and first surfaces of the silicon substrate are reversed, a first doped layer 41 is deposited on the second sub-intrinsic layer 22 in the first process doping chamber 910 in the third coating apparatus 1003. During the fabrication of heterojunction solar cells using this system, a second flipping process is performed.

[0148] In addition, optionally, in the above-mentioned coating system, a heating chamber 300 may be provided between the first process chamber 100 and the second process chamber 200, that is, between the first low-temperature process chamber and the second high-temperature process chamber. For the setting of the heating chamber 300, reference may be made to the technical content in FIG3 , which will not be further explained here.

[0149] In addition, as shown in Figure 11, optionally, when the first intrinsic passivation layer 20 further includes a fifth sub-intrinsic layer 23, wherein the first sub-intrinsic layer 21, the fifth sub-intrinsic layer 23, and the second sub-intrinsic layer 22 are stacked in sequence; the second intrinsic passivation layer 30 further includes a sixth sub-intrinsic layer 33, wherein the third sub-intrinsic layer 31, the sixth sub-intrinsic layer 33, and the fourth sub-intrinsic layer 32 are stacked in sequence. In the above-mentioned coating system, a third process chamber 400 can also be provided between the first process chamber 100 and the second process chamber 200. The third process chamber 400 is used to prepare the fifth sub-intrinsic layer 23 and the sixth sub-intrinsic layer 33. The specific system schematic diagram can be seen in Figure 11. For the configuration of the third process chamber 400 and related processes, please refer to the relevant technical content in Figure 4 and will not be further explained here.

[0150] Optionally, the above-mentioned system for preparing heterojunction solar cells may also include equipment for preparing a transparent conductive layer in a heterojunction solar cell, equipment for preparing electrodes, etc. These equipments can refer to relevant technologies and are not further described here.

[0151] Based on the same inventive concept, as shown in FIG. 1 to FIG. 11 , this embodiment provides a method for preparing a heterojunction solar cell. The method may use at least two of the aforementioned apparatuses for preparing a heterojunction solar cell, or use the aforementioned system. The method comprises:

[0152] Providing a silicon substrate 10, wherein the silicon substrate 10 includes a first surface and a second surface disposed opposite to each other;

[0153] Using one of the apparatuses for preparing heterojunction solar cells, a first sub-intrinsic layer 21 is deposited on a first surface of a silicon substrate 10 at a first process temperature in a first process chamber 100. A second sub-intrinsic layer 22 is deposited on the surface of the first sub-intrinsic layer 21 in a second process chamber 200 at a second process temperature.

[0154] Then, the silicon substrate 10 is flipped over, that is, the first surface and the second surface are turned over.

[0155] Using another apparatus for preparing a heterojunction solar cell, a third sub-intrinsic layer 31 is deposited on the second surface of the silicon substrate 10 at a first process temperature in the first process chamber 100. A second sub-intrinsic layer 32 is deposited on the surface of the third sub-intrinsic layer 31 at a second process temperature in the second process chamber 200.

[0156] The first process temperature is different from the second process temperature; preferably, the first process temperature is in the range of 130-200°C, and the second process temperature is in the range of 180-250°C. The first process temperature is lower than the second process temperature, and the first process temperature is at least 25°C lower than the second process temperature.

[0157] It should be understood that the method for preparing a heterojunction solar cell in this embodiment and the aforementioned device for preparing a heterojunction solar cell are based on the same inventive concept, and therefore have at least all the features and advantages of the device for preparing a heterojunction solar cell, which will not be repeated here.

[0158] The preparation method of the embodiment of the present invention has a simple process and is easy to implement. The prepared intrinsic passivation layer has good film quality and good passivation effect. It can improve the parallel resistance, short-circuit current and open-circuit voltage of heterojunction solar cells and has good application prospects.

[0159] Specifically, in the method for preparing a heterojunction solar cell, before preparing the first intrinsic passivation layer 20 and the second intrinsic passivation layer 30 , a step of performing a texturing and cleaning treatment on the silicon substrate may be further included.

[0160] In some embodiments, in a method for fabricating a heterojunction solar cell, a first intrinsic passivation layer 20 is formed on a first surface of a silicon substrate 10, and a second intrinsic passivation layer 30 is formed on a second surface of the silicon substrate 10. The first intrinsic passivation layer 20 includes a first sub-intrinsic layer 21 proximate the first surface of the silicon substrate 10, and a second sub-intrinsic layer 22 located on the first sub-intrinsic layer 21. The second intrinsic passivation layer 30 includes a third sub-intrinsic layer 31 proximate the second surface of the silicon substrate 10, and a fourth sub-intrinsic layer 32 located on the third sub-intrinsic layer 31. In this embodiment, the first sub-intrinsic layer 21 and the third sub-intrinsic layer 31 are formed using a low-temperature process in the first process chambers 100 of two separate devices, and the second sub-intrinsic layer 22 and the fourth sub-intrinsic layer 32 are formed using a high-temperature process in the second process chambers 200 of two separate devices. Furthermore, preferably, the first sub-intrinsic layer 21 and the third sub-intrinsic layer 31 are prepared by a low-temperature process in the first process chambers 100 of the two devices, and the second sub-intrinsic layer 22 and the fourth sub-intrinsic layer 32 are prepared by a high-temperature process in the second process chambers 200 of the two devices.

[0161] Furthermore, the high conversion efficiency of heterojunction solar cells is primarily due to their high switching voltage and excellent surface passivation, with the intrinsic passivation layer between the silicon wafer and the doped layer being key to surface passivation. The inevitable epitaxial growth at the a-Si:H / c-Si interface during the intrinsic a-Si:H deposition process is detrimental to surface passivation. To prevent epitaxy, a passivation layer with a high hydrogen content must be deposited at the a-Si:H / c-Si interface. In this embodiment, the first sub-intrinsic layer deposited at low temperature exhibits inferior film quality compared to high-temperature deposition in the prior art, with more voids and defects, but it nonetheless provides a good anti-epitaxial effect. The second sub-intrinsic layer, deposited at high temperature, serves as the main passivation layer. By adjusting process parameters (e.g., power, pressure, and reactant gases), a lower second deposition rate is achieved, resulting in a denser film with fewer defects and a better passivation effect. Therefore, preferably, the deposition rate within the first process chamber 100 is the first deposition rate, and the deposition rate within the second process chamber 200 is the second deposition rate, with the first deposition rate being greater than the second deposition rate.

[0162] This embodiment adopts a chamber-based coating method, which facilitates the regulation of the coating temperature and can independently control the process temperatures of two or more film layers.

[0163] In this embodiment, the first process temperature is lower than the second process temperature, and the first deposition rate is lower than the second deposition rate. Optionally, the first process temperature is at least 25°C lower than the second process temperature. Furthermore, the first process temperature may be less than 200°C, and the second process temperature may be ≥180°C or ≥200°C. Compared to the existing first process temperature and second process temperature both being above 200°C, this embodiment reduces the first process temperature for preparing the first sub-intrinsic layer 21, and taking into account the influence of the deposition rate, reduces the first deposition rate at the same time.

[0164] In some preferred embodiments, the first process temperature ranges from 130° C. to 200° C., and may further be 150° C. to 180° C.; the second process temperature ranges from 180° C. to 250° C., and may further be 200° C. to 240° C. For example, the process temperature in the first process chamber 100 , i.e., the deposition temperature, may be 150° C., 160° C., 170° C., 180° C., 190° C., etc., and the process temperature in the second process chamber 200 , i.e., the deposition temperature, may be 180° C., 200° C., 205° C., 210° C., 220° C., 230° C., 240° C., etc.

[0165] In some embodiments, the thickness of the first sub-intrinsic layer 21 is 0.5nm to 2nm, for example, it can be 0.5nm, 0.6nm, 0.8nm, 1nm, 1.2nm, 1.5nm, 1.8nm, 2nm, etc.; the thickness of the third sub-intrinsic layer 31 is 0.75nm to 3nm, for example, it can be 0.75nm, 0.8nm, 4nm, 1nm, 1.2nm, 1.5nm, 1.8nm, 2nm, 2.5nm, 3nm, etc.; the thickness of the second sub-intrinsic layer 22 is 3nm to 6nm, for example, it can be 3nm, 3.5nm, 3.8nm, 4nm, 4.5nm, 5nm, 5.6nm, 6nm, etc.; the thickness of the fourth sub-intrinsic layer 32 is 2nm to 5nm, for example, it can be 2nm, 2.5nm, 3nm, 2.5nm, 4nm, 4.5nm, 5nm, etc.

[0166] The thickness of the second sub-intrinsic layer 22 is preferably greater than that of the first sub-intrinsic layer 21, and the thickness of the fourth sub-intrinsic layer 32 is preferably greater than that of the third sub-intrinsic layer 31. Thus, within the aforementioned film layer thickness range, the efficacy of each film layer can be fully utilized, and while ensuring the functional effects of each film layer, costs can be reduced.

[0167] In some embodiments, the thickness of the first intrinsic passivation layer 20 is 3nm to 8nm, that is, the total thickness of the first sub-intrinsic layer 21 and the second sub-intrinsic layer 22 is 3nm to 8nm, and can further be 5nm to 8nm; illustratively, the thickness of the first intrinsic passivation layer 20 can be 3nm, 4nm, 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 8nm, etc.

[0168] The thickness of the second intrinsic passivation layer 30 is 2nm~8nm, that is, the total thickness of the third sub-intrinsic layer 31 and the fourth sub-intrinsic layer 32 is 2nm~8nm, and can further be 4nm~8nm; illustratively, the thickness of the second intrinsic passivation layer 30 can be 2nm, 3nm, 4nm, 5nm, 5.5nm, 6nm, 6.5nm, 7nm, 8nm, etc.

[0169] In a specific implementation process, the thickness of each intrinsic passivation film layer can be controlled by controlling operating conditions such as the forming time of each intrinsic passivation film layer.

[0170] Therefore, using each intrinsic passivation layer within the above-mentioned thickness range or the total thickness of the passivation layer within the above-mentioned range is easier to implement and convenient to process and manufacture, and at the same time has better film quality and good use effect, which helps to improve the surface passivation effect of heterojunction solar cells.

[0171] Optionally, the reaction gas used in forming the first and third sub-intrinsic layers can be silane, or a combination of silane and hydrogen. The first sub-intrinsic layer (using the first sub-intrinsic layer as an example) located near the surface of the silicon substrate 10 needs to have a good anti-epitaxial effect. This sub-layer has the most disordered atomic structure and the lowest crystallinity. The process gas typically primarily uses silane, or a combination of silane and a small amount of hydrogen.

[0172] Optionally, the reaction gases used in preparing the second and fourth intrinsic sub-layers may include silane and hydrogen. The second intrinsic sub-layer (taking the second intrinsic sub-layer as an example) away from the surface of the silicon substrate 10 should achieve a better passivation effect.

[0173] It should be understood that one or more transition sub-layers may be provided between the first and second intrinsic sub-layers, or none. Similarly, one or more transition sub-layers may be provided between the third and fourth intrinsic sub-layers, or none.

[0174] Furthermore, the method for preparing a heterojunction solar cell may also include the step of preparing a doping layer. For example, after forming a first intrinsic passivation layer 20 on the first surface of the silicon substrate 10, a first doping layer 41 is deposited on the first intrinsic passivation layer 20, the silicon wafer is flipped over, and a second intrinsic passivation layer 30 is deposited on the second surface of the silicon substrate 10. A second doping layer 42 is deposited on the second intrinsic passivation layer 30. The doping type of the second doping layer 42 is opposite to that of the first doping layer 41, with one being N-type doping, such as phosphorus doping, and the other being P-type doping, such as boron doping. Alternatively, after forming the first intrinsic passivation layer 20 on the first surface of the silicon substrate 10, the silicon wafer is flipped over, and a second intrinsic passivation layer 30 is deposited on the second surface of the silicon substrate 10. A second doping layer 42 is deposited on the second intrinsic passivation layer 30. The silicon wafer is then flipped over again, and the first doping layer 41 is deposited on the first intrinsic passivation layer 20.

[0175] Optionally, the first doping layer 41 may be an N-type doping layer (such as an N-type phosphorus doping layer), and the second doping layer 42 may be a P-type doping layer (P-type boron doping layer).

[0176] Furthermore, the process may further include the step of preparing a transparent conductive layer. Specifically, a first transparent conductive layer 51 is deposited on the first doping layer 41 , and a second transparent conductive layer 52 is deposited on the second doping layer 42 .

[0177] Furthermore, the process may further include a step of preparing electrodes. Specifically, a first electrode 61 is formed on the first transparent conductive layer 51, and a second electrode 62 is formed on the second transparent conductive layer 52, thereby obtaining a heterojunction solar cell.

[0178] It should be pointed out here that in the preparation method of the heterojunction solar cell, the specific processes of preparing the doping layer, preparing the transparent conductive layer, preparing the electrode, etc. can refer to the existing technology and adopt conventional production process flow or operation mode. This embodiment does not limit this and will not be described in detail here.

[0179] In this embodiment, the first sub-intrinsic layer 21 is deposited at low temperature. Separate chambers are used for deposition of the first and second sub-intrinsic layers 21 and 22, enabling independent control of the process temperatures for both layers. Compared to high-temperature deposition, the lower deposition temperature (150-200°C) of the first sub-intrinsic layer 21 significantly increases the hydrogen content of the film. Furthermore, a low-refractive-index amorphous silicon film can be obtained at a relatively low deposition rate (e.g., 0.25-0.50 nm / s), meeting the passivation requirements of heterojunction solar cells. Furthermore, low-temperature deposition of the first sub-intrinsic layer 21 results in a looser film structure, improved passivation, and reduced parasitic light absorption. Application to heterojunction solar cells can significantly improve parallel resistance, short-circuit current, and open-circuit voltage. Furthermore, low-temperature deposition of the first sub-intrinsic layer 21 offers a wider process window and reduced sensitivity to deposition temperature, thereby minimizing the impact of equipment fluctuations on cell efficiency.

[0180] Parts not described in detail in the specification of the present invention are well known to those skilled in the art.

[0181] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. It should be noted that the terms "and / or" or " / " used in this article are merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone.

[0182] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A device for preparing a heterojunction solar cell, characterized in that: The heterojunction solar cell comprises a silicon substrate, a first intrinsic passivation layer and a first doping layer stacked in sequence on a first surface of the silicon substrate, and a second intrinsic passivation layer and a second doping layer stacked in sequence on a second surface of the silicon substrate, wherein the first intrinsic passivation layer comprises a first sub-intrinsic layer and a second sub-intrinsic layer, and the second intrinsic passivation layer comprises a third sub-intrinsic layer and a fourth sub-intrinsic layer; the device comprises: A first process chamber, used for preparing the first sub-intrinsic layer; a second process chamber, the second process chamber being connected to the first process chamber, and the second process chamber being used for preparing the second sub-intrinsic layer; Alternatively, the first process chamber is used to prepare the third sub-intrinsic layer; a second process chamber, the second process chamber being connected to the first process chamber, and the second process chamber being used for preparing the fourth sub-intrinsic layer; The process temperature in the first process chamber is at least 25° C. lower than the process temperature in the second process chamber.

2. The device for preparing a heterojunction solar cell according to claim 1, characterized in that: The process temperature in the first process chamber ranges from 130 to 200° C., and the process temperature in the second process chamber ranges from 180 to 250° C.

3. The device for preparing a heterojunction solar cell according to claim 1, characterized in that: The first process chamber is connected to the second process chamber through a first gate valve, a first heating device and a second heating device are respectively provided in the first process chamber and the second process chamber, and a first transmission mechanism and a second transmission mechanism are also respectively provided in the first process chamber and the second process chamber; After completing the preparation of the first sub-intrinsic layer or the third sub-intrinsic layer in the first process chamber, open the first gate valve, enter into the second process chamber, adjust the temperature of the second heating device, and prepare the corresponding second sub-intrinsic layer or the fourth sub-intrinsic layer.

4. The device for preparing a heterojunction solar cell according to claim 1, characterized in that: The device further comprises a heating chamber, wherein the heating chamber is located between the first process chamber and the second process chamber; The outlet end of the first process chamber is connected to the inlet end of the heating chamber through a second gate valve, and the outlet end of the heating chamber is connected to the inlet end of the second process chamber through a third gate valve.

5. The device for preparing a heterojunction solar cell according to claim 1, characterized in that: The device further includes a third process chamber, wherein the third process chamber is located between the first process chamber and the second process chamber; The outlet end of the first process chamber is connected to the inlet end of the third process chamber through a fourth gate valve, and the outlet end of the third process chamber is connected to the inlet end of the second process chamber through a fifth gate valve.

6. The device for preparing a heterojunction solar cell according to claim 5, characterized in that: The first intrinsic passivation layer further includes a fifth sub-intrinsic layer, wherein the first sub-intrinsic layer, the fifth sub-intrinsic layer and the second sub-intrinsic layer are sequentially stacked; and / or the second intrinsic passivation layer further includes a sixth sub-intrinsic layer, wherein the third sub-intrinsic layer, the sixth sub-intrinsic layer and the fourth sub-intrinsic layer are sequentially stacked; The third process chamber is used to prepare the fifth sub-intrinsic layer or the sixth sub-intrinsic layer, the process temperature in the third process chamber is greater than or equal to the process temperature in the first process chamber, and the process temperature in the third process chamber is less than or equal to the process temperature in the second process chamber.

7. The device for preparing a heterojunction solar cell according to any one of claims 1 to 6, characterized in that: The device also includes a buffer cavity, in which a transmission mechanism is provided; The first process chamber is connected to the first end of the buffer chamber through a sixth gate valve, and the second process chamber is connected to the second end of the buffer chamber through a seventh gate valve. The first end and the second end are arranged at an angle.

8. A system for preparing a heterojunction solar cell, characterized in that: The heterojunction solar cell comprises a silicon substrate, a first intrinsic passivation layer and a first doping layer stacked in sequence on a first surface of the silicon substrate, and a second intrinsic passivation layer and a second doping layer stacked in sequence on a second surface of the silicon substrate, wherein the first intrinsic passivation layer comprises a first sub-intrinsic layer and a second sub-intrinsic layer, and the second intrinsic passivation layer comprises a third sub-intrinsic layer and a fourth sub-intrinsic layer; The system comprises in sequence: a first coating device and a second coating device, characterized in that: The first coating device at least comprises: A first process chamber, used for preparing the first sub-intrinsic layer; a second process chamber, the second process chamber being connected to the first process chamber, and the second process chamber being used for preparing the second sub-intrinsic layer; A first process doping chamber, used for preparing the first doping layer; The second coating device at least comprises: A first process chamber, used for preparing the third sub-intrinsic layer; a second process chamber, the second process chamber being connected to the first process chamber, and the second process chamber being used for preparing the fourth sub-intrinsic layer; A second process doping cavity, used for preparing the second doping layer; Wherein, the process temperature in the first process chamber is at least 25° C. lower than the process temperature in the second process chamber.

9. A system for preparing a heterojunction solar cell, characterized in that: The heterojunction solar cell comprises a silicon substrate, a first intrinsic passivation layer and a first doping layer stacked in sequence on a first surface of the silicon substrate, and a second intrinsic passivation layer and a second doping layer stacked in sequence on a second surface of the silicon substrate, wherein the first intrinsic passivation layer comprises a first sub-intrinsic layer and a second sub-intrinsic layer, and the second intrinsic passivation layer comprises a third sub-intrinsic layer and a fourth sub-intrinsic layer; The system comprises in sequence: a first coating device, a second coating device and a third coating device, characterized in that: The first coating device at least comprises: A first process chamber, used for preparing the first sub-intrinsic layer; a second process chamber, the second process chamber being connected to the first process chamber, and the second process chamber being used for preparing the second sub-intrinsic layer; The second coating device at least comprises: A first process chamber, used for preparing the third sub-intrinsic layer; a second process chamber, the second process chamber being connected to the first process chamber, and the second process chamber being used for preparing the fourth sub-intrinsic layer; A second process doping cavity, used for preparing the second doping layer; The third coating equipment at least includes: A first process doping chamber, used for preparing the first doping layer; Wherein, the process temperature in the first process chamber is at least 25° C. lower than the process temperature in the second process chamber.

10. The system for preparing a heterojunction solar cell according to claim 8 or 9, characterized in that: A heating chamber is further arranged between the first process chamber and the second process chamber.

11. The system for preparing a heterojunction solar cell according to claim 8 or 9, characterized in that: A third process chamber is also provided between the first process chamber and the second process chamber, which is used to prepare a fifth sub-intrinsic layer between the first sub-intrinsic layer and the second sub-intrinsic layer, or to prepare a sixth sub-intrinsic layer between the third sub-intrinsic layer and the fourth sub-intrinsic layer.

12. A method for preparing a heterojunction solar cell, characterized in that: The method uses at least two devices for preparing heterojunction solar cells according to any one of claims 1 to 7; the method comprises: Providing a silicon substrate, the silicon substrate comprising a first surface and a second surface arranged opposite to each other; In a first process chamber of a device, a first sub-intrinsic layer is deposited on a first surface of a silicon substrate under conditions of a first process temperature and a first deposition rate, and in a second process chamber, a second sub-intrinsic layer is deposited on a surface of the first sub-intrinsic layer under conditions of a second process temperature and a second deposition rate; In a first process chamber of another device, a third sub-intrinsic layer is deposited on a second surface of the silicon substrate under the conditions of a first process temperature and a first deposition rate; and in a second process chamber, a fourth sub-intrinsic layer is deposited on a surface of the third sub-intrinsic layer under the conditions of a second process temperature and a second deposition rate; The first process temperature is at least 25° C. lower than the second process temperature.

13. The method for preparing a heterojunction solar cell according to claim 12, characterized in that: The first process temperature ranges from 130 to 200°C, and the second process temperature ranges from 180 to 250°C.

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