Clock synchronization method, device, and storage medium

Abstract

Embodiments of the present disclosure relate to the technical field of communications, and provide a clock synchronization method, a device, and a storage medium. The method comprises: acquiring slave clock configuration information, and according to the slave clock configuration information, generating and broadcasting a clock request configuration packet; establishing clock links with a plurality of second clock source devices that configure a master clock according to the clock request configuration packet, until there are a preset number of clock links of a first clock source device and there is no abnormal clock link, so as to obtain the plurality of clock links; selecting a target clock link among the plurality of clock links, and by means of the target clock link, performing clock synchronization on the second clock source devices corresponding to the target clock link.

Description

Clock synchronization method, device and storage medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure is based on and claims the priority of Chinese patent application No. 202310715370.2 filed on June 15, 2023, and all the disclosed contents are incorporated into this disclosure by reference. Technical Field

[0003] The embodiments of the present disclosure relate to the field of communication technologies, and in particular to a clock synchronization method, device, and storage medium. Background Art

[0004] With the advancement of wireless communication technology and the increasing use of wireless access equipment, high-precision time synchronization between devices is essential to reliably meet user needs. This is the context for the emergence of 1588v2 clocks. 1588v2 clocks are high-precision clocks that utilize the IEEE 1588 protocol (a standard for precision clock synchronization for networked measurement and control systems). 1588v2 clocks are a universal specification that enhances the timing synchronization capabilities of network systems, enabling strict timing synchronization in distributed communication networks and finding application in industrial automation systems. The basic concept is to synchronize the internal clocks of network devices (clients) with the master clock of the host computer through hardware and software, achieving synchronization setup times of less than 10μs. This significantly improves the timing synchronization performance of the entire network compared to the 1000μs latency of Ethernet networks that do not implement IEEE 1588.

[0005] 1588v2 clocks are a master-slave synchronization system. Slave devices must rely on the normal operation of the master clock synchronization server and a reliable transmission link for clock synchronization. Complex network environments place high demands on the clock synchronization server and link. Abnormalities in the clock synchronization server, link, and communication transmission jitter can cause the 1588v2 clock source to become unavailable, leading to clock synchronization failure.

[0006] Summary of the Invention

[0007] The embodiments of the present disclosure provide a clock synchronization method, device, and storage medium, aiming to improve the accuracy of clock synchronization.

[0008] In a first aspect, an embodiment of the present disclosure provides a clock synchronization method, applied to a first clock source device, the method comprising:

[0009] Obtain slave clock configuration information, and generate and broadcast a clock request configuration message based on the slave clock configuration information;

[0010] Establishing clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock links of the first clock source device reach a preset number and there are no abnormal clock links, thereby obtaining multiple clock links;

[0011] A target clock link is selected from multiple clock links, and clock synchronization is performed with a second clock source device corresponding to the target clock link through the target clock link.

[0012] In a second aspect, the embodiments of the present disclosure further provide another clock synchronization method, which is applied to a second clock source device, and the method includes:

[0013] Obtain a clock request configuration message, and if the preset master clock configuration conditions are met, perform master clock configuration according to the clock request configuration message to generate master clock configuration information;

[0014] Establishing a clock link with the first clock source device that broadcasts the clock request configuration message according to the master clock configuration information;

[0015] Perform clock synchronization with the first clock source device through a clock link.

[0016] In a third aspect, an embodiment of the present disclosure further provides a device, comprising a processor, a memory, a computer program stored in the memory and executable by the processor, and a data bus for realizing connection and communication between the processor and the memory, wherein when the computer program is executed by the processor, the steps of any one of the clock synchronization methods provided in the specification of the present disclosure are implemented.

[0017] In a fourth aspect, an embodiment of the present disclosure further provides a storage medium for computer-readable storage, characterized in that the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of any clock synchronization method provided in the specification of this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] FIG1 is a flow chart of a clock synchronization method provided by an embodiment of the present disclosure;

[0019] FIG2 is a schematic diagram of a process for configuring a first clock source device according to an embodiment of the present disclosure;

[0020] FIG3 is a schematic flow chart of sub-steps of the clock synchronization method in FIG1 ;

[0021] FIG4 is a schematic diagram of a process for configuring a second clock source device according to an embodiment of the present disclosure;

[0022] FIG5 is a schematic diagram of a scenario of establishing a clock link according to an embodiment of the present disclosure;

[0023] FIG6 is a schematic diagram of another scenario of establishing a clock link according to an embodiment of the present disclosure;

[0024] FIG7 is a schematic diagram of a process for establishing a clock link according to an embodiment of the present disclosure;

[0025] FIG8 is a schematic diagram of another scenario of establishing a clock link according to an embodiment of the present disclosure;

[0026] FIG9 is a flow chart of another clock synchronization method provided by an embodiment of the present disclosure;

[0027] FIG10 is a schematic block diagram of the structure of a device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present disclosure without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0029] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, combined, or partially merged, so the actual execution order may vary depending on the actual situation.

[0030] It should be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used in this disclosure, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms.

[0031] The embodiments of the present disclosure provide a clock synchronization method, device, and storage medium. The clock synchronization method can be applied to a device, which can be an electronic device such as a mobile phone, a base station, a router, a server, a tablet computer, a laptop computer, a desktop computer, a personal digital assistant, and a wearable device. For example, the first clock source device is a mobile phone, which obtains slave clock configuration information and generates and broadcasts a clock request configuration message based on the slave clock configuration information; establishes a clock link with multiple second clock source devices that perform master clock configuration based on the clock request configuration message, until the clock link of the first clock source device reaches a preset number and there are no abnormal clock links, thereby obtaining multiple clock links; selects a target clock link from the multiple clock links, and performs clock synchronization with the second clock source device corresponding to the target clock link through the target clock link.

[0032] The following describes some embodiments of the present disclosure in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0033] Please refer to FIG. 1 , which is a flow chart of a clock synchronization method provided by an embodiment of the present disclosure.

[0034] As shown in FIG1 , the clock synchronization method includes steps S101 to S103 .

[0035] Step S101: Obtain slave clock configuration information, and generate and broadcast a clock request configuration message based on the slave clock configuration information.

[0036] The slave clock configuration information is characteristic information for configuring the master and slave clocks, and includes a domain number, a user profile Profile type of an IP clock, and an Internet Protocol Address (IP address) of the first clock source device.

[0037] In one embodiment, a user management engine in a first clock source device configures a 1588v2 clock configuration function enable item to enable the first clock source device to enter clock link configuration mode. The user management engine is a configuration function provided in the first clock source device. The specific operating mode of the user management engine can be configured based on actual conditions and is not specifically limited in this embodiment of the present disclosure. However, the user management engine can accurately enable the first clock source device to enter clock link configuration mode, significantly improving the efficiency of clock link configuration.

[0038] It should be noted that the user management engine can also be set in other terminal devices. For example, the terminal device can be a mobile phone, which is equipped with a user management engine. The user management engine in the mobile phone configures a 1588v2 clock configuration function enable item instruction and sends the 1588v2 clock configuration function enable item instruction to the first clock source device. The first clock source device configures the 1588v2 clock configuration function enable item according to the 1588v2 clock configuration function enable item instruction. By controlling the first clock source device to configure the 1588v2 clock configuration function enable item under the control of the 1588v2 clock configuration function enable item instruction configured by other terminal devices, the flexibility of establishing a clock link can be improved.

[0039] In one embodiment, slave clock configuration information is obtained to determine whether the first clock source device meets the conditions of an abnormal clock source state and not serving as a master clock device; if the first clock source device meets the conditions of an abnormal clock source state and not serving as a master clock device, a clock request configuration message is generated and broadcast based on the slave clock configuration information; if the first clock source device does not meet at least one of the conditions of an abnormal clock source state and not serving as a master clock device, only a preset clock request configuration message is broadcast, and a clock link is established based on the broadcasted preset clock request configuration message. The preset clock request configuration message is pre-set in the first clock source device and may be generated during a previous clock link establishment. By determining whether the first clock source device meets the conditions of an abnormal clock source state and not serving as a master clock device, the efficiency and accuracy of establishing the clock link can be improved.

[0040] Exemplarily, as shown in Figure 2, step S201 detects whether the clock source status of the first clock source device is abnormal; if the clock source status of the first clock source device is not abnormal, step S202 is executed to ensure that the first clock source device maintains the current configuration; if the clock source status of the first clock source device is abnormal, step S203 is executed to determine whether the first clock source device serves as the 1588v2 master clock; if the first clock source device serves as the 1588v2 master clock, step S202 is executed to ensure that the first clock source device maintains the current configuration; if the first clock source device does not serve as the 1588v2 master clock, step S204 is executed to configure the first clock source device with a 1588v2 slave clock according to the slave clock configuration information; step S205 generates and broadcasts a clock request configuration message according to the slave clock configuration information.

[0041] In one embodiment, a clock request configuration message is generated and broadcast based on the slave clock configuration information by adding a clock request configuration flag, domain number, IP clock user profile type, and device IP address to the message to generate and broadcast the clock request configuration message. By adding the clock request configuration flag, domain number, IP clock user profile type, and device IP address to the message, the clock request configuration message can be accurately generated, significantly improving the efficiency and accuracy of establishing a clock link.

[0042] In one embodiment, after a clock request configuration message is generated, the clock request configuration message is broadcast so that each second clock source device can receive the clock request configuration message. It should be noted that the scope of broadcasting the clock request configuration message can be determined based on actual conditions and is not specifically limited in this embodiment of the present disclosure. For example, the broadcast scope is within a preset local area network. The preset local area network can be set based on actual conditions and is not specifically limited in this embodiment of the present disclosure. For example, the preset local area network is a local area network composed of multiple base stations.

[0043] Step S102: Establish clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message, until the clock links of the first clock source device reach a preset number and there are no abnormal clock links, thereby obtaining multiple clock links.

[0044] Among them, the clock link is a communication link used for clock synchronization.

[0045] In one embodiment, as shown in FIG3 , step S102 includes sub-steps S1021 and S1022 .

[0046] Sub-step S1021: When the clock link of the first clock source device has not reached the preset number, establish clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock link of the first clock source device reaches the preset number, thereby obtaining multiple clock links.

[0047] The preset number can be set according to actual conditions, and the embodiment of the present disclosure does not specifically limit this. For example, the preset number can be set to 5.

[0048] In one embodiment, if the number of clock links to a first clock source device does not reach a preset number, a second clock source device receives a clock request configuration message and, if it meets preset master clock configuration conditions, performs master clock configuration according to the clock request configuration message, generating master clock configuration information. Based on the master clock configuration information, a clock link is established with the first clock source device that broadcast the clock request configuration message. The preset master clock configuration conditions include the second clock source device being in a normal clock source state and not serving as a master or slave clock source for the first clock source device that broadcast the clock request configuration message. The second clock source device performs master clock configuration according to the clock request configuration message, accurately generating master clock configuration information, and establishes a clock link with the first clock source device based on the master clock configuration information.

[0049] In one embodiment, the master clock is configured according to the clock request configuration message, and the master clock configuration information can be generated by parsing the clock request configuration message, generating the domain number, the IP clock profile type and the device IP address, and synchronously sending the domain number, the IP clock profile type and the device IP address to the 1588v2 master clock to complete the configuration of the master clock.

[0050] In one embodiment, a method for establishing a clock link with a first clock source device that broadcasts a clock request configuration message based on the master clock configuration information may include: establishing a communication connection with the first clock source device based on the master clock configuration information, and establishing the clock link after exchanging clock messages with the first clock source device. The clock link can be accurately established after the first clock source device and the second clock source device exchange clock messages.

[0051] Exemplarily, as shown in Figure 4, step S301, the second clock source device obtains a clock request configuration message; step S302 determines whether the clock source status of the second clock source device is abnormal; if the clock source status of the second clock source device is abnormal, execute step S303 to maintain the current configuration and end the establishment of the clock link; if the clock source status of the second clock source device is normal, step S304 determines whether the second clock source device serves as the master clock source or slave clock source of the first clock source device; if the second clock source device serves as the master clock source or slave clock source of the first clock source device, execute step S303 to maintain the current configuration and end the establishment of the clock link; if the second clock source device does not serve as the master clock source or slave clock source of the first clock source device, step S305 performs the master clock configuration according to the clock request configuration message to generate the master clock configuration information.

[0052] In one embodiment, if the number of clock links with a first clock source device does not reach a preset number, clock links are established with multiple second clock source devices that have been configured as master clocks based on clock request configuration messages until the number of clock links with the first clock source device reaches the preset number, thereby obtaining multiple clock links. By establishing clock links with each of the second clock source devices, multiple clock links can be accurately obtained, greatly improving the stability of clock synchronization.

[0053] In one embodiment, if a first clock source device has fewer than a preset number of clock links, and a newly added second clock source device exists in the local area network (LAN) in which the first clock source device resides, a clock request configuration message is broadcast; and a clock link is established with the newly added second clock source device that performs master clock configuration according to the clock request configuration message. By establishing clock links with the newly added second clock source device in the LAN, the number of clock links can be increased, thereby improving the stability of clock synchronization.

[0054] For example, as shown in FIG5 , if the number of clock links of the first clock source device 11 has not reached a preset number, where the preset number is 3, a clock request configuration message is generated and broadcast based on the slave clock configuration information. The second clock source device a21 receives the clock request configuration message, performs master clock configuration based on the clock request configuration message, generates master clock configuration information, and establishes a clock link with the first clock source device 11 based on the master clock configuration information. The second clock source device b22 receives the clock request configuration message, performs master clock configuration based on the clock request configuration message, generates master clock configuration information, and establishes a clock link with the first clock source device 11 based on the master clock configuration information. The second clock source device d24 receives the clock request configuration message, performs master clock configuration based on the clock request configuration message, generates master clock configuration information, and establishes a clock link with the first clock source device 11 based on the master clock configuration information. If the number of clock links of the first clock source device 11 has reached the preset number of 3, the first clock source device 11 does not establish a clock link with the second clock source device c23.

[0055] For example, as shown in Figure 6, the first clock source device 31 establishes clock links with the second clock source device e41, the second clock source device f42 and the second clock source device g43 respectively, and when there is a newly added second clock source device h44 in the local area network where the first clock source device 31 is located, the clock request configuration message is broadcast; the second clock source device h44 receives the clock request configuration message, and performs master clock configuration according to the clock request configuration message, generates master clock configuration information, and establishes a clock link with the first clock source device 31 according to the master clock configuration information.

[0056] Sub-step S1022: When the number of clock links of the first clock source device reaches a preset number and there are abnormal clock links, rebuild each abnormal clock link until there are no abnormal clock links in the clock links of the first clock source device, thereby obtaining multiple reconstructed clock links.

[0057] In one embodiment, when the number of clock links of a first clock source device reaches a preset number and an abnormal clock link exists, one abnormal clock link is deleted, and a clock link is re-established with a second clock source device other than the second clock source device to which the deleted abnormal clock link belongs according to a clock request configuration message; when it is determined that an abnormal clock link still exists, the steps of deleting one abnormal clock link and re-establishing a clock link with a second clock source device other than the second clock source device to which the deleted abnormal clock link belongs according to a clock request configuration message are performed until no abnormal clock link exists, thereby obtaining multiple clock links. By deleting the abnormal clock link and re-establishing the clock link, the stability of clock synchronization is improved while maximizing the reuse of the resources of the second clock source device is achieved.

[0058] Exemplarily, as shown in Figure 7, step S401 determines whether the clock link of the first clock source device reaches the preset number; when the clock link of the first clock source device reaches the preset number, execute step S402 to determine whether there is an abnormal clock link; when there is no abnormal clock link, execute step S403 to determine that the clock link of the first clock source device has been established; when there is an abnormal clock link, execute step S404 to delete an abnormal clock link; step S405 broadcasts a clock request configuration message; when the clock link of the first clock source device does not reach the preset number, execute step S405 to broadcast a clock request configuration message; step S406 the second clock source device establishes a clock link with the first clock source device according to the clock request configuration message.

[0059] For example, as shown in Figure 8, the first clock source device 51 has established clock links with the second clock source device i61, the second clock source device j62 and the second clock source device k63 respectively, wherein there is an abnormality in the clock link between the first clock source device 51 and the second clock source device k63, the clock link between the first clock source device 51 and the second clock source device k63 is deleted, the first clock source device 51 broadcasts a clock request configuration message, the second clock source device m64 receives the clock request configuration message, and performs master clock configuration according to the clock request configuration message, generates master clock configuration information, and establishes a clock link with the first clock source device 51 according to the master clock configuration information.

[0060] Step S103: Select a target clock link from the multiple clock links, and perform clock synchronization with a second clock source device corresponding to the target clock link through the target clock link.

[0061] In one embodiment, a target clock link is selected from a plurality of clock links, and clock synchronization is performed with a second clock source device corresponding to the target clock link via the target clock link, so that the first clock source device and the second clock source device complete clock synchronization. The target clock link can accurately and stably achieve clock synchronization between the first clock source device and the second clock source device.

[0062] It should be noted that the method of selecting the target clock link can be set according to actual conditions, and the embodiments of the present disclosure do not specifically limit this. For example, a clock link is randomly selected from multiple clock links as the target clock link.

[0063] In one embodiment, if a clock synchronization failure occurs between a first clock source device and a second clock source device, the clock link with the second clock source device is disconnected, and a target clock link is selected from multiple clock links that have not failed. Clock synchronization is then performed with the second clock source device corresponding to the target clock link via the target clock link. If a clock synchronization failure occurs with the first clock source device, clock synchronization can be completed in a timely manner by switching to the surviving clock link, thereby significantly improving the accuracy and stability of clock synchronization.

[0064] The clock synchronization method in the above embodiment obtains slave clock configuration information and, based on the slave clock configuration information, generates and broadcasts a clock request configuration message. It then establishes clock links with multiple second clock source devices that perform master clock configuration based on the clock request configuration message, until the number of clock links of the first clock source device reaches a preset number and no abnormal clock links remain, thereby obtaining multiple clock links. A target clock link is selected from the multiple clock links, and clock synchronization is performed with the second clock source device corresponding to the target clock link via the target clock link. This solution can accurately establish multiple clock links between the first clock source device and multiple second clock source devices, and perform clock synchronization based on the target clock link among the multiple clock links, greatly improving the accuracy and stability of clock synchronization of the first clock source device.

[0065] Please refer to FIG. 9 , which is a flow chart of another clock synchronization method provided by an embodiment of the present disclosure.

[0066] As shown in FIG9 , the clock synchronization method includes steps S501 to S503 .

[0067] Step S501: Obtain a clock request configuration message, and if a preset master clock configuration condition is met, perform master clock configuration according to the clock request configuration message to generate master clock configuration information.

[0068] In one embodiment, a user management engine in a first clock source device configures a 1588v2 clock configuration function enable item to enable the first clock source device to enter clock link configuration mode. The user management engine is a configuration function provided in the first clock source device and can be configured based on actual circumstances. This embodiment of the present disclosure does not specifically limit this. The user management engine accurately enables the first clock source device to enter clock link configuration mode, significantly improving the efficiency of clock link configuration.

[0069] In one embodiment, slave clock configuration information is obtained to determine whether the first clock source device meets the conditions of an abnormal clock source state and not serving as a master clock device; if the first clock source device meets the conditions of an abnormal clock source state and not serving as a master clock device, a clock request configuration message is generated and broadcast based on the slave clock configuration information; if the first clock source device does not meet at least one of the conditions of an abnormal clock source state and not serving as a master clock device, only a preset clock request configuration message is broadcast, and a clock link is established based on the broadcasted preset clock request configuration message. The preset clock request configuration message is pre-set in the first clock source device and may be generated during a previous clock link establishment. By determining whether the first clock source device meets the conditions of an abnormal clock source state and not serving as a master clock device, the efficiency and accuracy of establishing the clock link can be improved.

[0070] In one embodiment, if the number of clock links to a first clock source device does not reach a preset number, a second clock source device receives a clock request configuration message and, if it meets preset master clock configuration conditions, performs master clock configuration according to the clock request configuration message, generating master clock configuration information. Based on the master clock configuration information, a clock link is established with the first clock source device that broadcast the clock request configuration message. The preset master clock configuration conditions include the second clock source device being in a normal clock source state and not serving as a master or slave clock source for the first clock source device that broadcast the clock request configuration message. The second clock source device performs master clock configuration according to the clock request configuration message, accurately generating master clock configuration information, and establishes a clock link with the first clock source device based on the master clock configuration information.

[0071] Step S502: Establish a clock link with the first clock source device that broadcasts the clock request configuration message according to the master clock configuration information.

[0072] In one embodiment, the clock request configuration message is parsed to generate the domain number, IP clock profile type, and device IP address. These domain number, IP clock profile type, and device IP address are then synchronously sent to the 1588v2 master clock to complete the master clock configuration. Based on the master clock configuration information, a communication connection is established with the first clock source device. After exchanging clock messages with the first clock source device, a clock link is established. After the first clock source device and the second clock source device exchange clock messages, the clock link can be accurately established.

[0073] Step S503: Perform clock synchronization with the first clock source device through the clock link.

[0074] In one embodiment, after the clock link is established, clock synchronization is performed with the first clock source device according to the clock link. The clock link can accurately synchronize the clock with the first clock source device, greatly improving the accuracy and stability of clock synchronization.

[0075] The clock synchronization method in the above embodiment obtains a clock request configuration message, and when the preset master clock configuration conditions are met, performs master clock configuration according to the clock request configuration message to generate master clock configuration information; establishes a clock link with the first clock source device that broadcasts the clock request configuration message based on the master clock configuration information; and performs clock synchronization with the first clock source device through the clock link, thereby greatly improving the accuracy and stability of clock synchronization.

[0076] Please refer to FIG10 , which is a schematic block diagram of the structure of a device provided in an embodiment of the present disclosure.

[0077] As shown in FIG10 , a device 600 includes a processor 601 and a memory 602 . The processor 601 and the memory 602 are connected via a bus 603 , such as an I 2 C (Inter-Integrated Circuit) bus.

[0078] Specifically, the processor 601 is used to provide computing and control capabilities to support the operation of the entire device. The processor 601 can be a central processing unit (CPU), and the processor 601 can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0079] Specifically, the memory 602 may be a Flash chip, a read-only memory (ROM) disk, an optical disk, a USB flash drive, or a mobile hard disk.

[0080] Those skilled in the art will understand that the structure shown in Figure 10 is merely a block diagram of a partial structure related to the scheme of the present disclosure, and does not constitute a limitation on the device to which the scheme of the present disclosure is applied. The specific device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0081] The processor is configured to run a computer program stored in a memory, and implement any one of the clock synchronization methods provided in the embodiments of the present disclosure when executing the computer program.

[0082] In one embodiment, the processor 601 is configured to run a computer program stored in a memory, and implement the following steps when executing the computer program:

[0083] Obtaining slave clock configuration information, and generating and broadcasting a clock request configuration message based on the slave clock configuration information;

[0084] Establishing clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock links of the first clock source device reach a preset number and there are no abnormal clock links, thereby obtaining multiple clock links;

[0085] A target clock link is selected from the plurality of clock links, and clock synchronization is performed with a second clock source device corresponding to the target clock link through the target clock link.

[0086] In one embodiment, after obtaining the slave clock configuration information, the processor 601 is further configured to:

[0087] Determining whether the first clock source device meets the condition that the clock source state is abnormal and does not serve as a master clock device;

[0088] When the first clock source device does not meet at least one of the conditions of abnormal clock source status and not serving as a master clock device, only a preset clock request configuration message is broadcasted to establish a clock link according to the broadcasted preset clock request configuration message.

[0089] In one embodiment, the clock request configuration message includes a clock request configuration flag, a domain number, a user configuration file Profile type of the IP clock, and a device IP address.

[0090] In one embodiment, when implementing the establishment of clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock links of the first clock source device reach a preset number and no abnormal clock links exist, and multiple clock links are obtained, the processor 601 is configured to implement:

[0091] If the number of clock links of the first clock source device does not reach a preset number, establish clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the number of clock links of the first clock source device reaches a preset number, thereby obtaining multiple clock links;

[0092] When the number of clock links of the first clock source device reaches a preset number and there are abnormal clock links, each abnormal clock link is rebuilt until there are no abnormal clock links in the clock links of the first clock source device, thereby obtaining multiple rebuilt clock links.

[0093] In one embodiment, when the number of clock links in the first clock source device reaches a preset number and an abnormal clock link exists, the processor 601 reconstructs each abnormal clock link until no abnormal clock link exists in the clock link of the first clock source device, and a plurality of reconstructed clock links are obtained, and is configured to implement:

[0094] Deleting an abnormal clock link, and re-establishing a clock link with a second clock source device other than the second clock source device to which the deleted abnormal clock link belongs according to the clock request configuration message;

[0095] When it is determined that abnormal clock links still exist, the steps of deleting an abnormal clock link and re-establishing a clock link with a second clock source device other than the second clock source device to which the deleted abnormal clock link belongs are performed according to the clock request configuration message, until there are no abnormal clock links, and multiple clock links are obtained.

[0096] In one embodiment, the processor 601 is further configured to implement, when the clock link of the first clock source device does not reach a preset number, establishing clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message:

[0097] In a case where a newly added second clock source device exists in the local area network where the first clock source device is located, broadcasting the clock request configuration message;

[0098] A clock link is established with the newly added second clock source device that performs master clock configuration according to the clock request configuration message.

[0099] In one embodiment, after implementing the clock synchronization with the second clock source device corresponding to the target clock link through the target clock link, the processor 601 is further configured to implement:

[0100] Selecting a backup target clock link from the plurality of clock links when it is determined that clock synchronization between the first clock source device and the second clock source device corresponding to the target clock link is abnormal;

[0101] Clock synchronization is performed with a second clock source device corresponding to the target clock link via the backup target clock link.

[0102] In one embodiment, the processor 601 is further configured to implement:

[0103] Obtain a clock request configuration message, and if a preset master clock configuration condition is met, perform master clock configuration according to the clock request configuration message to generate master clock configuration information;

[0104] Establishing a clock link with the first clock source device that broadcasts the clock request configuration message according to the master clock configuration information;

[0105] Perform clock synchronization with the first clock source device through the clock link

[0106] In one embodiment, the preset master clock configuration condition includes that the clock source status of the second clock source device is normal and that the second clock source device is not serving as the master clock source or slave clock source of the first clock source device that broadcasts the clock request configuration message.

[0107] In one embodiment, when the processor 601 is used to implement the establishment of a clock link with the first clock source device that broadcasts the clock request configuration message according to the master clock configuration information, it is configured to implement:

[0108] A communication connection is established with the first clock source device according to the master clock configuration information, and a clock link is established after interacting with the first clock source device through clock messages.

[0109] It should be noted that those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the device described above can refer to the corresponding process in the aforementioned clock synchronization method embodiment, and will not be repeated here.

[0110] An embodiment of the present disclosure also provides a storage medium for computer-readable storage, wherein the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of any clock synchronization method provided in the specification of the present disclosure.

[0111] The storage medium may be an internal storage unit of the device described in the aforementioned embodiment, such as a hard disk or memory of the device. The storage medium may also be an external storage device of the device, such as a plug-in hard disk, a SmartMedia Card (SMC), a Secure Digital (SD) card, a flash memory card, etc. equipped on the device.

[0112] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media generally embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0113] It should be understood that the term "and / or" used in this disclosure refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations. It should be noted that, in this article, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system that includes a series of elements includes not only those elements, but also includes other elements that are not explicitly listed, or also includes elements that are inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "including a..." does not exclude the presence of other identical elements in the process, method, article or system that includes the element.

[0114] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The above description is only a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present disclosure, and these modifications or replacements should be included in the scope of protection of the present disclosure.

Claims

1. A clock synchronization method, applied to a first clock source device, the method include: Obtaining slave clock configuration information, and generating and broadcasting a clock request configuration message according to the slave clock configuration information; Establishing clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock links of the first clock source device reach a preset number and there are no abnormal clock links, thereby obtaining multiple clock links; A target clock link is selected from the multiple clock links, and clock synchronization is performed with a second clock source device corresponding to the target clock link through the target clock link.

2. The clock synchronization method according to claim 1, in, After acquiring the slave clock configuration information, the method further includes: Determine whether the first clock source device meets the condition that the clock source state is abnormal and does not serve as a master clock device; When the first clock source device does not meet at least one of the conditions of abnormal clock source state and not serving as a master clock device, only a preset clock request configuration message is broadcasted to establish a clock link according to the broadcasted preset clock request configuration message.

3. The clock synchronization method according to claim 2, in, The clock request configuration message includes a clock request configuration flag, a domain number, a user configuration file Profile type of the IP clock, and a device IP address.

4. The clock synchronization method according to claim 1, in, The step of establishing clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock links of the first clock source device reach a preset number and there are no abnormal clock links, thereby obtaining multiple clock links, includes: When the clock link of the first clock source device does not reach a preset number, establish clock links with multiple second clock source devices that perform master clock configuration according to the clock request configuration message until the clock link of the first clock source device reaches a preset number, thereby obtaining multiple clock links; When the number of clock links of the first clock source device reaches a preset number and there are abnormal clock links, each abnormal clock link is rebuilt until there are no abnormal clock links in the clock links of the first clock source device, thereby obtaining multiple rebuilt clock links.

5. The clock synchronization method according to claim 4, in, When the clock links of the first clock source device reach a preset number and there are abnormal clock links, reconstructing each abnormal clock link until there are no abnormal clock links in the clock links of the first clock source device, thereby obtaining a plurality of reconstructed clock links, including: Deleting an abnormal clock link, and re-establishing a clock link with a second clock source device other than the second clock source device to which the deleted abnormal clock link belongs according to the clock request configuration message; When it is determined that abnormal clock links still exist, the steps of deleting an abnormal clock link and re-establishing a clock link with a second clock source device other than the second clock source device to which the deleted abnormal clock link belongs are performed, until no abnormal clock links exist, and multiple clock links are obtained.

6. The clock synchronization method according to claim 4, in, The step of establishing clock links with a plurality of second clock source devices that perform master clock configuration according to the clock request configuration message when the clock links of the first clock source device do not reach a preset number further includes: In the case where a newly added second clock source device exists in the local area network where the first clock source device is located, broadcasting the clock request configuration message; A clock link is established with the newly added second clock source device that performs master clock configuration according to the clock request configuration message.

7. The clock synchronization method according to claim 1, in, After performing clock synchronization with a second clock source device corresponding to the target clock link through the target clock link, the method further includes: When it is determined that the clock synchronization between the first clock source device and the second clock source device corresponding to the target clock link is abnormal, selecting a backup target clock link from the multiple clock links; Clock synchronization is performed with a second clock source device corresponding to the target clock link through the backup target clock link.

8. A clock synchronization method, applied to a second clock source device, the method include: Obtain a clock request configuration message, and if a preset master clock configuration condition is met, perform master clock configuration according to the clock request configuration message to generate master clock configuration information; Establishing a clock link with a first clock source device that broadcasts the clock request configuration message according to the master clock configuration information; Clock synchronization is performed with the first clock source device via the clock link.

9. The clock synchronization method according to claim 8, in, The preset master clock configuration condition includes that the clock source status of the second clock source device is normal and the second clock source device is not used as the master clock source or slave clock source of the first clock source device that broadcasts the clock request configuration message.

10. The clock synchronization method according to claim 8, in, The establishing a clock link with the first clock source device that broadcasts the clock request configuration message according to the master clock configuration information includes: A communication connection is established with the first clock source device according to the master clock configuration information, and a clock link is established after interacting with the first clock source device through clock messages.

11. A device, comprising a processor, a memory, a computer program stored in the memory and executable by the processor, and a data bus for realizing connection and communication between the processor and the memory, wherein when the computer program is executed by the processor, the steps of the clock synchronization method as described in any one of claims 1 to 10 are realized.

12. A storage medium for computer-readable storage, wherein the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of the clock synchronization method according to any one of claims 1 to 10.

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