Multi-thread concurrent management method and related apparatus

Abstract

The present application discloses a multi-thread concurrent management method and a related apparatus. The method may comprise: dividing a target global variable into multiple sub-variable regions, wherein the target global variable is used for controlling multi-thread access to target data, and each sub-variable region among the plurality of sub-variable regions comprises one or more flag bits; dividing multiple threads into multiple thread groups, wherein the multiple threads are used for applying for a permission to read the target data; authorizing a target thread in a target thread group to modify the flag bit in a target sub-variable region, wherein one thread group among the multiple thread groups has one-to-one correspondence to one sub-variable region among the multiple sub-variable regions; and if the target thread has successfully modified the flag bit, allowing the target thread to read the target data. Embodiments of the present application are applied to multi-thread concurrent CAS operation scenarios, and can improve the success rate of CAS operations.

Description

A multi-thread concurrent management method and related device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on June 15, 2023, with application number 202310717179.1 and application name “A multi-threaded concurrent management method and related device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to a multi-threaded concurrency management method and related devices. Background Art

[0003] A thread is a single, sequential flow of control within a process and serves as the smallest unit of program execution. In operating systems that introduce threading, threads are considered the basic unit of independent execution and scheduling. Threads can execute concurrently, including multiple threads within a process, threads in different processes, and threads on different cores in a multi-core computer system.

[0004] When multiple threads access the same shared data concurrently, they may need to access the same shared data. This means that the shared data may be shared by different threads. To ensure the integrity of the shared data, atomic operations, such as compare and swap (CAS), are required when multiple threads access the shared data simultaneously. This prevents concurrent threads from modifying shared data simultaneously; a thread cannot read shared data that is being modified by another thread; and multiple threads can read shared data simultaneously. CAS operations are commonly used in read-write locks or other functions that implement similar read-write functionality (such as pinbuffer / unpinbuffer). Read-write locks have two states: read lock and write lock. When a thread holds the write lock, it can read and write the shared data; other threads cannot hold the write or read lock. When a thread holds the read lock, it can read the shared data; other threads can also hold the read lock. Read-write locks typically use a variable to control their state, and CAS operations can be used to ensure consistency between multiple threads.

[0005] However, as the number of computer cores continues to increase and the computing power of single cores continues to increase, the concurrency and speed of threads are further improved. In high-concurrency scenarios, the failure rate of CAS operations performed by multiple threads concurrently is high, and CAS operation retries are severe. The overhead of CAS operations increases exponentially, becoming a bottleneck limiting computer performance.

[0006] Therefore, how to provide a method for improving the success rate of multi-threaded concurrent CAS operations is a problem that needs to be solved urgently.

[0007] Summary of the Invention

[0008] The embodiments of the present application provide a multi-threaded concurrent management method and related devices, which are applied in the scenario of multi-threaded concurrent CAS operations and can improve the success rate of CAS operations.

[0009] In a first aspect, an embodiment of the present application provides a multi-threaded concurrency management method, which may include: dividing a target global variable into multiple sub-variable areas; the target global variable is used to control multi-threaded access to target data, and each sub-variable area in the multiple sub-variable areas includes one or more flag bits; dividing multiple threads into multiple thread groups; the multiple threads are used to apply for permission to read the target data; authorizing a target thread in a target thread group to modify the flag bit in a target sub-variable area; wherein the target thread group is one of the multiple thread groups, the target sub-variable area is one of the multiple sub-variable areas, and one thread group in the multiple thread groups corresponds to one of the multiple sub-variable areas; if the target thread successfully modifies the flag bit, the target thread is allowed to read the target data.

[0010] In the prior art, when multiple threads apply to read shared data and concurrently modify the global variables used to control multi-threaded access to shared data, only one thread can successfully modify the value of the global variable at a time, resulting in a large number of modification operations failing and being retried, a low modification success rate, a large instruction overhead for modification operations, and serious waste of resources. In an embodiment of the present application, the global variable used to control multi-threaded access to shared data is divided into multiple sub-variable areas, and the multiple threads applying to read the shared data are divided into multiple thread groups, so that one thread group corresponds to one sub-variable area, and different thread groups correspond to different sub-variable areas, so that when threads in different thread groups apply to read shared data, they can obtain permission to read the shared data by modifying the value of the corresponding sub-variable area. Among them, when applying to read shared data, the threads of different thread groups modify the values ​​of different sub-variable areas independently, so that the value of each sub-variable area can be successfully modified by one thread respectively, that is, in one round of concurrent modification, multiple threads can successfully modify. Therefore, when the above method is applied to the scenario of multi-threaded concurrent CAS operations, if multiple threads apply to read shared data and concurrent CAS operations modify the values ​​of different sub-variable areas, multiple CAS operations can be successful, which improves the success rate of CAS operations and thus reduces resource waste.

[0011] In a possible implementation, the method further includes: determining the total number of threads that can currently read the target data according to the status of a flag bit in each sub-variable area.

[0012] In this embodiment of the present application, the number of threads currently able to read shared data represented by each sub-variable region is determined based on the state of the flag bit in each sub-variable region. The total number of threads currently able to read shared data is the sum of the number of threads determined in each sub-variable region. If a thread holds a read lock and another thread applies for a write lock, the lock will fail and the thread will go into hibernation. When the total number of threads holding a read lock reaches 0, the thread that previously applied for a write lock and was temporarily dormant can be awakened.

[0013] In a possible implementation, when the target thread group includes multiple threads, within one clock cycle, one thread in the target thread group is allowed to successfully modify the flag bit in the target sub-variable area.

[0014] In an embodiment of the present application, when multiple threads in the same thread group concurrently apply to read the target data, that is, when they concurrently attempt to modify the flag bit of the sub-variable area, only one thread is allowed to successfully modify it, thereby ensuring the consistency of the modification of the flag bit in the sub-variable area and avoiding confusion.

[0015] In a possible implementation, the step of authorizing a target thread in a target thread group to modify a flag bit in a target subvariable area includes:

[0016] If no thread currently exclusively owns the target data, the target thread in the target thread group is authorized to modify the flag bit in the target sub-variable area through a compare and swap (CAS) operation.

[0017] In an embodiment of the present application, when a thread modifies the flag bit of a sub-variable area, it can first determine whether the target data has been exclusively occupied. If no other thread has exclusively occupied the target data, the thread can modify the flag bit through a CAS operation to ensure the consistency of the modification and avoid confusion.

[0018] In a possible implementation, each sub-variable area further includes a control status bit, and the control status bit is used to indicate whether the target data is exclusively occupied; and the method further includes:

[0019] When the first thread of the target thread group applies for exclusive use of the target data, authorizing the first thread to modify the control status bit of each sub-variable area respectively;

[0020] If the first thread successfully modifies the control status bit, the first thread is allowed to exclusively use the target data.

[0021] In an embodiment of the present application, each sub-variable region may also include a control status bit that can be used to identify whether the target data is exclusively used by a thread. When a thread requests exclusive use of the target data, the thread must modify the control status bit in each sub-variable region. This allows other threads to determine whether the target data is exclusively used by simply checking the control status bit in the sub-variable region corresponding to their own thread group when they subsequently request to read the target data. If the thread requesting exclusive use of the target data successfully modifies the control status bit, the thread is allowed to exclusively use the target data.

[0022] In a possible implementation, the authorizing the first thread to modify the control status bit of each sub-variable area includes:

[0023] If no thread currently exclusively owns or reads the target data, the first thread is authorized to modify the control status bit of each sub-variable area through a CAS operation.

[0024] In an embodiment of the present application, during the process of modifying the control status bit of a sub-variable area by a thread, it can first be determined whether the target data has been exclusively occupied or read. If no other thread has exclusively occupied or read the target data, the thread can modify the control status bit of each sub-variable area through a CAS operation to ensure the consistency of the modification and avoid confusion when multiple threads apply for exclusive use of the target data at the same time.

[0025] In a possible implementation, the global variable is a lock state variable, the flag bit is a read lock count bit, and threads in the multiple thread groups modify the flag bit in the sub-variable area to add a read lock or an unread lock.

[0026] In an embodiment of the present application, the method for controlling multi-threaded access to shared data can be a read-write lock. The global variable can be a lock state variable, and the flag bit can be a read lock count bit. The process of multiple threads applying to read the target data and modifying the flag bit is equivalent to an encryption and unlock operation. When the lock state variable is partitioned and threads are grouped, and multiple threads can modify the read lock count bit of the partition in parallel, multiple threads can successfully modify the read lock count bit, thereby improving the success rate of encryption and unlock.

[0027] In a possible implementation, the global variable is a lock state variable, the control state bit is a write lock state bit, and threads in the multiple thread groups modify the control state bit in the sub-variable area to add a write lock or release a write lock.

[0028] In an embodiment of the present application, the method for controlling multi-threaded access to shared data can be a read-write lock. In this case, the global variable can be a lock state variable, and the control state bit can be a write lock state bit. The process of multiple threads applying for exclusive access to the target data and modifying the write lock state bit is equivalent to adding and removing the write lock. When a thread applies for exclusive access to the target data, it needs to modify the write lock state bit in each sub-variable area. When other threads subsequently apply to read the target data, they only need to determine whether the target data is exclusively owned, that is, whether any thread holds the write lock, by checking the write lock state bit in the sub-variable area corresponding to their own thread group.

[0029] In a second aspect, an embodiment of the present application provides a multi-threaded concurrency management device, which may include: a first processing unit, configured to divide a target global variable into a plurality of sub-variable regions; the target global variable is used to control multi-threaded access to target data, each of the plurality of sub-variable regions including one or more flag bits;

[0030] A second processing unit is configured to divide the plurality of threads into a plurality of thread groups; the plurality of threads are configured to apply for permission to read the target data;

[0031] Authorizing a target thread in a target thread group to modify a flag bit in a target sub-variable region; wherein the target thread group is one of the multiple thread groups, the target sub-variable region is one of the multiple sub-variable regions, and one thread group in the multiple thread groups corresponds to one of the multiple sub-variable regions;

[0032] The third processing unit is configured to allow the target thread to read the target data if the target thread successfully modifies the flag bit.

[0033] In a possible implementation, the apparatus further includes:

[0034] A determining unit is configured to determine the total number of threads that can currently read the target data according to the status of the flag bit in each sub-variable area.

[0035] In a possible implementation, when the target thread group includes multiple threads, within one clock cycle, one thread in the target thread group is allowed to successfully modify the flag bit in the target sub-variable area.

[0036] In a possible implementation, the second processing unit is specifically configured to:

[0037] If no thread currently exclusively owns the target data, the target thread in the target thread group is authorized to modify the flag bit in the target sub-variable area through a compare and swap (CAS) operation.

[0038] In one possible implementation, each sub-variable region further includes a control status bit, the control status bit being used to indicate whether the target data is exclusively occupied; the second processing unit is further configured to authorize the first thread of the target thread group to modify the control status bit of each sub-variable region when the first thread applies for exclusive use of the target data;

[0039] The third processing unit is further configured to allow the first thread to exclusively use the target data if the first thread successfully modifies the control status bit.

[0040] In a possible implementation, the second processing unit is specifically configured to:

[0041] If no thread currently exclusively owns or reads the target data, the first thread is authorized to modify the control status bit of each sub-variable area through a CAS operation.

[0042] In a possible implementation, the global variable is a lock state variable, the flag bit is a read lock count bit, and threads in the multiple thread groups modify the flag bit in the sub-variable area to add a read lock or an unread lock.

[0043] In a possible implementation, the global variable is a lock state variable, the control state bit is a write lock state bit, and threads in the multiple thread groups modify the control state bit in the sub-variable area to add a write lock or release a write lock.

[0044] In a third aspect, an embodiment of the present application provides a multi-threaded concurrency management device, comprising a processor configured to support the device in implementing the corresponding functions of the multi-threaded concurrency management method provided in the first aspect. The device may also include a memory coupled to the processor and storing program instructions and data necessary for the device. The device may also include an interface circuit for communicating with other devices, other equipment, or a communication network.

[0045] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium for storing computer software instructions used by a device apparatus for implementing a multi-threaded concurrent management method provided by one or more of the second aspects above, which includes a program designed for executing the above aspects.

[0046] In the fifth aspect, an embodiment of the present application provides a computer program, which includes instructions. When the computer program is executed by a computer, it enables the computer to execute a process executed by an apparatus for implementing a multi-threaded concurrent management method provided by one or more of the above-mentioned second aspects.

[0047] In a sixth aspect, an embodiment of the present application provides an electronic device, comprising a processor configured to support the electronic device in implementing the corresponding functions of the multi-threaded concurrency management method provided in the first aspect. The electronic device may further include a memory coupled to the processor and storing program instructions and data necessary for the electronic device. The electronic device may further include a communication interface for enabling the electronic device to communicate with other devices or a communication network.

[0048] In a seventh aspect, an embodiment of the present application provides a chip system, which includes a processor for supporting a device to implement the functions involved in the first aspect above, for example, generating or processing the information involved in the multi-threaded concurrency management method above. In one possible design, the chip system also includes a memory, which is used to store program instructions and data necessary for the device. The chip system can be composed of a chip, or it can include a chip and other discrete devices.

[0049] In an eighth aspect, an embodiment of the present application provides a server comprising a communication interface, a memory, and a processor; the communication interface, the memory, and the processor are coupled, the communication interface is used for the server to communicate with other devices or a communication network, the memory is used to store computer program code, and the computer program code comprises computer instructions. When the processor reads the computer instructions from the memory, the server executes any possible implementation method as in the first aspect.

[0050] In the ninth aspect, an embodiment of the present application provides a vehicle-mounted device, including a communication interface, a memory and a processor; the communication interface, the memory and the processor are coupled, the communication interface is used for the vehicle-mounted device to communicate with other devices or a communication network, the memory is used to store computer program code, and the computer program code includes computer instructions. When the processor reads the computer instructions from the memory, the vehicle-mounted device executes any possible implementation method as in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0052] FIG1 is a schematic diagram of the structure of a lock state variable;

[0053] FIG2 is a flow chart of a read-write lock;

[0054] FIG3 is a schematic diagram of the result of a multi-threaded CAS operation performed simultaneously;

[0055] FIG4 is a schematic diagram of a system architecture of a multi-threaded concurrent management method application provided in an embodiment of the present application;

[0056] FIG5 is a flow chart of a multi-threaded concurrency management method provided in an embodiment of the present application;

[0057] FIG6 is a schematic diagram of the structure of a lock state variable partition provided in an embodiment of the present application;

[0058] FIG7 is a schematic diagram showing the result of a multi-threaded group performing a CAS operation simultaneously according to an embodiment of the present application;

[0059] FIG8 is a perf flame graph of performance analysis provided by an embodiment of the present application;

[0060] FIG9 is another performance analysis perf flame graph provided in an embodiment of the present application;

[0061] FIG10 is another performance analysis perf flame graph provided in an embodiment of the present application;

[0062] FIG11 is a schematic structural diagram of a multi-threaded concurrency management device provided in an embodiment of the present application;

[0063] FIG12 is a schematic structural diagram of another multi-threaded concurrency management device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0064] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0065] The terms "first," "second," "third," and "fourth," etc., in the specification and claims of this application and the accompanying drawings are used to distinguish different objects, not to describe a specific order. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0066] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in one or more embodiments of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0067] As used in this specification, the terms "component," "module," "system," and the like are used to refer to computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of illustration, both an application running on a computing device and a computing device can be a component. One or more components can reside in a process and / or an execution thread, and a component can be located on a computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component across a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0068] First, some terms in this application are explained to facilitate understanding by those skilled in the art.

[0069] (1) Atomic operation refers to an uninterruptible operation or a series of operations, that is, an operation that will not be interrupted by the thread scheduling mechanism, and there will be no context switch during operation. Atomic operations mainly include simple addition and subtraction operations, compare and exchange (CAS) operations, and assignment operations. When multiple threads access shared data at the same time, executing CAS atomic operations to modify the variables of read-write locks or other functions that implement similar read-write functions can ensure the atomicity of the variable value modification in multi-threaded concurrent scenarios to avoid confusion. In the embodiment of the present application, the variable is divided into multiple regions, and multiple threads are grouped. When a thread in the target group reads shared data, the count value of the corresponding target region in the variable can be modified through the CAS operation. That is, by dividing the CAS operations of concurrent threads into multiple regions, the concurrency conflicts of the CAS operations are reduced, thereby improving the success rate of the CAS operations.

[0070] (2) Read-write lock, including read lock and write lock. Among them, only one thread can occupy the read-write lock in the write lock state at a time, but multiple threads can occupy the read-write lock in the read lock state at the same time. Therefore, when the read-write lock is in the write lock state, all threads attempting to lock this lock (including read lock and write lock) will be blocked before the lock is unlocked. When the read-write lock is in the read lock state, other threads attempting to add read locks can obtain access rights, but if a thread wants to add write locks, it must wait until all threads release the locks. Read-write locks generally use a variable for state control, and consistency can be ensured between multiple threads through CAS operations. In the embodiment of the present application, the variable used to control the read-write lock state can be partitioned and multiple threads performing concurrent CAS operations can be grouped. When a thread in the target group applies for a read lock (i.e., when reading shared data), the count value of the corresponding target area in the variable can be modified through the CAS operation, and the other areas are used to process the concurrent CAS operations of threads in other groups, thereby improving the success rate of CAS.

[0071] (3) The compare and swap (CAS) operation will pass in three values: the address of the target variable to be modified, the original value of the variable, and the new value to be modified. When performing a CAS operation, memory access is exclusively controlled in certain units (usually within the range of a cache line). If the value of the target variable in memory (the target variable address) is equal to the "original value of the variable" passed in by the CAS operation, the target variable in memory is changed to the "new value to be modified" passed in by the CAS operation; if the value of the target variable in memory is inconsistent with the "original value of the variable" passed in by the CAS operation, the modification fails and the current value of the target variable is transmitted. This ensures the atomicity of target variable value modifications in multi-threaded concurrent scenarios.

[0072] (4) Concurrency means that multiple threads can run part of the logic within a period of time. In this case, the current thread can start executing regardless of whether the previous thread has completed, without having to wait for the previous thread to complete.

[0073] (5) In this application, "plurality" means two or more. "and / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0074] First, we analyze and propose the technical problems that this application aims to solve. In the prior art, CAS operations are commonly used in read-write locks or other functions that implement similar read-write functions (such as pinbuffer / unpinbuffer), as shown in the following solutions 1 and 2:

[0075] Solution 1: Read-write locks are commonly implemented using a lock status variable. See Figure 1, which shows the structure of a lock status variable. Taking the Linux rwlock as an example, the variable shown in Figure 1 indicates that no thread currently holds the write lock, while three threads hold the read lock. When the variable is 0, the read-write lock is idle, meaning no thread holds the lock (read or write). When the highest bit is 1, it indicates that a thread holds the write lock. When the thread releases the write lock, the highest bit is set to 0. Each time a thread acquires the read lock, the variable is incremented by 1. Each time a thread releases the read lock (i.e., unread the lock), the variable is decremented by 1. To ensure consistency in variable modifications across multiple threads, threads synchronize using CAS instructions to ensure that only one thread can modify the variable at a time. Of course, the write lock status bit does not necessarily have to be in the highest bit, nor do all bits in the variable need to be used for read-write lock counting. Several bits can be used for other customized identification purposes.

[0076] This solution has the following disadvantages:

[0077] When a large number of threads concurrently access a shared resource for read-only access, a large number of read locks are acquired concurrently, resulting in a high failure rate for read lock acquisition. See Figure 2, which illustrates a read-write lock acquisition process. In Solution 1, when a thread applies for a write lock (as in Method 1 in Figure 2), the lock state is first checked to determine whether it is already a read lock or a write lock. If it is already locked, the write lock application fails and a new application is required (either immediately or by waiting for another release process to wake it up). If it is not locked, the variable write lock state is set to 1, and an atomic CAS operation is performed on the variable. If the modification succeeds, the write lock is acquired successfully. If the modification fails, it indicates that another thread has already locked and modified the variable value, resulting in a write lock acquisition failure and the thread enters a retry, wait, or other process. When a thread applies for a read lock (as in Method 2 in Figure 2), the lock state is first checked to determine whether it is already a write lock. If a write lock has been added, the read lock application fails and needs to be reapplied (you can retry immediately or wait to be awakened by other release processes); if a write lock has not been added, the variable read lock count bit needs to be increased by 1, and then the CAS atomic operation is performed on the variable. If the modification is successful, the read lock is successfully added; if the modification fails, it means that other threads have modified the variable value during this period, that is, when multiple threads concurrently add read locks, other threads successfully add read locks, causing this thread to fail to add read locks and enter retry or other processes. Under normal circumstances, the read lock process will be retried immediately based on the latest value of the current lock status variable.

[0078] As can be seen, when two threads simultaneously attempt to acquire a read lock, the CAS operation of one thread will fail. After checking the latest lock state and finding that the lock is not write-locked, the thread will immediately attempt to acquire a read lock again. Furthermore, when a large number of threads concurrently access a shared resource for read-only access, a large number of read locks will be acquired concurrently, increasing the number of read lock acquisition failures and the failure rate. See Figure 3, which illustrates the results of simultaneous CAS operations by multiple threads. Taking four threads concurrently acquiring read locks as an example, the current value is read from the memory storing the lock state variable, and the old and new values ​​are the input values ​​for the CAS operation. In four rounds of concurrent CAS operations, there are four valid CAS operations (i.e., OK) and six invalid CAS operations (i.e., failed). This means that the CAS operation succeeded four times and failed six times (three in the first round, two in the second round, and one in the third round). Each CAS operation is quite expensive and requires synchronized memory access across multiple cores and shards, which consumes memory bandwidth and computing resources.

[0079] Solution 2: Other functions that implement similar read and write functions (such as pinbuffer / unpinbuffer) control the sharing, exclusivity, and other status identification of data pages. Among them, sharing uses a sharing count, which is similar to adding a read lock and unreading a read lock. Pinbuffer can be simply understood as adding a read lock, and unpinbuffer can be simply understood as an unreading lock. Taking the Kunpeng 2P+openGauss (open source Gauss) scenario as an example, when multiple threads perform high-concurrency queries on the same table (data that can be shared), each query requires read-only access to the index root directory. Similar to the high concurrency of CAS operations with read locks, there are also problems like those in Solution 1. The CAS operation failure rate is high, the number of CAS operation retries is high, and the CAS instructions account for 51% of the entire server CPU overhead.

[0080] To this end, the present application proposes a multi-threaded concurrent management method and related devices, which are applied to the scenario of multi-threaded concurrent CAS operations and can improve the success rate of CAS operations. Specifically, the global variables of shared data are divided into multiple areas, and the multiple threads applying to read the shared data are divided into multiple thread groups. One thread group corresponds to one variable area, and different thread groups correspond to different variable areas, so that when threads in different thread groups apply to read shared data, they can obtain the permission to read the shared data by modifying the value of the corresponding variable area. Among them, when applying to read shared data, the modification of the values ​​of different variable areas between threads in different thread groups is independent, so that the value of each variable area can be successfully modified separately. Therefore, when multiple threads apply to read shared data and concurrent CAS operations modify the values ​​of different variable areas, multiple CAS operations can be successful, which improves the success rate of CAS operations.

[0081] To better understand the multi-threaded concurrency management method provided in the embodiments of the present application, the system architecture and / or application scenarios of the multi-threaded concurrency management method provided in the embodiments of the present application are described below. It is understood that the system architecture and application scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application.

[0082] The system architecture applicable to the multi-threaded concurrent management method provided by the embodiment of the present application can be seen in Figure 4. Figure 4 is a schematic diagram of the system architecture of a multi-threaded concurrent management method application provided by the embodiment of the present application, which system architecture may include one or more central processing units (CPUs), one or more graphics processing units (GPUs), or one or more system-on-chips (SOCs), and includes a memory. Wherein, the basic unit for the processor to run independently and schedule independently is a thread. For example, the system architecture shown in Figure 4 includes multiple CPUs (such as CPU1-CPU5), wherein any one CPU (such as CPU1) can be used to execute the multi-threaded concurrent management method provided by the embodiment of the present application, first dividing the global variable for controlling multi-threaded access to shared data into multiple sub-variable areas, and grouping multiple threads requesting to read shared data in multiple CPUs. When multiple CPU concurrent threads read shared data in a memory, threads of different thread groups can be authorized to modify the flag bits in different sub-variable areas. If the thread modification flag bit is successful, CPU1 can allow it to read the shared data in the memory. For example, when CPU1 runs independently and schedules thread 1 to apply for reading shared data in the memory (taking the application for a read lock as an example), thread 1 can only modify the flag bit of the first partition of the global variable (such as the lock state variable). After the modification is successful, thread 1 can read the shared data; when CPU2 runs independently and schedules thread 2 to apply for reading the shared data, thread 2 can only modify the flag bit of the second partition of the global variable. After the modification is successful, thread 2 can read the shared data. Similarly, when CPU3 runs or schedules thread 3 and CPU4 runs or schedules thread 4 to apply for reading the shared data, thread 3 and thread 4 can modify the flag bits of the third partition and the fourth partition respectively. After the modification is successful, thread 3 and thread 4 can read the shared data. Among them, the length of the global variable can be 1 byte to 16 bytes, or even longer or shorter. The range can be different in different architecture instruction sets. Figure 4 only takes the global variable length equal to the cache line length as an example, which should not constitute a limitation of this application. It should be noted that each partition of the global variable can also include a control status bit (such as a write lock status bit). When a CPU runs or schedules a thread to apply for exclusive use of the shared data, the control status bit of each partition can be modified. For example, when CPU5 runs or schedules thread 5 to exclusively use the shared data in the memory in Figure 4, the control status bit of each of the four partitions can be modified. After the modification is successful, thread 5 can perform operations such as reading and writing on the shared data.

[0083] It should be noted that the embodiments of the present application can be applied to various computer system architectures. The architecture in FIG4 above is only an exemplary implementation in the embodiments of the present application. The architecture applicable to the embodiments of the present application includes but is not limited to the above architecture. It should be understood that the architecture of the computer can have more or fewer units / modules than shown in the figure, can combine two or more units / modules, or can have different unit / module configurations. Various units / modules can be implemented in hardware, software, or a combination of hardware and software including one or more signal processing and / or application-specific integrated circuits.

[0084] It is understandable that the multi-threaded concurrency management method provided in the embodiment of the present application can be executed by an electronic device. An electronic device refers to a device that can be abstracted as a computer system, wherein an electronic device that supports the above-mentioned multi-threaded concurrency management function can also be called a multi-threaded concurrency management device. The multi-threaded concurrency management device can be the entire device of the electronic device, such as: a server, a vehicle-mounted computer or a terminal device, and the terminal device can be a smart wearable device, a smart phone, a tablet computer, a laptop computer, a desktop computer, etc.; it can also be a system / device composed of multiple entire devices; it can also be a partial device in the electronic device, such as: a chip related to the multi-threaded concurrency management function, such as a processor, a system chip (system on a chip, SoC), etc., which is not specifically limited in the embodiment of the present application. Among them, the system chip is also called a system on chip. It is understandable that the above-mentioned multi-threaded concurrency management method provided in the embodiment of the present application can also be applied to the operating system, database, application software, middleware or underlying software of the above-mentioned electronic device.

[0085] For ease of understanding, the technical solution provided in this application will be described below with reference to more drawings.

[0086] In this application, unless otherwise specified, the same or similar parts between the various embodiments or implementation methods can refer to each other. In the various embodiments in this application, and the various implementation methods / implementation methods / implementation methods in each embodiment, if there is no special explanation and logical conflict, the terms and / or descriptions between different embodiments and the various implementation methods / implementation methods / implementation methods in each embodiment are consistent and can be referenced to each other. The technical features in different embodiments and the various implementation methods / implementation methods / implementation methods in each embodiment can be combined to form new embodiments, implementation methods, implementation methods, or implementation methods according to their inherent logical relationships. The implementation methods of this application described below do not constitute a limitation on the scope of protection of this application.

[0087] 5 , which is a flow chart of a multi-threaded concurrency management method provided by an embodiment of the present application, including but not limited to the following steps:

[0088] S501: Divide the target global variable into multiple sub-variable areas.

[0089] Specifically, the target global variable is used to control multi-threaded access to target data, which is a resource that can be shared by multiple threads and is generally referred to as shared data or shared resources. The target data can be specific data, such as a table that can be shared and queried; the target data can also refer to a critical section, that is, a program fragment that accesses a shared resource (such as a shared device, shared memory, etc.). To ensure the integrity of the target data, it is necessary to set a global variable (i.e., a target global variable) for controlling multi-threaded access to the target data. After dividing this global variable into regions, multiple sub-variable regions are obtained, each of which can include one or more flag bits. Subsequently, threads in different thread groups can modify the flag bits of different sub-variable regions. Taking the global variable as a lock state variable as an example, the flag bit can be called a read lock count bit. For example, see Figure 6, Figure 6 shows a structural diagram of a lock state variable partition provided by an embodiment of the present application, wherein the length of the lock state variable is 8 bytes as an example. The lock state variable is divided into four 2-byte regions (including partition 1, partition 2, partition 3, and partition 4) in the figure, and each partition can include one or more read lock count bits. Optionally, when dividing the global variable into regions, the regions can be divided equally (as shown in FIG6 ) or unequally. For example, the regions can be divided into four sub-variable regions with lengths of 1 byte, 1 byte, 2 bytes, and 4 bytes, respectively. This is not specifically limited here. Optionally, the lengths of the sub-variable regions can be divided according to the number of threads in different thread groups. When the number of threads in a thread group is large, the length of the sub-variable region corresponding to the thread group can be longer; conversely, when the number of threads in a thread group is small, the length of the sub-variable region corresponding to the thread group can be shorter.

[0090] It should be noted that, in order to ensure the consistency of the modification of the subvariable area flag bit, the thread generally modifies the flag bit through an atomic operation (such as a CAS operation). Because the minimum unit that the atomic operation can currently operate is 1 byte, then the minimum length of a single subvariable area in the global variable should be 1 byte; the maximum length of the entire global variable supports the maximum number of bytes (such as a cache line (cacheline)) that the computer can perform atomic operations on. Understandably, with the development of computer technology, if the minimum unit and maximum unit that can perform atomic operations change, in the embodiment of the present application, the length range that the global variable and the subvariable area can support can also change accordingly, that is, the minimum length of the above-mentioned current single subvariable area is 1 byte, and the maximum length of the entire global variable is a cache line, which should not constitute a limitation on the embodiment of the present application.

[0091] S502: Divide the multiple threads into multiple thread groups.

[0092] S503: Authorize the target thread in the target thread group to modify the flag bit in the target subvariable area.

[0093] Specifically, the multiple threads applying to read the target data can be grouped so that the threads in the multiple thread groups can modify the mark bits in the above-mentioned multiple sub-variable areas respectively, and the threads in the target thread group modify the mark bits of the target sub-variable area. Among them, one thread group corresponds to one sub-variable area, and different thread groups correspond to different sub-variable areas, that is to say, one thread group in the multiple thread groups corresponds to one sub-variable area in the multiple sub-variable areas. Exemplarily, the above-mentioned multiple threads may need to read the target data in the process of executing a certain task, so they apply for permission to read the target data. In other words, the above-mentioned multiple threads can not only be used to apply for permission to read the target data, but can also be used to complete other tasks.

[0094] Optionally, when the target thread group among the multiple thread groups includes multiple threads, within one clock cycle, only one thread in the target thread group is allowed to successfully modify the flag bit in the sub-variable area corresponding to the target thread group (i.e., the target sub-variable area). In other words, when multiple threads in the same thread group concurrently modify the flag bit of the sub-variable area corresponding to the thread group, only one thread can successfully modify the flag bit, thereby ensuring the consistency of the modification of the flag bit of the sub-variable area and avoiding confusion. Other threads in the same thread group that fail to modify the flag bit can try again to modify the flag bit of the sub-variable area corresponding to the thread group.

[0095] Optionally, the grouping of threads can be based on thread IDs, for example, threads 0-9 belong to group 1, threads 10-19 belong to group 2, threads 20-29 belong to group 3, etc.; the grouping of threads can also be based on identifying the group of the threads when they are created, for example, the threads created by CPU1 are identified as group 1, the threads created by CPU2 are identified as group 2, and the threads created by CPU3 are identified as group 3, etc.

[0096] S504: If the target thread successfully modifies the flag bit, the target thread is allowed to read the target data.

[0097] Specifically, if a thread in the plurality of thread groups successfully modifies the mark bit when attempting to modify the mark bit, a request to read the target data may be applied for through this thread, that is, this thread is allowed to read the target data.

[0098] For ease of understanding, referring to the example of dividing the global variable (lock state variable) into 4 sub-variable areas in FIG6 above, when grouping multiple threads, they can be divided into 4 groups (including Group 1, Group 2, Group 3 and Group 4). For example, the threads in Group 1 can modify the mark bit (read lock count bit) in Partition 1, the threads in Group 2 can modify the mark bit in Partition 2, and so on. In other words, when the thread in Group 1 applies to read the target data, it is equivalent to applying for a read lock. The thread can judge the lock status of the 2 bytes corresponding to the thread group (for example, Partition 1) based on the group of its own thread group, determine whether no thread holds a write lock, and then modify the read lock count bit of the 2 bytes (such as an atomic addition operation). If the modification is successful, the thread holds the read lock. Corresponding to the read request is the release. When the thread in the first group wants to release the target data, it is equivalent to applying for a read lock. The thread modifies the read lock count bit of the 2 bytes (partition 1) corresponding to the thread group according to the group of its thread group (atomic minus 1 operation). If the modification is successful, the thread releases the read lock.

[0099] In a possible implementation, each of the above sub-variable areas may further include a control status bit, which is used to indicate whether the target data is exclusively owned. Still taking the global variable as the lock state variable as an example, the control status bit is a write lock status bit, which is used to indicate whether a thread holds a write lock. For example, the structure of the lock state variable partition shown in FIG6 above is shown. In addition to the read lock count bit, each partition also includes a write lock status bit. In addition to steps S501-S504, the above method may further include steps S505 and S506, wherein,

[0100] S505 : When a first thread of a target thread group among the multiple thread groups applies for exclusive use of the target data, the first thread is authorized to modify the control status bit of each sub-variable area respectively.

[0101] S506: If the first thread successfully modifies the control status bit, the first thread is allowed to exclusively use the target data.

[0102] Specifically, if a thread in the above-mentioned multiple thread groups applies for exclusive use of the above-mentioned target data, the thread needs to modify the control status bit in each sub-variable area. If the thread successfully modifies the control status bit, the thread can apply for exclusive use of the above-mentioned target data through this thread, that is, the thread is allowed to exclusively use the above-mentioned target data. Still taking the global variable shown in Figure 6 as the lock state variable, the lock state variable length is 8 bytes, and the four sub-variable areas are all 2 bytes as an example, the control status bit is the write lock status bit. When a thread in the above-mentioned multiple thread groups applies for exclusive use of the target data, it is equivalent to applying for a write lock. The thread needs to perform a lock status check on the 8 bytes to determine whether no thread holds a write lock or a read lock. Then, the write lock status bit in each 2-byte partition is modified (such as an atomic addition operation). If the modification is successful, the thread holds the write lock. Corresponding to applying for exclusive control is releasing exclusive control. When a thread wants to release exclusive control of the target data, it is equivalent to applying for a write lock. The thread modifies the write lock status bit in each 2-byte partition (such as an atomic minus 1 operation). If the modification is successful, the thread releases the write lock.

[0103] In a possible implementation, the above method may further include step S507 in addition to steps S501 to S506, wherein:

[0104] S507: Determine the total number of threads that can currently read the target data according to the status of the flag bit in each sub-variable area.

[0105] Specifically, when it is necessary to count the total number of threads currently allowed to read the target data, this can be determined based on the flag bit status of each sub-variable area. Still taking the global variable shown in FIG6 as the lock state variable, the lock state variable length is 8 bytes, and the four sub-variable areas are all 2 bytes as an example, when it is necessary to determine the total number of threads currently holding read locks, the number of threads holding read locks indicated by the read lock count bits in each sub-variable area can be added together to obtain the total number of threads holding read locks. For example, the read lock count bits of partition 1 indicate that 3 threads hold read locks, partition 2 indicates that 5 threads hold read locks, partition 3 indicates that 2 threads hold read locks, and partition 4 indicates that 2 threads hold read locks, then the total number of threads holding read locks is 12.

[0106] Optionally, in some scenarios, such as when the read-write lock is in the read lock state and another thread attempts to apply for a write lock, the write lock request will fail, and the thread may temporarily sleep. After the thread applies for the write lock, the read-write lock will typically block subsequent read lock requests to prevent the read lock state from being occupied for a long time, causing the thread requesting the write lock to wait for a long time. When the last thread holding the read lock releases the read lock, that is, when it is determined that the total number of threads that can currently read the target data is 0, the thread that was previously dormant due to the failed write lock request can be awakened. Then, through this thread's write lock request, it can be given the write lock, allowing it to perform read and write operations on the target data.

[0107] It should be noted that in low concurrency scenarios, that is, when the read-lock conflict is not obvious, the performance change of the computer system by the embodiment of the present application may not be significant. However, in high concurrency scenarios, that is, when the read-lock conflict is obvious between multiple threads, the more sub-variable areas that can be independently modified during the read-lock operation, the more threads that can successfully complete the read-lock operation, and the more obvious the performance benefits obtained by the computer system. See Figure 7, which is a schematic diagram of the result of a multi-threaded grouping and simultaneous CAS operation provided by the embodiment of the present application. Taking 4 threads adding read locks at the same time, the 4 threads are divided into 2 groups, each with 2 threads as an example, the present value is read in the memory storing the lock state variable, and the old value and the new value are the incoming values ​​of the CAS operation. In the two rounds of concurrent CAS operations, the valid CAS operation is 4 times, and the invalid CAS operation is 2 times, which is reduced from 6 times in the example of Figure 3 to 2 times, and the number of concurrent rounds is also reduced from 4 rounds to 2 rounds. When threads 1 and 2 in group 1 simultaneously acquire a read lock (the first round of concurrency), only one thread (for example, thread 1) can successfully modify the flag bit of the subvariable area corresponding to the thread group. Thread 2 can then immediately retry the read lock process (round 2) based on the latest value of the subvariable area, successfully modify the flag bit of the subvariable area, and obtain the read lock. Similarly, when threads 3 and 4 in group 2 simultaneously acquire a read lock (the first round of concurrency), one thread (for example, thread 3) successfully modifies the flag bit and obtains the read lock. The other thread can then successfully modify the flag bit in round 2 and also obtain the read lock.

[0108] Furthermore, if the four threads are divided into four groups, with one thread in each group, that is, the four threads are in different thread groups, when these four threads concurrently apply for read locks, they can modify the mark bit of the sub-variable area corresponding to each thread group. At this time, from the perspective of the sub-variable area, only one thread applies to modify the mark bit. Therefore, these four threads can successfully modify the mark bit of the sub-variable area in one round of concurrency, that is, the number of modification operation failures is 0.

[0109] When the embodiment of the present application is applied to other scenarios that implement similar read and write functions (such as pinbuffer / unpinbuffer), the performance of the computer system can also be greatly improved. The pinbuffer / unpinbuffer function implements functions similar to read and write, and can share, exclusively, and control other state identifications of data pages. Among them, sharing adopts a shared count (similar to adding and unreading locks), and each time a thread queries a data page, it needs to add a read lock to the index root directory page. In the Kunpeng 2P+openGauss (open source Gauss) scenario, the concurrent access volume of the same page is extremely large. In the case where the multi-threaded concurrency management method of the embodiment of the present application is not adopted, the performance of the computer system can be seen in Figure 8. Figure 8 is a performance analysis perf flame graph provided by the embodiment of the present application, wherein, when the query performance of openGauss is 1.1 million queries per second (QPS), the atomic operation instruction overhead of adding and unreading locks has exceeded 50%, and the CPU is fully loaded.

[0110] When the multi-threaded concurrency management method of the embodiment of the present application is adopted, two sub-variable areas are divided, two thread groups are divided, and the flag bits of the sub-variable areas are modified in two ways, the performance of the computer system can be seen in Figure 9. Figure 9 is another performance analysis perf flame graph provided by the embodiment of the present application, in which the query performance of openGauss is improved to 1.2 million QPS, and the atomic operation instruction overhead of unlocking and unlocking has been reduced to 39.5%.

[0111] Furthermore, the performance of the computer system, when the sub-variable regions are divided into six sub-variable regions, divided into six thread groups, and the flag bits of the sub-variable regions are modified in six ways, can be seen in Figure 10. Figure 10 is another performance analysis perf flame graph provided by an embodiment of the present application. In it, the query performance of openGauss is improved to 1.56 million QPS, and the atomic operation instruction overhead of unlocking and decoding has been reduced to 14%. Compared with the performance shown in Figure 8, the query performance of openGauss is improved by 41%, and the unlocking and decoding performance is improved by 5 times.

[0112] In summary, the present application proposes a multi-threaded concurrent management method, which divides the global variables used to control multi-threaded access to shared data into multiple areas, divides the multiple threads applying to read the shared data into multiple thread groups, and makes one thread group correspond to one variable area, and different thread groups correspond to different variable areas, so that when threads in different thread groups apply to read shared data, they can obtain the permission to read the shared data by modifying the value of the corresponding variable area. Among them, when applying to read shared data, the modification of the values ​​of different variable areas between threads in different thread groups is independent, so that the value of each variable area can be modified successfully separately, that is, in one round of concurrent modification, multiple threads can modify successfully. Therefore, when the above method is applied to the scenario of multi-threaded concurrent CAS operations, if multiple threads apply to read shared data, and concurrent CAS operations modify the values ​​of different variable areas, multiple CAS operations can be successful, thereby improving the success rate of CAS operations.

[0113] The above describes the method of the embodiment of the present application in detail. The following briefly describes the relevant devices of the embodiment of the present application.

[0114] Please refer to Figure 11, which is a schematic diagram of the structure of a multi-threaded concurrency management device provided in an embodiment of the present application. The device 110 may include a first processing unit 1101, a second processing unit 1102, and a third processing unit 1103, and may also include a determination unit 1104. The detailed description of each unit is as follows:

[0115] A first processing unit 1101 is configured to divide a target global variable into a plurality of sub-variable regions; the target global variable is used to control multi-threaded access to target data, and each of the plurality of sub-variable regions includes one or more flag bits;

[0116] The second processing unit 1102 is configured to divide a plurality of threads into a plurality of thread groups; the plurality of threads are configured to apply for permission to read the target data;

[0117] Authorizing a target thread in a target thread group to modify a flag bit in a target sub-variable region; wherein the target thread group is one of the multiple thread groups, the target sub-variable region is one of the multiple sub-variable regions, and one thread group in the multiple thread groups corresponds to one of the multiple sub-variable regions;

[0118] The third processing unit 1103 is configured to allow the target thread to read the target data if the target thread successfully modifies the flag bit.

[0119] In a possible implementation, the apparatus further includes:

[0120] The determining unit 1104 is configured to determine the total number of threads that can currently read the target data according to the status of the flag bit in each sub-variable area.

[0121] In a possible implementation, when a target thread group among the multiple thread groups includes multiple threads, within one clock cycle, one thread in the target thread group is allowed to successfully modify a flag bit in a target sub-variable area corresponding to the target thread group.

[0122] In a possible implementation, the second processing unit 1102 is specifically configured to:

[0123] If no thread currently exclusively owns the target data, the target thread in the target thread group is authorized to modify the flag bit in the target sub-variable area through a compare and swap (CAS) operation.

[0124] In one possible implementation, each sub-variable region further includes a control status bit, where the control status bit is used to indicate whether the target data is exclusively occupied. The second processing unit 1102 is further used to authorize a first thread of a target thread group among the multiple thread groups to modify the control status bit of each sub-variable region when the first thread applies for exclusive use of the target data.

[0125] The third processing unit 1103 is further configured to allow the first thread to exclusively use the target data if the first thread successfully modifies the control status bit.

[0126] In a possible implementation, the second processing unit 1102 is specifically configured to:

[0127] If no thread currently exclusively owns or reads the target data, the first thread is authorized to modify the control status bit of each sub-variable area through a CAS operation.

[0128] In a possible implementation, the global variable is a lock state variable, the flag bit is a read lock count bit, and threads in the multiple thread groups modify the flag bit in the sub-variable area to add a read lock or an unread lock.

[0129] In a possible implementation, the global variable is a lock state variable, the control state bit is a write lock state bit, and threads in the multiple thread groups modify the control state bit in the sub-variable area to add a write lock or release a write lock.

[0130] It should be noted that the functions of each functional unit / module in the multi-threaded concurrency management device described in the embodiments of the present application can be found in the relevant description in the above method embodiments and will not be repeated here.

[0131] As shown in FIG12 , FIG12 is a schematic diagram of the structure of another multi-threaded concurrency management device provided in an embodiment of the present application. The device 120 includes at least one processor 1201, at least one memory 1202, and at least one communication interface 1203. In addition, the device may also include common components such as an antenna, which will not be described in detail here.

[0132] The processor 1201 may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the above program.

[0133] The communication interface 1203 is used to communicate with other devices or communication networks, such as Ethernet, radio access network (RAN), core network, wireless local area network (WLAN), etc.

[0134] The memory 1202 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory may exist independently and be connected to the processor via a bus. The memory may also be integrated with the processor.

[0135] The memory 1202 is used to store application code for executing the multi-threaded concurrent management method described above, and the execution is controlled by the processor 1201. The processor 1201 is used to execute the application code stored in the memory 1202.

[0136] The code stored in the memory 1202 can execute the multi-threaded concurrency management method provided in Figure 5 above, such as dividing the target global variable into multiple sub-variable areas; the target global variable is used to control multi-threaded access to target data, and each sub-variable area in the multiple sub-variable areas includes one or more flag bits; dividing multiple threads into multiple thread groups; the multiple threads are used to apply for permission to read the target data; authorizing the target thread in the target thread group to modify the flag bit in the target sub-variable area; the target thread group is one of the multiple thread groups, and the target sub-variable area is one of the multiple sub-variable areas, and one thread group in the multiple thread groups and one sub-variable area in the multiple sub-variable areas have a one-to-one correspondence; if the target thread successfully modifies the flag bit, the target thread is allowed to read the target data.

[0137] It should be noted that the functions of each functional unit in the multi-threaded concurrency management device 120 described in the embodiment of the present application can be found in the relevant descriptions of steps S501 to S504 in the method embodiment described in Figure 5 above, and will not be repeated here.

[0138] It should be noted that the multi-threaded concurrency management device described in this application is not limited to this. The multi-threaded concurrency management device can be located in any electronic device, such as a server, computer, mobile phone, tablet and other devices. The multi-threaded concurrency management device can specifically be a chip or chipset or a circuit board equipped with a chip or chipset. The chip or chipset or the circuit board equipped with a chip or chipset can work under the necessary software drive. For example, the multi-threaded concurrency management device can be:

[0139] (1) Independent integrated circuits, chips, chip systems or subsystems;

[0140] (2) a collection of one or more ICs, optionally including a storage component for storing data and computer programs;

[0141] (3) Modules that can be embedded in other devices;

[0142] (4)Others, etc.

[0143] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program code is stored. When the processor executes the computer program code, the computer executes the method in any of the aforementioned embodiments.

[0144] An embodiment of the present application further provides an electronic device, which may be in the form of a chip product. The electronic device includes a processor configured to support the electronic device in implementing the corresponding functions of the method in any of the aforementioned embodiments. The electronic device may also include a memory coupled to the processor to store program instructions and data necessary for the electronic device. The electronic device may also include a communication interface for the electronic device to communicate with other devices or a communication network.

[0145] An embodiment of the present application further provides a computer program product, which, when executed on a computer, enables the computer to execute the method in any of the aforementioned embodiments.

[0146] An embodiment of the present application provides a chip system, which includes a processor for supporting a device in implementing the functions described in the first aspect, such as generating or processing information used in the multi-threaded concurrent management method. In one possible design, the chip system further includes a memory for storing program instructions and data necessary for the device. The chip system may consist of a chip or may include a chip and other discrete components.

[0147] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0148] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.

[0149] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0150] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0151] In addition, the functional units in the embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0152] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to execute all or part of the steps of the above-mentioned methods in each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (abbreviated as: ROM) or random access memory (abbreviated as: RAM) and other media that can store program codes.

[0153] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A multi-threaded concurrent management method, characterized in that: The method comprises: Dividing a target global variable into a plurality of sub-variable areas; the target global variable is used to control multi-threaded access to target data, each of the plurality of sub-variable areas comprising one or more flag bits; Dividing a plurality of threads into a plurality of thread groups; the plurality of threads are used to apply for permission to read the target data; Authorize a target thread in a target thread group to modify a flag bit in a target sub-variable region; wherein the target thread group is one of the multiple thread groups, the target sub-variable region is one of the multiple sub-variable regions, and one of the multiple thread groups and one of the multiple sub-variable regions correspond to each other one by one; If the target thread successfully modifies the mark bit, the target thread is allowed to read the target data.

2. The method according to claim 1, characterized in that The method further comprises: The total number of threads that can currently read the target data is determined by the state of the mark bit in each sub-variable area.

3. The method according to any one of claims 1-2, wherein when the target thread group includes multiple threads, within one clock cycle, one thread in the target thread group is allowed to successfully modify the mark bit in the target sub-variable area.

4. The method according to any one of claims 1 to 3, characterized in that The target thread in the target thread group is authorized to modify the mark bit in the target sub-variable area, including: If no thread currently exclusively occupies the target data, the target thread in the target thread group is authorized to modify the flag bit in the target sub-variable area through a compare and exchange (CAS) operation.

5. The method according to any one of claims 1 to 4, characterized in that Each sub-variable area further includes a control status bit, and the control status bit is used to indicate whether the target data is exclusively occupied; the method further includes: When the first thread of the target thread group applies for exclusive use of the target data, authorizing the first thread to modify the control state bit of each sub-variable area respectively; If the first thread successfully modifies the control status bit, the first thread is allowed to exclusively occupy the target data.

6. The method according to claim 5, characterized in that The authorizing the first thread to modify the control status bit of each sub-variable area respectively includes: If no thread currently exclusively occupies or reads the target data, the first thread is authorized to modify the control status bit of each sub-variable area through a CAS operation.

7. The method according to any one of claims 1 to 6, characterized in that The global variable is a lock state variable, the mark bit is a read lock count bit, and the threads in the multiple thread groups modify the mark bit in the sub-variable area to add a read lock or an unread lock.

8. The method according to any one of claims 5 to 6, characterized in that: The global variable is a lock state variable, the control state bit is a write lock state bit, and the threads in the multiple thread groups modify the control state bit in the sub-variable area to add a write lock or release a write lock.

9. A multi-thread concurrent management device, characterized in that: include: A first processing unit is used to divide a target global variable into a plurality of sub-variable areas; the target global variable is used to control multi-threaded access to target data, and each of the plurality of sub-variable areas includes one or more flag bits; A second processing unit, configured to divide the plurality of threads into a plurality of thread groups; The multiple threads are used to apply for permission to read the target data; Authorize a target thread in a target thread group to modify a flag bit in a target sub-variable region; wherein the target thread group is one of the multiple thread groups, the target sub-variable region is one of the multiple sub-variable regions, and one of the multiple thread groups and one of the multiple sub-variable regions correspond to each other one by one; The third processing unit is configured to allow the target thread to read the target data if the target thread successfully modifies the mark bit.

10. The device according to claim 9, characterized in that The device also includes: A determination unit is used to determine the total number of threads that can currently read the target data according to the state of the mark bit in each sub-variable area.

11. The device according to any one of claims 9 to 10, characterized in that When the target thread group includes multiple threads, within one clock cycle, one thread in the target thread group is allowed to successfully modify the mark bit in the target sub-variable area.

12. The device according to any one of claims 9 to 11, characterized in that The second processing unit is specifically configured to: If no thread currently exclusively occupies the target data, the target thread in the target thread group is authorized to modify the flag bit in the target sub-variable area through a compare and exchange (CAS) operation.

13. The device according to any one of claims 9 to 12, characterized in that Each sub-variable area further includes a control status bit, and the control status bit is used to indicate whether the target data is exclusively occupied; the second processing unit is further used to authorize the first thread to modify the control status bit of each sub-variable area respectively when the first thread of the target thread group applies for exclusive use of the target data; The third processing unit is further configured to allow the first thread to exclusively occupy the target data if the first thread successfully modifies the control status bit.

14. The device according to claim 13, characterized in that The second processing unit is specifically configured to: If no thread currently exclusively occupies or reads the target data, the first thread is authorized to modify the control status bit of each sub-variable area through a CAS operation.

15. The device according to any one of claims 9 to 14, characterized in that The global variable is a lock state variable, the mark bit is a read lock count bit, and the threads in the multiple thread groups modify the mark bit in the sub-variable area to add a read lock or an unread lock.

16. The device according to any one of claims 13 to 14, characterized in that The global variable is a lock state variable, the control state bit is a write lock state bit, and the threads in the multiple thread groups modify the control state bit in the sub-variable area to add a write lock or release a write lock.

17. A multi-thread concurrent management device, characterized in that: The method comprises a processor and an interface circuit, wherein the interface circuit is used to receive signals from other communication devices and transmit them to the processor or send signals from the processor to other communication devices, and the processor is used to implement the method as described in any one of claims 1 to 8 through a logic circuit or executing code instructions.

18. A computer-readable storage medium, characterized in that: The storage medium stores a computer program or instruction. When the computer program or instruction is executed by the communication device, the method according to any one of claims 1 to 8 is implemented.

19. A computer program, characterized in that The computer program comprises instructions, and when the computer program is executed by a communication device, the method according to any one of claims 1 to 8 is implemented.

20. A server, characterized in that: The server comprises a processor and a memory, wherein the memory is used to store program codes, and when the program codes are executed by the processor, the server implements the method according to any one of claims 1 to 8.

21. A chip system, characterized in that: The chip system includes a processor for supporting the device to implement the functions involved in the method as described in any one of claims 1-8.

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