Shift register unit and driving method therefor, display substrate, and display device

Abstract

A shift register unit and a driving method therefor, a display substrate, and a display device. The shift register unit comprises: a node control sub-circuit configured to, under the control of signals of a first clock signal end and a second clock signal end, provide to a first node a signal of a signal input end or a first power supply end, and provide to a second node a signal of a second power supply end or the first clock signal end; a pull-down sub-circuit configured to provide to the first node a signal of a third power supply end; and an output sub-circuit configured to, under the control of the signals of the first node, the second node, and the second power supply end, provide to a first signal output end the signal of the first power supply end or the second clock signal end, wherein the absolute value of a voltage value of the signal of the third power supply end is less than the absolute value of a voltage value of the signal of the second power supply end.

Description

Shift register unit and driving method thereof, display substrate, and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 13, 2023, with application number 202310701919.2 and invention name “Shift register unit and its driving method, display substrate, display device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of display technology, and particularly to a shift register unit and a driving method thereof, a display substrate, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting elements and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] In a first aspect, the present disclosure provides a shift register unit, comprising: a node control subcircuit, an output subcircuit, and a pull-down subcircuit;

[0007] The node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node, and the second node, respectively, and is configured to provide a signal from the signal input terminal or the first power supply terminal to the first node, and provide a signal from the second power supply terminal or the first clock signal terminal to the second node under the control of the signals from the first clock signal terminal and the second clock signal terminal;

[0008] The pull-down sub-circuit is electrically connected to the first node and the third power supply terminal, respectively, and is configured to provide a signal of the third power supply terminal to the first node;

[0009] The output sub-circuit is electrically connected to the second clock signal terminal, the first power terminal, the second power terminal, the first signal output terminal, the first node, and the second node, respectively, and is configured to provide a signal from the first power terminal or the second clock signal terminal to the first signal output terminal under the control of the signals from the first node, the second node, and the second power terminal;

[0010] An absolute value of a voltage value of a signal at the third power supply terminal is smaller than an absolute value of a voltage value of a signal at the second power supply terminal.

[0011] In an exemplary embodiment, the pull-down sub-circuit includes: an eleventh transistor;

[0012] A first electrode of the eleventh transistor is electrically connected to the third power supply terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.

[0013] In an exemplary embodiment, the control electrode of the eleventh transistor is electrically connected to the first node.

[0014] In an exemplary embodiment, the node control subcircuit includes: a first transistor, a second transistor, a third transistor, a sixth transistor, and a seventh transistor;

[0015] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0016] The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0017] A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the second node;

[0018] The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fourth node;

[0019] The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first node.

[0020] In an exemplary embodiment, the output sub-circuit includes: a fourth transistor, a fifth transistor, and an eighth transistor;

[0021] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first signal output terminal;

[0022] The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first signal output terminal;

[0023] The control electrode of the eighth transistor is electrically connected to the second power supply terminal, the first electrode of the eighth transistor is connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node.

[0024] In an exemplary embodiment, the pull-down sub-circuit includes: an eleventh transistor;

[0025] The control electrode of the eleventh transistor is electrically connected to the third node.

[0026] In an exemplary embodiment, the output subcircuit further includes: at least one of a first capacitor and a second capacitor;

[0027] The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power supply terminal;

[0028] The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the first signal output terminal.

[0029] In an exemplary embodiment, the output sub-circuit is further electrically connected to the third clock signal terminal and the second signal output terminal, respectively, and is configured to provide a signal from the second power supply terminal or the third clock signal terminal to the second signal output terminal under the control of the signals of the first node and the second node.

[0030] In an exemplary embodiment, the output sub-circuit includes: a fourth transistor, a fifth transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0031] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first signal output terminal;

[0032] The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first signal output terminal;

[0033] The control electrode of the eighth transistor is electrically connected to the second power supply terminal, the first electrode of the eighth transistor is connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node;

[0034] The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is connected to the third clock signal terminal, and the second electrode of the ninth transistor is electrically connected to the second signal output terminal;

[0035] The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the second signal output terminal.

[0036] In an exemplary embodiment, the output sub-circuit further includes: a twelfth transistor; the control electrode of the ninth transistor is electrically connected to the first node through the twelfth transistor;

[0037] The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the control electrode of the ninth transistor.

[0038] In an exemplary embodiment, the output subcircuit further includes: at least one of a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor;

[0039] The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power supply terminal;

[0040] The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the first signal output terminal;

[0041] A first plate of the third capacitor is electrically connected to the control electrode of the ninth transistor, and a second plate of the third capacitor is connected to the second signal output terminal;

[0042] The first plate of the fourth capacitor is electrically connected to the second node, and the second plate of the fourth capacitor is connected to the second power supply terminal.

[0043] In an exemplary embodiment, the signal at the third clock signal terminal and the signal at the second clock signal terminal are inverted signals.

[0044] In an exemplary embodiment, further comprising: an output control subcircuit;

[0045] The output control subcircuit is electrically connected to the first power supply terminal and the first signal output terminal respectively, and is configured to store a voltage difference between the signal at the first signal output terminal and the signal at the first power supply terminal.

[0046] In an exemplary embodiment, the output control subcircuit includes: a fifth capacitor;

[0047] The first electrode of the fifth capacitor is electrically connected to the first power supply terminal, and the second electrode of the fifth capacitor is electrically connected to the first signal output terminal.

[0048] In an exemplary embodiment, the signal at the first clock signal terminal and the signal at the second clock signal terminal are not active level signals at the same time.

[0049] In a second aspect, the present disclosure further provides a display substrate, including: a substrate, and sub-pixels, gate lines, and a gate driving circuit disposed on the substrate. The substrate is provided with a display area and a non-display area. The gate driving circuit is located in the non-display area, the sub-pixels and the gate lines are located in the display area, and the gate lines are electrically connected to the sub-pixels and the gate driving circuit respectively;

[0050] The gate driving circuit includes: a plurality of cascaded shift register units as described above. Among them, the first signal output terminal of the i-th shift register unit is connected to the signal input terminal of the (i + 1)-th shift register unit, where 1 ≤ i < N, and N is the total number of stages of the shift register units.

[0051] In an exemplary embodiment, the first signal output terminal of the shift register unit is electrically connected to the gate line.

[0052] In an exemplary embodiment, it further includes: an initial signal line, a first clock signal line, a second clock signal line, a first power supply line, a second power supply line, and a third power supply line disposed on the substrate and located in the non-display area;

[0053] Any one of the initial signal line, the first clock signal line, the second clock signal line, the first power supply line, the second power supply line, and the third power supply line extends along a first direction, the gate line extends along a second direction, and the first direction intersects the second direction.

[0054] In an exemplary embodiment, the initial signal line, the first clock signal line, the second clock signal line, and the first power supply line are arranged in sequence along the direction close to the display area and are located on the side of the shift register unit away from the display area.

[0055] In an exemplary embodiment, the shift register unit includes: a plurality of transistors. The second power supply line is located on the side of the first power supply line close to the display area and is located between the plurality of transistors of the shift register unit.

[0056] In an exemplary embodiment, the third power supply line is located on the side of the second power supply line close to the display area, and the orthographic projection of the third power supply line on the substrate partially overlaps the orthographic projection of the shift register unit on the substrate.

[0057] In an exemplary embodiment, the shift register unit includes: a first transistor, a second transistor, a third transistor, a sixth transistor, and a seventh transistor;

[0058] At least a part of any one of the first transistor, the second transistor, the third transistor, the sixth transistor, and the seventh transistor is located between the first power supply line and the second power supply line.

[0059] In an exemplary embodiment, the shift register unit includes: a fourth transistor, a fifth transistor, an eighth transistor, an eleventh transistor, and a twelfth transistor, and the number of the second power line is at least one;

[0060] At least a portion of any one of the fourth transistor, the fifth transistor, the eighth transistor, the eleventh transistor, and the twelfth transistor is located on a side of the second power line close to the display area.

[0061] In an exemplary embodiment, the shift register unit includes: a second capacitor;

[0062] The second capacitor is located on a side of the third power line close to the display area.

[0063] In an exemplary embodiment, the further comprising: a third clock signal line and a fourth clock signal line disposed on the substrate and located in the non-display area, wherein either the third clock signal line or the fourth clock signal line extends along the first direction;

[0064] There are two second power lines. The second power line close to the display area is located on the side of any one of the third clock signal line and the fourth clock signal line close to the display area, and the second power line away from the display area is located between the first power line and the third power line.

[0065] In an exemplary embodiment, the shift register unit includes: a fourth transistor, a fifth transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor, and a fourth capacitor;

[0066] The fourth transistor, the fifth transistor, the eighth transistor, the eleventh transistor, and the twelfth transistor are located between the second power line and any one of the third clock signal line and the fourth clock signal line, which are away from the display area, and the ninth transistor and the tenth transistor are located on a side of the second power line close to the display area;

[0067] An orthographic projection of the second power line close to the display area on the substrate partially overlaps with an orthographic projection of the fourth capacitor on the substrate.

[0068] In an exemplary embodiment, the first clock signal terminal of the i-th stage shift register unit is electrically connected to one of the first clock signal line and the second clock signal line, and the second clock signal terminal of the i-th stage shift register unit is electrically connected to the other of the first clock signal line and the second clock signal line;

[0069] The first clock signal terminals of adjacent shift register units are connected to different signal lines, and the second clock signal terminals of adjacent shift register units are connected to different signal lines.

[0070] In an exemplary embodiment, the shift register unit includes: a fourth transistor and a fifth transistor;

[0071] An orthographic projection of the third power line on the substrate partially overlaps with orthographic projections of the fourth transistor and the fifth transistor on the substrate.

[0072] In an exemplary embodiment, the active layer of the eighth transistor extends along the second direction, any one of the first electrode and the second electrode of the eighth transistor extends along the first direction, and the gate electrode of the eighth transistor at least partially extends along the first direction.

[0073] In an exemplary embodiment, the gate electrode of the eleventh transistor is an integral structure with the gate electrode of the fifth transistor, the orthographic projection of the first electrode of the eleventh transistor on the substrate partially overlaps with the orthographic projection of the third power line on the substrate, and is electrically connected to the third power line, and the second electrode of the eleventh transistor is an integral structure with the first electrode of the eighth transistor and the first electrode of the twelfth transistor.

[0074] In an exemplary embodiment, a width of any one of the first power line, the second power line, and the third power line along the second direction is smaller than a width of any one of the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line along the second direction.

[0075] In an exemplary embodiment, the third clock signal terminal of the i-th stage shift register unit is electrically connected to one of the third clock signal line and the fourth clock signal line, and the third clock signal terminal of the i+1-th stage shift register unit is electrically connected to the other of the third clock signal line and the fourth clock signal line.

[0076] In example embodiments, channel widths of active layers of the tenth transistor and the ninth transistor are greater than a channel width of an active layer of the fourth transistor.

[0077] In an exemplary embodiment, a channel width of the active layer of the tenth transistor or the ninth transistor is not less than 90 micrometers.

[0078] In an exemplary embodiment, a channel width of the active layer of the fourth transistor is no greater than 50 micrometers.

[0079] In example embodiments, channel widths of active layers of the ninth and tenth transistors are greater than a channel width of the active layer of the fifth transistor.

[0080] In an exemplary embodiment, a channel width of the active layer of the ninth transistor and the tenth transistor is not less than 90 micrometers.

[0081] In an exemplary embodiment, a channel width of the active layer of the fifth transistor is no greater than 50 micrometers.

[0082] In an exemplary embodiment, the second signal output terminal of the shift register unit is electrically connected to the gate line.

[0083] In a third aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0084] In a fourth aspect, the present disclosure further provides a method for driving a shift register unit, which is configured to drive the shift register unit. The method includes:

[0085] The node control subcircuit provides a signal from the signal input terminal or the first power terminal to the first node and provides a signal from the second power terminal or the first clock signal terminal to the second node under the control of the signals from the first clock signal terminal and the second clock signal terminal;

[0086] The pull-down sub-circuit provides a signal from the third power supply terminal to the first node;

[0087] The output sub-circuit provides a signal from the first power supply terminal or the second clock signal terminal to the first signal output terminal under the control of the signals from the first node and the second node.

[0088] In an exemplary embodiment, the shift register unit further includes: an output control subcircuit;

[0089] The method further includes: the output subcircuit provides a signal from the second power supply terminal or the third clock signal terminal to the second signal output terminal under the control of the signals from the first node and the second node;

[0090] The output control subcircuit stores a voltage difference between a signal at the first signal output terminal and a signal at the first power supply terminal.

[0091] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0092] Summary of the Figures

[0093] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0094] FIG1 is a structural diagram 1 of a shift register unit provided by an embodiment of the present disclosure;

[0095] FIG2 is an equivalent circuit diagram of a pull-down subcircuit;

[0096] FIG3 is an equivalent circuit diagram of another pull-down sub-circuit;

[0097] FIG4 is an equivalent circuit diagram of a node control subcircuit;

[0098] FIG5 is an equivalent circuit diagram 1 of the output subcircuit;

[0099] FIG6 is an equivalent circuit diagram of the output subcircuit;

[0100] FIG7 is a second structural diagram of a shift register unit provided in an embodiment of the present disclosure;

[0101] FIG8 is an equivalent circuit diagram 3 of the output subcircuit;

[0102] FIG9 is a fourth equivalent circuit diagram of the output subcircuit;

[0103] FIG10 is a third structural diagram of a shift register unit provided in an embodiment of the present disclosure;

[0104] FIG11 is an equivalent circuit diagram of the output control subcircuit;

[0105] FIG12 is an equivalent circuit diagram 1 of a shift register unit;

[0106] FIG13 is a second equivalent circuit diagram of a shift register unit;

[0107] FIG14 is a third equivalent circuit diagram of a shift register unit;

[0108] FIG15 is a fourth equivalent circuit diagram of a shift register unit;

[0109] FIG16 is a fifth equivalent circuit diagram of a shift register unit;

[0110] FIG17 is a sixth equivalent circuit diagram of a shift register unit;

[0111] FIG18 is an equivalent circuit diagram 7 of a shift register unit;

[0112] FIG19 is a signal timing simulation diagram of the shift register unit provided in FIG12 and FIG13;

[0113] FIG20 is a signal timing simulation diagram of the shift register provided by FIG14 to FIG18;

[0114] FIG21 is a comparison diagram of signals at the first node and the second signal output terminal of different shift register units;

[0115] FIG22 is a schematic structural diagram of a display device;

[0116] FIG23 is a schematic diagram of a planar structure of a display substrate;

[0117] FIG24 is a second schematic diagram of a planar structure of a display substrate;

[0118] FIG25 is a third schematic plan view of a display substrate;

[0119] FIG26A is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0120] FIG26B is an operation timing diagram of the pixel driving circuit provided in FIG26A ;

[0121] FIG27A is a schematic diagram of an equivalent circuit of another pixel driving circuit;

[0122] FIG27B is an operation timing diagram of the pixel driving circuit provided in FIG27A ;

[0123] FIG28 is a cascade diagram of a gate drive circuit;

[0124] FIG29 is a second cascade diagram of a gate drive circuit;

[0125] FIG30 is a structural schematic diagram 1 of a display substrate;

[0126] FIG31 is a second structural diagram of a display substrate;

[0127] FIG32 is a schematic diagram of FIG30 after forming a semiconductor layer pattern;

[0128] FIG33 is a schematic diagram of FIG31 after forming a semiconductor layer pattern;

[0129] FIG34 is a schematic diagram of the first conductive layer pattern in FIG30;

[0130] FIG35 is a schematic diagram of FIG30 after forming a first conductive layer pattern;

[0131] FIG36 is a schematic diagram of the first conductive layer pattern in FIG31;

[0132] FIG37 is a schematic diagram of FIG31 after forming a first conductive layer pattern;

[0133] FIG38 is a schematic diagram of the second conductive layer pattern in FIG30;

[0134] FIG39 is a schematic diagram of FIG30 after forming a second conductive layer pattern;

[0135] FIG40 is a schematic diagram of the second conductive layer pattern in FIG31;

[0136] FIG41 is a schematic diagram of FIG31 after forming a second conductive layer pattern;

[0137] FIG42 is a schematic diagram of FIG30 after forming a third insulating layer pattern;

[0138] FIG43 is a schematic diagram of FIG31 after forming a third insulating layer pattern;

[0139] FIG44 is a schematic diagram of a third conductive layer pattern in FIG30 ;

[0140] FIG45 is a schematic diagram of FIG30 after forming a third conductive layer pattern;

[0141] FIG46 is a schematic diagram of the third conductive layer pattern in FIG31;

[0142] FIG47 is a schematic diagram of FIG31 after forming a third conductive layer pattern;

[0143] FIG48 is a schematic diagram of FIG30 after forming a fourth insulating layer pattern;

[0144] FIG49 is a schematic diagram of FIG31 after forming a fourth insulating layer pattern;

[0145] FIG50 is a schematic diagram of the fourth conductive layer pattern in FIG30 and FIG31;

[0146] FIG51 is a schematic diagram of FIG30 after forming a fourth conductive layer pattern;

[0147] FIG52 is a schematic diagram of FIG31 after forming a fourth conductive layer pattern.

[0148] Details

[0149] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings below. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0150] In the drawings, the sizes of various components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0151] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0152] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0153] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0154] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0155] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0156] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0157] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0158] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0159] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0160] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0161] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0162] The display substrate includes a pixel driver circuit, a light-emitting element, and a gate driver circuit. The gate driver circuit is configured to provide gate signals to the transistors in the pixel driver circuit, enabling the pixel driver circuit to drive the light-emitting element to emit light. The display substrate utilizes low-temperature polysilicon (LTPS) technology, which boasts advantages such as high resolution, high response speed, high brightness, and a high aperture ratio. While popular in the market, LTPS technology also has drawbacks, such as high production costs and high power consumption. This is why low-temperature polycrystalline oxide (LTPO) technology has emerged. Compared to LTPS technology, the pixel driver circuit includes low-temperature polysilicon transistors. LTPO technology incorporates both low-temperature polysilicon transistors and metal oxide transistors. Metal oxide transistors have lower leakage current, resulting in faster pixel response. The display substrate incorporates an additional oxide layer, which reduces the energy required to activate the pixels, thereby reducing power consumption during screen display. Display products using LTPO technology include a driver circuit to control the metal oxide transistors within the display product. As display substrates increase in size, resolution, and refresh rate, the compensation time of pixel driver circuits within a frame is becoming increasingly shorter. Furthermore, the driver circuits used to control metal oxide transistors (MOS transistors) in display substrates often experience insufficient voltage at some nodes, preventing the output signal from the driver circuit from reaching the desired voltage. This results in weak driving capability for the MOS transistors, which in turn leads to a lowered conduction level for the MOS transistors, impacting the performance of the pixel driver circuit and, consequently, reducing the display quality of the display substrate.

[0163] Figure 1 is a structural diagram of a shift register unit according to an embodiment of the present disclosure. As shown in Figure 1 , the shift register unit according to an embodiment of the present disclosure may include: a node control subcircuit, an output subcircuit, and a pull-down subcircuit.

[0164] As shown in Figure 1, the node control sub-circuit is electrically connected to the signal input terminal IN, the first clock signal terminal CK1, the second clock signal terminal CK2, the first power supply terminal V1, the second power supply terminal V2, the first node N1 and the second node N2, respectively, and is configured to provide the signal of the signal input terminal IN or the first power supply terminal V1 to the first node N1, and provide the signal of the second power supply terminal V2 or the first clock signal terminal CK1 to the second node N2 under the control of the signal of the first clock signal terminal CK1 and the second clock signal terminal CK2; the pull-down sub-circuit is electrically connected to the first node N1 and the third power supply terminal V3, respectively, and is configured to provide the signal of the third power supply terminal V3 to the first node N1; the output sub-circuit is electrically connected to the second clock signal terminal CK2, the first power supply terminal V1, the second power supply terminal V2, the first signal output terminal OUT1, the first node N1 and the second node N2, respectively, and is configured to provide the signal of the first power supply terminal V1 or the second clock signal terminal CK2 to the first signal output terminal OUT1 under the control of the signal of the second power supply terminal V2, the first node N1 and the second node N2.

[0165] In an exemplary embodiment, the first power terminal V1 continuously provides a high level signal, and the second power terminal V2 and the third power terminal V3 continuously provide a low level signal.

[0166] In an exemplary embodiment, the absolute value of the voltage value of the signal at the third power supply terminal V3 is smaller than the absolute value of the voltage value of the signal at the second power supply terminal V2. Exemplarily, the width of the signal line connected to the second power supply terminal V2 is different from the width of the signal line connected to the third power supply terminal V3.

[0167] In an exemplary embodiment, a signal at either the first clock signal terminal CK1 or the second clock signal terminal CK2 may be a periodic pulse signal.

[0168] In an exemplary embodiment, the signal at the signal output terminal IN is a single pulse signal.

[0169] The shift register unit provided by the embodiment of the present disclosure includes: a node control subcircuit, an output subcircuit and a pull-down subcircuit, wherein the node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node and the second node, and is configured to provide the signal of the signal input terminal or the first power supply terminal to the first node, and provide the signal of the second power supply terminal or the first clock signal terminal to the second node under the control of the signals of the first clock signal terminal and the second clock signal terminal; the pull-down subcircuit is electrically connected to the first node and the third power supply terminal, and is configured to provide the signal of the third power supply terminal to the first node; the output subcircuit is electrically connected to the second clock signal terminal, the first power supply terminal, the first signal output terminal, the first node and the second node, and is configured to provide the signal of the first power supply terminal or the second clock signal terminal to the first signal output terminal under the control of the signals of the first node and the second node, and the absolute value of the voltage value of the signal of the third power supply terminal is smaller than the absolute value of the voltage value of the signal of the second power supply terminal. The shift register unit provided by the present disclosure can pull down the signal of the first node to a low-level signal with a lower voltage value by setting a pull-down sub-circuit, so that some transistors in the shift register unit can be fully turned on, and thus the voltage of the output signal of the shift register unit can reach a predetermined voltage, thereby improving the driving capability of the shift register unit, and can ensure the conduction capability of the transistors in the pixel driving circuit, thereby improving the performance of the pixel driving circuit and the display effect of the display substrate.

[0170] In an exemplary embodiment, Figure 2 is an equivalent circuit diagram of one pull-down sub-circuit, and Figure 3 is an equivalent circuit diagram of another pull-down sub-circuit. As shown in Figures 2 and 3, the pull-down sub-circuit may include an eleventh transistor T11. A first electrode of the eleventh transistor T11 is electrically connected to the third power supply terminal V3, and a second electrode of the eleventh transistor T11 is electrically connected to the first node N1.

[0171] In an exemplary embodiment, Figure 4 is an equivalent circuit diagram of a node control subcircuit. As shown in Figure 4, the node control subcircuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6, and a seventh transistor T7. Among them, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the first power supply terminal V1, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, the first electrode of the seventh transistor T7 is connected to the fourth node, and the second electrode of the seventh transistor T7 is electrically connected to the first node N1.

[0172] In an exemplary embodiment, FIG5 is an equivalent circuit diagram of an output subcircuit. As shown in FIG5 , the output subcircuit may include: a fourth transistor T4, a fifth transistor T5, and an eighth transistor T8. The control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected to the first signal output terminal OUT1; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1; and the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3.

[0173] In an exemplary embodiment, as shown in FIG. 2 , the control electrode of the eleventh transistor T11 may be electrically connected to the first node N1 .

[0174] In an exemplary embodiment, as shown in FIG. 3 , the control of the eleventh transistor may be electrically connected to the third node N3 .

[0175] In an exemplary embodiment, Figure 6 is an equivalent circuit diagram of the output sub-circuit. As shown in Figure 6, the output sub-circuit may include at least one of a first capacitor C1 and a second capacitor C2. The first plate of the first capacitor C1 is electrically connected to the second node N2, and the second plate of the first capacitor C1 is electrically connected to the first power supply terminal V1. The first plate of the second capacitor C2 is electrically connected to the third node, and the second plate of the second capacitor C2 is electrically connected to the first signal output terminal OUT1. Figure 6 illustrates an example in which the output sub-circuit also includes the first capacitor C1 and the second capacitor C2.

[0176] In an exemplary embodiment, FIG7 is a second schematic diagram of the structure of a shift register unit provided in an embodiment of the present disclosure. As shown in FIG7 , the output sub-circuit is electrically connected to the second clock signal terminal CK2, the first power supply terminal V1, the first signal output terminal OUT1, the first node N1, the second node N2, the third clock signal terminal CK3, the second power supply terminal V2, and the second signal output terminal OUT2, respectively. The output sub-circuit is configured to provide a signal from the first power supply terminal V1 or the second clock signal terminal CK2 to the first signal output terminal OUT1, and to provide a signal from the second power supply terminal V2 or the third clock signal terminal CK3 to the second signal output terminal OUT2, under the control of signals from the first node N1 and the second node N2.

[0177] In an exemplary embodiment, the signals at the first signal output terminal OUT1 and the second signal output terminal OUT2 are single pulse signals, and the signal at the first signal output terminal OUT1 and the signal at the second signal output terminal OUT2 are inverted signals of each other, that is, when the signal at the first signal output terminal OUT1 is a high-level signal, the signal at the second signal output terminal OUT2 is a low-level signal, and when the signal at the first signal output terminal OUT1 is a low-level signal, the signal at the second signal output terminal OUT2 is a high-level signal.

[0178] In an exemplary embodiment, the first signal output terminal OUT1 is configured to output a cascade signal, which is a low-level signal, and the second signal output terminal OUT2 is configured to output a gate scan signal, which is exemplarily a high-level signal or a low-level signal.

[0179] In an exemplary embodiment, Figure 8 is a third equivalent circuit diagram of an output sub-circuit. As shown in Figure 8 , the output sub-circuit may include: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. Among them, the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected to the first signal output terminal OUT1; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1; the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3; the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is connected to the third clock signal terminal CK3, and the second electrode of the ninth transistor T9 is electrically connected to the second signal output terminal OUT2; the control electrode of the tenth transistor T10 is electrically connected to the second node N2, the first electrode of the tenth transistor T10 is connected to the second power supply terminal V2, and the second electrode of the tenth transistor T10 is electrically connected to the second signal output terminal OUT2.

[0180] In an exemplary embodiment, FIG9 is an equivalent circuit diagram of an output subcircuit. As shown in FIG9 , the output subcircuit may include: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and a twelfth transistor T12. The control electrode of the ninth transistor T9 is electrically connected to the first node N1 through the twelfth transistor T12. The control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the first power supply terminal V1, and the second electrode of the fourth transistor T4 is electrically connected to the first signal output terminal OUT1; the control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1; the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3; the ninth transistor T The control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is connected to the third clock signal terminal CK3, and the second electrode of the ninth transistor T9 is electrically connected to the second signal output terminal OUT2; the control electrode of the tenth transistor T10 is electrically connected to the second node N2, the first electrode of the tenth transistor T10 is connected to the second power supply terminal V2, the second electrode of the tenth transistor T10 is electrically connected to the second signal output terminal OUT2, the control electrode of the twelfth transistor T12 is electrically connected to the second power supply terminal V2, the first electrode of the twelfth transistor T12 is electrically connected to the first node N1, and the second electrode of the twelfth transistor T12 is electrically connected to the control electrode of the ninth transistor T9.

[0181] In an exemplary embodiment, the twelfth transistor T12 is a continuously conducting transistor, which can ensure the stability of the signal at the control electrode of the ninth transistor T9, avoid large deviation of the output signal of the shift register unit, and ensure the stability of the output signal of the shift register unit.

[0182] In an exemplary embodiment, as shown in FIG8 and FIG9 , the output sub-circuit may further include at least one of a first capacitor C1 , a second capacitor C2 , a third capacitor C3 , and a fourth capacitor C4 .

[0183] In an exemplary embodiment, as shown in Figures 8 and 9, the first plate of the first capacitor C1 is electrically connected to the second node N2, and the second plate of the first capacitor C1 is electrically connected to the first power supply terminal V1; the first plate of the second capacitor C2 is electrically connected to the third node N3, and the second plate of the second capacitor C2 is connected to the first signal output terminal OUT1; the first plate of the third capacitor C3 is electrically connected to the control electrode of the ninth transistor T9, and the second plate of the third capacitor C3 is connected to the second signal output terminal OUT2; the first plate of the fourth capacitor C4 is electrically connected to the second node N2, and the second plate of the fourth capacitor C4 is connected to the second power supply terminal V2.

[0184] In an exemplary embodiment, the output subcircuit may include a second capacitor C2 and a fourth capacitor C4, or may include the second capacitor C2, or may include the first capacitor C1 and the third capacitor C3, or may include the third capacitor C3, or may include the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4. Figures 8 and 9 illustrate the output subcircuit as comprising the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4. The first capacitor C1 ensures the stability of the second node N2, the second capacitor C2 ensures the voltage difference between the signal at the third node N3 and the first signal output terminal OUT1, the third capacitor ensures the voltage difference between the signal at the first node N1 and the second signal output terminal OUT2, and the fourth capacitor C4 ensures the stability of the signal at the second node N2.

[0185] In an exemplary embodiment, Figure 10 is a third structural schematic diagram of the shift register unit provided in an embodiment of the present disclosure. As shown in Figure 10, the shift register unit may further include: an output control subcircuit. The output control subcircuit is electrically connected to the first power supply terminal V1 and the first signal output terminal OUT1, respectively, and is configured to store the voltage difference between the signal of the first signal output terminal OUT1 and the first power supply terminal V1. The output subcircuit of the shift register unit in Figure 10 can be electrically connected to the second clock signal terminal CK2, the first power supply terminal V1, the first node N1, the second node N2 and the first signal output terminal OUT1, or can be electrically connected to the second clock signal terminal CK2, the third clock signal line CK3, the first power supply terminal V1, the second power supply terminal V2, the first node N1, the second node N2, the first signal output terminal OUT1 and the second signal output terminal OUT2.

[0186] In the present disclosure, the signal output by the first signal output terminal OUT1 is a cascade signal. That is, the signal line connected to the first signal output terminal OUT1 does not flow through the display area where the pixel driving circuit is located. This means that the signal line connected to the first signal output terminal OUT1 has a small load and is easily affected by the parasitic capacitance of some transistors in the output subcircuit, resulting in fluctuations in the signal at the first signal output terminal OUT1. However, the present disclosure, by providing an output control subcircuit, can make the signal output by the first signal output terminal OUT1 more stable, thereby improving the performance of the shift register unit.

[0187] In an exemplary embodiment, Figure 11 is an equivalent circuit diagram of the output control subcircuit. As shown in Figure 11, in this exemplary embodiment, the output control subcircuit includes a fifth capacitor C5. A first plate of the fifth capacitor C5 is electrically connected to the first power supply terminal V1, and a second plate of the fifth capacitor C5 is electrically connected to the first signal output terminal OUT1.

[0188] In the exemplary embodiment, the dotted lines in FIG. 10 and FIG. 11 indicate that they may or may not be connected.

[0189] In an exemplary embodiment, FIG12 is an equivalent circuit diagram 1 of a shift register unit, and FIG13 is an equivalent circuit diagram 2 of the shift register unit. As shown in FIG12 and FIG13 , the shift register unit may further include an output control subcircuit, wherein the node control subcircuit includes a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6, and a seventh transistor T7; the output subcircuit includes a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, and at least one of a first capacitor C1 and a second capacitor C2; the pull-down subcircuit includes an eleventh transistor T11; and the output control subcircuit includes a fifth capacitor C5. FIG12 illustrates the shift register unit including the second capacitor C2, while FIG13 illustrates the shift register unit including the first capacitor C1 and the second capacitor C2. FIG12 illustrates the shift register unit using the example of the control electrode of the eleventh transistor being electrically connected to the third node N3, while FIG13 illustrates the shift register unit using the example of the control electrode of the eleventh transistor being electrically connected to the first node N1.

[0190] In an exemplary embodiment, as shown in FIG12 and FIG13 , a control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, a first electrode of the first transistor T1 is connected to the signal input terminal IN, and a second electrode of the first transistor T1 is electrically connected to the first node N1; a control electrode of the second transistor T2 is electrically connected to the first node N1, a first electrode of the second transistor T2 is connected to the first clock signal terminal CK1, and a second electrode of the second transistor T2 is electrically connected to the second node N2; a control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, a first electrode of the third transistor T3 is connected to the second power supply terminal V2, and a second electrode of the third transistor T3 is electrically connected to the second node N2; a control electrode of the fourth transistor T4 is electrically connected to the second node N2, a first electrode of the fourth transistor T4 is connected to the first power supply terminal V1, and a second electrode of the fourth transistor T4 is electrically connected to the first signal output terminal OUT1; a control electrode of the fifth transistor T5 is electrically connected to the third node N3, a first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, and a second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1; and a control electrode of the sixth transistor T6 is electrically connected to the second node N2. A first electrode of the sixth transistor T6 is connected to the first power supply terminal V1, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node; a control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, a first electrode of the seventh transistor T7 is connected to the fourth node, and a second electrode of the seventh transistor T7 is electrically connected to the first node N1; a control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, a first electrode of the eighth transistor T8 is connected to the first node N1, and a second electrode of the eighth transistor T8 is electrically connected to the third node N3; a control electrode of the eleventh transistor T11 is electrically connected to the first node N1 or the third Node N3 is electrically connected; a first electrode of the eleventh transistor T11 is electrically connected to the third power supply terminal V3, and a second electrode of the eleventh transistor T11 is electrically connected to the first node N1; a first plate of the first capacitor C1 is electrically connected to the second node N2, and a second plate of the first capacitor C1 is electrically connected to the first power supply terminal V1; a first plate of the second capacitor C2 is electrically connected to the third node N3, and a second plate of the second capacitor C2 is electrically connected to the first signal output terminal OUT1; a first plate of the fifth capacitor C5 is electrically connected to the first power supply terminal V1, and a second electrode of the fifth capacitor C5 is electrically connected to the first signal output terminal OUT1. FIG12 illustrates the case where the control electrode of the eleventh transistor T11 is electrically connected to the third node N3, and FIG13 illustrates the case where the control electrode of the eleventh transistor T11 is electrically connected to the first node N1.

[0191] In an exemplary embodiment, transistors can be classified into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0192] In an exemplary embodiment, the first to eighth transistors T1 to T8 and the eleventh transistor T11 may all be P-type transistors.

[0193] In an exemplary embodiment, FIG14 is a third equivalent circuit diagram of a shift register unit, and FIG15 is a fourth equivalent circuit diagram of the shift register unit. As shown in FIG14 and FIG15 , the shift register unit further includes an output control subcircuit, a node control subcircuit including a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6, and a seventh transistor T7; an output subcircuit including a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10; and at least one of a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4; a pull-down subcircuit including an eleventh transistor T11; and an output control subcircuit including a fifth capacitor C5. FIG14 and FIG15 illustrate the shift register unit as including the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4. FIG14 illustrates the shift register unit as an example in which the control electrode of the eleventh transistor is electrically connected to the third node N3, while FIG15 illustrates the shift register unit as an example in which the control electrode of the eleventh transistor is electrically connected to the first node N1.

[0194] In an exemplary embodiment, as shown in Figures 14 and 15, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N 2, a first electrode of the fourth transistor T4 is connected to the first power supply terminal V1, and a second electrode of the fourth transistor T4 is electrically connected to the first signal output terminal OUT1; a control electrode of the fifth transistor T5 is electrically connected to the third node N3, a first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, and a second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1; a control electrode of the sixth transistor T6 is electrically connected to the second node N2, a first electrode of the sixth transistor T6 is connected to the first power supply terminal V1, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node; a control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, a first electrode of the seventh transistor T7 is connected to the fourth node, and a second electrode of the seventh transistor T7 is electrically connected The control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the first electrode of the eighth transistor T8 is connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3; the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is connected to the third clock signal terminal CK3, and the second electrode of the ninth transistor T9 is electrically connected to the second signal output terminal OUT2; the control electrode of the tenth transistor T10 is electrically connected to the second node N2, the first electrode of the tenth transistor T10 is connected to the second power supply terminal V2, and the second electrode of the tenth transistor T10 is electrically connected to the second signal output terminal OUT2; the control electrode of the eleventh transistor T11 is electrically connected to the first node N1 or the first node N2. The third node N3 is electrically connected, the first electrode of the eleventh transistor T11 is electrically connected to the third power supply terminal V3, and the second electrode of the eleventh transistor T11 is electrically connected to the first node N1; the first plate of the first capacitor C1 is electrically connected to the second node N2, and the second plate of the first capacitor C1 is electrically connected to the first power supply terminal V1; the first plate of the second capacitor C2 is electrically connected to the third node N3, and the second plate of the second capacitor C2 is connected to the first signal output terminal OUT1; the first plate of the third capacitor C3 is electrically connected to the control electrode of the ninth transistor T9, and the second plate of the third capacitor C3 is connected to the second signal output terminal OUT2; the first plate of the fourth capacitor C4 is electrically connected to the second node N2, and the second plate of the fourth capacitor C4 is connected to the second power supply terminal V2;A first electrode of the fifth capacitor C5 is electrically connected to the first power supply terminal V1, and a second electrode of the fifth capacitor C5 is electrically connected to the first signal output terminal OUT1. FIG. 14 illustrates the case where the control electrode of the eleventh transistor T11 is electrically connected to the third node N3, while FIG. 15 illustrates the case where the control electrode of the eleventh transistor T11 is electrically connected to the first node N1.

[0195] In an exemplary embodiment, the first to eleventh transistors T1 to T11 may all be P-type transistors.

[0196] In an exemplary embodiment, FIG16 is an equivalent circuit diagram 5 of a shift register unit, FIG17 is an equivalent circuit diagram 6 of a shift register unit, and FIG18 is an equivalent circuit diagram 7 of a shift register unit. As shown in FIG16 to FIG18 , the device further includes an output control subcircuit, a node control subcircuit including a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6, and a seventh transistor T7, an output subcircuit including a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a twelfth transistor T12, and at least one of a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4, a pull-down subcircuit including an eleventh transistor T11, and an output control subcircuit including a fifth capacitor C5. FIG16 and FIG17 illustrate the shift register unit including the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4, while FIG18 illustrates the shift register unit including the second capacitor C2 and the fourth capacitor C4. 16 and 18 are described by taking the example that the control electrode of the eleventh transistor T11 is electrically connected to the third node N3 , and FIG. 17 is described by taking the example that the control electrode of the eleventh transistor T11 is electrically connected to the first node N1 .

[0197] In an exemplary embodiment, as shown in FIG16 to FIG18, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK1, the first electrode of the first transistor T1 is connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is connected to the first clock signal terminal CK1, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the fourth transistor T4 is electrically connected to the first clock signal terminal CK1, the first electrode of the third transistor T3 is connected to the second power supply terminal V2, and the second electrode of the third transistor T3 is electrically connected to the second node N2; The control electrode of the fifth transistor T5 is electrically connected to the third node N3, the first electrode of the fifth transistor T5 is connected to the second clock signal terminal CK2, and the second electrode of the fifth transistor T5 is electrically connected to the first signal output terminal OUT1; the control electrode of the sixth transistor T6 is electrically connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the first power supply terminal V1, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node; the control electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CK2, and the first electrode of the seventh transistor T7 is electrically connected to the first clock signal terminal CK2. a control electrode of the eighth transistor T8 electrically connected to the second power supply terminal V2, a first electrode of the eighth transistor T8 connected to the first node N1, and a second electrode of the eighth transistor T8 electrically connected to the third node N3; a control electrode of the ninth transistor T9 electrically connected to the second electrode of the twelfth transistor T12, a first electrode of the ninth transistor T9 connected to the third clock signal terminal CK3, and a second electrode of the ninth transistor T9 electrically connected to the second signal output terminal OUT2; a control electrode of the tenth transistor T10 electrically connected to the second node N2, a first electrode of the tenth transistor T10 connected to the second power supply terminal V2, and a second electrode of the tenth transistor T10 electrically connected to the second signal output terminal OUT2; electrically connected to the second signal output terminal OUT2; a control electrode of the eleventh transistor T11 is electrically connected to the first node N1 or the third node N3, a first electrode of the eleventh transistor T11 is electrically connected to the third power supply terminal V3, and a second electrode of the eleventh transistor T11 is electrically connected to the first node N1; a control electrode of the twelfth transistor T12 is electrically connected to the second power supply line, and a first electrode of the twelfth transistor T12 is electrically connected to the first node N1; a first plate of the first capacitor C1 is electrically connected to the second node N2, and a second plate of the first capacitor C1 is electrically connected to the first power supply terminal VGH; a first plate of the second capacitor C2 is electrically connected to the third node N3, and a second plate of the second capacitor C2 is connected to the first signal output terminal OUT1;A first plate of the third capacitor C3 is electrically connected to the control electrode of the ninth transistor T9, and a second plate of the third capacitor C3 is electrically connected to the second signal output terminal OUT2; a first plate of the fourth capacitor C4 is electrically connected to the second node N2, and a second plate of the fourth capacitor C4 is connected to the second power supply terminal V2; a first plate of the fifth capacitor C5 is electrically connected to the first power supply terminal V1, and a second plate of the fifth capacitor C5 is electrically connected to the first signal output terminal OUT1.

[0198] In an exemplary embodiment, the first to eleventh transistors T1 to T11 may all be P-type transistors.

[0199] In an exemplary embodiment, the signal at the first clock signal terminal CK1 and the signal at the second clock signal terminal CK2 are not simultaneously active level signals. For example, when the signal at the first clock signal terminal CK1 is active level, the signal at the second clock signal terminal CK2 is inactive level; and when the signal at the second clock signal terminal CK2 is active level, the signal at the first clock signal terminal CK1 is inactive level.

[0200] In an exemplary embodiment, the signal at the third clock signal terminal CK3 and the signal at the second clock signal terminal CK2 may or may not be inverted signals. When the signal at the third clock signal terminal CK3 and the signal at the second clock signal terminal CK2 are inverted signals, when the signal at the third clock signal terminal CK3 is a valid level signal, the signal at the second clock signal terminal CK2 is an inactive level signal; and when the signal at the third clock signal terminal CK3 is an inactive level signal, the signal at the second clock signal terminal CK2 is a valid level signal.

[0201] In an exemplary embodiment, the signals of the first signal output terminal OUT1 and the second signal output terminal OUT2 are inverted signals of each other.

[0202] Figure 19 is a signal timing simulation diagram of the shift register unit provided in Figures 12 and 13. Figure 19 is illustrated by taking an example where all transistors in the shift register unit are P-type transistors.

[0203] In an exemplary embodiment, for the shift register unit provided in FIG. 12 and FIG. 13 , since the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2 , the eighth transistor T8 is continuously turned on.

[0204] As shown in FIG12 and FIG19 , the operation process of the control shift register unit provided in FIG12 includes the following stages:

[0205] In the first phase S1, i.e., the input phase, the signals at the signal input terminal IN and the first clock signal terminal CK1 are low-level signals, while the signal at the second clock signal terminal GCK2 is high-level. The signal at the first clock signal terminal CK1 is low-level, the first transistor T1 and the third transistor T3 are conductive, the low-level signal at the signal input terminal IN is written to the first node N1, and the low-level signal at the second power supply terminal V2 is written to the second node N2. Because the eighth transistor T8 is continuously conductive, the signals at the third node N3 and the first node N1 are both low-level signals. The signal at the first node N1 is low-level, the second transistor T2 is conductive, and the low-level signal at the first clock signal terminal CK1 is written to the second node N2, ensuring that the signal at the second node N2 remains low-level. The signal at the second node N2 is low-level, the fourth transistor T4 and the sixth transistor T6 are conductive, the high-level signal at the first power supply terminal V1 is written to the first signal output terminal OUT1 and the fourth node N4, and the low-level signal at the second power supply terminal V2 is written to the second signal output terminal OUT2. The signal at the third node N3 is low, the fifth transistor T5 and the eleventh transistor T11 are turned on, and the signal at the third power supply terminal V3 is written to the first node N1, further pulling down the signal level at the first node N1, causing the signal at the first node N1 to remain low. Because the signal at the second clock signal terminal CK2 is high, the seventh transistor T7 is turned off, and the high signal at the fourth node N4 is not written to the first node N1, preventing the signal at the first node N1 from being pulled high. In this stage, the signals at the first, second, and third nodes N1, N2, and N3, are low, while the signal at the fourth node N4 is high. The signal at the first power supply terminal V1 is written to the first signal output terminal OUT1, and the output signal at the first signal output terminal OUT1 is high.

[0206] In the second phase S2, i.e., the output phase, the signals at the signal input terminal IN and the first clock signal terminal CK1 are high-level signals, while the signal at the second clock signal terminal GCK2 is low-level. The signal at the first clock signal terminal CK1 is high-level, the first transistor T1 and the third transistor T3 are turned off, and the signal at the first node N1 remains low-level. Because the eighth transistor T8 is continuously on, the signals at the third node N3 and the first node N1 are both low-level signals. The signal at the first node N1 is low-level, the second transistor T2 is on, the high-level signal at the first clock signal terminal CK1 is written to the second node N2, and the signal at the second node N2 is high-level. The fourth transistor T4 and the sixth transistor T6 are off, and the high-level signal at the first power supply terminal V1 cannot be written to the first signal output terminal OUT1. The signal at the third node N3 is low-level, the fifth transistor T5 and the eleventh transistor T11 are on, and the signal at the third power supply terminal V3 is written to the first node N1, maintaining the signal at the first node N1 at a low level. The low-level signal at the second clock signal terminal CK2 is written to the first signal output terminal OUT1. Since the signal at the second clock signal terminal CK2 is a low-level signal, the seventh transistor T7 is turned on, and the signal at the fourth node N4 is pulled low by the signal at the first node N1, resulting in the signal at the fourth node N4 being a low-level signal. In this stage, the signals at the first node N1, the third node N3, and the fourth node N4 are low-level signals, and the signal at the second node N2 is a high-level signal. The low-level signal at the second clock signal terminal CK2 is written to the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a low-level signal.

[0207] In the third phase S3, the signals at the signal input terminal IN and the second clock signal terminal GCK2 are high, while the signal at the first clock signal terminal CK1 is low. The signal at the first clock signal terminal CK1 is low, the first transistor T1 and the third transistor T3 are turned on, the high signal at the signal input terminal IN is written to the first node N1, and the low signal at the second power supply terminal V2 is written to the second node N2. Because the eighth transistor T8 is continuously turned on, the signals at the third node N3 and the first node N1 are both high. The signal at the first node N1 is high, and the second transistor T2 is turned off. The signal at the second node N2 is low, the fourth transistor T4 and the sixth transistor T6 are turned on, and the high signal at the first power supply terminal V1 is written to the first signal output terminal OUT1 and the fourth node N4. The signal at the third node N3 is high, the fifth transistor T5 and the eleventh transistor T11 are turned off, and the signal at the third power supply terminal V3 cannot be written to the first node N1. The signal at the first node N1 remains high, and the high signal at the second clock signal terminal CK2 cannot be written to the first signal output terminal OUT1. Since the signal at the second clock signal terminal CK2 is a high-level signal, the seventh transistor T7 is turned off. In this stage, the signal at the second node N2 is a low-level signal, the signals at the first node N1, the third node N3, and the fourth node N4 are high-level signals, the signal at the first power supply terminal V1 is written to the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a high-level signal.

[0208] In the fourth stage S4, the signals at the signal input terminal IN and the first clock signal terminal CK1 are high, while the signal at the second clock signal terminal CK2 is low. The signal at the first clock signal terminal CK1 is high, the first transistor T1 and the third transistor T3 are off, and the signal at the first node N1 remains high. Because the eighth transistor T8 remains on, the signals at the third node N3 and the first node N1 are both high. The signal at the first node N1 remains high, and the second transistor T2 is off. The signal at the second node N2 remains low, the fourth transistor T4 and the sixth transistor T6 are on, and the high signal at the first power supply terminal V1 is written to the first signal output terminal OUT1 and the fourth node N4. The signal at the third node N3 is high, the fifth transistor T5 and the eleventh transistor T11 are off, and the signal at the third power supply terminal V3 cannot be written to the first node N1. The signal at the first node N1 remains high, and the high signal at the second clock signal terminal CK2 cannot be written to the first signal output terminal OUT1. Because the signal at the second clock signal terminal CK2 remains high, the seventh transistor T7 is off. In this stage, the signal of the second node N2 is a low level signal, the signals of the first node N1, the third node N3 and the fourth node N4 are high level signals, the signal of the first power supply terminal V1 is written into the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a high level signal.

[0209] The working process of the shift register unit further includes: a plurality of third stages S3 and fourth stages S4, and the third stages S3 and the fourth stages S4 work alternately.

[0210] The difference between the shift register unit provided in Figure 13 and the shift register unit provided in Figure 12 is that the nodes to which the control electrode of the eleventh transistor is connected are different. Figure 12 is illustrated by taking the control electrode of the eleventh transistor being connected to the third node as an example, and Figure 13 is illustrated by taking the control electrode of the eleventh transistor being connected to the first node. Since the signals of the first node N1 and the third node N3 are both high-level signals or both low-level signals, that is, the eleventh transistor in the shift register units provided in Figures 12 and 13 is turned on or turned off at the same time, the working process of the shift register unit provided in Figure 13 is the same as that of the shift register unit provided in Figure 12.

[0211] Figure 20 is a signal timing simulation diagram of the shift register provided by Figures 14 to 18. Figure 20 is illustrated by taking an example where all transistors in the shift register are P-type transistors.

[0212] In the exemplary embodiment, for the shift register units provided in Figures 14 and 15 , since the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal V2, the eighth transistor T8 is continuously turned on. For the shift register units provided in Figures 16 to 18 , the control electrodes of the eighth transistor T8 and the twelfth transistor T12 are both electrically connected to the second power supply terminal V2, and the eighth transistor T8 and the twelfth transistor T12 are continuously turned on.

[0213] As shown in FIG14 and FIG20 , the operation process of the control shift register unit provided in FIG14 includes the following stages:

[0214] In the first phase S1, i.e., the input phase, the signals at the signal input terminal IN, the first clock signal terminal CK1, and the third clock signal terminal CK3 are low-level signals, and the signal at the second clock signal terminal GCK2 is high-level. The signal at the first clock signal terminal CK1 is low-level, the first transistor T1 and the third transistor T3 are conductive, the low-level signal at the signal input terminal IN is written to the first node N1, and the low-level signal at the second power supply terminal V2 is written to the second node N2. Because the eighth transistor T8 is continuously conductive, the signals at the third node N3 and the first node N1 are both low-level signals. The signal at the first node N1 is low-level, the second transistor T2 and the ninth transistor T9 are conductive, the low-level signal at the first clock signal terminal CK1 is written to the second node N2, ensuring that the signal at the second node N2 remains low-level, and the low-level signal at the third clock signal terminal CK3 is written to the second signal output terminal OUT2. The signal at the second node N2 is low, and the fourth, sixth, and tenth transistors T4, T6, and T10 are turned on. The high-level signal at the first power supply terminal V1 is written to the first signal output terminal OUT1 and the fourth node N4, while the low-level signal at the second power supply terminal V2 is written to the second signal output terminal OUT2. The signal at the third node N3 is low, and the fifth and eleventh transistors T5 and T11 are turned on. The signal at the third power supply terminal V3 is written to the first node N1, further pulling down the signal level at the first node N1, causing the signal at the first node N1 to remain low. Because the signal at the second clock signal terminal CK2 is high, the seventh transistor T7 is turned off, and the high-level signal at the fourth node N4 is not written to the first node N1, preventing the signal at the first node N1 from being pulled high. In this stage, the signals of the first node N1, the second node N2 and the third node N3 are low-level signals, the signal of the fourth node N4 is a high-level signal, the signal of the first power supply terminal V1 is written into the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a high-level signal. The signal of the third clock signal terminal CK3 and the signal of the second power supply terminal V2 are written into the second signal output terminal OUT2, and the output signal of the second signal output terminal OUT2 is a low-level signal.

[0215] In the second phase S2, i.e., the output phase, the signals at the signal input terminal IN, the first clock signal terminal CK1, and the third clock signal terminal CK3 are high-level signals, while the signal at the second clock signal terminal GCK2 is low-level. The signal at the first clock signal terminal CK1 is high-level, the first transistor T1 and the third transistor T3 are off, and the signal at the first node N1 remains low-level. Because the eighth transistor T8 is continuously on, the signals at the third node N3 and the first node N1 are both low-level signals. The signal at the first node N1 is low-level, the second transistor T2 and the ninth transistor T9 are on, the high-level signal at the first clock signal terminal CK1 is written to the second node N2, the signal at the second node N2 is high-level, the high-level signal at the third clock signal terminal CK3 is written to the second signal output terminal OUT2, the signal at the second node N2 is high-level, the fourth transistor T4, the sixth transistor T6, and the tenth transistor T10 are off, the high-level signal at the first power supply terminal V1 cannot be written to the first signal output terminal OUT1, and the low-level signal at the first low-level signal terminal VGL1 cannot be written to the second signal output terminal OUT2. The signal at the third node N3 is a low-level signal. The fifth transistor T5 and the eleventh transistor T11 are turned on. The signal at the third power supply terminal V3 is written to the first node N1, maintaining the signal at the first node N1 at a low level. The low-level signal at the second clock signal terminal CK2 is written to the first signal output terminal OUT1. Because the signal at the second clock signal terminal CK2 is a low-level signal, the seventh transistor T7 is turned on. The signal at the fourth node N4 is pulled low by the signal at the first node N1, and the signal at the fourth node N4 is a low-level signal. In this stage, the signals at the first node N1, the third node N3, and the fourth node N4 are low-level signals, and the signal at the second node N2 is a high-level signal. The low-level signal at the second clock signal terminal CK2 is written to the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is a low-level signal. The signal at the third clock signal terminal CK3 is written to the second signal output terminal OUT2, and the output signal of the second signal output terminal OUT2 is a high-level signal.

[0216] In the third phase S3, the signals at the signal input terminal IN and the second clock signal terminal GCK2 are high-level signals, while the signals at the first clock signal terminal CK1 and the third clock signal terminal CK3 are low-level signals. The signal at the first clock signal terminal CK1 is low-level, the first transistor T1 and the third transistor T3 are turned on, the high-level signal at the signal input terminal IN is written to the first node N1, and the low-level signal at the second power supply terminal V2 is written to the second node N2. Because the eighth transistor T8 is continuously turned on, the signals at the third node N3 and the first node N1 are both high-level signals. The signal at the first node N1 is high-level, and the second transistor T2 and the ninth transistor T9 are turned off. The signal at the second node N2 is low-level, the fourth transistor T4, the sixth transistor T6, and the tenth transistor T10 are turned on, the high-level signal at the first power supply terminal V1 is written to the first signal output terminal OUT1 and the fourth node N4, and the low-level signal at the second power supply terminal V2 is written to the second signal output terminal OUT2. The signal at the third node N3 is high, the fifth transistor T5 and the eleventh transistor T11 are disconnected, and the signal at the third power supply terminal V3 cannot be written to the first node N1. The signal at the first node N1 remains high, and the high-level signal at the second clock signal terminal CK2 cannot be written to the first signal output terminal OUT1. Because the signal at the second clock signal terminal CK2 is high, the seventh transistor T7 is disconnected. In this stage, the signal at the second node N2 is low, and the signals at the first node N1, the third node N3, and the fourth node N4 are high. The signal at the first power supply terminal V1 is written to the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is high. The signal at the second power supply terminal V2 is written to the second signal output terminal OUT2, and the output signal of the second signal output terminal OUT2 is low.

[0217] In the fourth stage S4, the signals at the signal input terminal IN, the first clock signal terminal CK1, and the third clock signal terminal CK3 are high-level signals, and the signal at the second clock signal terminal CK2 is low-level signal. The signal at the first clock signal terminal CK1 is high-level signal, the first transistor T1 and the third transistor T3 are turned off, and the signal at the first node N1 remains high-level signal. Because the eighth transistor T8 is continuously turned on, the signal at the third node N3 and the signal at the first node N1 are both high-level signals. The signal at the first node N1 is high-level signal, the second transistor T2 and the ninth transistor T9 are turned off, and the high-level signal at the third clock signal terminal CK3 cannot be written to the second output signal terminal. The signal at the second node N2 remains low-level signal, the fourth transistor T4, the sixth transistor T6, and the tenth transistor T10 are turned on, the high-level signal at the first power supply terminal V1 is written to the first signal output terminal OUT1 and the fourth node N4, and the low-level signal at the second power supply terminal V2 is written to the second signal output terminal OUT2. The signal at the third node N3 is high, the fifth transistor T5 and the eleventh transistor T11 are disconnected, and the signal at the third power supply terminal V3 cannot be written to the first node N1. The signal at the first node N1 remains high, and the high-level signal at the second clock signal terminal CK2 cannot be written to the first signal output terminal OUT1. Because the signal at the second clock signal terminal CK2 is high, the seventh transistor T7 is disconnected. In this stage, the signal at the second node N2 is low, and the signals at the first node N1, the third node N3, and the fourth node N4 are high. The signal at the first power supply terminal V1 is written to the first signal output terminal OUT1, and the output signal of the first signal output terminal OUT1 is high. The signal at the second power supply terminal V2 is written to the second signal output terminal OUT2, and the output signal of the second signal output terminal OUT2 is low.

[0218] The working process of the shift register unit includes: a plurality of third stages S3 and fourth stages S4, and the third stages S3 and the fourth stages S4 work alternately.

[0219] The shift register unit provided in Figure 15 is different from the shift register unit provided in Figure 14 in that the nodes to which the control electrode of the eleventh transistor is connected are different. Figure 14 is illustrated by taking the control electrode of the eleventh transistor being connected to the third node as an example, and Figure 15 is illustrated by taking the control electrode of the eleventh transistor being connected to the first node. Since the signals of the first node N1 and the third node N3 are both high-level signals or both low-level signals, that is, the eleventh transistor in the shift register units provided in Figures 14 and 15 is turned on or turned off at the same time, the working process of the shift register unit provided in Figure 15 is the same as that of the shift register unit provided in Figure 14.

[0220] The difference between the shift register unit provided in Figure 16 and the shift register unit provided in Figure 14 is that the shift register unit provided in Figure 16 also includes: a twelfth transistor T12. Since the twelfth transistor T12 is turned on, the second transistor T12 can be equivalent to a section of wire and will not affect the working process of other transistors of the shift register unit. Therefore, the working process of the shift register unit provided in Figure 16 is the same as that of the shift register unit provided in Figure 14.

[0221] The difference between the shift register unit provided in Figures 17 and 18 and the shift register unit provided in Figure 15 is that the shift register unit provided in Figures 17 and 18 also includes: a twelfth transistor T12. Since the twelfth transistor T12 is turned on, the second transistor T12 can be equivalent to a section of wire and will not affect the working process of other transistors of the shift register unit. Therefore, the working process of the shift register unit provided in Figures 17 and 18 is the same as that of the shift register unit provided in Figure 15.

[0222] The setting of the eleventh transistor T11 in the present disclosure can pull the first node N1 down to the signal of the third power supply terminal V3 with a lower voltage value, thereby improving the conduction degree of the ninth transistor T9, so that the fifth transistor T5 and the ninth transistor T9 can be fully turned on.

[0223] FIG21 is a comparison diagram of the signals of the first node and the second signal output terminal of different shift register units. In FIG21, N1-1 and OUT2-1 refer to the first node and the second signal output terminal of any one of the shift register units in FIG14 to FIG18 provided in the present application, respectively, and N1-2 and OUT2-2 refer to the first node and the second signal output terminal of the shift register unit in which the transistors only include the first transistor to the tenth transistor, respectively. As shown in FIG21, during the output phase and part of the output phase, the voltage value of the signal of N1-1 is less than the voltage value of the signal of N1-2, and the rising edge duration of the signal of OUT2-1 is less than the rising edge duration of the signal of OUT2-2, that is, the shift register unit provided by the present disclosure can increase the voltage value of the output signal of the second signal output terminal, thereby improving the performance of the shift register unit.

[0224] The embodiment of the present disclosure further provides a driving method of a shift register unit, which is configured to drive the shift register unit. The driving method of the shift register unit may include the following steps:

[0225] Step 100: Under the control of the first clock signal terminal and the second clock signal terminal, the node control subcircuit provides a signal from the signal input terminal or the first power terminal to the first node, and provides a signal from the second power terminal or the first clock signal terminal to the second node.

[0226] Step 200: The pull-down sub-circuit provides a signal of the third power terminal to the first node.

[0227] Step 300: The output sub-circuit provides a first power supply terminal or a second clock signal terminal to a first signal output terminal under the control of signals at a first node and a second node.

[0228] The shift register unit is the shift register unit provided by any of the aforementioned embodiments, and its implementation principle and implementation effect are similar, which will not be described in detail here.

[0229] In an exemplary embodiment, the driving method of the shift register unit may further include: the output subcircuit providing a signal from the second power supply terminal or the third clock signal terminal to the second signal output terminal under control of the signals from the first node and the second node.

[0230] In an exemplary embodiment, the shift register unit may further include an output control subcircuit; and the driving method of the shift register unit may further include the output control subcircuit storing a voltage difference between a signal at the first signal output terminal and a signal at the first power supply terminal.

[0231] The present disclosure also provides a display device. Figure 22 is a schematic diagram of the structure of a display device. As shown in Figure 22, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a display substrate. The display substrate includes a pixel array, wherein the timing controller is connected to the data driver, the scan driver, and the light-emitting driver, respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn), the scan driver is connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, and the pixel driving circuit may be connected to the scan signal lines, the light-emitting signal lines, and the data signal lines, respectively. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number. The scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register unit and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number. The light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register unit and may generate an emission signal in a manner such that an emission stop signal provided in the form of an off-level pulse is sequentially transmitted to a next-stage circuit under the control of a clock signal. o may be a natural number.

[0232] In an exemplary embodiment, the display device may be a liquid crystal display (LCD) or an organic light emitting diode (OLED) display device. The display device may be any product or component with a display function, such as an LCD panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system.

[0233] Figure 23 is a schematic diagram of a planar structure of a display substrate (I), Figure 24 is a schematic diagram of a planar structure of a display substrate (II), and Figure 25 is a schematic diagram of a planar structure of a display substrate (III). As shown in Figures 23 to 25, the display substrate may include a plurality of pixel units P arranged in a matrix. The plurality of pixel units P include a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and at least one third subpixel P3 that emits a third color light. The first subpixel P1, the second subpixel P2, and the third subpixel P3 each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first subpixel P1, the second subpixel P2 and the third subpixel P3 are respectively connected to the pixel driving circuits of the subpixels, and the light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuits of the subpixels.

[0234] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, and the third subpixel P3 may be a green subpixel (G) that emits green light. In an exemplary embodiment, the subpixels may be rectangular, diamond-shaped, pentagonal, or hexagonal, and the three subpixels may be arranged horizontally, vertically, or in a triangular pattern, although this disclosure is not limited thereto.

[0235] In exemplary embodiments, as shown in Figures 23 and 25 , a pixel unit may include three sub-pixels, which may be arranged horizontally, vertically, or in a herringbone pattern, without limitation in this disclosure. Figure 23 illustrates the arrangement in a horizontally parallel manner, while Figure 25 illustrates the arrangement in a herringbone pattern.

[0236] In an exemplary embodiment, as shown in FIG24 , a pixel unit may include four sub-pixels, which may be a first sub-pixel, a second sub-pixel, and two third sub-pixels. The four sub-pixels may be arranged horizontally, vertically, or in a square pattern, which is not limited in this disclosure. FIG24 illustrates an example of a square pattern of four sub-pixels.

[0237] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a stacked electrode (anode), an organic light emitting layer, and a second electrode (cathode).

[0238] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0239] In an exemplary embodiment, the display substrate is an LTPO display substrate.

[0240] FIG26A is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG26A , the pixel driving circuit may include seven transistors (first transistor M1 to seventh transistor M7) and one capacitor C.

[0241] As shown in Figure 26A, the gate electrode of the first transistor M1 is electrically connected to the reset signal line Reset, the first electrode of the first transistor M1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor M1 is electrically connected to the first node N1; the gate electrode of the second transistor M2 is electrically connected to the second scan signal line Gate2, the first electrode of the second transistor M2 is electrically connected to the first node N1, and the second electrode of the second transistor M2 is electrically connected to the third node N3; the gate electrode of the third transistor M3 is electrically connected to the first node N1, the first electrode of the third transistor M3 is electrically connected to the second node N2, and the second electrode of the third transistor M3 is electrically connected to the third node N3; the gate electrode of the fourth transistor M4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor M4 is electrically connected to the data signal line Data, and the The second electrode of the fourth transistor M4 is electrically connected to the second node N2; the gate electrode of the fifth transistor M5 is electrically connected to the light-emitting signal line EM, the first electrode of the fifth transistor M5 is electrically connected to the high-level power supply line VDD, and the second electrode of the fifth transistor M5 is electrically connected to the second node N2; the gate electrode of the sixth transistor M6 is electrically connected to the light-emitting signal line EM, the first electrode of the sixth transistor M6 is electrically connected to the third node N3, and the second electrode of the sixth transistor M6 is electrically connected to the fourth node N4; the gate electrode of the seventh transistor M7 is electrically connected to the first scanning signal line Gate1, the first electrode of the seventh transistor M7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor M7 is electrically connected to the fourth node N4; the first plate of the capacitor C is electrically connected to the first node N1, and the second plate of the capacitor C is electrically connected to the high-level power supply line VDD.

[0242] In an exemplary embodiment, the first transistor M1 to the seventh transistor M7 may be low-temperature polysilicon thin-film transistors, or may be oxide thin-film transistors, or may be low-temperature polysilicon thin-film transistors and oxide thin-film transistors. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form an LTPO display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0243] In an exemplary embodiment, the first transistor M1 and the second transistor M2 are of opposite transistor types to the third transistor M3 to the seventh transistor M7. For example, the first transistor M1 and the second transistor M2 may be N-type transistors, and the third transistor M3 to the seventh transistor M7 may be P-type transistors.

[0244] In example embodiments, the first and second transistors M1 and M2 may be oxide transistors, and the third to seventh transistors M3 to M7 may be low-temperature polysilicon transistors.

[0245] In an exemplary embodiment, the voltage value of the signal of the first initial signal line INIT1 is constant and is a DC signal. The voltage value of the signal of the first initial signal line INIT1 may be -3V.

[0246] In an exemplary embodiment, the voltage value of the signal of the second initial signal line INIT2 is constant and is a DC signal. The voltage value of the signal of the second initial signal line INIT2 may be 0V.

[0247] In an exemplary embodiment, the light emitting device L′ may be electrically connected to the fourth node N4 and the low-level power line VSS, respectively.

[0248] In an exemplary embodiment, the high-level power line VDD continuously provides a high-level signal, and the low-level power line VSS continuously provides a low-level signal.

[0249] FIG26B is a timing diagram of the operation of the pixel driving circuit provided in FIG26A. The following illustrates an exemplary embodiment of the present disclosure through the operation process of the pixel driving circuit illustrated in FIG26A during the display phase. FIG26B is illustrated by taking the first transistor M1 and the second transistor M2 as N-type transistors, and the third transistor M3 to the seventh transistor M7 as P-type transistors as an example. The pixel driving circuit in FIG26B includes the first transistor M1 to the seventh transistor M7, a capacitor C, and eight signal lines (data signal line Data, a first scan signal line Gate1, a second scan signal line Gate2, a reset signal line Reset, a first initial signal line INIT1, a second initial signal line INIT2, an emitting signal line EM, and a high-level power line VDD).

[0250] 26A and 26B , the operation process of the pixel driving circuit may include:

[0251] The first stage P1 is called the initialization stage. The signal of the reset signal line Reset is a high-level signal, the first transistor M1 is turned on, and the signal of the first initial signal line INIT1 is written into the first node N1 through the turned-on first transistor M1, initializing (resetting) the first node N1, clearing the pre-stored voltage inside it, and completing the initialization.

[0252] In the second phase P2, also known as the data writing phase or the threshold compensation phase, the first scanning signal line Gate1 is a low-level signal, the second scanning signal line Gate2 is a low-level signal, and the data signal line Data outputs a data voltage. During this phase, the third transistor M3 is turned on because the first node N1 is a low-level signal. The signal of the first scan signal line Gate1 is a low-level signal, the fourth transistor M4 is turned on, and the seventh transistor M7 is turned on. The signal of the second scan signal line Gate2 is a high-level signal, and the second transistor M2 is turned on. The data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor M4, the second node N2, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor M3. The seventh transistor M7 is turned on, and the signal of the second initial signal line INIT2 is written into the fourth node N4 through the turned-on seventh transistor M7, thereby initializing (resetting) the first electrode of the light-emitting device L, clearing the pre-stored voltage therein, and completing the initialization.

[0253] In the third stage P3, referred to as the light-emitting stage, the signal of the light-emitting signal line EM is a low-level signal, the fifth transistor M5 and the sixth transistor M6 are turned on, and the power supply voltage output by the high-level power line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, thereby driving the light-emitting device L to emit light.

[0254] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the gate electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is: I=K*(Vgs-Vth)2=K*[(Vdd-Vd+|Vth|)-Vth]2=K*(Vdd-Vd)2

[0255] Wherein, I is the driving current flowing through the third transistor M3, that is, the driving current driving the light-emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0256] In an exemplary embodiment, FIG27A is a schematic diagram of an equivalent circuit of another pixel driving circuit. As shown in FIG27A , the pixel driving circuit may include eight transistors (first transistor M1 to eighth transistor M8), one capacitor C, and nine signal lines (data signal line Data, control signal line Scan, scan signal line Gate, reset signal line Reset, emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, high-level power line VDD, and low-level power line VSS).

[0257] In an exemplary embodiment, a first plate of capacitor C is connected to a high-level power supply line VDD, and a second plate of capacitor C is connected to a first node N1. A control electrode of first transistor M1 is connected to reset signal line Reset, a first electrode of first transistor M1 is connected to a first initialization signal line INIT1, and a second electrode of first transistor M1 is connected to a fourth node N4. A control electrode of second transistor M2 is connected to scan signal line Gate, a first electrode of second transistor M2 is connected to a fourth node N4, and a second electrode of second transistor M2 is connected to a second node N2. A control electrode of third transistor M3 is connected to first node N1, a first electrode of third transistor M3 is connected to a second node N2, and a second electrode of third transistor M3 is connected to a third node N3. A control electrode of fourth transistor M4 is connected to scan signal line Gate, a first electrode of fourth transistor M4 is connected to a data signal line Data, and a second electrode of fourth transistor M4 is connected to a third node N3. A control electrode of fifth transistor M5 is connected to emission signal line EM, a first electrode of fifth transistor M5 is connected to a high-level power supply line VDD, and a second electrode of fifth transistor M5 is connected to a third node N3. A control electrode of the sixth transistor M6 is connected to the light emitting signal line EM, a first electrode of the sixth transistor M6 is connected to the second node N2, and a second electrode of the sixth transistor M6 is connected to the first electrode of the light emitting device L. A control electrode of the seventh transistor M7 is connected to the reset signal line Reset, a first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, a second electrode of the seventh transistor M7 is connected to the first electrode of the light emitting device L, and a second electrode of the light emitting device L is connected to the low-level power supply line VSS. A control electrode of the eighth transistor M8 is connected to the control signal line Scan, a first electrode of the eighth transistor M8 is connected to the first node N1, and a second electrode of the eighth transistor M8 is connected to the fourth node N4.

[0258] In an exemplary embodiment, the control electrode of the seventh transistor M7 may also be connected to the scan signal line Gate, the first electrode of the seventh transistor M7 is connected to the second initial signal line INIT2, the second electrode of the seventh transistor M7 is connected to the first electrode of the light-emitting device L, and the second electrode of the light-emitting device L is connected to the low-level power line VSS.

[0259] In an exemplary embodiment, the signal of the high-level power line VDD is a continuously provided high-level signal, and the signal of the low-level power line VSS is a low-level signal.

[0260] In an exemplary embodiment, the eighth transistor M8 is a metal oxide transistor and is an N-type transistor, and the first to seventh transistors M1 to M7 are low-temperature polysilicon transistors and are P-type transistors.

[0261] In an exemplary embodiment, the eighth transistor M8 is an oxide transistor, which can reduce leakage current, improve the performance of the pixel driving circuit, and reduce the power consumption of the pixel driving circuit.

[0262] FIG27B is a timing diagram of the operation of the pixel driving circuit provided in FIG27A. The following describes an exemplary embodiment of the present disclosure through the operation process of the pixel driving circuit illustrated in FIG27B. The operation process of the pixel driving circuit may include:

[0263] The first phase A1 is called the reset phase. The signals on the control signal line Scan, the emission signal line EM, and the scan signal line Gate are all high-level signals, and the signal on the reset signal line Reset is low-level. The reset signal line Reset is low-level, the first transistor M1 is turned on, the signal on the first initialization signal line INIT1 is supplied to the fourth node N4, the seventh transistor M7 is turned on, and the initial voltage on the second initialization signal line INIT2 is supplied to the first electrode of the light-emitting device L, initializing (resetting) the first electrode of the light-emitting device L. For example, the pre-stored voltage within the first electrode is cleared, completing the initialization and ensuring that the light-emitting device L does not emit light. The signal on the control signal line Scan is high-level, the eighth transistor M8 is turned on, and the signal on the fourth node N4 is supplied to the first node N1, initializing the capacitor C and clearing the existing data voltage in the capacitor C. The signals on the scan signal line Gate and the emission signal line EM are high-level signals, and the second transistor M2, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are turned off. During this phase, the light-emitting device L does not emit light.

[0264] In the second phase A2, also known as the data writing phase or threshold compensation phase, the signal on the scan signal line Gate is a low-level signal, the signals on the reset signal line Reset, the luminescence signal line EM, and the control signal line Scan are high-level signals, and the data signal line Data outputs a data voltage. During this phase, since the first node N1 is a low-level signal, the third transistor M3 is turned on. The signal on the scan signal line Gate is a low-level signal, the second transistor M2 and the fourth transistor M4 are turned on, the signal on the control signal line Scan is a high-level signal, and the eighth transistor M8 is turned on. The second transistor M2, the fourth transistor M4, and the eighth transistor M8 are turned on, so that the data voltage output by the data signal line Data is provided to the first node N1 through the third node N3, the turned-on third transistor M3, the second node N2, the turned-on second transistor M2, the fourth node N4, and the turned-on eighth transistor M8. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the capacitor C until the voltage at the first node N1 reaches Vd-|Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor M3. The signal of the reset signal line Reset is a low-level signal, and the first transistor M1 and the seventh transistor M7 are turned off. The signal of the emission signal line EM is a high-level signal, and the fifth transistor M5 and the sixth transistor M6 are turned off.

[0265] In the third phase A3, known as the light-emitting phase, the signals on the control signal line Scan and the light-emitting signal line EM are both low-level signals, while the signals on the scan signal line Gate and the reset signal line Reset are high-level signals. The reset signal line Reset is also low-level, and the first transistor M1 and the seventh transistor M7 are turned off. The control signal line Scan is low-level, while the signals on the scan signal line Gate and the reset signal line Reset are high-level signals. The second transistor M2, the fourth transistor M4, and the eighth transistor M8 are turned off. The signal on the light-emitting signal line EM is low-level, and the fifth transistor M5 and the sixth transistor M6 are turned on. The power supply voltage output from the high-level power supply line VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, driving the light-emitting device L to emit light.

[0266] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor M3 is: I = K*(Vgs-Vth)2 = K*[(Vdd-Vd+|Vth|)-Vth]2 = K*(Vdd-Vd)2

[0267] Among them, I is the driving current flowing through the third transistor M3, which is also the driving current for driving the light-emitting device L. K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the high-level power supply line VDD.

[0268] The display substrate provided by the embodiments of the present disclosure may include: a substrate, and sub-pixels, gate lines, and a gate driving circuit provided on the substrate. The substrate is provided with a display area and a non-display area. The gate driving circuit is located in the non-display area, and the sub-pixels and gate lines are located in the display area. The gate lines are electrically connected to the sub-pixels and the gate driving circuit respectively.

[0269] In an exemplary embodiment, the sub-pixel includes: a pixel driving circuit and a light-emitting device. When the pixel driving circuit is the pixel driving circuit provided in FIG. 26A, the gate line may include: at least one of a reset signal line, a first scan signal line, a second scan signal line, and a light-emitting signal line.

[0270] In an exemplary embodiment, the sub-pixel includes: a pixel driving circuit and a light-emitting device. When the pixel driving circuit is the pixel driving circuit provided in FIG. 27A, the gate line may include: at least one of a reset signal line, a first scan signal line, a second scan signal line, a control signal line, and a light-emitting signal line.

[0271] The shift register unit is the shift register unit provided in any of the foregoing embodiments, and the implementation principle and implementation effect are similar, which will not be elaborated here.

[0272] FIG. 28 is a schematic diagram of the cascade of the gate driving circuit I, and FIG. 29 is a schematic diagram of the cascade of the gate driving circuit II. As shown in FIGS. 28 and 29, the first signal output terminal OUT1 of the i-th stage shift register unit GOA(i) is connected to the signal input terminal IN of the (i + 1)-th stage shift register unit GOA(i + 1), where 1 ≤ i < N, and N is the total number of stages of the shift register unit. Among them, FIG. 28 is described by taking the shift register unit provided in FIGS. 12 and 13 as an example, and FIG. 29 is described by taking the shift register unit provided in FIGS. 14 to 18 as an example.

[0273] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. Among them, the rigid substrate may be, but is not limited to, one or more of glass and conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0274] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The first and second inorganic material layers may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: first coating a layer of polyimide on a glass carrier, and forming a first flexible (PI1) layer after curing; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing a layer of amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating the amorphous silicon layer with another layer of polyimide, and forming a second flexible (PI2) layer after curing; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thereby completing the preparation of the substrate.

[0275] In an exemplary embodiment, as shown in FIG. 28 , the first signal output terminal OUT1 of the shift register unit may be electrically connected to the gate line.

[0276] In an exemplary embodiment, as shown in FIG. 29 , the second signal output terminal OUT2 of the shift register unit may be electrically connected to the gate line.

[0277] In an exemplary embodiment, FIG30 is a first schematic structural diagram of a display substrate, and FIG31 is a second schematic structural diagram of a display substrate. FIG30 is illustrated using the shift register unit shown in FIG12 as an example, while FIG31 is illustrated using the shift register unit shown in FIG18 as an example. As shown in FIG28 to FIG31 , the display substrate may further include: an initial signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a first power line VGH, a second power line VGL1, and a third power line VGL2, disposed on the substrate and located in a non-display area.

[0278] In an exemplary embodiment, the signal input terminal IN of the first-stage shift register unit GOA(1) is electrically connected to the initial signal line STV, the first power supply terminal of the i-th stage shift register unit is electrically connected to the first power supply line VGH, the second power supply terminal of the i-th stage shift register unit is electrically connected to the second power supply line VGL1, and the third power supply terminal of the i-th stage shift register unit is electrically connected to the third power supply line VGL2.

[0279] In an exemplary embodiment, any one of the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, the second power line VGL1, and the third power line VGL2 extends along a first direction D1, and the gate line extends along a second direction D2, and the first direction D1 intersects the second direction D2.

[0280] In an exemplary embodiment, as shown in Figures 30 and 31, the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2 and the first power line VGH are arranged in sequence along the direction close to the display area and are located on the side of the shift register unit away from the display area.

[0281] In an exemplary embodiment, as shown in FIG. 30 and FIG. 31 , the shift register unit includes a plurality of transistors, and the second power line VGL1 is located on a side of the first power line VGH close to the display area and between the plurality of transistors of the shift register unit.

[0282] In an exemplary embodiment, as shown in FIG30 and FIG31 , the third power line VGL2 is located on a side of the second power line VGL1 close to the display area, and its orthographic projection on the substrate partially overlaps with the orthographic projection of the shift register unit on the substrate.

[0283] In an exemplary embodiment, as shown in Figures 30 and 31, the shift register unit includes a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6, and a seventh transistor T7. At least a portion of any one of the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 is located between a first power line VGH and a second power line VGL1.

[0284] In an exemplary embodiment, as shown in FIG31 , the shift register unit includes: a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, an eleventh transistor T11, and a twelfth transistor T12, and the number of the second power line VGL1 is at least one, wherein at least a portion of any one of the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the eleventh transistor T11, and the twelfth transistor T12 is located on a side of the second power line VGL1 close to the display area.

[0285] In an exemplary embodiment, as shown in FIG. 30 and FIG. 31 , the shift register unit includes: a second capacitor C2 ; the second capacitor C2 is located on a side of the third power line VGL2 close to the display area.

[0286] In an exemplary embodiment, as shown in FIG. 31 , the display substrate may further include a third clock signal line CLK3 and a fourth clock signal line CLK4 disposed on the base and located in the non-display area, wherein either one of the third clock signal line CLK3 and the fourth clock signal line CLK4 extends along the first direction D1 .

[0287] In an exemplary embodiment, as shown in FIG31 , the number of the second power lines VGL1 is two, the second power line VGL1 close to the display area is located on a side of any one of the third clock signal line CLK3 and the fourth clock signal line CLK4 close to the display area, and the second power line VGL1 away from the display area is located between the first power line VGH and the third power line VGL2.

[0288] In an exemplary embodiment, as shown in FIG31 , the shift register unit includes a fourth transistor T4, a fifth transistor T5, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a fourth capacitor C4. The fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the eleventh transistor T11, and the twelfth transistor T12 are located between the second power line VGL1 and any one of the third clock signal line CLK3 and the fourth clock signal line CLK4, which are located away from the display area. The ninth transistor T9 and the tenth transistor T10 are located on a side of the second power line VGL1 close to the display area.

[0289] In an exemplary embodiment, as shown in FIG. 31 , an orthographic projection of the second power line VGL1 close to the display area on the substrate partially overlaps with an orthographic projection of the fourth capacitor C4 on the substrate.

[0290] In an exemplary embodiment, as shown in Figures 28 to 31, the first clock signal terminal CK1 of the i-th stage shift register unit is electrically connected to one of the first clock signal line CLK1 and the second clock signal line CLK2, and the second clock signal terminal CK2 of the i-th stage shift register unit is electrically connected to the other of the first clock signal line CLK1 and the second clock signal line CLK2; the first clock signal terminals of adjacent shift register units are connected to different signal lines, and the second clock signal terminals of adjacent shift register units are connected to different signal lines. For example, for example, the first clock signal terminal CK1 of the odd-numbered shift register unit can be electrically connected to the first clock signal line CLK1, the second clock signal terminal CK2 of the odd-numbered shift register unit can be electrically connected to the second clock signal line CLK2, the first clock signal terminal CK1 of the even-numbered shift register unit can be electrically connected to the second clock signal line CLK2, the second clock signal terminal CK2 of the even-numbered shift register unit can be electrically connected to the first clock signal line CLK1, or the first clock signal terminal CK1 of the odd-numbered shift register unit can be electrically connected to the second clock signal line CLK2, the second clock signal terminal CK2 of the odd-numbered shift register unit can be electrically connected to the first clock signal line CLK1, and the The first clock signal terminal CK1 of the even-numbered shift register unit can be electrically connected to the first clock signal line CLK1, and the second clock signal terminal CK2 of the even-numbered shift register unit can be electrically connected to the second clock signal line CLK2. Figures 28 and 29 are illustrated by the example that the first clock signal terminal CK1 of the odd-numbered shift register unit can be electrically connected to the first clock signal line CLK1, the second clock signal terminal CK2 of the odd-numbered shift register unit can be electrically connected to the second clock signal line CLK2, the first clock signal terminal CK1 of the even-numbered shift register unit can be electrically connected to the second clock signal line CLK2, and the second clock signal terminal CK2 of the even-numbered shift register unit can be electrically connected to the first clock signal line CLK1.

[0291] In an exemplary embodiment, as shown in Figures 29 and 31, the third clock signal terminal CK3 of the i-th shift register unit is electrically connected to one of the third clock signal line CLK3 and the fourth clock signal line CLK4, and the third clock signal terminal CK3 of the (i+1)-th shift register unit is electrically connected to the other of the third clock signal line CLK3 and the fourth clock signal line CLK4. Exemplarily, the third clock signal terminal CK3 of the odd-numbered shift register unit is electrically connected to the third clock signal line CLK3, and the third clock signal terminal CK3 of the even-numbered shift register unit is electrically connected to the fourth clock signal line CLK4, or the third clock signal terminal CK3 of the odd-numbered shift register unit is electrically connected to the fourth clock signal line CLK4, and the third clock signal terminal CK3 of the even-numbered shift register unit is electrically connected to the third clock signal line CLK3. 29 illustrates an example in which the third clock signal terminal CK3 of the odd-numbered shift register unit is electrically connected to the third clock signal line CLK3 and the third clock signal terminal CK3 of the even-numbered shift register unit is electrically connected to the fourth clock signal line CLK4.

[0292] In an exemplary embodiment, as shown in FIG. 30 and FIG. 31 , an orthographic projection of the third power line VGL2 on the substrate partially overlaps with an orthographic projection of the fourth transistor T4 and the fifth transistor T5 on the substrate.

[0293] In an exemplary embodiment, as shown in Figures 30 and 31, the active layer T81 of the eighth transistor T8 extends along the second direction D2, any one of the first electrode T83 and the second electrode T84 of the eighth transistor T8 extends along the first direction D1, and the gate electrode T82 of the eighth transistor T8 at least partially extends along the first direction D1.

[0294] In an exemplary embodiment, as shown in Figures 30 and 31, the gate electrode T112 of the eleventh transistor is an integral structure with the gate electrode T52 of the fifth transistor, the orthographic projection of the first electrode T113 of the eleventh transistor on the substrate partially overlaps with the orthographic projection of the third power line VGL2 on the substrate, and is electrically connected to the third power line VGL2, and the second electrode T114 of the eleventh transistor is an integral structure with the first electrode T83 of the eighth transistor and the first electrode T123 of the twelfth transistor.

[0295] In an exemplary embodiment, as shown in FIG. 31 , a width of any one of the first power line VGH, the second power line VGL1, and the third power line VGL2 along the second direction D2 is smaller than a width of any one of the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4 along the second direction D2.

[0296] In an exemplary embodiment, since the signals of the clock signal lines are AC signals, a wider width of any one of the first clock signal line CLK1 , the second clock signal line CLK2 , the third clock signal line CLK3 and the fourth clock signal line CLK4 along the second direction D2 can reduce the load of the clock signal lines.

[0297] In an exemplary embodiment, a channel width of an active layer of the tenth transistor is greater than a channel width of an active layer of the fourth transistor.

[0298] In an exemplary embodiment, the channel width of the active layer of the tenth transistor is not less than 90 micrometers. Exemplarily, the channel width of the active layer of the tenth transistor may be approximately 100 micrometers.

[0299] In example embodiments, a channel length of the active layer of the tenth transistor may be approximately 3.5 micrometers, and a channel width-to-length ratio of the active layer of the tenth transistor may be approximately 100 / 3.5.

[0300] In an exemplary embodiment, the channel width of the active layer of the fourth transistor is no greater than 50 micrometers. Exemplarily, the channel width of the active layer of the fourth transistor may be approximately 25 micrometers.

[0301] In example embodiments, a channel length of the active layer of the fourth transistor may be approximately 3.5 micrometers, and a channel width-to-length ratio of the active layer of the fourth transistor may be approximately 25 / 3.5.

[0302] In an exemplary embodiment, a channel width of an active layer of the ninth transistor is greater than a channel width of an active layer of the fifth transistor.

[0303] In an exemplary embodiment, the channel width of the active layer of the ninth transistor is not less than 90 micrometers. Exemplarily, the channel width of the active layer of the ninth transistor may be approximately 100 micrometers.

[0304] In example embodiments, a channel length of the active layer of the ninth transistor may be approximately 3.5 micrometers, and a channel width-to-length ratio of the active layer of the ninth transistor may be approximately 100 / 3.5.

[0305] In an exemplary embodiment, the channel width of the active layer of the fifth transistor is no greater than 50 micrometers. Exemplarily, the channel width of the active layer of the fifth transistor may be approximately 25 micrometers.

[0306] In example embodiments, a channel length of the active layer of the fifth transistor may be approximately 3.5 micrometers, and a channel width-to-length ratio of the active layer of the fifth transistor may be approximately 25 / 3.5.

[0307] In an exemplary embodiment, the display substrate may further include: a driving structure layer disposed on the base; the driving structure layer includes: a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially stacked on the base; the shift register unit includes: a plurality of transistors and a plurality of capacitors, each capacitor including: a first plate and a second plate;

[0308] The semiconductor layer includes at least: an active layer of a plurality of transistors located in at least one shift register unit;

[0309] The first conductive layer at least includes: control electrodes of a plurality of transistors located in at least one shift register unit and first plates of a plurality of capacitors;

[0310] The second conductive layer includes at least: second plates of a plurality of capacitors located in at least one shift register unit;

[0311] The third conductive layer at least includes: an initial signal line, a first clock signal line, a second clock signal line, a first power line, a second power line, a third clock signal line, a fourth clock signal line, and first electrodes and second electrodes of a plurality of transistors located in at least one shift register unit;

[0312] The fourth conductive layer at least includes: a third power line.

[0313] In an exemplary embodiment, the driving structure layer may further include: a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer and a flat layer, wherein the first insulating layer is located between the semiconductor layer and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, the third insulating layer is located between the second conductive layer and the third conductive layer, the fourth insulating layer is located between the third conductive layer and the fourth conductive layer, the fifth insulating layer is located on the side of the fourth conductive layer away from the substrate, and the flat layer is located on the side of the fifth insulating layer away from the substrate.

[0314] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0315] (1) Forming a semiconductor layer pattern on a substrate, including: depositing a semiconductor thin film on the substrate, and patterning the semiconductor thin film through a patterning process to form a semiconductor layer pattern. As shown in Figures 32 and 33, Figure 32 is a schematic diagram of Figure 30 after the semiconductor layer pattern is formed, and Figure 33 is a schematic diagram of Figure 31 after the semiconductor layer pattern is formed.

[0316] In an exemplary embodiment, as shown in FIG. 32 , the semiconductor layer pattern may include active layers T11 to T81 of first to eighth transistors and T111 of an eleventh transistor of at least one shift register unit, and an active link block AL.

[0317] In an exemplary embodiment, as shown in FIG. 33 , the semiconductor layer pattern may include active layers T11 to T121 of first to twelfth transistors of at least one shift register cell and an active link block AL.

[0318] In an exemplary embodiment, as shown in Figures 32 and 33, the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor are integrally formed, and the active layer T61 of the sixth transistor and the active layer T71 of the seventh transistor are integrally formed. The active layer T11 of the first transistor, the active layer T21 of the second transistor, the active layer T31 of the third transistor, the active layer T81 of the eighth transistor, the active layer T111 of the eleventh transistor, and the active connection block AL may be provided separately.

[0319] In an exemplary embodiment, as shown in FIG. 33 , the active layer T91 of the ninth transistor and the active layer T101 of the fourth transistor are an integrated structure, and the active layer T121 of the twelfth transistor may be provided separately.

[0320] In an exemplary embodiment, as shown in Figures 32 and 33, the active layer T11 of the first transistor and the active layer T61 of the sixth transistor (also the active layer T71 of the seventh transistor) are arranged along the second direction D2, and the active layer T11 of the first transistor of the current shift register unit is located on the side of the active layer T61 of the sixth transistor (also the active layer T71 of the seventh transistor) of the current shift register unit that is closer to the shift register unit of the previous stage. The active layer T21 of the second transistor is located on the side of the active layer T11 of the first transistor that is closer to the display area. The active layer T31 of the third transistor and the active connection block AL are arranged along the second direction D2 and are located on the side of the active layer T21 of the second transistor that is closer to the display area. The active layer T81 of the eighth transistor, the active layer T111 of the eleventh transistor, and the active layer T41 of the fourth transistor (also the active layer T51 of the fifth transistor) are arranged in sequence along the second direction D2 and are located on a side of the active layer T31 of the third transistor close to the display area, wherein the active layer T111 of the eleventh transistor of the shift register unit at this level is located on a side of the active layer T81 of the eighth transistor of the shift register unit at this level close to the shift register unit at the next level, and the active layer T41 of the fourth transistor of the shift register unit at this level (also the active layer T51 of the fifth transistor) is located on a side of the active layer T111 of the eleventh transistor of the shift register unit at this level close to the shift register unit at the next level.

[0321] In an exemplary embodiment, as shown in Figure 33, the active layer T121 of the twelfth transistor of the shift register unit at this level is located on the side of the active layer T81 of the eighth transistor of the shift register unit at this level close to the shift register unit at the previous level, and the active layer of the ninth transistor of the shift register unit at this level (which is also the active layer of the fourth transistor) is located on the side of the active layer T41 of the fourth transistor (which is also the active layer T51 of the fifth transistor) close to the display area.

[0322] In an exemplary embodiment, as shown in Figures 32 and 33, the active layers T11 of the first transistor to T71 of the seventh transistor are strip-shaped and extend along a first direction D1. The active layers T81 of the eighth transistor and T11 of the eleventh transistor are strip-shaped and extend along a second direction D2. The active connection block AL may be block-shaped.

[0323] 32 and 33 , the active layer of the ninth transistor (also the active layer of the fourth transistor) is strip-shaped and extends along the first direction D1. The active layer T121 of the twelfth transistor is strip-shaped and extends along the second direction D2.

[0324] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. The first region and the second region will be conductive after the subsequent formation of the first conductive layer, and therefore can also be referred to as a conductive region. In an exemplary embodiment, the second region T61-2 of the active layer T61 of the sixth transistor can also serve as the first region T71-2 of the active layer T31 of the seventh transistor, the second region T41-2 of the active layer T41 of the fourth transistor can also serve as the second region T51-2 of the active layer T51 of the fifth transistor, and the second region T91-2 of the active layer T91 of the ninth transistor can also serve as the second region T101-2 of the active layer T101 of the fourth transistor. a first region T11-1 and a second region T11-2 of an active layer T11 of a first transistor, a first region T21-1 and a second region T21-2 of an active layer T21 of a second transistor, a first region T31-1 and a second region T31-2 of an active layer T31 of a third transistor, a first region T41-1 of an active layer T41 of a fourth transistor, a first region T51-1 of an active layer T51 of a fifth transistor, a first region T61-1 of an active layer T61 of a sixth transistor, and an active layer T71 of a seventh transistor. The second region T71-2 of the layer T71, the first region T81-1 and the second region T81-2 of the active layer T81 of the eighth transistor, the first region T91-1 of the active layer T91 of the ninth transistor, the first region T101-1 of the active layer T101 of the fourth transistor, the first region T111-1 and the second region T111-2 of the active layer T111 of the eleventh transistor, and the first region T121-1 and the second region T121-2 of the active layer T121 of the twelfth transistor can be set separately.

[0325] (2) forming a first conductive layer pattern, including: depositing a first insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first insulating film and the first conductive film through a patterning process to form a first insulating layer pattern and a first conductive layer pattern disposed on the first insulating layer pattern, as shown in Figures 34 to 37, wherein Figure 34 is a schematic diagram of the first conductive layer pattern in Figure 30, Figure 35 is a schematic diagram of Figure 30 after the first conductive layer pattern is formed, Figure 36 is a schematic diagram of the first conductive layer pattern in Figure 31, and Figure 37 is a schematic diagram of Figure 31 after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0326] In an exemplary embodiment, as shown in Figures 34 and 35, the first conductive layer pattern may include: the control electrode T12 of the first transistor to the control electrode T82 of the eighth transistor located in at least one shift register unit, the control electrode T112 of the eleventh transistor, the first electrode plate C21 of the second capacitor, and the first connecting line L1.

[0327] In an exemplary embodiment, as shown in Figures 36 and 37, the first conductive layer pattern may include: a control electrode T12 of the first transistor to a control electrode T122 of the twelfth transistor located in at least one shift register unit, a first plate C21 of the second capacitor, a first plate C41 of the fourth capacitor, and a first connecting line L1.

[0328] In an exemplary embodiment, as shown in Figures 34 to 37, the control electrode T12 of the first transistor and the control electrode T32 of the third transistor are integrated. The control electrode T52 of the fifth transistor, the control electrode T112 of the eleventh transistor, and the first electrode plate C21 of the second capacitor are integrated. The control electrode T42 of the fourth transistor and the control electrode T62 of the sixth transistor are integrated. The control electrode T22 of the second transistor, the control electrode T72 of the seventh transistor, the control electrode T82 of the eighth transistor, and the first connection line L1 can be provided separately.

[0329] In an exemplary embodiment, as shown in Figures 36 and 37, the control electrode T42 of the fourth transistor, the control electrode T62 of the sixth transistor, the control electrode T102 of the fourth transistor, and the first plate C41 of the fourth capacitor are integrally formed. The control electrode T82 of the eighth transistor and the control electrode T122 of the twelfth transistor are integrally formed. The control electrode T92 of the ninth transistor can be provided separately.

[0330] In an exemplary embodiment, as shown in Figures 34 to 37, the control electrode T12 of the first transistor includes a first connection portion T12A and a second connection portion T12B. The first connection portion T12A extends along a first direction D1, and the second connection portion T12B is shaped like a triangle (┐). The second connection portion T12B is connected to the middle portion of the first connection portion T12A. The control electrode T32 of the third transistor can be strip-shaped and extends along a second direction D2. The control electrode T32 of the third transistor is connected to the end of the second connection portion T12B.

[0331] In an exemplary embodiment, as shown in Figures 34 to 37, the shape of the first electrode C21 of the second capacitor can be square, the shape of the control electrode T52 of the fifth transistor is strip-shaped and extends along the second direction D2, the shape of the control electrode T112 of the eleventh transistor is "┌", and the control electrode T52 of the fifth transistor and the control electrode T112 of the eleventh transistor are located on the side of the first electrode C21 of the second capacitor away from the display area.

[0332] In an exemplary embodiment, as shown in FIG. 34 and FIG. 35 , the control electrode T42 of the fourth transistor (also the control electrode T62 of the sixth transistor) is shaped like a strip and extends along the second direction D2 .

[0333] In an exemplary embodiment, as shown in Figures 36 and 37 , the first plate C41 of the fourth capacitor can be square in shape. The control electrode T102 of the fourth transistor includes a plurality of first branch segments T102A, each extending along the second direction D2 and arranged along the first direction D1. The control electrode T62 of the sixth transistor and the control electrode T42 of the fourth transistor are located on a side of the first plate C41 of the fourth capacitor away from the display area, while the control electrode T102 of the fourth transistor is located on a side of the first plate C41 of the fourth capacitor closer to the display area. Figures 36 and 37 illustrate this using two first branch segments T102A as an example.

[0334] In an exemplary embodiment, as shown in FIG. 34 to FIG. 37 , the control electrode T82 of the eighth transistor may be shaped like a groove with an opening facing upward.

[0335] In an exemplary embodiment, as shown in FIG. 36 and FIG. 37 , the control electrode T122 of the twelfth transistor is shaped like a strip and extends along the first direction D1 .

[0336] In an exemplary embodiment, as shown in Figures 36 and 37 , the control electrode T92 of the ninth transistor includes a second connecting segment T92A and a plurality of second branch segments T92B. The second connecting segment T92A is shaped like a Chinese character "┐" (┐), the second branch segments T92B extend along the second direction D2, and the plurality of second branch segments T92B are arranged along the first direction D1. The second connecting segment T92A is equivalent to the back of a comb, and the plurality of second branch segments T92B are equivalent to the teeth of a comb.

[0337] In example embodiments, as shown in FIG. 34 to FIG. 37 , the control electrode T22 of the second transistor, the control electrode T72 of the seventh transistor, and the first connection line L1 may be strip-shaped and at least partially extend along the second direction D2 .

[0338] In an exemplary embodiment, the first connection segment T12A and the second connection segment T12B of the control electrode T12 of the first transistor are respectively arranged across the active layer of the first transistor, the control electrode T22 of the second transistor is arranged across the active layer of the second transistor, the control electrode T32 of the third transistor is arranged across the active layer of the third transistor, the control electrode T42 of the fourth transistor is arranged across the active layer of the fourth transistor, the control electrode T52 of the fifth transistor is arranged across the active layer of the fifth transistor, the control electrode T62 of the sixth transistor is arranged across the active layer of the sixth transistor, and the control electrode T72 of the seventh transistor is arranged across the active layer of the seventh transistor. On the active layer of the transistor, the control electrode T82 of the eighth transistor is arranged across the active layer of the eighth transistor, the multiple second branch segments T92B of the control electrode T92 of the ninth transistor are arranged across the active layer of the ninth transistor, the multiple first branch segments T102A of the control electrode T102 of the fourth transistor are arranged across the active layer of the fourth transistor, the control electrode T112 of the eleventh transistor is arranged across the active layer of the eleventh transistor, and the control electrode T122 of the twelfth transistor is arranged across the active layer of the twelfth transistor. That is, the extension direction of the control electrode of at least one transistor is perpendicular to the extension direction of the active layer.

[0339] In an exemplary embodiment, this process also includes a conductorization process. After forming the first conductive layer, the semiconductor layer in the region shielded by the control electrodes of multiple transistors (i.e., the region where the semiconductor layer and the control electrodes overlap) is used as the channel region of the transistors. The semiconductor layer in the region not shielded by the first conductive layer is processed into a conductorized layer to form the electrode connection portion of the transistors. As shown in FIG24 , the active connection line AL in the present disclosure is processed into a conductorized layer to form a conductorized active connection line AL. After the conductorization, the second region of the active layer of the sixth transistor (also the first region of the active layer of the seventh transistor) can be reused as the second electrode T64 of the sixth transistor and the first electrode T73 of the seventh transistor.

[0340] (3) forming a second conductive layer pattern, comprising: depositing a second insulating film and a second conductive film on the substrate having the aforementioned pattern, patterning the second insulating film and the second conductive film through a patterning process to form a second insulating layer pattern and a second conductive layer pattern located on the second insulating layer pattern, as shown in Figures 38 to 41, wherein Figure 38 is a schematic diagram of the second conductive layer pattern in Figure 30, Figure 39 is a schematic diagram of Figure 30 after the second conductive layer pattern is formed, Figure 40 is a schematic diagram of the second conductive layer pattern in Figure 31, and Figure 41 is a schematic diagram of Figure 31 after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0341] In an exemplary embodiment, as shown in FIG. 38 and FIG. 39 , the second conductive layer pattern may include a second plate C22 of a second capacitor located in at least one shift register unit and a second connection line L2 .

[0342] In an exemplary embodiment, as shown in Figures 40 and 41, the second conductive layer pattern may include: a second plate C22 of a second capacitor located in at least one shift register unit, a second plate C42 of a fourth capacitor, a second connection line L2, a third connection line L3 and a fourth connection line L4.

[0343] In an exemplary embodiment, as shown in FIG. 38 to FIG. 41 , the second plate C22 of the second capacitor is square in shape, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first plate of the second capacitor on the substrate.

[0344] In an exemplary embodiment, as shown in FIG. 40 and FIG. 41 , the second plate C42 of the fourth capacitor is square in shape, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the first plate of the fourth capacitor on the substrate.

[0345] In an exemplary embodiment, as shown in FIG. 38 to FIG. 41 , the second connection line L2 may be shaped like a bar and at least partially extend along the second direction D2 .

[0346] 40 and 41 , the third connection line L3 may be shaped like a bar and extend at least partially in the second direction D2. The fourth connection line L4 may be shaped like a bar and extend at least partially in the first direction D1.

[0347] (4) forming a third insulating layer pattern, comprising: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, and patterning the third insulating film through a patterning process to form a third insulating layer pattern covering the aforementioned structure, wherein the third insulating layer is provided with a plurality of via patterns, as shown in FIG42 and FIG43 , FIG42 is a schematic diagram of FIG30 after the third insulating layer pattern is formed, and FIG43 is a schematic diagram of FIG31 after the third insulating layer pattern is formed.

[0348] In an exemplary embodiment, as shown in FIG. 42 , the plurality of via patterns may include first to thirteenth vias V1 to V13 , seventeenth to V17 , eighteenth to V18 , twenty-first to V27 , twenty-ninth to V29 , thirtieth to V30 , and thirty-second to V32 .

[0349] In an exemplary embodiment, as shown in FIG. 43 , the plurality of via hole patterns may include a first via hole V1 to a thirty-fourth via hole V34 .

[0350] In an exemplary embodiment, the orthographic projection of the first via V1 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first transistor on the substrate, the first insulating layer and the second insulating layer within the first via V1 are etched away to expose the surface of the first region of the active layer of the first transistor, and the first via V1 is configured to connect the first electrode of the subsequently formed first transistor to the first region of the active layer of the first transistor through the via.

[0351] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the first transistor on the substrate, the first insulating layer and the second insulating layer within the second via V2 are etched away to expose the surface of the second region of the active layer of the first transistor, and the second via V2 is configured to connect the second electrode of the subsequently formed first transistor (which is also the second electrode of the seventh transistor) to the second region of the active layer of the first transistor through the via.

[0352] In an exemplary embodiment, the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the second transistor on the substrate, the first insulating layer and the second insulating layer in the third via V3 are etched away to expose the surface of the first area of ​​the active layer of the second transistor, and the third via V3 is configured to connect the first electrode of the subsequently formed second transistor to the first area of ​​the active layer of the second transistor through the via.

[0353] In an exemplary embodiment, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the second transistor on the substrate, the first insulating layer and the second insulating layer in the fourth via V4 are etched away to expose the surface of the second region of the active layer of the second transistor, and the fourth via V4 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor) to the second region of the active layer of the second transistor through the via.

[0354] In an exemplary embodiment, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the third transistor on the substrate, the first insulating layer and the second insulating layer in the fifth via V5 are etched away to expose the surface of the first area of ​​the active layer of the third transistor, and the fifth via V5 is configured to connect the first electrode of the subsequently formed third transistor to the first area of ​​the active layer of the third transistor through the via.

[0355] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the third transistor on the substrate, the first insulating layer and the second insulating layer within the sixth via V6 are etched away to expose the surface of the second region of the active layer of the third transistor, and the sixth via V6 is configured to connect the second electrode of the subsequently formed third transistor (which is also the second electrode of the second transistor) to the second region of the active layer of the third transistor through the via.

[0356] In an exemplary embodiment, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the fourth transistor on the substrate, the first insulating layer and the second insulating layer in the seventh via V7 are etched away to expose the surface of the first area of ​​the active layer of the fourth transistor, and the seventh via V7 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active layer of the fourth transistor through the via.

[0357] In an exemplary embodiment, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the fourth transistor (also the second region of the active layer of the fifth transistor) on the substrate, the first insulating layer and the second insulating layer within the eighth via V8 are etched away to expose the surface of the second region of the active layer of the fourth transistor (also the second region of the active layer of the fifth transistor), and the eighth via V8 is configured to connect the second electrode of the subsequently formed fourth transistor (also the second electrode of the fifth transistor) to the second region of the active layer of the fourth transistor (also the second region of the active layer of the fifth transistor) through the via.

[0358] In an exemplary embodiment, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the fifth transistor on the substrate, the first insulating layer and the second insulating layer in the ninth via V9 are etched away to expose the surface of the first area of ​​the active layer of the fifth transistor, and the ninth via V9 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of ​​the active layer of the fifth transistor through the via.

[0359] In an exemplary embodiment, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the sixth transistor on the substrate, the first insulating layer and the second insulating layer in the tenth via V10 are etched away, exposing the surface of the first region of the active layer of the sixth transistor, and the tenth via V10 is configured to connect the first electrode of the subsequently formed sixth transistor to the first region of the active layer of the sixth transistor through the via.

[0360] In an exemplary embodiment, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the seventh transistor on the substrate, the first insulating layer and the second insulating layer within the eleventh via V11 are etched away to expose the surface of the second region of the active layer of the seventh transistor, and the eleventh via V11 is configured to connect the second electrode of the subsequently formed seventh transistor (which is also the second electrode of the first transistor) to the second region of the active layer of the seventh transistor through the via.

[0361] In an exemplary embodiment, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the eighth transistor on the substrate, the first insulating layer and the second insulating layer in the twelfth via V12 are etched away to expose the surface of the first area of ​​the active layer of the eighth transistor, and the twelfth via V12 is configured to connect the first electrode of the subsequently formed eighth transistor (which is also the second electrode of the eleventh transistor and the first electrode of the twelfth transistor) to the first area of ​​the active layer of the eighth transistor through the via.

[0362] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eighth transistor on the substrate, the first insulating layer and the second insulating layer in the thirteenth via V13 are etched away to expose the surface of the first region of the active layer of the eighth transistor, and the thirteenth via V13 is configured to connect the second electrode of the subsequently formed eighth transistor to the second region of the active layer of the eighth transistor through the via.

[0363] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the ninth transistor on the substrate, the first insulating layer and the second insulating layer in the fourteenth via V14 are etched away to expose the surface of the first area of ​​the active layer of the ninth transistor, and the fourteenth via V14 is configured to connect the first electrode of the subsequently formed ninth transistor to the first area of ​​the active layer of the ninth transistor through the via.

[0364] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the ninth transistor (also the second area of ​​the active layer of the fourth transistor) on the substrate, the first insulating layer and the second insulating layer in the fifteenth via V15 are etched away to expose the surface of the second area of ​​the active layer of the ninth transistor (also the second area of ​​the active layer of the fourth transistor), and the fifteenth via V15 is configured to connect the second electrode of the subsequently formed ninth transistor (also the second electrode of the fourth transistor) to the second area of ​​the active layer of the ninth transistor (also the second area of ​​the active layer of the fourth transistor) through the via.

[0365] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the fourth transistor on the substrate, the first insulating layer and the second insulating layer in the sixteenth via V16 are etched away to expose the surface of the first area of ​​the active layer of the fourth transistor, and the sixteenth via V16 is configured to connect the first electrode of the subsequently formed fourth transistor to the first area of ​​the active layer of the fourth transistor through the via.

[0366] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the eleventh transistor on the substrate, the first insulating layer and the second insulating layer in the seventeenth via V17 are etched away to expose the surface of the first region of the active layer of the eleventh transistor, and the seventeenth via V17 is configured to connect the first electrode of the subsequently formed eleventh transistor to the first region of the active layer of the eleventh transistor through the via.

[0367] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the eleventh transistor on the substrate, the first insulating layer and the second insulating layer in the eighteenth via V18 are etched away to expose the surface of the first region of the active layer of the eleventh transistor, and the eighteenth via V18 is configured to connect the second electrode of the subsequently formed eleventh transistor (which is also the first electrode of the eighth transistor and the first electrode of the twelfth transistor) to the second region of the active layer of the eleventh transistor through the via.

[0368] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the twelfth transistor on the substrate, the first insulating layer and the second insulating layer in the nineteenth via V19 are etched away to expose the surface of the first area of ​​the active layer of the twelfth transistor, and the nineteenth via V19 is configured to connect the first electrode of the subsequently formed twelfth transistor (which is also the second electrode of the eleventh transistor and the first electrode of the eighth transistor) to the first area of ​​the active layer of the twelfth transistor through the via.

[0369] In an exemplary embodiment, the orthographic projection of the twentieth via V20 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the twelfth transistor on the substrate, the first insulating layer and the second insulating layer within the twentieth via V20 are etched away to expose the surface of the first region of the active layer of the twelfth transistor, and the twentieth via V20 is configured to connect the second electrode of the subsequently formed twelfth transistor to the second region of the active layer of the twelfth transistor through the via.

[0370] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the active connection portion on the substrate, the first insulating layer and the second insulating layer within the twenty-first via V21 are etched away to expose the surface of the active connection portion, and the twenty-first via V21 is configured to connect the second electrode of the subsequently formed second transistor (which is also the second electrode of the third transistor) to the active connection portion through the via.

[0371] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the control electrode of the first transistor (also the control electrode of the third transistor) on the substrate, the second insulating layer in the twenty-second via V22 is etched away to expose the surface of the control electrode of the first transistor (also the control electrode of the third transistor), and the twenty-second via V22 is configured to connect one of the subsequently formed first clock signal line and the second clock signal line and the first electrode of the second transistor to the control electrode of the first transistor (also the control electrode of the third transistor) through the via.

[0372] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 on the substrate is located within the range of the orthographic projection of the control electrode of the second transistor on the substrate, the second insulating layer in the twenty-third via V23 is etched away to expose the surface of the control electrode of the second transistor, and the twenty-third via V23 is configured to connect the second electrode of the first transistor (also the first electrode of the seventh transistor) and the first electrode of the eighth transistor (also the second electrode of the eleventh transistor and the first electrode of the twelfth transistor) formed subsequently to the control electrode of the second transistor through the via.

[0373] In an exemplary embodiment, the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the control electrode of the fourth transistor (also the control electrode of the sixth transistor, the control electrode of the fourth transistor and the first plate of the fourth capacitor) on the substrate, and the second insulating layer in the twenty-fourth via V24 is etched away to expose the surface of the control electrode of the fourth transistor (also the control electrode of the sixth transistor, the control electrode of the fourth transistor and the first plate of the fourth capacitor). The twenty-fourth via V24 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the third transistor) to the control electrode of the fourth transistor (also the control electrode of the sixth transistor, the control electrode of the fourth transistor and the first plate of the fourth capacitor) through the via.

[0374] In an exemplary embodiment, the orthographic projection of the twenty-fifth via V25 on the substrate is located within the range of the orthographic projection of the control electrode of the fifth transistor (also the control electrode of the eleventh transistor and the first plate of the second capacitor) on the substrate, and the second insulating layer in the twenty-fifth via V25 is etched away to expose the surface of the control electrode of the fifth transistor (also the control electrode of the eleventh transistor and the first plate of the second capacitor). The twenty-fifth via V25 is configured to connect the second electrode of the subsequently formed eighth transistor to the control electrode of the fifth transistor (also the control electrode of the eleventh transistor and the first plate of the second capacitor) through the via.

[0375] In an exemplary embodiment, the orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the control electrode of the seventh transistor on the substrate, the second insulating layer in the twenty-sixth via V26 is etched away to expose the surface of the control electrode of the seventh transistor, and the twenty-sixth via V26 is configured to connect the subsequently formed first clock signal line and another of the second clock signal lines and the first electrode of the fifth transistor to the control electrode of the seventh transistor through the via.

[0376] In an exemplary embodiment, the orthographic projection of the twenty-seventh via V27 on the substrate is located within the range of the orthographic projection of the control electrode of the eighth transistor (also the control electrode of the twelfth transistor) on the substrate, the second insulating layer in the twenty-seventh via V27 is etched away to expose the surface of the control electrode of the eighth transistor (also the control electrode of the twelfth transistor), and the twenty-seventh via V27 is configured to connect a subsequently formed first second power line to the control electrode of the eighth transistor (also the control electrode of the twelfth transistor) through the via.

[0377] In an exemplary embodiment, the orthographic projection of the twenty-eighth via V28 on the substrate is located within the range of the orthographic projection of the control electrode of the ninth transistor on the substrate, the second insulating layer in the twenty-eighth via V28 is etched away to expose the surface of the control electrode of the ninth transistor, and the twenty-eighth via V28 is configured to connect the second electrode of the subsequently formed twelfth transistor to the control electrode of the ninth transistor through the via.

[0378] In an exemplary embodiment, the orthographic projection of the twenty-ninth via V29 on the substrate is located within the range of the orthographic projection of the first connecting line on the substrate, the second insulating layer in the twenty-ninth via V29 is etched away to expose the surface of the first connecting line, and the twenty-ninth via V29 is configured to connect the second electrode of the fourth transistor of the subsequently formed shift register unit at this level (also the second electrode of the fifth transistor) and the first electrode of the first transistor of the next-level shift register unit to the first connecting line through the via.

[0379] In an exemplary embodiment, the orthographic projection of the 30th via V30 on the substrate is located within the range of the orthographic projection of the second plate of the second capacitor on the substrate, the 30th via V30 exposes the surface of the second plate of the second capacitor, and the 30th via V30 is configured to connect the second electrode of the subsequently formed fourth transistor (which is also the second electrode of the fifth transistor) to the second plate of the second capacitor through the via.

[0380] In an exemplary embodiment, the orthographic projection of the thirty-first via V31 on the substrate is located within the range of the orthographic projection of the second plate of the fourth capacitor on the substrate, the thirty-first via V31 exposes the surface of the second plate of the fourth capacitor, and the thirty-first via V31 is configured to connect a subsequently formed second second power line to the second plate of the fourth capacitor through the via.

[0381] In an exemplary embodiment, the orthographic projection of the thirty-second via V32 on the substrate is located within the range of the orthographic projection of the second connecting line on the substrate, the thirty-second via V32 exposes the surface of the second connecting line, and the thirty-second via V32 is configured to connect the first electrode of the subsequently formed sixth transistor and the first electrode of the fourth transistor to the second connecting line through the via.

[0382] In an exemplary embodiment, the orthographic projection of the thirty-third via V33 on the substrate is located within the range of the orthographic projection of the third connecting line on the substrate, the thirty-third via V33 exposes the surface of the third connecting line, and the thirty-third via V33 is configured to connect the first electrode of the subsequently formed ninth transistor and one of the third clock signal line and the fourth clock signal line to the third connecting line through the via.

[0383] In an exemplary embodiment, the orthographic projection of the thirty-fourth via V34 on the substrate is located within the range of the orthographic projection of the fourth connecting line on the substrate, the thirty-fourth via V34 exposes the surface of the fourth connecting line, and the thirty-fourth via V34 is configured to connect the second electrode of the subsequently formed ninth transistor (which is also the second electrode of the fourth transistor) to the fourth connecting line through the via.

[0384] (5) forming a third conductive layer pattern, including: depositing a third metal film on the substrate having the aforementioned pattern formed thereon, and patterning the third metal film through a patterning process to form a third metal layer pattern, as shown in Figures 44 to 47 , wherein Figure 44 is a schematic diagram of the third conductive layer pattern in Figure 30 , Figure 45 is a schematic diagram of Figure 30 after the third conductive layer pattern is formed, Figure 46 is a schematic diagram of the third conductive layer pattern in Figure 31 , and Figure 47 is a schematic diagram of Figure 31 after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0385] In an exemplary embodiment, as shown in Figures 44 and 45, the third conductive layer pattern may include: an initial signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a first power line VGH, a second power line VGL1, and the first electrode T13 and the second electrode T14 of the first transistor located in at least one shift register unit to the first electrode T83 and the second electrode T83 of the eighth transistor, and the first electrode T113 and the second electrode 114 of the eleventh transistor.

[0386] In an exemplary embodiment, as shown in Figures 46 and 47, the third conductive layer pattern may include: an initial signal line STV, a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a first power line VGH, two second power lines VGL1, and the first electrode T13 and the second electrode T14 of the first transistor to the first electrode T123 and the second electrode 124 of the twelfth transistor located in at least one shift register unit.

[0387] In an exemplary embodiment, as shown in Figures 44 to 47, the second electrode T14 of the first transistor and the second electrode T74 of the seventh transistor are integrally formed. The second electrode T24 of the second transistor and the second electrode T34 of the third transistor are integrally formed. The second electrode T44 of the fourth transistor and the second electrode T54 of the fifth transistor are integrally formed. The first power line VGH and the first electrode T63 of the sixth transistor are integrally formed. The first second power line VGL1 and the first electrode T33 of the third transistor are integrally formed. The second second power line VGL1 and the first electrode T103 of the fourth transistor are integrally formed.

[0388] 44 and 45 , the first electrode T83 of the eighth transistor and the second electrode T114 of the eleventh transistor are integrally formed. The second power line VGL1 and the first electrode T33 of the third transistor are integrally formed.

[0389] In an exemplary embodiment, as shown in Figures 46 and 47, the first electrode T83 of the eighth transistor, the second electrode T114 of the eleventh transistor, and the first electrode T123 of the twelfth transistor are integrally structured. The second electrode T94 of the ninth transistor and the second electrode T104 of the fourth transistor are integrally structured. The first second power line VGL1 and the first electrode T33 of the third transistor are integrally structured. The second second power line VGL1 and the first electrode T103 of the fourth transistor are integrally structured.

[0390] In an exemplary embodiment, as shown in Figures 44 and 45, the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, and the second power line VGL1 are sequentially arranged along a side close to the display area. Any one of the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, and the second power line VGL1 extends along the first direction D1.

[0391] In an exemplary embodiment, as shown in Figures 46 and 47, the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, the first second power line VGL1, the third clock signal line CLK3, the fourth clock signal line CLK4, and the second second power line VGL1 are sequentially arranged along a side close to the display area. Any of the initial signal line STV, the first clock signal line CLK1, the second clock signal line CLK2, the first power line VGH, the first second power line VGL1, the third clock signal line CLK3, the fourth clock signal line CLK4, and the second second power line VGL1 extends along the first direction D1.

[0392] In an exemplary embodiment, as shown in Figures 44 to 47 , the first electrode T13 of the first transistor can be square in shape and extend along a first direction D1. The first electrode T13 of the first transistor is connected to the first region of the active layer of the first transistor via a first via, and is connected to the first connection line of the shift register unit in the previous stage via the twenty-ninth via. As shown in Figures 44 and 45 , the first electrode T13 of the first transistor is located between the first power line VGH and the second power line VGL1. As shown in Figures 46 and 47 , the first electrode T13 of the first transistor is located between the first power line VGH and the first second power line VGL1.

[0393] In an exemplary embodiment, as shown in Figures 44 to 47, the second electrode T14 of the first transistor (also the second electrode T74 of the seventh transistor) can be shaped like a ┌. The second electrode T14 of the first transistor (also the second electrode T74 of the seventh transistor) is connected to the second region of the active layer of the first transistor via a second via, to the second region of the active layer of the seventh transistor via an eleventh via V11, and to the control electrode of the second transistor via a twenty-third via. As shown in Figures 44 and 45, the second electrode T14 of the first transistor (also the second electrode T74 of the seventh transistor) is located between the first power line VGH and the second power line VGL1. As shown in Figures 46 and 47, the second electrode T14 of the first transistor (also the second electrode T74 of the seventh transistor) is located between the first power line VGH and the first second power line VGL1.

[0394] In an exemplary embodiment, as shown in Figures 44 to 47, the first electrode T23 of the second transistor can be strip-shaped and extend along the first direction D1. The first electrode T23 of the second transistor is connected to the first region of the active layer of the second transistor via a third via and is connected to the control electrode of the first transistor (which is also the control electrode of the third transistor) via a twenty-second via. As shown in Figures 44 and 45, the first electrode T23 of the second transistor is located between the first power line VGH and the second power line VGL1. As shown in Figures 46 and 47, the first electrode T23 of the second transistor is located between the first power line VGH and the first second power line VGL1.

[0395] In an exemplary embodiment, as shown in Figures 44 to 47, the second electrode T24 of the second transistor (also the second electrode T34 of the third transistor) can be shaped like a zigzag line and extend at least partially along the first direction D1. As shown in Figures 44 and 45, the second electrode T24 of the second transistor (also the second electrode T34 of the third transistor) is located between the first power line VGH and the second power line VGL1. The second electrode T24 of the second transistor (also the second electrode T34 of the third transistor) is connected to the second region of the active layer of the second transistor via a fourth via, to the second region of the active layer of the third transistor via a sixth via, to the active connection portion via a twenty-first via, and to the control electrode of the fourth transistor (also the control electrode of the sixth transistor) via a twenty-fourth via. As shown in Figures 46 and 47, the second electrode T24 of the second transistor (also the second electrode T34 of the third transistor) is located between the first power line VGH and the first second power line VGL1. The second electrode T24 of the second transistor (which is also the second electrode T34 of the third transistor) is connected to the second area of ​​the active layer of the second transistor through the fourth via, is connected to the second area of ​​the active layer of the third transistor through the sixth via, is connected to the active connection portion through the twenty-first via, and is connected to the control electrode of the fourth transistor (which is also the control electrode of the sixth transistor, the control electrode of the fourth transistor, and the first plate of the fourth capacitor) through the twenty-fourth via.

[0396] In an exemplary embodiment, as shown in Figures 44 to 47 , the first electrode T33 of the third transistor may be strip-shaped and extend along the second direction D2. The first electrode T33 of the third transistor is connected to the first region of the active layer of the third transistor via a fifth via. As shown in Figures 44 and 45 , the first electrode T33 of the third transistor is located between the first power line VGH and the second power line VGL1. As shown in Figures 46 and 47 , the first electrode T33 of the third transistor is located between the first power line VGH and the first second power line VGL1.

[0397] In an exemplary embodiment, as shown in Figures 44 to 47 , the first electrode T43 of the fourth transistor can be strip-shaped and extend along the second direction D2. The first electrode T43 of the fourth transistor is connected to the first region of the active layer of the fourth transistor via a seventh via and to the second connection line via a thirty-second via. As shown in Figures 44 and 45 , the first electrode T43 of the fourth transistor is located on the side of the second power line VGL1 closest to the display area. As shown in Figures 46 and 47 , the first electrode T43 of the fourth transistor is located between the first second power line VGL1 and the third clock signal line CLK3.

[0398] In an exemplary embodiment, as shown in FIG. 44 to FIG. 47 , the shape of the second electrode T44 of the fourth transistor (also the second electrode T54 of the fifth transistor) may be The second electrode T44 of the fourth transistor (also the second electrode T54 of the fifth transistor) is connected to the second region of the active layer of the fourth transistor (also the second region of the active layer of the fifth transistor) through the eighth via, is connected to the first connecting line through the twenty-ninth via, and is connected to the second plate of the second capacitor through the thirtieth via. As shown in Figures 44 and 45, the second electrode T44 of the fourth transistor (also the second electrode T54 of the fifth transistor) is located on the side of the second power line VGL1 close to the display area. As shown in Figures 46 and 47, the second electrode T44 of the fourth transistor (also the second electrode T54 of the fifth transistor) is located between the first second power line VGL1 and the third clock signal line CLK3.

[0399] In an exemplary embodiment, as shown in Figures 44 to 47 , the first electrode T53 of the fifth transistor can be strip-shaped and extend along the second direction D2. The first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor via a ninth via and to the control electrode of the seventh transistor via a twenty-sixth via. As shown in Figures 44 and 45 , the first electrode T53 of the fifth transistor is located on the side of the second power line VGL1 closest to the display area. As shown in Figures 46 and 47 , the first electrode T53 of the fifth transistor is located between the first second power line VGL1 and the third clock signal line CLK3.

[0400] In an exemplary embodiment, as shown in Figures 44 to 47 , the first electrode T63 of the sixth transistor can be strip-shaped and extend along the second direction D2. The first electrode T63 of the sixth transistor is connected to the first region of the active layer of the sixth transistor via a tenth via and to the second connection line via a thirty-second via. As shown in Figures 44 and 45 , the first electrode T63 of the sixth transistor is located between the first power line VGH and the second power line VGL1. As shown in Figures 46 and 47 , the first electrode T63 of the sixth transistor is located between the first power line VGH and the first second power line VGL1.

[0401] In an exemplary embodiment, as shown in Figures 44 and 45, the first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor) may be L-shaped. The first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor) is located on a side of the second power line VGL1 that is closer to the display area. The first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor) is connected to the first region of the active layer of the eighth transistor via a twelfth via, to the second region of the active layer of the eleventh transistor via an eighteenth via, and to the control electrode of the second transistor via a twenty-third via.

[0402] In an exemplary embodiment, as shown in Figures 46 and 47, the first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor and the first electrode T123 of the twelfth transistor) may be shaped like an "L." The first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor and the first electrode T123 of the twelfth transistor) is located between the first second power supply line VGL1 and the third clock signal line CLK3. The first electrode T83 of the eighth transistor (also the second electrode T114 of the eleventh transistor and the first electrode T123 of the twelfth transistor) is connected to the first region of the active layer of the eighth transistor via a twelfth via, to the second region of the active layer of the eleventh transistor via an eighteenth via, to the first region of the active layer of the twelfth transistor via a nineteenth via, and to the control electrode of the second transistor via a twenty-third via.

[0403] In an exemplary embodiment, as shown in Figures 44 to 47, the second electrode T84 of the eighth transistor can be strip-shaped and extend along the first direction D1. The second electrode T84 of the eighth transistor is connected to the second region of the active layer of the eighth transistor via a thirteenth via hole, and is connected to the control electrode of the fifth transistor (which is also the control electrode of the eleventh transistor and the first plate of the second capacitor) via a twenty-fifth via hole. As shown in Figures 44 and 45, the second electrode T84 of the eighth transistor is located on the side of the second power line VGL1 closest to the display area. As shown in Figures 46 and 47, the second electrode T84 of the eighth transistor is located between the first second power line VGL1 and the third clock signal line CLK3.

[0404] In an exemplary embodiment, as shown in FIG. 46 and FIG. 47 , the first electrode T93 of the ninth transistor may be shaped like a character "[." The first electrode T93 of the ninth transistor is located on a side of the second power line VGL1 close to the display area. The first electrode T93 of the ninth transistor is connected to the first region of the active layer of the ninth transistor via a fourteenth via hole and to the third connection line via a thirty-third via hole.

[0405] In an exemplary embodiment, as shown in Figures 46 and 47, the first electrode T103 of the fourth transistor can be strip-shaped and extend along the first direction D1. The first electrode T103 of the fourth transistor is located on a side of the second power line VGL1 close to the display area. The first electrode T103 of the fourth transistor is connected to the first region of the active layer of the fourth transistor through a sixteenth via hole.

[0406] In an exemplary embodiment, as shown in Figures 46 and 47, the first electrode 94 of the ninth transistor (also the second electrode T104 of the fourth transistor) can be shaped like a comb, with the teeth located on the side of the comb back away from the display area. The first electrode 94 of the ninth transistor (also the second electrode T104 of the fourth transistor) is located on the side of the second power line VGL1 that is closer to the display area. The first electrode 94 of the ninth transistor (also the second electrode T104 of the fourth transistor) is connected to the second region of the active layer of the ninth transistor (also the second region of the active layer of the fourth transistor) via a fifteenth via hole, and is connected to the fourth connection line via a thirty-fourth via hole.

[0407] In an exemplary embodiment, as shown in Figures 44 to 47 , the first electrode T113 of the eleventh transistor may be strip-shaped and extend along a first direction D1. The first electrode T113 of the eleventh transistor is connected to the first region of the active layer of the eleventh transistor via a seventeenth via. As shown in Figures 44 and 45 , the first electrode T113 of the eleventh transistor is located on a side of the second power line VGL1 that is closer to the display area. As shown in Figures 46 and 47 , the first electrode T113 of the eleventh transistor is located between the first second power line VGL1 and the third clock signal line CLK3.

[0408] In an exemplary embodiment, as shown in Figures 44 to 47, the second electrode T124 of the twelfth transistor may be strip-shaped and extend along the second direction D2. The second electrode T124 of the twelfth transistor is located between the first second power line VGL1 and the third clock signal line CLK3. The second electrode T124 of the twelfth transistor is connected to the second region of the active layer of the twelfth transistor through a twentieth via hole and is connected to the control electrode of the ninth transistor through a twenty-eighth via hole.

[0409] In an exemplary embodiment, as shown in Figures 44 to 47, the control electrode of the first transistor (also the control electrode of the third transistor) is connected to one of the first clock signal line CLK1 and the second clock signal line CLK2 through the 22nd via. Figures 45 and 47 illustrate the example of the control electrode of the first transistor (also the control electrode of the third transistor) being connected to the first clock signal line CLK1 through the 22nd via.

[0410] In an exemplary embodiment, as shown in Figures 44 to 47, the control electrode of the seventh transistor is connected to the other of the first clock signal line CLK1 and the second clock signal line CLK2 through the 26th via. Figures 45 and 47 illustrate an example in which the control electrode of the seventh transistor is connected to the second clock signal line CLK2 through the 26th via.

[0411] In an exemplary embodiment, as shown in FIG. 44 and FIG. 45 , the control electrode of the eighth transistor (also the control electrode of the twelfth transistor) is connected to the second power line VGL1 through a twenty-seventh via hole.

[0412] In an exemplary embodiment, as shown in FIG. 46 and FIG. 47 , the control electrode of the eighth transistor (also the control electrode of the twelfth transistor) is connected to the first second power line VGL1 through a twenty-seventh via hole.

[0413] In an exemplary embodiment, as shown in FIG. 46 and FIG. 47 , the second plate of the fourth capacitor is connected to the second second power line VGL1 through a thirty-first via hole.

[0414] 46 and 47, the third connection line is connected to one of the third clock signal line CLK3 and the fourth clock signal line CLK4 through the 33rd via hole. FIG47 illustrates an example in which the third connection line is connected to the third clock signal line CLK3 through the 33rd via hole.

[0415] In an exemplary embodiment, as shown in FIG. 47 , an orthographic projection of the second power line VGL1 on the substrate partially overlaps an orthographic projection of the fourth capacitor on the substrate.

[0416] (6) forming a fourth insulating layer pattern, comprising: depositing a fourth insulating film on a substrate having the aforementioned pattern formed thereon, and patterning the fourth insulating film through a patterning process to form a fourth insulating layer pattern covering the aforementioned structure, wherein the fourth insulating layer is provided with a via pattern, as shown in FIG48 and FIG49 , FIG48 is a schematic diagram of FIG30 after the fourth insulating layer pattern is formed, and FIG49 is a schematic diagram of FIG31 after the fourth insulating layer pattern is formed.

[0417] In an exemplary embodiment, as shown in FIG. 48 and FIG. 49 , the via hole pattern may include a thirty-fifth via hole V35 .

[0418] In an exemplary embodiment, the orthographic projection of the thirty-fifth via V35 on the substrate is located within the range of the orthographic projection of the first electrode of the eleventh transistor on the substrate, the thirty-fifth via V35 exposes the surface of the first electrode of the eleventh transistor, and the thirty-fifth via V35 is configured to connect a subsequently formed third power line to the first electrode of the eleventh transistor through the via.

[0419] (7) Forming a fourth conductive layer pattern, including: depositing a fourth metal film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth metal film through a patterning process to form a fourth metal layer pattern, as shown in FIG50 to FIG52 , FIG50 is a schematic diagram of the fourth conductive layer pattern in FIG30 and FIG31 , FIG51 is a schematic diagram of FIG30 after the fourth conductive layer pattern is formed, and FIG52 is a schematic diagram of FIG31 after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0420] In exemplary embodiments, as shown in FIG. 50 to FIG. 52 , the fourth conductive layer pattern may include a third power line VGL2 .

[0421] In an exemplary embodiment, as shown in Figures 50 to 52, the third power line VGL2 may be linear and extend along the first direction D1. The third power line VGL2 is connected to the first electrode of the eleventh transistor through the thirty-fifth via hole. The orthographic projection of the third power line VGL2 on the substrate partially overlaps with the orthographic projections of the fourth and fifth transistors on the substrate.

[0422] In an exemplary embodiment, as shown in FIG51 , the orthographic projection of the third power line VGL2 on the substrate is located on a side of the orthographic projection of the second power line on the substrate closer to the display area. As shown in FIG52 , the orthographic projection of the third power line VGL2 on the substrate is located between the orthographic projection of the first second power line on the substrate and the orthographic projection of the third clock signal line on the substrate.

[0423] (8) forming a planar layer pattern, comprising: depositing a fifth insulating film on the substrate having the aforementioned pattern, coating a second planar film, and patterning the fifth insulating film and the second planar film through a patterning process to form a fifth insulating layer pattern and a planar layer pattern covering the aforementioned pattern.

[0424] At this point, the drive structure layer is completed on the substrate. In a plane parallel to the display substrate, the drive structure layer may include multiple shift register units, and the drive structure layer may be disposed on the substrate. The drive structure layer may include a semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a fifth insulating layer, and a planar layer disposed sequentially on the substrate.

[0425] In exemplary embodiments, the semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer, or may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0426] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0427] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer.

[0428] In an exemplary embodiment, the planar layer may be made of an organic material such as resin.

[0429] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer is prepared on the driving structure layer. The preparation process of the light emitting structure layer may include the following operations.

[0430] An anode conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the anode conductive film is patterned using a patterning process to form an anode conductive layer pattern arranged on the flat layer. A pixel definition film is deposited on the substrate on which the aforementioned pattern is formed, and the pixel definition film is patterned using a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern. An organic light-emitting material is coated on the substrate on which the pixel definition layer pattern is formed, and the organic light-emitting material is patterned using a patterning process to form an organic structure layer pattern. A cathode conductive film is deposited on the substrate on which the organic material layer pattern is formed, and the cathode conductive film is patterned using a patterning process to form a cathode conductive layer.

[0431] At this point, the light-emitting structure layer is prepared on the substrate.

[0432] In an exemplary embodiment, the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0433] In exemplary embodiments, the anode conductive layer includes at least a plurality of anode patterns.

[0434] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0435] In an exemplary embodiment, the organic structure layer may include at least an organic light emitting layer of a light emitting device.

[0436] In an exemplary embodiment, the cathode conductive layer may include at least cathodes of a plurality of light emitting devices.

[0437] In an exemplary embodiment, the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material thereof, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0438] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0439] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0440] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0441] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A shift register unit, comprising: a node control subcircuit, an output subcircuit, and a pull-down subcircuit; The node control subcircuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal, the first node, and the second node, respectively, and is configured to provide a signal from the signal input terminal or the first power supply terminal to the first node, and provide a signal from the second power supply terminal or the first clock signal terminal to the second node under the control of the signal from the first clock signal terminal and the second clock signal terminal; The pull-down sub-circuit is electrically connected to the first node and the third power supply terminal, respectively, and is configured to provide a signal of the third power supply terminal to the first node; The output subcircuit is electrically connected to the second clock signal terminal, the first power terminal, the second power terminal, the first signal output terminal, the first node and the second node respectively, and is configured to provide a signal from the first power terminal or the second clock signal terminal to the first signal output terminal under the control of the signals from the first node, the second node and the second power terminal; An absolute value of a voltage value of a signal at the third power supply terminal is smaller than an absolute value of a voltage value of a signal at the second power supply terminal.

2. The shift register unit according to claim 1, wherein: The pull-down sub-circuit comprises: an eleventh transistor; A first electrode of the eleventh transistor is electrically connected to the third power supply terminal, and a second electrode of the eleventh transistor is electrically connected to the first node.

3. The shift register unit according to claim 2, wherein: The control electrode of the eleventh transistor is electrically connected to the first node.

4. The shift register unit according to claim 1, wherein: The node control subcircuit includes: a first transistor, a second transistor, a third transistor, a sixth transistor and a seventh transistor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node; A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the second node; The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the fourth node; The control electrode of the seventh transistor is electrically connected to the second clock signal terminal, the first electrode of the seventh transistor is connected to the fourth node, and the second electrode of the seventh transistor is electrically connected to the first node.

5. The shift register unit according to claim 1, wherein: The output sub-circuit comprises: a fourth transistor, a fifth transistor and an eighth transistor; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first signal output terminal; The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first signal output terminal; The control electrode of the eighth transistor is electrically connected to the second power supply terminal, the first electrode of the eighth transistor is connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node.

6. The shift register unit according to claim 5, wherein: The pull-down sub-circuit comprises: an eleventh transistor; The eleventh transistor control electrode is electrically connected to the third node.

7. The shift register unit according to claim 5, wherein: The output subcircuit further includes: at least one of a first capacitor and a second capacitor; The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power supply terminal; The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the first signal output terminal.

8. The shift register unit according to claim 1, wherein: The output subcircuit is also electrically connected to the third clock signal terminal and the second signal output terminal respectively, and is configured to provide a signal from the second power supply terminal or the third clock signal terminal to the second signal output terminal under the control of the signals of the first node and the second node.

9. The shift register unit according to claim 8, wherein: The output sub-circuit comprises: a fourth transistor, a fifth transistor, an eighth transistor, a ninth transistor and a tenth transistor; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first signal output terminal; The control electrode of the fifth transistor is electrically connected to the third node, the first electrode of the fifth transistor is connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first signal output terminal; The control electrode of the eighth transistor is electrically connected to the second power supply terminal, the first electrode of the eighth transistor is connected to the first node, and the second electrode of the eighth transistor is electrically connected to the third node; The control electrode of the ninth transistor is electrically connected to the first node, the first electrode of the ninth transistor is connected to the third clock signal terminal, and the second electrode of the ninth transistor is electrically connected to the second signal output terminal; The control electrode of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is connected to the second power supply terminal, and the second electrode of the tenth transistor is electrically connected to the second signal output terminal.

10. The shift register unit according to claim 9, wherein: The output sub-circuit further includes: a twelfth transistor; the control electrode of the ninth transistor is electrically connected to the first node through the twelfth transistor; The control electrode of the twelfth transistor is electrically connected to the second power supply terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the control electrode of the ninth transistor.

11. The shift register unit according to claim 9 or 10, wherein: The output subcircuit further includes: at least one of a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; The first plate of the first capacitor is electrically connected to the second node, and the second plate of the first capacitor is electrically connected to the first power supply terminal; The first plate of the second capacitor is electrically connected to the third node, and the second plate of the second capacitor is electrically connected to the first signal output terminal; A first electrode plate of the third capacitor is electrically connected to the control electrode of the ninth transistor, and a second electrode plate of the third capacitor is connected to the second signal output terminal; The first plate of the fourth capacitor is electrically connected to the second node, and the second plate of the fourth capacitor is connected to the second power supply terminal.

12. The shift register unit according to claim 8, wherein: The signal at the third clock signal end and the signal at the second clock signal end are inverted signals to each other.

13. The shift register unit according to claim 1, further comprising: output control subcircuit; The output control subcircuit is electrically connected to the first power supply terminal and the first signal output terminal respectively, and is configured to store a voltage difference between the signal at the first signal output terminal and the signal at the first power supply terminal.

14. The shift register unit according to claim 13, wherein: The output control subcircuit comprises: a fifth capacitor; The first electrode of the fifth capacitor is electrically connected to the first power supply terminal, and the second electrode of the fifth capacitor is electrically connected to the first signal output terminal.

15. The shift register unit according to claim 1, wherein: The signals of the first clock signal terminal and the second clock signal terminal are not simultaneously valid level signals.

16. A display substrate, comprising: A substrate, sub-pixels, gate lines, and a gate driving circuit disposed on the substrate. The substrate is provided with a display area and a non-display area. The gate driving circuit is located in the non-display area, and the sub-pixels and the gate lines are located in the display area. The gate lines are electrically connected to the sub-pixels and the gate driving circuit respectively. The gate driving circuit includes: a plurality of cascaded shift register units as described in any one of claims 1 to 15. Among them, the first signal output terminal of the i-th stage shift register unit is connected to the signal input terminal of the i + 1-th stage shift register unit, where 1 ≤ i < N, and N is the total number of stages of the shift register units.

17. The display substrate according to claim 16, wherein: The first signal output terminal of the shift register unit is electrically connected to the gate line.

18. The display substrate according to claim 16, further comprising: An initial signal line, a first clock signal line, a second clock signal line, a first power supply line, a second power supply line, and a third power supply line disposed on the substrate and located in the non-display area. Any one of the initial signal line, the first clock signal line, the second clock signal line, the first power supply line, the second power supply line, and the third power supply line extends along a first direction, and the gate line extends along a second direction. The first direction intersects the second direction.

19. The display substrate according to claim 18, wherein: The initial signal line, the first clock signal line, the second clock signal line, and the first power supply line are arranged in sequence along the direction close to the display area and are located on the side of the shift register unit away from the display area.

20. The display substrate according to claim 18, wherein: The shift register unit includes: a plurality of transistors. The second power supply line is located on the side of the first power supply line close to the display area and is located between the plurality of transistors of the shift register unit.

21. The display substrate according to claim 18, wherein: The third power supply line is located on the side of the second power supply line close to the display area, and its orthographic projection on the substrate partially overlaps with the orthographic projection of the shift register unit on the substrate.

22. The display substrate according to claim 18, wherein: The shift register unit includes: a first transistor, a second transistor, a third transistor, a sixth transistor, and a seventh transistor. At least a part of any one of the first transistor, the second transistor, the third transistor, the sixth transistor, and the seventh transistor is located between the first power supply line and the second power supply line.

23. The display substrate according to claim 18, wherein: The shift register unit includes: a fourth transistor, a fifth transistor, an eighth transistor, an eleventh transistor, and a twelfth transistor. The number of the second power supply lines is at least one. At least a part of any one of the fourth transistor, the fifth transistor, the eighth transistor, the eleventh transistor, and the twelfth transistor is located on the side of the second power supply line close to the display area.

24. The display substrate according to claim 18, wherein: The shift register unit includes: a second capacitor. The second capacitor is located on the side of the third power supply line close to the display area.

25. The display substrate according to claim 18 or 19, further comprising: A third clock signal line and a fourth clock signal line disposed on the substrate and located in the non-display area. Any one of the third clock signal line and the fourth clock signal line extends along the first direction. There are two second power lines. The second power line close to the display area is located on a side of any one of the third clock signal line and the fourth clock signal line close to the display area, and the second power line far from the display area is located between the first power line and the third power line.

26. The display substrate according to claim 25, wherein: The shift register unit includes: a fourth transistor, a fifth transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a twelfth transistor and a fourth capacitor; The fourth transistor, the fifth transistor, the eighth transistor, the eleventh transistor and the twelfth transistor are located between the second power line and any one of the third clock signal line and the fourth clock signal line far from the display area, and the ninth transistor and the tenth transistor are located on a side of the second power line close to the display area; The orthographic projection of the second power line close to the display area on the substrate partially overlaps with the orthographic projection of the fourth capacitor on the substrate.

27. The display substrate according to claim 18, wherein: The first clock signal terminal of the i-th shift register unit is electrically connected to one of the first clock signal line and the second clock signal line, and the second clock signal terminal of the i-th shift register unit is electrically connected to the other of the first clock signal line and the second clock signal line; The first clock signal terminals of adjacent shift register units are connected to different signal lines, and the second clock signal terminals of adjacent shift register units are connected to different signal lines.

28. The display substrate according to claim 21, wherein: The shift register unit comprises: a fourth transistor and a fifth transistor; An orthographic projection of the third power line on the substrate partially overlaps with orthographic projections of the fourth transistor and the fifth transistor on the substrate.

29. The display substrate according to claim 23, wherein: The active layer of the eighth transistor extends along the second direction, any one of the first electrode and the second electrode of the eighth transistor extends along the first direction, and the gate electrode of the eighth transistor at least partially extends along the first direction.

30. The display substrate according to claim 23, wherein: The gate electrode of the eleventh transistor is an integral structure with the gate electrode of the fifth transistor, the orthographic projection of the first electrode of the eleventh transistor on the substrate partially overlaps with the orthographic projection of the third power line on the substrate, and is electrically connected to the third power line, and the second electrode of the eleventh transistor is an integral structure with the first electrode of the eighth transistor and the first electrode of the twelfth transistor.

31. The display substrate according to claim 25, wherein: A width of any one of the first power line, the second power line and the third power line along the second direction is smaller than a width of any one of the first clock signal line, the second clock signal line, the third clock signal line and the fourth clock signal line along the second direction.

32. The display substrate according to claim 25, wherein: The third clock signal terminal of the i-th stage shift register unit is electrically connected to one of the third clock signal line and the fourth clock signal line, and the third clock signal terminal of the i+1-th stage shift register unit is electrically connected to the other of the third clock signal line and the fourth clock signal line.

33. The display substrate according to claim 26, wherein: A channel width of the active layer of the ninth transistor and the tenth transistor is greater than a channel width of the active layer of the fourth transistor.

34. The display substrate according to claim 33, wherein: The channel width of the active layer of the tenth transistor and the ninth transistor is not less than 90 micrometers.

35. The display substrate according to claim 33, wherein: The channel width of the active layer of the fourth transistor is not greater than 50 micrometers.

36. The display substrate according to claim 26, wherein: The channel widths of the active layers of the tenth and ninth transistors are greater than the channel width of the active layer of the fifth transistor.

37. The display substrate according to claim 36, wherein: A channel width of the active layer of the ninth transistor and the tenth transistor is not less than 90 micrometers.

38. The display substrate according to claim 36, wherein: The channel width of the active layer of the fifth transistor is not greater than 50 micrometers.

39. The display substrate according to claim 26, wherein: The second signal output terminal of the shift register unit is electrically connected to the gate line.

40. A display device comprising: A display substrate as claimed in any one of claims 16 to 39.

41. A method for driving a shift register unit, configured to drive the shift register unit according to any one of claims 1 to 15, the method comprising: The node control subcircuit provides a signal from the signal input terminal or the first power supply terminal to the first node and provides a signal from the second power supply terminal or the first clock signal terminal to the second node under the control of the signals from the first clock signal terminal and the second clock signal terminal; The pull-down sub-circuit provides a signal of the third power supply terminal to the first node; The output subcircuit provides a signal from the first power supply terminal or the second clock signal terminal to the first signal output terminal under the control of the signals from the first node and the second node.

42. The method according to claim 41, wherein: The shift register unit further includes: an output control subcircuit; The method further comprises: the output subcircuit provides a signal from a second power supply terminal or a third clock signal terminal to a second signal output terminal under the control of the signals from the first node and the second node; The output control subcircuit stores a voltage difference between the signal at the first signal output terminal and the signal at the first power supply terminal.

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