Array substrate and display device

Abstract

An array substrate, comprising: a base, multiple scanning lines provided on the base, at least one dummy wire, and a scanning drive circuit. The multiple scanning lines are located in a display region and extend in a first direction. The at least one dummy wire is located in a frame region and extends in a second direction. The scanning drive circuit is located in the frame region. At least one scanning line comprises a scanning connection end and an extension end which extend to the frame region, and the scanning connection end is electrically connected to the scanning drive circuit. The at least one dummy wire is disconnected at the extension end of at least one scanning line, so that the orthographic projection of the at least one dummy wire on the base does not overlap the orthographic projection of the extension end of the at least one scanning line on the base.

Description

Array substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on June 12, 2023, with application number 202310698843.2 and invention name “Array Substrate and Display Device”, the contents of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to the field of display technology, and in particular to an array substrate and a display device. Background Art

[0003] Touch and Display Driver Integration (TDDI) products have gradually become the mainstream touch technology due to their advantages such as lightweight, high integration, and high performance. TDDI technology is currently widely used in mobile and touch display products.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] Embodiments of the present disclosure provide an array substrate and a display device.

[0007] On the one hand, an embodiment of the present disclosure provides an array substrate, comprising: a substrate, a plurality of scan lines arranged on the substrate, at least one dummy trace, and a scan drive circuit. The substrate includes a display area and a frame area located around the display area. The plurality of scan lines are located at least in the display area and extend along a first direction. At least one dummy trace is located in the frame area and extends along a second direction. The scan drive circuit is located in the frame area. At least one scan line includes a scan connection end and an extension end extending to the frame area, and the scan connection end is electrically connected to the scan drive circuit. At least one dummy trace is disconnected at the extension end of the at least one scan line, so that the at least one dummy trace does not overlap with the extension end of the at least one scan line in the orthographic projection of the substrate. The second direction intersects with the first direction.

[0008] In some exemplary embodiments, the at least one dummy routing line includes: a plurality of dummy routing segments arranged in sequence along the second direction, a first break is provided between adjacent dummy routing segments in the second direction, and the length of the first break along the second direction is greater than the length of the extended end of the at least one scan line along the second direction.

[0009] In some exemplary embodiments, the array substrate further includes: a first common voltage signal line and a second common voltage signal line located in the border area; the first common voltage signal line is electrically connected to the second common voltage signal line, the first common voltage signal line is located on a side of the second common voltage signal line away from the substrate, and the first common voltage signal line and the second common voltage signal line at least partially overlap in their positive projections on the substrate.

[0010] In some exemplary embodiments, at least one dummy routing segment of the at least one dummy routing line is electrically connected to at least one of the second common voltage signal line and the first common voltage signal line.

[0011] In some exemplary embodiments, the array substrate further comprises: a plurality of first connection lines located in the border region, wherein the scan connection ends of the scan lines are electrically connected to the scan driving circuit via the first connection lines, and the first connection lines are located on a side of the scan lines away from the substrate.

[0012] In some exemplary embodiments, the array substrate further comprises: a plurality of first connection electrodes located in the border region, wherein the scan connection end of the scan line is electrically connected to the first connection line via the first connection electrodes, and the first connection electrodes are located on a side of the first connection line away from the substrate.

[0013] In some exemplary embodiments, the first connecting electrode and the first common voltage signal line are in the same layer structure, the first common voltage signal line has a plurality of first hollow portions, and the orthographic projection of the first connecting electrode on the substrate is located within the first hollow portions.

[0014] In some exemplary embodiments, the array substrate further comprises: a first voltage line located in the border region, and a plurality of second connecting lines. The first voltage line is located on a side of the first common voltage signal line and the second common voltage signal line away from the display region, and is located on a side of the scan driver circuit closer to the display region. The first voltage line is electrically connected to the scan driver circuit via the second connecting lines, and the first voltage line is configured to provide a first voltage signal to the scan driver circuit.

[0015] In some exemplary embodiments, the border region includes at least a left border region and a right border region located on both sides of the display region along the first direction; the scan drive circuit includes a first drive circuit located in the left border region and a second drive circuit located in the right border region; the first drive circuit includes a plurality of cascaded first drive units, and the second drive circuit includes a plurality of cascaded second drive units. In the left border region, the first drive units of the first drive circuit at level 2a-1 and the first drive units of the second drive circuit at level 2a are electrically connected to the first voltage line via the same second connection line. In the right border region, the second drive units of the second drive circuit at level 2b-1 and the second drive units of the second drive circuit at level 2b are electrically connected to the first voltage line via the same second connection line; a and b are integers greater than 0.

[0016] In some exemplary embodiments, the array substrate further comprises: a plurality of second connection electrodes located in the border region, the first voltage line being electrically connected to the second connection line via the second connection electrodes; the second connection electrodes being located on a side of the first voltage line and the second connection line away from the substrate, the second connection electrodes being co-layered with the first common voltage signal line; and a plurality of notches being defined at an edge of the first common voltage signal line away from the display region, at least one of the notches being configured to accommodate a second connection electrode, the orthographic projection of the notch on the substrate overlapping the orthographic projection of the second connection electrode on the substrate in the first direction.

[0017] In some exemplary embodiments, the plurality of notches and the extending ends of the plurality of scan lines are spaced apart along the second direction.

[0018] In some exemplary embodiments, the frame area includes at least a left frame area and a right frame area located on both sides of the display area along the first direction, and each of the left frame area and the right frame area is provided with at least one dummy trace.

[0019] In some exemplary embodiments, the border area includes at least: a left border area and a right border area located on both sides of the display area along the first direction; in the left border area or the right border area, the scanning connection ends and the extension ends of the multiple scan lines are spaced apart along the second direction.

[0020] In some exemplary embodiments, the array substrate further comprises: a plurality of sub-pixels located in the display area, the plurality of sub-pixels being arranged in a plurality of rows, and each row of sub-pixels comprising a plurality of sub-pixels arranged along a first direction. The scan drive circuit comprises: a first drive circuit located in the left border area, and a second drive circuit located in the right border area. The scan connection end of at least one scan line extending to the left border area is electrically connected to the first drive circuit; the first drive circuit is configured to provide a data signal to the 2i-1th row of sub-pixels in the display area. The scan connection end of at least one scan line extending to the right border area is electrically connected to the second drive circuit; the second drive circuit is configured to provide a scan signal to the 2ith row of sub-pixels in the display area; i is an integer greater than 0.

[0021] In some exemplary embodiments, the border area further includes: a lower border area located on one side of the display area along the second direction. The array substrate further includes: a plurality of auxiliary scanning lines located in the lower border area and extending along the first direction, a plurality of first auxiliary driving units located in the left border area, and a plurality of second auxiliary driving units in the right border area. The at least one auxiliary scanning line includes: an auxiliary scanning connection end extending to the left border area and an auxiliary extension end extending to the right border area; or, an auxiliary scanning connection end extending to the right border area and an auxiliary extension end extending to the left border area. The auxiliary scanning connection end of the at least one auxiliary scanning line is electrically connected to the first auxiliary driving unit or the second auxiliary driving unit. In the left border area or the right border area, the auxiliary scanning connection ends and the auxiliary extension ends of the plurality of auxiliary scanning lines are spaced apart along the second direction.

[0022] In some exemplary embodiments, the plurality of first auxiliary driving units are configured to provide a reset signal to the first driving circuit; and the plurality of second auxiliary driving units are configured to provide a reset signal to the second driving circuit.

[0023] In some exemplary embodiments, the at least one dummy trace is arranged around an extended end of the at least one scan line from a side away from the display area.

[0024] On the other hand, an embodiment of the present disclosure provides a display device including the array substrate as described above.

[0025] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0026] Summary of the Figures

[0027] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0028] FIG1 is a schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0029] FIG2 is a schematic diagram of a touch structure of an array substrate according to at least one embodiment of the present disclosure;

[0030] FIG3 is a schematic diagram of a partial structure of a display area of ​​an array substrate according to at least one embodiment of the present disclosure;

[0031] FIG4 is a schematic diagram of a scan driving circuit according to at least one embodiment of the present disclosure;

[0032] FIG5 is a schematic diagram of a local film layer in FIG1 ;

[0033] 6A is a partial plan view of the boundary area between the display area and the right frame area according to at least one embodiment of the present disclosure;

[0034] FIG6B is a partial plan view of the right frame area according to at least one embodiment of the present disclosure;

[0035] FIG7A is a schematic partial cross-sectional view along the QQ' direction in FIG6A;

[0036] FIG7B is a schematic partial cross-sectional view along the RR′ direction in FIG6A ;

[0037] FIG8A is a schematic plan view of the array substrate after the first conductive layer is formed in FIG6A ;

[0038] FIG8B is a schematic plan view of the array substrate after the first conductive layer is formed in FIG6B ;

[0039] FIG9A is a schematic plan view of the array substrate after the semiconductor layer is formed in FIG6A ;

[0040] FIG9B is a schematic plan view of the array substrate after the semiconductor layer is formed in FIG6B ;

[0041] FIG10A is a schematic plan view of the array substrate after the second conductive layer is formed in FIG6A ;

[0042] FIG10B is a plan view of the array substrate after the second conductive layer is formed in FIG6B ;

[0043] FIG11A is a schematic diagram of the second conductive layer in FIG10A ;

[0044] FIG11B is a schematic diagram of the second conductive layer in FIG10B ;

[0045] FIG12 is a schematic plan view of the array substrate after the third insulating layer is formed in FIG6A;

[0046] FIG13 is a plan view schematically showing the array substrate after the first transparent conductive layer is formed in FIG6A;

[0047] FIG14A is a schematic plan view of the array substrate after the fourth insulating layer is formed in FIG6A;

[0048] FIG14B is a schematic plan view of the array substrate after the fourth insulating layer is formed in FIG6B ;

[0049] FIG15A is a schematic diagram of the second transparent conductive layer in FIG6A;

[0050] FIG15B is a schematic diagram of the second transparent conductive layer in FIG6B ;

[0051] FIG16 is a schematic diagram of a local area in FIG6A;

[0052] FIG17 is another schematic diagram of a scan driving circuit according to at least one embodiment of the present disclosure;

[0053] FIG18 is a schematic plan view of the lower right corner of an array substrate according to at least one embodiment of the present disclosure;

[0054] FIG19A is a schematic diagram of the array substrate after the first conductive layer is formed in FIG18 ;

[0055] FIG19B is a schematic diagram of the array substrate after the semiconductor layer is formed in FIG18;

[0056] FIG19C is a schematic diagram of the array substrate after the second conductive layer is formed in FIG18 ;

[0057] FIG19D is a schematic diagram of the second conductive layer in FIG19C ;

[0058] FIG19E is a schematic diagram of the array substrate after the fourth insulating layer is formed in FIG18 ;

[0059] FIG19F is a schematic diagram of the second transparent conductive layer in FIG18 ;

[0060] FIG20 is another schematic diagram of an array substrate according to at least one embodiment of the present disclosure;

[0061] FIG21 is a schematic diagram of a partial film layer of FIG20;

[0062] FIG. 22 is another schematic diagram of an array substrate according to at least one embodiment of the present disclosure.

[0063] Details

[0064] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into one or more forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other in any way.

[0065] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of various components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0066] In the present disclosure, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. In the present disclosure, "plurality" refers to a number of two or more.

[0067] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements are appropriately changed according to the direction in which the constituent elements are described. Therefore, the words and phrases are not limited to those described in the specification and can be appropriately replaced according to the circumstances.

[0068] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0069] In this disclosure, a transistor refers to a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0070] In this disclosure, to distinguish the two electrodes of a transistor other than the gate electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode. The first electrode can be a source electrode or a drain electrode, and the second electrode can be a drain electrode or a source electrode. In addition, the gate of the transistor is referred to as the control electrode. In cases where transistors with opposite polarity are used or where the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0071] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0072] In this disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus includes a state where the angle is greater than 85° and less than 95°.

[0073] The terms “approximately” and “substantially” in the present disclosure do not strictly define the limits and allow for errors within the range of process and measurement errors.

[0074] In some implementations, the array substrate may include: a plurality of scan lines extending along a first direction and a plurality of data lines extending along a second direction in the display area. The plurality of data lines and the plurality of scan lines may intersect to form a plurality of sub-pixel areas. A dummy trace may be provided in the border area of ​​the array substrate to ensure process uniformity. During the preparation of the array substrate, electrostatic discharge (ESD) occurs. If the extended ends of the scan lines are not electrically connected, static discharge will occur at the extended ends of the scan lines. Since the scan lines and the dummy traces are located in different film layers and their extension directions intersect, the static electricity released at the extended ends of the scan lines may break through the insulating layer between the scan lines and the dummy traces, causing a short circuit between the scan lines and the dummy traces. The short circuit between the scan lines and the dummy traces may affect the stability of the scan signals transmitted by the scan lines. For example, the dummy traces transmit common voltage signals, and after a short circuit, the scan signals may be pulled down, causing abnormalities in the scan signals and resulting in functional defects such as horizontal stripes, thereby affecting the display effect.

[0075] This embodiment provides an array substrate, comprising: a substrate, a plurality of scan lines, at least one dummy trace, and a scan drive circuit. The substrate includes a display area and a frame area located around the display area. The plurality of scan lines are located at least in the display area and extend along a first direction. At least one dummy trace is located in the frame area and extends along a second direction. The second direction intersects the first direction, for example, the second direction may be perpendicular to the first direction. The scan drive circuit is located in the frame area. At least one scan line includes a scan connection end extending to the frame area and an extension end, and the scan connection end is electrically connected to the scan drive circuit. At least one dummy trace is disconnected at the extension end of the at least one scan line, so that the at least one dummy trace does not overlap with the extension end of the at least one scan line in the orthographic projection of the substrate.

[0076] The array substrate provided in this embodiment can avoid the dummy line from crossing the extended end of the scan line by setting the dummy line to be disconnected at the extended end of the scan line, thereby reducing the risk of short circuit between the scan line and the dummy line caused by electrostatic discharge at the extended end of the scan line, and further improving the functional display defects such as horizontal stripes.

[0077] In some exemplary embodiments, at least one dummy trace may include: a plurality of dummy trace segments arranged sequentially along a second direction, with a first break provided between adjacent dummy trace segments in the second direction. The length of the first break along the second direction may be greater than the length of the extended end of at least one scan line along the second direction. For example, the first break may correspond to the extended end of a scan line. In this example, by disconnecting the dummy trace to form the first break, the dummy trace can be prevented from intersecting the extended end of the scan line.

[0078] In some exemplary embodiments, the array substrate may further include: a first common voltage signal line and a second common voltage signal line located in the border area. The first common voltage signal line is electrically connected to the second common voltage signal line, and the first common voltage signal line may be located on a side of the second common voltage signal line away from the substrate, and the first common voltage signal line and the second common voltage signal line at least partially overlap in their orthographic projections on the substrate. In some examples, at least one dummy trace segment of at least one dummy trace is electrically connected to at least one of the second common voltage signal line and the first common voltage signal line. For example, at least one dummy trace segment of the dummy trace may be electrically connected to the second common voltage signal line and the first common voltage signal line, or at least one dummy trace segment of the dummy trace may be electrically connected to the first common voltage signal line, or at least one dummy trace segment of the dummy trace may be electrically connected to the second common voltage signal line. In some examples, all dummy trace segments of the dummy trace can be electrically connected to the first common voltage signal line or the second common voltage signal line; alternatively, some dummy trace segments can be electrically connected to the first common voltage signal line, while other dummy trace segments can be electrically connected to the second common voltage signal line. This embodiment is not limited to this. In this embodiment, by providing a dummy trace electrically connected to the first common voltage signal line or the second common voltage signal line, common voltage transmission is achieved, which can prevent the floating dummy trace from affecting surrounding structures.

[0079] The solution of this embodiment is illustrated below through multiple examples.

[0080] FIG1 is a schematic diagram of an array substrate according to at least one embodiment of the present disclosure. FIG1 only briefly illustrates the partial structures of the display area and the frame area. In some examples, as shown in FIG1 , the array substrate of this example may include: a display area AA and a frame area BB located around the display area AA. The frame area BB may surround the display area AA. In some examples, the display area AA may be rectangular, and the frame area BB may be a rectangular ring. However, this embodiment is not limited to this. In other examples, the display area AA may have other shapes.

[0081] In some examples, as shown in FIG1 , the border area BB may include: a left border area B1, a right border area B2, an upper border area B3, and a lower border area B4. The left border area B1 and the right border area B2 may be located on both sides of the display area AA along a first direction X, and the upper border area B3 and the lower border area B4 may be located on both sides of the display area AA along a second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X may be perpendicular to the second direction Y. The left border area B1 may be connected to the upper border area B3 and the lower border area B4, and the right border area B2 may be connected to the upper border area B3 and the lower border area B4. The connected area of ​​the left border area B1 and the upper border area B3 may form an upper left corner, the connected area of ​​the right border area B2 and the upper border area B3 may form an upper right corner, the connected area of ​​the left border area B1 and the lower border area B4 may form a lower left corner, and the connected area of ​​the right border area B2 and the lower border area B4 may form a lower right corner.

[0082] In some examples, the left frame area B1 and the right frame area B2 may be provided with a scan driving circuit, and the bottom frame area B4 may be provided with an integrated chip (eg, a TDDI chip).

[0083] In some examples, the display device including the array substrate may be a liquid crystal display device, for example, a touch display device with an embedded touch structure. For example, the display device may include: an array substrate, an opposing substrate, and a liquid crystal layer disposed between the array substrate and the opposing substrate. In some examples, the display device may be an advanced super-dimensional switch (ADS) type touch display device, or a high-aperture ratio advanced super-dimensional switch (HADS) type touch display device. The array substrate may include pixel electrodes and common electrodes, and the pixel electrodes and common electrodes may generate an electric field that controls the deflection of liquid crystal molecules in the liquid crystal layer. The opposing substrate may include a base substrate, a color filter layer, and a black matrix.

[0084] Figure 2 is a schematic diagram of the touch structure of the array substrate of at least one embodiment of the present disclosure. In some examples, the array substrate of this example may adopt self-capacitive touch technology. As shown in Figure 2, the touch structure of the array substrate may include: a plurality of touch sensing blocks (as self-capacitive electrodes) 17 arranged in an array, and a plurality of touch signal lines 16 electrically connected to the plurality of touch sensing blocks 17 respectively. The black dots in Figure 2 represent electrical connections. The plurality of touch signal lines 16 may extend along the second direction Y and be arranged along the first direction X. Each touch signal line 16 may be electrically connected to one touch sensing block 17. In some examples, when a touch is performed, a touching object (for example, a human finger) touches a display device including an array substrate, and the capacitance of the touch sensing block 17 at the touch point changes. The integrated chip can determine the touch position by detecting the change in the self-capacitance of the touch sensing block 17.

[0085] FIG3 is a schematic diagram of a partial structure of the display area of ​​an array substrate of at least one embodiment of the present disclosure. In some examples, as shown in FIG1 and FIG3, the array substrate of this example may include at least: a substrate and a plurality of pixel units disposed on the substrate and located in the display area AA, a plurality of touch signal lines 16, a plurality of data lines 12, and a plurality of scan lines 11. The plurality of data lines 12 may extend along the second direction Y and be arranged along the first direction X; the plurality of scan lines 11 may extend along the first direction X and be arranged sequentially along the second direction Y. The plurality of data lines 12 and the plurality of scan lines 11 may intersect to form a plurality of sub-pixel areas. For example, the area defined by the intersection of adjacent data lines 12 and adjacent scan lines 11 may be a sub-pixel area. One sub-pixel may be provided in each sub-pixel area. At least one pixel unit may include three sub-pixels (for example, a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3) arranged sequentially along the first direction X. The multiple sub-pixels in the display area are arranged in multiple rows and columns. A row of sub-pixels includes multiple sub-pixels arranged along a first direction X, and a column of sub-pixels includes multiple sub-pixels arranged along a second direction Y. For example, after being combined with an opposing substrate, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 can be configured to emit light of different colors.

[0086] In some examples, the sub-pixel area may include: an opening area and a non-opening area surrounding the opening area. In some examples, the non-opening area may be an area blocked by the black matrix of the opposing substrate, and the opening area may be an area not blocked by the black matrix. For example, adjacent scan lines 11 and data lines 12 may be located in the non-opening area. In some examples, the array substrate of this embodiment is used to implement a display function, and the opening area of ​​each sub-pixel area may be configured to perform display, and the non-opening area surrounds the opening area and does not perform display. However, this embodiment is not limited to this. In some examples, the array substrate may be used to implement other functions.

[0087] In some examples, as shown in FIG3 , each sub-pixel may include a switching transistor 14, a pixel electrode 13, and a common electrode located within the sub-pixel region. The switching transistor 14 may be located in a non-opening region of the sub-pixel region, such as at the intersection of the data line 12 and the scan line 11. The pixel electrode 13 and the common electrode may be located at least in the opening region of the sub-pixel region. The common electrodes of multiple sub-pixels may be interconnected and integrated.

[0088] In some examples, as shown in FIG3 , the switching transistor may be a thin film transistor (TFT). The switching transistor 14 may include a control electrode, an active layer, a first electrode, and a second electrode. The control electrode of the switching transistor 14 may be electrically connected to the scan line 11, the first electrode may be electrically connected to the data line 12, and the second electrode may be electrically connected to the pixel electrode 13. Under the control of the scan line 11, the switching transistor 14 may provide a data signal transmitted by the data line 12 to the pixel electrode 13.

[0089] In some examples, as shown in FIG3 , a touch signal line 16 may be provided in conjunction with each pixel unit, and each touch signal line 16 may be provided in the same position in the corresponding pixel unit. For example, the touch signal line 16 may be located on one side of the data line 12 connected to the first sub-pixel P1 of the corresponding pixel unit. A column of pixel units may be provided between two adjacent touch signal lines 16. Three data lines 12 may be provided between two adjacent touch signal lines 16, and the three data lines 12 may be electrically connected to the switching transistors 14 of the three columns of sub-pixels, respectively. However, this embodiment is not limited to this. In other examples, two or three touch signal lines may be provided in conjunction with at least one pixel unit. For example, the two touch signal lines may be located on the same side of the data line connected to the first sub-pixel of the corresponding pixel unit; or, three touch signal lines may be provided in correspondence with at least one pixel unit, and the three data lines connected to the three sub-pixels of the pixel unit may be adjacent to the three touch signal lines in a one-to-one correspondence. In other words, multiple data lines and multiple touch signal lines may be arranged in a spaced relationship along the first direction.

[0090] In some examples, the common electrodes of sub-pixels can be reused as a touch sensing block. During the display phase, a common voltage is provided to the common electrodes via touch signal lines 16 to implement the display function. During the touch phase, touch signals detected by the common electrodes are transmitted via touch signal lines 16 to implement the touch function. The common electrodes of multiple sub-pixels can be connected to form a touch sensing block. For example, isolated common electrodes within multiple pixel units can be connected to form a touch sensing block.

[0091] FIG4 is a schematic diagram of a scan drive circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG1 and FIG4 , the array substrate may further include a scan drive circuit located in the border area BB. The scan drive circuit may include a first drive circuit 24a located in the left border area B1 and a second drive circuit 24b located in the right border area B2. The first drive circuit 24a may include a plurality of first drive units 241, which may be a plurality of shift register circuits in a cascade relationship; the second drive circuit 24b may include a plurality of second drive units 242, which may be a plurality of shift register circuits in a cascade relationship. The plurality of first drive units 241 may be arranged sequentially along the second direction Y in the left border area B1, and the plurality of second drive units 242 may be arranged sequentially along the second direction Y in the right border area B2.

[0092] In some examples, as shown in Figures 1 and 4, a first drive unit 241 can be configured to provide a scan signal to a row of sub-pixels through a scan line 11, for example, a scan signal can be provided to the 2i-1th row of sub-pixels in the display area, and a second drive unit 242 can be configured to provide a scan signal to a row of sub-pixels through a scan line 11, for example, a scan signal can be provided to the 2ith row of sub-pixels, where i is an integer greater than 0. In other words, the scan signals for the odd-numbered rows of sub-pixels in the display area can be provided by the first drive circuit 24a, and the scan signals for the even-numbered rows of sub-pixels can be provided by the second drive circuit 24b, thereby realizing a unilateral drive mode with odd and even rows crossed. However, this embodiment is not limited to this. In other examples, the scan signals for the odd-numbered rows of sub-pixels can be provided by the second drive circuit, and the scan signals for the even-numbered rows of sub-pixels can be provided by the first drive circuit. The use of an odd-even row crossed drive mode in this example can reduce the number of drive units, thereby facilitating a narrow frame.

[0093] In some examples, as shown in FIG4 , the first driving circuit 24a includes multiple first driving units 241 that can be cascade-connected. For example, the first driving circuit 24a can include a first-stage first driving unit to an N-stage first driving unit, where N is an integer greater than 0. The output end of the a-stage first driving unit can provide an input signal to the a+2-stage first driving unit, and the output end of the a+2-stage first driving unit can provide a reset signal to the a-stage first driving unit; a is an integer greater than 0.

[0094] In some examples, each stage of the first driving unit of the first driving circuit 24a can be configured to provide a scan signal to an odd-numbered row of sub-pixels. For example, the first stage of the first driving unit can be configured to provide a scan signal to the first row of sub-pixels, the second stage of the first driving unit can be configured to provide a scan signal to the third row of sub-pixels, the third stage of the first driving unit can be configured to provide a scan signal to the fifth row of sub-pixels, the fourth stage of the first driving unit can be configured to provide a scan signal to the seventh row of sub-pixels, and so on.

[0095] In some examples, as shown in FIG4 , the plurality of second driving units 242 included in the second driving circuit 24 b may be connected in cascade. For example, the second driving circuit 24 b may include a first-stage second driving unit to an M-th-stage second driving unit, where M is an integer greater than 0. The output end of the b-th-stage second driving unit may provide an input signal to the b+2-th-stage second driving unit, and the output end of the b+2-th-stage second driving unit may provide a reset signal to the b-th-stage second driving unit; b is an integer greater than 0.

[0096] In some examples, each stage of the second driving unit of the second driving circuit 24b can be configured to provide a scan signal to an even-numbered row of sub-pixels. For example, the first stage of the second driving unit can be configured to provide a scan signal to the second row of sub-pixels, the second stage of the second driving unit can be configured to provide a scan signal to the fourth row of sub-pixels, the third stage of the second driving unit can be configured to provide a scan signal to the sixth row of sub-pixels, the fourth stage of the second driving unit can be configured to provide a scan signal to the eighth row of sub-pixels, and so on. In some examples, the sum of N and M can be equal to the total number of rows of sub-pixels in the display area.

[0097] In some examples, each of the multiple first drive units 241 and the multiple second drive units 242 may include at least: a first control transistor, a second control transistor and a first capacitor. The control electrode of the first control transistor may be electrically connected to the reset signal line, the first electrode may be electrically connected to the first voltage line, and the second electrode may be electrically connected to the control electrode of the second control transistor. The second electrode of the second control transistor may be electrically connected to the output end of the drive unit. The first electrode of the first capacitor may be electrically connected to the control electrode of the second control transistor, and the second electrode of the first capacitor may be electrically connected to the output end of the drive unit. The connection point between the second electrode of the first control transistor, the first electrode of the first capacitor and the control electrode of the second control transistor may be referred to as a pull-up node PU. For example, taking the first control transistor and the second control transistor as N-type transistors, after the potential of the pull-up node PU is pulled low, the second control transistor cannot be turned on, and the output end of the drive unit stops outputting. The first voltage line can be configured to provide a low-level first voltage signal.

[0098] In some examples, as shown in FIG4 , the reset signal line connected to the a-th first driving unit of the first driving circuit 24 a can be electrically connected to the output terminal of the a+2-th first driving unit. The reset signal line connected to the b-th second driving unit of the second driving circuit 24 b can be electrically connected to the output terminal of the b+2-th second driving unit.

[0099] FIG5 is a schematic diagram of a partial film layer in FIG1 . In some examples, as shown in FIG1 and FIG5 , the scan line 11 may include: a scan connection end 111 extending to the border area BB and an extension end 112. Since the array substrate of this example adopts a unilateral driving method with odd and even rows crossed, the scan connection end 111 of the scan line 11 may extend to the left border area B1 and be electrically connected to the first drive unit 241 of the first drive circuit, or may extend to the right border area B2 and be electrically connected to the second drive unit 242 of the second drive circuit; the extension end 112 of the scan line 11 may extend to the left border area B1 or the right border area B2 as an independently set end. For example, the scan line 11 electrically connected to the sub-pixels in the 2i-1th row may include: a scan connection end 111 extending to the left border area B1 and an extension end 112 extending to the right border area B2, and the scan connection end 111 extending to the left border area B1 can be electrically connected to a first driving unit 241 of the first driving circuit; the scan line 11 electrically connected to the sub-pixels in the 2ith row may include: an extension end 112 extending to the left border area B1 and a scan connection end 111 extending to the right border area B2, and the scan connection end 111 extending to the right border area B2 can be electrically connected to a second driving unit 242 of the second driving circuit.

[0100] In some examples, as shown in Figures 1 and 5, within the left frame area B1, the scan connection ends 111 and the extended ends 112 of the plurality of scan lines 11 may be spaced apart along the second direction Y. Within the right frame area B2, the extended ends 112 and the scan connection ends 111 of the plurality of scan lines 11 may be spaced apart along the second direction Y. The arrangement of the scan lines in this example can implement a unilateral driving method with odd and even rows interleaved.

[0101] In some examples, as shown in Figures 1 and 5, the array substrate may further include: a plurality of first connection lines (for example, including a plurality of first connection lines 231 and 232) located in the border area BB. The plurality of first connection lines 231 may be located in the left border area B1, and the first connection line 231 may be configured to electrically connect the output end of the first drive unit and the scan connection end 111 of the scan line 11 extending to the left border area B1. The plurality of first connection lines 232 may be located in the right border area B2, and the first connection line 232 may be configured to electrically connect the output end of the second drive unit and the scan connection end 111 of the scan line 11 extending to the right border area B2. The plurality of first connection lines 231 and 232 may be of the same layer structure and may be located on the side of the plurality of scan lines 11 away from the substrate.

[0102] In some examples, the first connection line 231 (or the first connection line 232) can be directly electrically connected to the scan connection terminal 111 of the scan line 11. For example, the scan line 11 can be located in the first conductive layer, the first connection line 231 or 232 can be located in the second conductive layer, a first insulating layer can be provided between the first conductive layer and the second conductive layer, and the first connection line 231 or 232 located in the second conductive layer can be electrically connected to the scan connection terminal 111 of the scan line 11 located in the first conductive layer through a via hole provided in the first insulating layer. However, this embodiment is not limited to this.

[0103] In some examples, as shown in Figures 1 and 5, the array substrate may further include: a first common voltage signal line 21 and a second common voltage signal line 22 located in the border area BB. The first common voltage signal line 21 may be located on a side of the second common voltage signal line 22 away from the substrate. The first common voltage signal line 21 may be a ring-shaped line surrounding the display area AA, for example, it may be a rectangular ring. The second common voltage signal line 22 may be a ring-shaped line surrounding the display area AA, for example, it may be a rectangular ring. The orthographic projection of the first common voltage signal line 21 on the substrate may at least partially overlap with the orthographic projection of the second common voltage signal line 22 on the substrate. For example, the orthographic projection of the first common voltage signal line 21 on the substrate may cover the orthographic projection of the second common voltage signal line 22 on the substrate.

[0104] In some examples, as shown in FIG1 , the first common voltage signal line 21 can be electrically connected to the second common voltage signal line 22 via a plurality of first vias V1. The first common voltage signal line 21 and the second common voltage signal line 22 can be configured to transmit a common voltage Vcom. For example, the first common voltage signal line 21 can be located in the second transparent conductive layer, the second common voltage signal line 22 can be located in the first conductive layer, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer can be disposed between the first conductive layer and the second transparent conductive layer. The fourth insulating layer can have a plurality of first vias V1 that expose a portion of the surface of the second common voltage signal line 22. The first common voltage signal line 21 can be electrically connected to the second common voltage signal line 22 via the plurality of first vias V1.

[0105] In some examples, as shown in FIG1 , the plurality of first vias V1 are divided into multiple groups. For example, a group of first vias V1 may include four first vias V1 arranged in a 2×2 array. The multiple groups of first vias V1 may be arranged in a ring around the display area AA to ensure that multiple locations of the first common voltage signal line 21 are electrically connected to the second common voltage signal line 22, thereby ensuring uniform transmission of the common voltage.

[0106] In some examples, as shown in Figures 1 and 5, the array substrate may further include: at least one dummy trace 25 located in the border area BB and extending along the second direction Y. In this example, a dummy trace 25 is provided in the left border area B1, and a dummy trace 25 is provided in the right border area B2. This example ensures the process uniformity of the array substrate by providing dummy traces in both the left and right border areas. The number of dummy traces can be determined according to the resolution of the array substrate and the number of touch sensing blocks. This embodiment is not limited to this. In other examples, two dummy traces 25 can be provided in the left border area B1, and two dummy traces 25 can be provided in the right border area B2.

[0107] In some examples, as shown in Figures 1 and 5 , the dummy traces 25 can be co-layered with the data lines 12 and touch signal lines 16 in the display area AA. Within the left and right border areas B1 and B2, the dummy traces 25 can be located on the side of the first and second common voltage signal lines 21 and 22 that is closer to the display area AA.

[0108] In some examples, as shown in Figures 1 and 5, the dummy routing line 25 located in the right frame area B2 may include: a plurality of dummy routing segments arranged in sequence along the second direction Y and extending along the second direction Y. The plurality of dummy routing segments may, for example, include: two first dummy routing segments 251 and a plurality of second dummy routing segments 252. Figures 1 and 5 illustrate this by taking one second dummy routing segment 252 as an example. The plurality of second dummy routing segments 252 may be arranged in sequence between the two first dummy routing segments 251. In this example, the number of second dummy routing segments within the right frame area B2 may be determined based on the number of extended ends of the scan lines within the right frame area B2. For example, if the number of extended ends of the scan lines within the right frame area B2 is N, the number of second dummy routing segments 252 of the dummy routing line may be N-1.

[0109] In some examples, as shown in Figures 1 and 5, the two first dummy trace segments 251 of the dummy trace 25 located in the right frame area B2 may not overlap with the orthographic projection of the scan line 11 of the array substrate on the substrate. The orthographic projection of at least one second dummy trace segment 252 of the dummy trace 25 on the substrate may partially overlap with the orthographic projection of the scan connection end 111 of a scan line 11 on the substrate.

[0110] In some examples, as shown in Figures 1 and 5, the first dummy routing segment 251 of the dummy routing line 25 located within the right frame area B2 may be provided with a first dummy connection portion 2511 on a side away from the second dummy routing segment 252. The first dummy connection portion 2511 and the first dummy routing segment 251 may be an integral structure connected to each other. The first dummy connection portion 2511 may extend at least along the second direction Y and be electrically connected to the second common voltage signal line 22 through a plurality of second vias V2. The first dummy routing segment 251 may be provided with a second dummy connection portion 2512 on a side near one end of the second dummy routing segment 252 and away from the display area AA. The second dummy connection portion 252 may extend at least along the first direction X and be electrically connected to the first common voltage signal line 21. The second dummy routing segment 252 may be provided with a third dummy connection portion 2521 and a fourth dummy connection portion 2522 on a side away from the display area AA. The third dummy connection portion 2521 and the fourth dummy connection portion 2522 of the second dummy routing segment 252 can be located on both sides of the scan connection end 111 of a scan line 11 along the second direction Y. The third dummy connection portion 2521 and the fourth dummy connection portion 2522 can be an integrated structure connected to the second dummy routing segment 252. For example, the third dummy connection portion 2521 is connected to one end of the second dummy routing segment 252, and the fourth dummy connection portion 2522 is connected to the other end of the second dummy routing segment 252. The third dummy connection portion 2521 and the fourth dummy connection portion 2522 can be located on a side of the second common voltage signal line 22 close to the display area AA and electrically connected to the first common voltage signal line 21. In this example, the first dummy routing segment 251 of the dummy routing is electrically connected to the second common voltage signal line 22 and the first common voltage signal line 21, and the second dummy routing segment 252 is electrically connected to the first common voltage signal line 21, thereby receiving the common voltage. This can avoid the floating connection of the dummy routing to generate capacitive coupling and affect the capacitance of the surrounding touch sensing blocks, thereby avoiding affecting the touch effect.

[0111] In some examples, as shown in Figures 1 and 5, a first break can be provided between adjacent dummy trace segments arranged sequentially along the second direction Y of the dummy trace 25 located in the right frame area B2. For example, a first break K1 can be provided between the first dummy trace segment 251 and the second dummy trace segment 252. The first break K1 corresponds to the location of the extended end 112 of a scan line 11. The length of the first break K1 along the second direction Y can be greater than the length of the extended end 112 of the scan line 11 along the second direction Y. By providing the first break, the orthographic projections of the dummy trace 25 and the extended end 112 of the scan line 11 on the substrate do not overlap, thereby preventing the dummy trace 25 from intersecting the extended end 112 of the scan line 11. This reduces the risk of electrostatic discharge at the extended end 112 of the scan line 11, which could break through the insulating layer and cause a short circuit between the dummy trace 25 and the scan line 11, thereby improving the resulting horizontal stripe-like functional display defects.

[0112] The design of the dummy traces in the left border area is similar to that in the right border area, so it will not be described in detail here.

[0113] Figure 6A is a partial plan view schematic diagram of the boundary area between the display area and the right frame area of ​​at least one embodiment of the present disclosure. Figure 6B is a partial plan view schematic diagram of the right frame area of ​​at least one embodiment of the present disclosure. Figure 6A illustrates the partial structure of the second drive unit of level 2b, the second drive unit of level 2b+1, and the second drive unit of level 2b+2 in the right frame area B2. Figure 6B illustrates the partial structure of the second drive unit of level 2b-1, the second drive unit of level 2b, the second drive unit of level 2b+1, and the second drive unit of level 2b+2 in the right frame area B2. Wherein, b is an integer greater than 0. Figure 7A is a partial cross-sectional schematic diagram along the Q-Q' direction in Figure 6A. Figure 7B is a partial cross-sectional schematic diagram along the R-R' direction in Figure 6A. In this example, a column of dummy sub-pixels can be set on the side of the multiple columns of sub-pixels close to the right frame area B2.

[0114] In some examples, as shown in Figures 7A and 7B, the array substrate may include: a substrate 300, a first conductive layer, a semiconductor layer, a second conductive layer, a first transparent conductive layer, and a second transparent conductive layer sequentially disposed on the substrate 300. A first insulating layer 301 may be disposed between the first conductive layer and the semiconductor layer, a second insulating layer 302 and a third insulating layer 303 may be disposed between the second conductive layer and the first transparent conductive layer, and a fourth insulating layer 304 may be disposed between the first transparent conductive layer and the second transparent conductive layer. The semiconductor layer and the second conductive layer may be in direct contact. The first insulating layer 301, the second insulating layer 302, and the fourth insulating layer 304 may be inorganic insulating layers, and the third insulating layer 303 may be an organic insulating layer. This embodiment is not limited to this.

[0115] The technical solution of this embodiment is further explained below through the preparation process of the array substrate of this exemplary embodiment. The "patterning process" mentioned in this disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in this disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0116] The phrases "A and B are arranged in the same layer" or "A and B are in the same layer structure" in this disclosure mean that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in the direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. In this example, "the shape of A" refers to the shape of the orthographic projection of A on the substrate.

[0117] The preparation process of the array substrate of this embodiment includes the following steps.

[0118] (1) Provide a substrate. In some examples, the substrate may be a transparent substrate, such as a quartz substrate, a glass substrate, or an organic resin substrate. However, this embodiment is not limited thereto.

[0119] (2) Forming a first conductive layer. In some examples, a first conductive film is deposited on a substrate, and the first conductive layer is patterned by a patterning process to form the first conductive layer. In some examples, the first conductive layer may also be referred to as a gate metal layer.

[0120] Figure 8A is a schematic plan view of the array substrate after the first conductive layer is formed in Figure 6A. Figure 8B is a schematic plan view of the array substrate after the first conductive layer is formed in Figure 6B.

[0121] In some examples, as shown in Figures 8A and 8B, the first conductive layer may at least include: multiple scan lines 11 and control electrodes 141 of multiple switching transistors located in the display area AA, multiple first virtual control blocks 141a, and a second common voltage signal line 22 located in the right frame area B2, a first voltage line 23, control electrodes of transistors of multiple second driving units (for example, including the control electrode 261 of the first control transistor, the control electrode 271 of the second control transistor) and the first plate 281 of the first capacitor, and a reset signal line 291.

[0122] In some examples, as shown in FIG8A , multiple scan lines 11 within the display area AA may extend along a first direction X and be arranged sequentially along a second direction Y. The scan line 11 may be substantially straight and extend along the first direction X. The control electrodes 141 of the multiple switching transistors arranged along the first direction X may be located on the same side of a scan line 11 along the second direction Y and may be interconnected and integrally connected to the scan line 11. The control electrodes 141 of the switching transistors may be substantially rectangular, and the rectangle may have chamfered or rounded corners.

[0123] In some examples, as shown in FIG8A , the first dummy control block 141a can be located on a side of the control electrodes 141 of multiple switching transistors arranged along the first direction X, close to the right frame area B2. Multiple first dummy control blocks 141a can be arranged along the second direction Y at the junction of the display area AA and the right frame area B2. The first dummy control block 141a can be an integral structure interconnected with the adjacent scan line 11. The first dummy control block 141a can serve as the control electrode of the switching transistor of the dummy sub-pixel.

[0124] In some examples, as shown in Figures 8A and 8B, within the right frame area B2, the extended ends 112 and the scan connection ends 111 of the plurality of scan lines 11 can be spaced apart along the second direction Y and located on a side of the second common voltage signal line 22 that is closer to the display area AA. The distance between the scan connection end 111 and the second common voltage signal line 22 along the first direction X can be smaller than the distance between the extended ends 112 and the second common voltage signal line 22 along the first direction X.

[0125] In some examples, as shown in Figures 8A and 8B, the second common voltage signal line 22 can extend at least along the second direction Y within the right frame area B2; and the first voltage line 23 can extend at least along the second direction Y within the right frame area B2. The first voltage line 23 can be located on a side of the second common voltage signal line 22 away from the display area AA. The first voltage line 23 can be configured to provide a low-level first voltage signal VGL to the plurality of second driving units.

[0126] In some examples, as shown in Figures 8A and 8B , the second driving unit can be located on a side of the first voltage line 23 away from the display area AA. The first plate 281 of the first capacitor of the second driving unit can serve as the first electrode of the first capacitor. The first plates 281 of the first capacitors of the plurality of cascaded second driving units can be arranged sequentially along the second direction Y. The orthographic projection of the first plates 281 of the first capacitor on the substrate can be substantially rectangular.

[0127] In some examples, as shown in FIG8B , the first plate 281 of the first capacitor and the control electrode 271 of the second control transistor of the second drive unit can be interconnected as an integral structure. The control electrode 271 of the second control transistor can be located on the side of the first plate 281 of the first capacitor away from the display area AA. The shape of the control electrode 271 of the second control transistor can be roughly rectangular. A control connection block 271-1 can be provided on the side of the control electrode 271 of the second control transistor away from the display area AA. One end of the control connection block 271-1 is connected to the control electrode 271 of the second control transistor, and the other end extends along the first direction X to the side away from the display area AA. The shape of the control connection block 271-1 of the second drive unit in the 2b-1 stage can be roughly 9-shaped, and the shape of the control connection block 271-1 of the second drive unit in the 2b stage can be roughly P-shaped. The control connection block 271-1 and the control electrode 271 of the second control transistor can be interconnected as an integral structure.

[0128] In some examples, as shown in FIG8B , the control electrode 261 of the first control transistor can be located on a side of the control electrode 271 of the second control transistor away from the display area AA along the first direction X. The control electrode 261 of the first control transistor of the second drive unit of the 2b-1 stage can be located on a side opposite to the control connection block 271-1 of the second control transistor along the second direction Y. The control electrode 261 of the first control transistor of the second drive unit of the 2b stage can be located on a side of the control connection block 271-1 of the second control transistor along the second direction Y. The shape of the control electrode 261 of the first control transistor can be substantially rectangular. The area of ​​the control electrode 261 of the first control transistor can be smaller than the area of ​​the control electrode 271 of the second control transistor.

[0129] In some examples, as shown in FIG8B , the first conductive layer pattern of the second driving unit of the 2b-1 stage and the first conductive layer pattern of the second driving unit of the 2b stage can be substantially symmetrical about a midline thereof in the second direction Y. The first conductive layer pattern of the second driving unit of the 2b stage and the first conductive layer pattern of the second driving unit of the 2b+1 stage can be substantially symmetrical about a midline thereof in the second direction Y.

[0130] In some examples, as shown in FIG8B , the reset signal line 291 can be located on a side of the control electrode 261 of the first control transistor away from the display area AA, and the reset signal line 291 and the control electrode 261 of the first control transistor can be an integral structure connected to each other. For example, the reset signal line 291 connected to the control electrode 261 of the first control transistor of the second driver unit of the 2b-1 stage can be electrically connected to the output terminal of the second driver unit of the 2b+1 stage.

[0131] (3) Forming a semiconductor layer. In some examples, a first insulating film and a semiconductor film are sequentially deposited on a substrate, and the semiconductor film is patterned by a patterning process to form a first insulating layer and a semiconductor layer disposed on the first insulating layer.

[0132] Fig. 9A is a schematic plan view of the array substrate after the semiconductor layer is formed in Fig. 6A. Fig. 9B is a schematic plan view of the array substrate after the semiconductor layer is formed in Fig. 6B.

[0133] In some examples, as shown in Figures 9A and 9B, the semiconductor layer may include at least: an active layer 140 of multiple switching transistors 14 located in the display area AA, and an active layer of multiple transistors of the second driving unit located in the right frame area B2 (for example, including at least: an active layer 260 of the first control transistor 26 and an active layer 270 of the second control transistor 27).

[0134] 9A , the active layer 140 of the switch transistor 14 may be substantially rectangular with chamfered or rounded corners, and the orthographic projection of the control electrode 141 of the switch transistor 14 on the substrate may cover the orthographic projection of the active layer 140 on the substrate.

[0135] In some examples, as shown in FIG9A , at the junction of the display area AA and the right frame area B2, the semiconductor layer may further include: a plurality of first dummy active blocks 140 a. The plurality of first dummy active blocks 140 a may be arranged in a column along the second direction Y, and located on a side of the active layer 140 of the plurality of switching transistors 14 close to the right frame area B2. The first dummy active blocks 140 a may serve as the active side of the switching transistors of the dummy sub-pixels. In this example, by providing a plurality of first dummy active blocks 140 a, uniformity of film preparation can be ensured.

[0136] 9A , the first dummy active block 140a may be substantially rectangular with chamfered or rounded corners. The orthographic projection of the first dummy active block 140a on the substrate may be within the orthographic projection of the first dummy control block 141a on the substrate.

[0137] 9B , the active layer 260 of the first control transistor 26 may be substantially rectangular with chamfered or rounded corners. The orthographic projection of the control electrode 261 of the first control transistor 26 on the substrate may cover the orthographic projection of the active layer 260 on the substrate.

[0138] 9B , the active layer 270 of the second control transistor 27 may be substantially rectangular with chamfered or rounded corners. The orthographic projection of the control electrode 271 of the second control transistor 27 on the substrate may cover the orthographic projection of the active layer 270 on the substrate.

[0139] In some examples, as shown in FIG9B , the semiconductor layer pattern of the second driving unit of the 2b-1 stage and the semiconductor layer pattern of the second driving unit of the 2b stage can be substantially symmetrical about a midline of the two driving units in the second direction Y. The semiconductor layer pattern of the second driving unit of the 2b stage and the semiconductor layer pattern of the second driving unit of the 2b+1 stage can be substantially symmetrical about a midline of the two driving units in the second direction Y.

[0140] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. The material of the semiconductor layer may include, for example, one or more materials such as amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, polythiophene, etc. The channel region may not be doped with impurities and have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, and are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors.

[0141] (4) Forming a second conductive layer. In some examples, a second conductive film is deposited on the substrate forming the aforementioned structure, and the second conductive film is patterned through a patterning process to form a second conductive layer. In some examples, the second conductive layer may also be referred to as a source / drain metal layer.

[0142] Figure 10A is a schematic plan view of the array substrate after the second conductive layer is formed in Figure 6A. Figure 10B is a schematic plan view of the array substrate after the second conductive layer is formed in Figure 6B. Figure 11A is a schematic view of the second conductive layer in Figure 10A. Figure 11B is a schematic view of the second conductive layer in Figure 10B.

[0143] In some examples, as shown in Figures 10A to 11B, the second conductive layer may include at least: multiple data lines 12, multiple touch signal lines 16, second poles 142 of multiple switching transistors, and dummy data lines 18 located in the display area AA; dummy traces 25 located in the right frame area B2, first connecting lines 232, first poles and second poles of multiple transistors of multiple second driving units (for example, including the first pole 272 and second pole 273 of the second control transistor, the first pole 262 and second pole 263 of the first control transistor), the second plate 282 of the first capacitor, and a second connecting line 292.

[0144] In some examples, as shown in Figures 10A and 11A , the shape of the data line 12 within the display area AA can be substantially a zigzag line extending along the second direction Y. The orthographic projection of the data line 12 on the substrate at least partially overlaps the orthographic projection of the first region of the active layer 140 of the switching transistor on the substrate. The overlapping portion of the data line 12 and the active layer 140 of the switching transistor can serve as the first electrode of the switching transistor.

[0145] 10A and 11A , the second electrode 142 of the switch transistor may be substantially L-shaped. The orthographic projection of the second electrode 142 of the switch transistor on the substrate at least partially overlaps the orthographic projection of the second region of the active layer 140 of the switch transistor on the substrate.

[0146] In some examples, as shown in FIG10A and FIG11A , the touch signal lines 16 in the display area AA may be substantially in the shape of a broken line extending along the second direction Y. Three data lines 12 may be arranged between two adjacent touch signal lines 16 .

[0147] In some examples, as shown in Figures 10A and 11A, the dummy data line 18 can be located on a side of the touch signal line 16 near the right frame area B2. The dummy data line 18 can be connected to a column of dummy sub-pixels. The dummy data line 18 can be shaped substantially like a zigzag line extending along the second direction Y. The orthographic projection of the dummy data line 18 on the substrate partially overlaps the orthographic projection of the plurality of first dummy active blocks 140a on the substrate.

[0148] In some examples, as shown in Figures 10A and 11B, a dummy trace 25 is provided in the right frame area B2. The dummy trace 25 is located on one side of the dummy data line 18. The dummy trace 25 may include at least a plurality of second dummy trace segments 252. The second dummy trace segments 252 may be substantially Σ-shaped. The orthographic projection of the second dummy trace segment 252 on the substrate overlaps with the orthographic projection of the scan line extending from the scan connection end 111 to the right frame area B2. The third dummy connection portion 2521 and the fourth dummy connection portion 2522 of the second dummy trace segment 252 may be located on either side of the scan connection end 111 of a scan line along the second direction Y. The third dummy connection portion 2521 and the fourth dummy connection portion 2522 of the second dummy trace segment 252 and the scan connection end 111 of the scan line may be aligned in the second direction Y. A first break K1 may be provided between adjacent second dummy wiring segments 252 , and the extended end 112 of the scan line may be inserted into the first break K1 .

[0149] In some examples, as shown in Figures 10A to 11B, the shape of the first connection line 232 can be roughly a broken line extending along the first direction X. The orthographic projection of the first connection line 232 on the substrate overlaps with the orthographic projections of the second common voltage signal line 22 and the first voltage line 23 on the substrate. The orthographic projection of the first end of the first connection line 232 on the substrate overlaps with the orthographic projection of the scan connection end 111 of the scan line on the substrate. The second end of the first connection line 232 can be electrically connected to the output end of a second driving unit. For example, the first end of the first connection line 232 and the output end of the second driving unit can be an integrated structure connected to each other.

[0150] In some examples, as shown in Figures 10B and 11B, the first electrode 272 of the second control transistor of the second drive unit has an orthographic projection on the substrate that overlaps with the orthographic projection of the active layer 270 on the substrate, and the shape of the first electrode 272 can be roughly comb-shaped. The second electrode 273 of the second control transistor has an orthographic projection on the substrate that overlaps with the orthographic projection of the active layer 270 on the substrate, and the shape of the second electrode 273 can be roughly comb-shaped. The comb-shaped structures of the first electrode 272 and the second electrode 273 of the second control transistor can be arranged in an intersecting manner. The second electrode 273 of the second control transistor and the second plate 282 of the first capacitor can be an integral structure connected to each other. The second plate 282 of the first capacitor can serve as the second electrode of the first capacitor and can also serve as the output terminal of the second drive unit and is electrically connected to the first connecting line 232. The first electrode 262 of the first control transistor of the second drive unit has an orthographic projection on the substrate that overlaps with the orthographic projection of the active layer 260 on the substrate, and the shape of the first electrode 262 can be roughly comb-shaped. The orthographic projection of the second electrode 263 of the first control transistor on the substrate overlaps with the orthographic projection of the active layer 260 on the substrate. The shape of the second electrode 263 can be roughly comb-shaped. The comb-tooth structure of the first electrode 262 and the second electrode 263 of the first control transistor can be arranged in an intersecting manner.

[0151] In some examples, as shown in Figures 10B and 11B, the first electrode 262 of the first control transistor of the second driver unit in the 2b-1 stage and the first electrode 262 of the first control transistor of the second driver unit in the 2b-2 stage can be electrically connected to the same second connection line 292. For example, the first electrode 262 of the first control transistor of the second driver unit in the 2b-1 stage, the first electrode 262 of the first control transistor of the second driver unit in the 2b-2 stage, and a second connection line 292 can be an interconnected, integral structure. The second connection line 292 can be located between the second plate 282 of the first capacitor of the second driver unit in the 2b-1 stage and the second plate 282 of the first capacitor of the second driver unit in the 2b-2 stage. The orthographic projection of the end of the second connection line 292 on the substrate can overlap with the orthographic projection of the first voltage line 23 on the substrate. In this example, two adjacent second driver units can be electrically connected to the first voltage line 23 via the same second connection line.

[0152] In some examples, as shown in FIG10B and FIG11B , the second conductive layer pattern of the second driving unit of the 2b-1 stage can be substantially symmetrical with the second conductive layer pattern of the second driving unit of the 2b stage about the second connection line 292. The second conductive layer pattern of the second driving unit of the 2b stage can be substantially symmetrical with the second conductive layer pattern of the second driving unit of the 2b+1 stage about a midline thereof along the second direction Y. The arrangement of the second driving units in this example facilitates circuit layout and saves space.

[0153] (5) Forming a second insulating layer and a third insulating layer. In some examples, a second insulating film is deposited on the substrate forming the aforementioned structure, and then a third insulating film is coated. The third insulating film is patterned by a patterning process to form a third insulating layer, and the second insulating film exposed by the third insulating layer is etched to form a second insulating layer. In some examples, the second insulating layer may also be referred to as a first passivation layer (PVX1).

[0154] Figure 12 is a schematic plan view of the array substrate after the third insulating layer is formed in Figure 6A. In some examples, as shown in Figure 12, the third insulating layer in the display area AA may be provided with a plurality of third via holes V3. The third insulating layer and the second insulating layer within the third via holes V3 may be removed, exposing a portion of the surface of the second electrode 142 of the switching transistor located in the second conductive layer.

[0155] In some examples, as shown in FIG12 , the third insulating layer in the right frame area B2 may be provided with multiple openings, for example, including a first opening Q1, a second opening Q2, a third opening Q3, and a fourth opening Q4. The third insulating layer within the first opening Q1 to the fourth opening Q4 may be removed, exposing the surface of the second insulating film. The orthographic projection of the first opening Q1 on the substrate at least partially overlaps with the orthographic projection of the third dummy connection portion 2511 or the fourth dummy connection portion 2512 of the second dummy trace segment of the dummy trace on the substrate. The orthographic projection of the second opening Q2 on the substrate at least partially overlaps with the orthographic projection of the first voltage line 23 and the second connection line 292 on the substrate. The orthographic projection of the third opening Q3 on the substrate partially overlaps with the orthographic projection of the scan line scan connection end 111 and the first connection line 232 on the substrate. The orthographic projection of the fourth opening Q4 on the substrate may be located within the orthographic projection of the second common voltage signal line 22 on the substrate.

[0156] (6) Forming a first transparent conductive layer. In some examples, a first transparent conductive film is deposited on the substrate forming the aforementioned structure, and the first transparent conductive film is patterned by a patterning process to form a first transparent conductive layer.

[0157] Figure 13 is a schematic plan view of the array substrate after the first transparent conductive layer is formed in Figure 6A. In some examples, as shown in Figure 13, the first transparent conductive layer in display area AA may include at least: a plurality of pixel electrodes 13 and a plurality of dummy pixel electrodes 13a. The pixel electrodes 13 may be electrically connected to the second electrode 142 of the switching transistor via a third via V3. The orthographic projection of the pixel electrode 13 on the substrate may be located within the sub-pixel region defined by the intersection of adjacent data lines 12 and adjacent scan lines 11. The orthographic projection of the touch signal line 16 on the substrate may overlap with the orthographic projection of the pixel electrode 13 on the substrate. The plurality of dummy pixel electrodes 13a may be arranged in a row along the second direction Y and located on the side of the plurality of pixel electrodes 13 near the right frame area B2. The orthographic projection of the dummy pixel electrode 13a on the substrate may overlap with the orthographic projection of the first dummy active block 140a on the substrate. The dummy pixel electrode 13a may serve as the pixel electrode of the dummy sub-pixel.

[0158] (7) Forming a fourth insulating layer. In some examples, a fourth insulating film is deposited on the substrate forming the aforementioned structure, and the fourth insulating film is patterned by a patterning process to form a fourth insulating layer. In some examples, the fourth insulating layer may also be referred to as a second passivation layer (PVX2).

[0159] Figure 14A is a schematic plan view of the array substrate after the fourth insulating layer is formed in Figure 6A. Figure 14B is a schematic plan view of the array substrate after the fourth insulating layer is formed in Figure 6B.

[0160] In some examples, as shown in FIG14A and FIG14B , the fourth insulating layer may have a plurality of vias, for example, a first via V1, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, and a tenth via V10.

[0161] In some examples, as shown in Figures 14A and 14B, the orthographic projection of the first via V1 on the substrate can be located within the orthographic projection of the fourth opening Q4 on the substrate. The fourth, third, second, and first insulating layers within the first via V1 can be removed, exposing a portion of the surface of the second common voltage signal line 22 located in the first conductive layer. The orthographic projections of the fourth and fifth vias V4 and V5 on the substrate can be located within the orthographic projection of the third opening Q3 on the substrate. The fourth, third, second, and first insulating layers within the fourth via V4 can be removed, exposing a portion of the surface of the scan connection end 111 of the scan line 11 located in the first conductive layer. The fourth, third, and second insulating layers within the fifth via V5 can be removed, exposing a portion of the surface of the first end of the first connection line 232 located in the second conductive layer. The orthographic projection of the sixth via V6 on the substrate can be located within the orthographic projection of the first opening Q1 on the substrate. The fourth, third, and second insulating layers within the sixth via V6 can be removed, exposing a portion of the surface of the third dummy connection portion 2521 or the fourth dummy connection portion 2522 of the second dummy trace segment 252 of the dummy trace 25 located in the second conductive layer. The orthographic projections of the seventh and eighth vias V7 and V8 onto the substrate can be located within the orthographic projection of the second opening Q2 onto the substrate. The fourth, third, and second insulating layers within the seventh via V7 can be removed, exposing a portion of the surface of the second connection line 292 located in the second conductive layer. The fourth, third, second, and first insulating layers within the eighth via V8 can be removed, exposing a portion of the surface of the first voltage line 23 located in the first conductive layer. The orthographic projections of the ninth and tenth vias V9 and V10 onto the substrate can be located within the orthographic projection of an opening in the third insulating layer onto the substrate. The fourth, third, second, and first insulating layers within the ninth via V9 can be removed, exposing a portion of the surface of the control connection block 271-1 located in the first conductive layer. The fourth insulating layer, the third insulating layer, and the second insulating layer in the tenth via hole V10 may be removed to expose a portion of the surface of the second electrode 263 of the first control transistor.

[0162] In this example, the third insulating layer is first dug out at the location where the via hole is formed, so as to avoid the via hole being too deep and affecting the electrical connection effect of the conductive film layer.

[0163] (8) Forming a second transparent conductive layer. In some examples, a second transparent conductive film is deposited on the substrate forming the aforementioned structure, and the second transparent conductive film is patterned by a patterning process to form a second transparent conductive layer.

[0164] Figure 15A is a schematic diagram of the second transparent conductive layer in Figure 6A. Figure 15B is a schematic diagram of the second transparent conductive layer in Figure 6B.

[0165] In some examples, as shown in Figures 6A, 6B, 15A and 15B, the second transparent conductive layer may include at least: a common electrode 15 located in the display area AA, a first common voltage signal line 21 located in the right frame area B2, and multiple connecting electrodes (for example, including a first connecting electrode 41, a second connecting electrode 42 and a third connecting electrode 43).

[0166] In some examples, as shown in FIG15A , the common electrodes 15 of the multiple sub-pixels in the display area AA may be interconnected integral structures. The common electrode 15 located in the sub-pixel region may have multiple (e.g., three or four) slits. The extension direction of the multiple slits may intersect with the first direction X and the second direction Y. The common electrode 15 may have slits in two different directions, thereby forming a dual-domain structure. However, this embodiment is not limited to this. For example, the common electrode may form a single-domain or multi-domain structure.

[0167] In some examples, the common electrodes 15 of multiple sub-pixels are electrically connected to each other so as to be reused as a touch sensing block. For example, the common electrode can be electrically connected to the touch signal line located in the second conductive layer through a via hole opened in the fourth insulating layer, the third insulating layer, and the second insulating layer; or the common electrode can be electrically connected to the electrode connection block located in the first transparent conductive layer through a via hole opened in the fourth insulating layer, and the electrode connection block is electrically connected to the touch signal line located in the second conductive layer through a via hole opened in the third insulating layer and the second insulating layer, thereby realizing the electrical connection between the common electrode and the touch signal line. This embodiment is not limited to this. In this example, a common voltage signal is applied to the common electrode in the display stage to realize the display function, and a touch signal is applied to the common electrode in the touch stage to realize the touch function. In this way, there is no need to additionally manufacture the film layer where the touch electrode is located, thereby saving the manufacturing process and reducing the thickness of the array substrate.

[0168] In some examples, as shown in Figures 15A and 15B, the first common voltage signal line 21 in the right frame area B2 can have multiple first hollow portions 211. The orthographic projection of the first hollow portion 211 on the substrate can be substantially rectangular, and the rectangle can have rounded or chamfered corners. The multiple first hollow portions 211 can be aligned in the second direction Y. The orthographic projection of the first hollow portion 211 of the first common voltage signal line 21 on the substrate can not overlap with the orthographic projection of the second common voltage signal line 22 on the substrate.

[0169] In some examples, as shown in Figures 15A and 15B, the first common voltage signal line 21 in the right frame area B2 can have a first edge close to the display area AA and a second edge away from the display area AA in the first direction X. The first edge can face the common electrode 15 of the display area AA, and the shape of the first edge and the edge of the integrated structure of the multiple common electrodes 15 in the display area AA can roughly match, for example, can be roughly in the shape of a broken line extending along the second direction Y. The second edge of the first common voltage signal line 21 can have multiple notches 213. The orthographic projection of the notch 213 on the substrate can be roughly rectangular. The multiple notches 213 can be arranged sequentially along the second direction Y.

[0170] In some examples, as shown in Figures 6A to 15B, the orthographic projection of the first common voltage signal line 21 on the substrate can overlap the orthographic projection of the second common voltage signal line 22 on the substrate. The first common voltage signal line 21 can be electrically connected to the second common voltage signal line 22 through multiple groups of first vias V1. For example, each group of first vias V1 can include two first vias V1 arranged along the first direction X. The multiple groups of first vias V1 within the right frame area B2 can be arranged sequentially along the second direction Y. The multiple groups of first vias V1 and the multiple first hollow portions 211 can be spaced apart in the second direction Y, thereby facilitating circuit layout.

[0171] In some examples, as shown in Figures 6A to 15B, the orthographic projection of the first common voltage signal line 21 on the substrate can overlap the orthographic projection of the second dummy routing segment 252 of the dummy routing line 25 on the substrate. The second dummy routing segment 252 can be located on a side of the first hollow portion 211 close to the display area AA. The third dummy connection portion 2521 or the fourth dummy connection portion 2522 of the second dummy routing segment 252 can be electrically connected to the first common voltage signal line 21 via two sixth vias V6 arranged along the first direction X.

[0172] In some examples, as shown in FIG7A , a first opening can be formed in the area where the third dummy connection portion 2521 (or the fourth dummy connection portion 2522) of the second dummy routing segment 252 is located, where the third insulating layer 303 is removed. The fourth insulating layer and the second insulating layer are etched away within the first opening to form two sixth vias V6, exposing the third dummy connection portion 2521 (or the fourth dummy connection portion 2522). The first common voltage signal line 21 can be electrically connected to the third dummy connection portion 2521 (or the fourth dummy connection portion 2522) through the first opening and the sixth vias V6. In this example, by etching the vias after forming the first opening in the third insulating layer, insufficient contact between the conductive film layer due to an excessive via depth can be avoided, thereby ensuring the effectiveness of the electrical connection between the first common voltage signal line and the second dummy routing segment.

[0173] In some examples, as shown in Figures 6A to 15B, the first connection electrode 41 can be located on a side of the second common voltage signal line 22 near the display area AA. The first connection electrode 41 can be electrically connected to the scan connection end 111 of the scan line 11 via two fourth vias V4 arranged along the second direction Y, and can also be electrically connected to the first end of the first connection line 232 via two fifth vias V5 arranged along the second direction Y. The orthographic projection of the first connection electrode 41 on the substrate can be located within the orthographic projection of the first hollow portion 211 of the first common voltage signal line 21 on the substrate. For example, the orthographic projection of each first hollow portion 211 on the substrate can overlap the orthographic projection of one first connection electrode 41 on the substrate. Multiple first connection electrodes 41 within the right frame area B2 can be arranged sequentially along the second direction Y. In this example, by providing the first hollow portion on the first common voltage signal line to avoid the first connection electrode, the first connection electrode can ensure the effectiveness of the electrical connection between the scan connection end of the scan line and the first connection line.

[0174] Figure 16 is a schematic diagram of a partial area in Figure 6A. In some examples, as shown in Figure 16, the orthographic projection of the first connecting electrode 41 on the substrate can be substantially rectangular, for example, the rectangle can have rounded or chamfered corners. The length L11 of the first connecting electrode 41 along the first direction X can be less than the length L12 along the second direction Y. For example, the length L11 of the first connecting electrode 41 along the first direction X can be 25 micrometers (μm) to 35 μm, for example, approximately 30 μm; the length L12 of the first connecting electrode 41 along the second direction Y can be 36 μm to 45 μm, for example, approximately 40 μm.

[0175] In some examples, as shown in FIG16 , in the first direction X, a first distance L13 is defined between an edge of the first connection electrode 41 proximal to the display area AA and an edge of the first hollow portion 211 proximal to the display area AA. A second distance L14 may be defined between an edge of the first connection electrode 41 distal to the display area AA and an edge of the first hollow portion 211 distal to the display area AA. The second distance L14 may be greater than or equal to the first distance L13. For example, the first distance L13 and the second distance L14 may both be greater than 6 μm. For example, the first distance L13 may be approximately 10 μm, and the second distance L14 may be approximately 15 μm.

[0176] In some examples, as shown in FIG16 , in the second direction Y, a third distance L15 is defined between the lower edge of the first connection electrode 41 and the adjacent edge of the first hollow portion 211, and a fourth distance L16 is defined between the upper edge of the first connection electrode 41 and the adjacent edge of the first hollow portion 211. The third distance L15 and the fourth distance L16 can be substantially the same. For example, the third distance L15 and the fourth distance L16 can both be approximately 15 μm.

[0177] In some examples, as shown in Figures 6A to 15B, the second connection electrode 42 can be located on a side of the second common voltage signal line 22 away from the display area AA. The orthographic projection of the second connection electrode 42 on the substrate can be roughly rectangular, for example, the rectangle can have chamfered or rounded corners. The second connection electrode 42 can be electrically connected to the second connection line 292 located on the second conductive layer through two seventh vias V7 arranged along the second direction Y, and can also be electrically connected to the first voltage line 23 located on the first conductive layer through two eighth vias V8. The two eighth vias V8 can be located on both sides of the two seventh vias V7 along the second direction Y. The orthographic projection of the second connection electrode 42 on the substrate at least partially overlaps with the orthographic projection of the first voltage line 23 on the substrate; for example, the orthographic projection of the first voltage line 23 on the substrate can cover the orthographic projection of the second connection electrode 42 on the substrate.

[0178] In some examples, as shown in FIG15A , the orthographic projection of the second connection electrode 42 on the substrate can be located within the orthographic projection of the recess 213 on the substrate. In the first direction X, the orthographic projection of the recess 213 on the substrate can cover the orthographic projection of the second connection electrode 42 on the substrate. The edge of the second connection electrode 42 away from the display area AA can be flush with the second edge of the first common voltage signal line 21 in the first direction X.

[0179] In some examples, as shown in FIG15A , a fifth distance L21 may be provided between the edge of the second connection electrode 42 proximate the display area AA and the bottom surface of the recess 213 in the first direction X. In the second direction Y, a sixth distance L22 may be provided between the lower edge of the second connection electrode 42 and the side surface of the recess 213, and a seventh distance L23 may be provided between the upper edge of the second connection electrode 42 and the side surface of the recess 213. The fifth distance L21, the sixth distance L22, and the seventh distance L23 may be greater than 6 μm. For example, the fifth distance L21 may be approximately 8 μm, the sixth distance L22 may be approximately 15 μm, and the seventh distance L23 may be approximately 15 μm. In this example, by arranging the first common voltage signal line to avoid the second connection electrode, the second connection electrode can ensure effective electrical connection to the first voltage line and the second connection line.

[0180] In some examples, as shown in FIG7B , a second opening can be formed in the area corresponding to the notch 213 of the first common voltage signal line 21, where the third insulating layer 303 is removed. The fourth insulating layer and the second insulating layer are etched away within the second opening to form two seventh vias V7, exposing a portion of the surface of the second connection line 292 located on the second conductive layer. The fourth insulating layer, the second insulating layer, and the first insulating layer are etched away within the second opening to form two eighth vias V8, exposing a portion of the surface of the first voltage line 23 located on the first conductive layer. The second connection electrode 42 can be electrically connected to the second connection line 292 through the seventh vias V7, and can also be electrically connected to the first voltage line 23 through the eighth vias V8. In this example, by etching the vias after forming the second opening in the third insulating layer, insufficient contact between the conductive film layers due to excessive via depth can be avoided, thereby ensuring effective electrical connection between the first voltage line and the second connection line.

[0181] In some examples, as shown in Figures 6A and 6B, within the right frame area B2, the multiple notches 213 of the first common voltage signal line 21 and the extended ends 112 of the multiple scan lines 11 can be spaced apart in the second direction Y. Since two adjacent second drive units can be electrically connected to the first voltage line 23 via the same second connection line and second connection electrode, and the second connection electrode is located within the notch, the two adjacent second drive units can share the second connection electrode within the same notch to achieve electrical connection to the first voltage line. By arranging the notches and the extended ends of the scan lines spaced apart in the second direction, a reasonable circuit layout can be achieved, which helps save space.

[0182] In some examples, the first insulating layer 301, the second insulating layer 302 and the fourth insulating layer 304 can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The third insulating layer 303 can be made of an organic insulating material. The first conductive film and the second conductive film can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Ti / Al / Ti. The first transparent conductive film and the second transparent conductive film can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, this embodiment is not limited to this.

[0183] The structure and fabrication process of the array substrate in the disclosed embodiments are merely illustrative. In some examples, the corresponding structure can be modified, and patterning processes can be added or removed, depending on actual needs. For example, the common electrode can be a sheet-like electrode structure without slits, thereby increasing the touch electrode area and enhancing touch performance. However, this embodiment is not limited to this.

[0184] The array substrate of this example can avoid the dummy line from crossing the extended end of the scan line by setting the dummy line to be disconnected at the extended end of the scan line, thereby reducing the risk of short circuit between the scan line and the dummy line caused by electrostatic discharge at the extended end of the scan line, and further improving the functional display defects such as horizontal stripes.

[0185] FIG17 is another schematic diagram of a scan drive circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG17 , the array substrate may further include: a plurality of auxiliary drive units (e.g., including first auxiliary drive units 35c and 35d, and second auxiliary drive units 35a and 35b). The first auxiliary drive units 35c and 35d may be located in the left frame area, and the second auxiliary drive units 35a and 35b may be located in the right frame area.

[0186] In some examples, as shown in FIG17 , the second auxiliary driving unit 35c located in the left frame area can be cascaded with the first driving unit of the N-1th stage, and the second auxiliary driving unit 35d can be cascaded with the first driving unit of the Nth stage. The output of the first driving unit of the Nth stage can be configured to provide an input signal to the first auxiliary driving unit 35d, and the output of the first auxiliary driving unit 35d can be configured to provide a reset signal to the first driving unit of the Nth stage; the output of the first driving unit of the N-1th stage can be configured to provide an input signal to the first auxiliary driving unit 35c, and the output of the first auxiliary driving unit 35c can be configured to provide a reset signal to the first driving unit of the N-1th stage. The second auxiliary driving unit 35a located in the right frame area can be cascaded with the second driving unit of the M-1th stage, and the second auxiliary driving unit 35b can be cascaded with the second driving unit of the Mth stage. The output end of the M-1th level second driving unit can be configured to provide an input signal to the second auxiliary driving unit 35a, and the output end of the second auxiliary driving unit 35a can be configured to provide a reset signal to the M-1th level second driving unit; the output end of the M-th level second driving unit can be configured to provide an input signal to the second auxiliary driving unit 35b, and the output end of the second auxiliary driving unit 35b can be configured to provide a reset signal to the M-th level second driving unit.

[0187] In this example, multiple auxiliary drive units are provided to provide reset signals to the last two stages of first drive units and the last two stages of second drive units, thereby ensuring the reset and driving effects of the first drive circuit and the second drive circuit. However, this embodiment is not limited to this. In other examples, separate reset signals can be provided to the last two stages of first drive units and the last two stages of second drive units.

[0188] In some examples, the circuit structure of the auxiliary driving unit is similar to the circuit structure of the first driving unit and the second driving unit. For example, the auxiliary driving unit may include at least a first auxiliary capacitor, wherein a first plate of the first auxiliary capacitor may be electrically connected to the pull-up node, and a second plate of the first auxiliary capacitor may be electrically connected to the output terminal of the auxiliary driving unit.

[0189] In some examples, as shown in FIG17 , the array substrate may further include: a plurality (e.g., four) auxiliary scan lines 31 located on the lower frame. The four auxiliary scan lines 31 may be electrically connected to the four auxiliary drive units in a one-to-one correspondence. In this example, by providing auxiliary scan lines electrically connected to the auxiliary drive units, not only a release path is provided for the output signals of the auxiliary drive units, but also process uniformity is ensured.

[0190] Figure 18 is a schematic plan view of the lower right corner of an array substrate according to at least one embodiment of the present disclosure. Figure 19A is a schematic view of the array substrate after the first conductive layer is formed in Figure 18. Figure 19B is a schematic view of the array substrate after the semiconductor layer is formed in Figure 18. Figure 19C is a schematic view of the array substrate after the second conductive layer is formed in Figure 18. Figure 19D is a schematic view of the second conductive layer in Figure 19C. Figure 19E is a schematic view of the array substrate after the fourth insulating layer is formed in Figure 18. Figure 19F is a schematic view of the second transparent conductive layer in Figure 18.

[0191] In some examples, as shown in Figure 19A, the first conductive layer may include at least: a first electrode 381 of a first auxiliary capacitor 38 of two second auxiliary driving units 35a and 35b located in the right frame area B2, a second common voltage signal line 22 and a first voltage line 23, four auxiliary scanning lines 31 and multiple second virtual control blocks 141b located in the lower frame area B4, and multiple data lead lines 321.

[0192] In some examples, as shown in FIG19A , the second common voltage signal line 22 may include a first signal segment 221 located within the right border area B2 and a second signal segment 222 located within the lower border area B4. The first signal segment 221 extends along the second direction Y, and the second signal segment 222 extends along the first direction X. The first signal segment 221 and the second signal segment 222 may be an interconnected, integral structure. For example, the first signal segment 221 may extend to the lower border area B4 and be electrically connected to the integrated chip.

[0193] In some examples, as shown in Figure 19A, the first electrodes 381 of the first auxiliary capacitors of the two second auxiliary driving units 35a and 35b can be arranged sequentially along the second direction Y and aligned with the first plates 281 of the first capacitors of the second driving units in the second direction Y.

[0194] In some examples, as shown in FIG19A , the four auxiliary scan lines 31 can be located on a side of the second signal segment 222 of the second common voltage signal line 22 close to the display area AA. Each auxiliary scan line 31 can include an auxiliary scan connection end 311 and an auxiliary extension end 312. In the lower right corner area, the auxiliary extension ends 312 and the auxiliary scan connection ends 311 of the four auxiliary scan lines 31 can be spaced apart along the second direction Y. Each auxiliary scan line 31 can be electrically connected to a plurality of second dummy control blocks 141b arranged along the first direction X, for example, they can be an integrated structure connected to each other. By providing a plurality of second dummy control blocks 141b, the first conductive layer pattern portions of the display area AA and the lower frame area B4 can be made consistent, thereby ensuring process uniformity.

[0195] 19A , the plurality of data lead lines 321 may be located on a side of the second common voltage signal line 22 away from the display area AA and may extend to electrically connect to the integrated chip.

[0196] In some examples, as shown in FIG19B , the semiconductor layer of the lower border area B4 may include at least a plurality of second dummy active blocks 140 b. The plurality of second dummy active blocks 140 b may be arranged in four rows and multiple columns. The orthographic projection of the second dummy active block 140 b on the substrate may be within the orthographic projection of the second dummy control block 141 b on the substrate. By providing a plurality of second dummy active blocks 140 b in this example, process uniformity can be ensured.

[0197] In some examples, as shown in Figures 19C and 19D, the dummy trace 25 located in the right frame area B2 may include a first dummy trace segment 251 and a second dummy trace segment 252. The first dummy trace segment 251 may have a first dummy connection portion 2511 and a second dummy connection portion 2512. The second dummy connection portion 2512 may extend to the lower frame area B4, and the orthographic projection of the second dummy connection portion 2512 on the substrate may overlap with the orthographic projection of the second signal segment 222 of the second common voltage signal line 22 on the substrate. The shape and connection method of the first dummy connection portion 2511 are similar to those of the third and fourth dummy connections of the second dummy trace segment 252, so they are not further described here. The dummy data line 18 in the display area AA may extend to the lower frame area B4 and be electrically connected to the second dummy connection portion 2512. For example, the dummy data line 18 and the second dummy connection portion 2512 may be an integrated structure connected to each other. The orthographic projection of the first dummy trace segment 251 on the substrate may overlap with the orthographic projection of the auxiliary scanning connection end and the auxiliary extension end of the auxiliary scanning line on the substrate. In this example, the dummy trace does not need to avoid the auxiliary scanning line.

[0198] In some examples, as shown in Figures 19C and 19D , the data lines 12 in the display area AA can extend to the lower frame area B4. The touch signal lines 16 can extend to the lower frame area B4 and be electrically connected to the touch lead lines 322 in the lower frame area B4. For example, the touch signal lines 16 and the touch lead lines 322 can be an integrated structure connected to each other.

[0199] In some examples, as shown in Figures 19C and 19D, the auxiliary scan line can be electrically connected to the output terminal of the second auxiliary driving unit via a fourth connection line 233. A third connection line 293 can be provided between the second auxiliary driving units 35a and 35b. The second auxiliary driving units 35a and 35b can share the third connection line 293 to be electrically connected to the first voltage line 23.

[0200] In some examples, as shown in Figure 19E, the fourth insulating layer in the lower right corner area may be provided with multiple vias, for example, including: the eleventh via V11, the twelfth via V12, the thirteenth via V13, the fourteenth via V14, the fifteenth via V15, the sixteenth via V16, the seventeenth via V17 and the eighteenth via V18.

[0201] In some examples, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the eleventh via hole V11 can be removed to expose a portion of the surface of the auxiliary scanning connection terminal 312 of the auxiliary scanning line. The fourth insulating layer, the third insulating layer, and the second insulating layer in the twelfth via hole V12 can be removed to expose a portion of the surface of the fourth connection line 233. The fourth insulating layer, the third insulating layer, and the second insulating layer in the thirteenth via hole V13 can be removed to expose a portion of the surface of the first dummy connection portion 2511 of the first dummy routing segment 251 of the dummy routing line 25. The fourth insulating layer, the third insulating layer, and the second insulating layer in the fourteenth via hole V14 can be removed to expose a portion of the surface of the second dummy connection portion 2512 of the first dummy routing segment 251 of the dummy routing line 25. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the fifteenth via hole V15 can be removed to expose a portion of the surface of the first voltage line 23. The fourth insulating layer, the third insulating layer, and the second insulating layer in the sixteenth via hole V16 can be removed to expose a portion of the surface of the third connection line 293. The fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the seventeenth via hole V17 can be removed to expose a portion of the surface of the data lead line 321. The fourth insulating layer, the third insulating layer, and the second insulating layer in the eighteenth via hole V18 can be removed to expose a portion of the surface of the data line 12 extending to the lower frame area B4.

[0202] In some examples, as shown in Figures 18 to 19F, the first common voltage signal line 21 may have a second hollow portion 212 at the lower right corner. The second hollow portion 212 may be aligned with the first hollow portion 211 in the second direction Y. The second hollow portion 212 may be located between the auxiliary drive unit and the auxiliary scan line in the first direction X. The orthographic projection of the second hollow portion 212 on the substrate may be roughly rectangular. The orthographic projection of the second hollow portion 212 on the substrate may cover the orthographic projections of three connection electrodes (for example, including a first connection electrode 41 and two fourth connection electrodes 44) on the substrate. The fourth connection electrode 44 may be electrically connected to the auxiliary scan connection terminal 311 of the auxiliary scan line through two eleventh vias V11 arranged vertically, and may also be electrically connected to the fourth connection line 233 through two twelfth vias V12 to achieve electrical connection with the output end of the second auxiliary drive unit. The first connection electrode and the two fourth connection electrodes 44 in the second hollow portion 212 may be arranged sequentially along the second direction Y.

[0203] In some examples, as shown in Figures 18 to 19F, the first common voltage signal line 21 can be electrically connected to the first dummy connection portion 2511 of the first dummy routing segment 251 of the dummy routing line 25 through two thirteenth vias V13. The first common voltage signal line 21 can be electrically connected to the second dummy connection portion 2512 of the first dummy routing segment 251 of the dummy routing line 25 through four fourteenth vias V14 arranged in a 2×2 array.

[0204] In some examples, as shown in Figures 18 to 19F, the fifth connection electrode 45 located in the second transparent conductive layer can be electrically connected to the first voltage line 23 through two fifteenth via holes V15, and can also be electrically connected to the third connection line 293 through two sixteenth via holes V16. The fifth connection electrode 45 can be located in a recess of the first common voltage signal line 21, so that the first common voltage signal line 21 avoids the fifth connection electrode 45, thereby ensuring effective electrical connection between the auxiliary driving unit and the first voltage line.

[0205] In some examples, as shown in Figures 18 to 19F, the sixth connection electrode 46 located in the second transparent conductive layer can be electrically connected to the data lead line 321 through two seventeenth via holes V17, and can also be electrically connected to the data line 12 through two eighteenth via holes V18, thereby realizing data signal transmission from the lower frame area to the display area. The plurality of sixth connection electrodes 46 can be located on a side of the first common voltage signal line 21 away from the display area AA.

[0206] The structure of the lower left corner of the array substrate in this example can be referenced to the structure of the lower right corner. The remaining structures of the display area and right frame region of the array substrate in this example can be referenced to the description of the previous embodiment, and are therefore not further described here. The auxiliary scanning connection end of the auxiliary scanning line extending to the left frame region can be electrically connected to the first auxiliary driving unit.

[0207] The array substrate of this example can ensure the reset and driving effects of the first driving circuit and the second driving circuit by providing the auxiliary driving unit and the auxiliary scanning line, and can also ensure process uniformity.

[0208] FIG20 is another schematic diagram of an array substrate according to at least one embodiment of the present disclosure. FIG21 is a schematic diagram of a partial film layer of FIG20 . In some examples, as shown in FIG20 and FIG21 , multiple dummy trace segments (including a first dummy trace segment 251 and a second dummy trace segment 252 ) of the dummy trace 25 located in the left border area B1 and the right border area B2 can all be electrically connected to the second common voltage signal line 22.

[0209] The remaining structures of the array substrate of this example can be referred to the description of the aforementioned embodiment, so they will not be described again here.

[0210] Figure 22 is another schematic diagram of an array substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 22, dummy traces 25 located in the left border area B1 and the right border area B2 can bend around the extended ends 112 of the scan lines, and the orthographic projections of the dummy traces 25 and the extended ends 112 of the scan lines on the substrate do not overlap. This example prevents the dummy traces from intersecting the extended ends of the scan lines, thereby reducing the risk of short circuits between the scan lines and the dummy traces caused by electrostatic discharge at the extended ends of the scan lines, and further improving functional display defects such as horizontal stripes.

[0211] The remaining structures of the array substrate of this example can be referred to the description of the aforementioned embodiment, so they will not be described again here.

[0212] In other examples, the dummy traces provided in the left frame area (or right frame area) of the array substrate may adopt a disconnection design to avoid the extended ends of the scan lines, and the dummy traces provided in the right frame area (or left frame area) may adopt a bypassing design to avoid the extended ends of the scan lines. In other examples, the dummy traces provided in the left frame area or right frame area of ​​the array substrate may adopt both a disconnection design and a bypassing design to avoid the extended ends of multiple scan lines. This embodiment is not limited to this.

[0213] At least one embodiment of the present disclosure further provides a display device including the array substrate as described above.

[0214] In some examples, a display device may include: an array substrate, an opposing substrate, and a liquid crystal layer disposed between the array substrate and the opposing substrate. The array substrate includes pixel electrodes and common electrodes (reused as touch electrodes) for generating an electric field that controls the deflection of liquid crystal molecules in the liquid crystal layer. In some examples, the opposing substrate may include a base substrate, and a black matrix and a color filter layer disposed on the base substrate. However, this embodiment is not limited to this.

[0215] In some exemplary embodiments, the display device may be any product or component with touch and display functions, such as a liquid crystal panel, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator.

[0216] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures may refer to the general design. In the absence of conflict, the embodiments of this disclosure and the features in the embodiments may be combined with each other to obtain new embodiments. It should be understood by those skilled in the art that the technical solutions of this disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of this disclosure, and should be included in the scope of the claims of this disclosure.

Claims

1. An array substrate, comprising: A substrate, comprising a display area and a frame area located around the display area; A plurality of scan lines, at least located in the display area and extending along a first direction; at least one dummy trace, located in the frame region and extending along a second direction, wherein the second direction intersects the first direction; A scanning driving circuit is located in the frame area; At least one of the plurality of scan lines comprises: a scan connection end extending to the frame area and an extension end, the scan connection end being electrically connected to the scan driving circuit; The at least one dummy routing line is disconnected at an extended end of the at least one scan line, so that the at least one dummy routing line and the extended end of the at least one scan line have no overlap in an orthographic projection on the substrate.

2. The array substrate according to claim 1, wherein: The at least one dummy routing line includes: a plurality of dummy routing line segments arranged in sequence along the second direction, a first break is provided between adjacent dummy routing line segments in the second direction, and a length of the first break along the second direction is greater than a length of an extended end of the at least one scanning line along the second direction.

3. The array substrate according to claim 2, further comprising: A first common voltage signal line and a second common voltage signal line located in the frame area; The first common voltage signal line is electrically connected to the second common voltage signal line, the first common voltage signal line is located on a side of the second common voltage signal line away from the substrate, and the orthographic projections of the first common voltage signal line and the second common voltage signal line on the substrate at least partially overlap.

4. The array substrate according to claim 3, wherein: At least one dummy routing segment of the at least one dummy routing line is electrically connected to at least one of the second common voltage signal line and the first common voltage signal line.

5. The array substrate according to claim 3, further comprising: A plurality of first connection lines located in the frame area; The scan connection end of the scan line is electrically connected to the scan driving circuit through the first connection line; The first connecting line is located at a side of the scanning line away from the substrate.

6. The array substrate according to claim 5, further comprising: A plurality of first connection electrodes located in the frame area; The scan connection end of the scan line is electrically connected to the first connection line through the first connection electrode, and the first connection electrode is located on a side of the first connection line away from the substrate.

7. The array substrate according to claim 6, wherein: The first connection electrode and the first common voltage signal line are in the same layer structure, the first common voltage signal line has a plurality of first hollow parts, and the orthographic projection of the first connection electrode on the substrate is located in the first hollow parts.

8. The array substrate according to claim 3, further comprising: A first voltage line located in the frame area, and a plurality of second connection lines; The first voltage line is located at a side of the first common voltage signal line and the second common voltage signal line away from the display area, and is located at a side of the scan driving circuit close to the display area; The first voltage line is electrically connected to the scan driving circuit through the second connecting line, and the first voltage line is configured to provide a first voltage signal to the scan driving circuit.

9. The array substrate according to claim 8, wherein: The frame area at least includes: a left frame area and a right frame area located on both sides of the display area along the first direction; The scanning driving circuit comprises: a first driving circuit located in the left frame area, and a second driving circuit located in the right frame area; the first driving circuit comprises: a plurality of cascaded first driving units, and the second driving circuit comprises: a plurality of cascaded second driving units; In the left frame area, the 2a-1 level first driving unit and the 2a level first driving unit of the first driving circuit are electrically connected to the first voltage line through the same second connecting line; In the right frame area, the 2b-1-level second driving unit and the 2b-level second driving unit of the second driving circuit are electrically connected to the first voltage line through the same second connecting line; a and b are integers greater than 0.

10. The array substrate according to claim 8, further comprising: a plurality of second connection electrodes located in the frame area, wherein the first voltage line is electrically connected to the second connection line through the second connection electrodes; The second connection electrode is located at a side of the first voltage line and the second connection line away from the substrate, and the second connection electrode and the first common voltage signal line are in the same layer structure; The first common voltage signal line has a plurality of notches at an edge away from the display area, at least one notch is configured to accommodate a second connecting electrode, and the orthographic projection of the notch on the substrate covers the orthographic projection of the second connecting electrode on the substrate in the first direction.

11. The array substrate according to claim 10, wherein: The plurality of notches and the extending ends of the plurality of scanning lines are spaced apart along the second direction.

12. The array substrate according to any one of claims 1 to 11, wherein: The frame area at least includes: a left frame area and a right frame area located on both sides of the display area along the first direction; The left frame area and the right frame area are both provided with at least one dummy wiring.

13. The array substrate according to any one of claims 1 to 12, wherein: The frame area at least includes: a left frame area and a right frame area located on both sides of the display area along the first direction; In the left frame area or the right frame area, the scanning connection ends and the extending ends of the plurality of scanning lines are arranged at intervals along the second direction.

14. The array substrate according to claim 13, further comprising: A plurality of sub-pixels located in the display area, the plurality of sub-pixels are arranged in a plurality of rows, and each row of sub-pixels includes a plurality of sub-pixels arranged along the first direction; The scanning driving circuit comprises: a first driving circuit located in the left frame area, and a second driving circuit located in the right frame area; The scanning connection end of at least one scanning line extending to the left frame area is electrically connected to the first driving circuit; the first driving circuit is configured to provide a data signal to the 2i-1th row of sub-pixels in the display area; The scan connection end of at least one scan line extending to the right frame area is electrically connected to the second drive circuit; the second drive circuit is configured to provide a scan signal to the 2i-th row of sub-pixels in the display area; i is an integer greater than 0.

15. The array substrate according to claim 14, wherein: The frame area further includes: a lower frame area located at one side of the display area along the second direction; The array substrate further comprises: a plurality of auxiliary scanning lines located in the lower frame area and extending along the first direction, a plurality of first auxiliary driving units located in the left frame area, and a plurality of second auxiliary driving units located in the right frame area; The at least one auxiliary scanning line includes: an auxiliary scanning connection end extending to the left frame area and an auxiliary extension end extending to the right frame area; or an auxiliary scanning connection end extending to the right frame area and an auxiliary extension end extending to the left frame area. The auxiliary extension end of the border area; The auxiliary scanning connection end of the at least one auxiliary scanning line is electrically connected to the first auxiliary driving unit or the second auxiliary driving unit; In the left frame area or the right frame area, the auxiliary scanning connection ends and the auxiliary extension ends of the plurality of auxiliary scanning lines are arranged at intervals along the second direction.

16. The array substrate according to claim 15, wherein: The plurality of first auxiliary driving units are configured to provide a reset signal to the first driving circuit; and the plurality of second auxiliary driving units are configured to provide a reset signal to the second driving circuit.

17. The array substrate according to any one of claims 1 to 16, wherein: The at least one dummy wiring goes around an extended end of the at least one scan line from a side away from the display area.

18. A display device comprising the array substrate according to any one of claims 1 to 17.

Images