Circuit board, and semiconductor package comprising same

Abstract

Disclosed in an embodiment of the present invention is a circuit board comprising: a first insulating layer; a first circuit pattern layer disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and the first circuit pattern layer, and including a cavity; a second circuit pattern layer disposed on the second insulating layer; and a connection layer passing through the second insulating layer and disposed along the edge of the cavity.

Description

Circuit boards and semiconductor packages including the same

[0001] Embodiments according to the present invention relate to circuit boards and semiconductor packages.

[0002] As the performance of electrical and electronic products continues to improve, technologies are being proposed and researched to attach a greater number of packages to a limited-size substrate. However, because typical packages are based on mounting a single semiconductor chip, achieving the desired performance is limited.

[0003] A typical circuit board or package substrate consists of a processor package, which houses the processor chip, and a memory package, which houses the memory chips, all connected together. These package substrates integrate the processor and memory chips into a single package, reducing the chip footprint and enabling high-speed signal transmission through short paths. Due to these advantages, these package substrates are widely used in mobile devices and other devices.

[0004] Meanwhile, the recent advancements in electronic devices, such as mobile devices, and the adoption of High Bandwidth Memory (HBM) have led to larger package sizes. Furthermore, as the number of functions required for application processors increases, there is a growing demand for separate processor chips for each function, along with circuit boards capable of mounting these processor chips. Even when the application processor is split into two processor chips, the number of terminals (input / output) provided on each processor chip is increasing.

[0005] In addition, due to recent trends such as 5G, the Internet of Things (IoT), increased image quality, and increased communication speed, the number of terminals on processor chips is gradually increasing due to the increase in power and signal quantity. Accordingly, the area, thickness, and circuit pattern density of circuit boards are also increasing. When the area and thickness of circuit boards increase, it becomes difficult to miniaturize products, and there are problems such as reliability issues such as warpage of circuit boards, and product price increases. Therefore, increasing the density of circuit patterns is more advantageous in terms of product price, reliability issues such as warpage, and product miniaturization than increasing the area and thickness of circuit boards. Therefore, miniaturization of circuit patterns and through-holes is required.

[0006] In addition, as at least one processor chip is mounted on a circuit board or package board and high integration is achieved, the need for electromagnetic shielding for the processor chip is also increasing.

[0007] An embodiment of the present invention provides a circuit board having improved input / output counts of the circuit board through a cavity disposed in some insulating layers, and a semiconductor package including the same.

[0008] In addition, the embodiment can provide a circuit board and a semiconductor package including the same that provide electromagnetic shielding by arranging a connection layer adjacent to a cavity and electrically connecting it to an upper shield layer.

[0009] In addition, the embodiment can provide a circuit board and a semiconductor package including the same, which prevent issues of non-formation of the side of the shield layer and reduction in manufacturing speed for forming the side shield layer by performing connection with the shield layer disposed on the upper side through a connection layer on the side of the cavity.

[0010] In addition, the embodiment can provide a circuit board that prevents warpage of the circuit board through a connecting layer and a semiconductor package including the same.

[0011] The problem to be solved in the embodiment is not limited to this, and it can be said that the purpose or effect that can be understood from the solution or implementation form of the problem described below is also included.

[0012] A circuit board according to an embodiment of the present invention includes a first insulating layer; a first circuit pattern layer disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and the first circuit pattern layer and including a cavity; a second circuit pattern layer disposed on the second insulating layer; and a connection layer penetrating the second insulating layer and disposed along an edge of the cavity.

[0013] The above-mentioned connecting layer may overlap the second circuit pattern layer in a direction perpendicular to the lamination direction outside the cavity.

[0014] The above-mentioned connection layer may be disposed between the second circuit pattern layer and the cavity or on the outside of the second circuit pattern layer.

[0015] The above connection layer can be electrically connected to the first circuit pattern layer.

[0016] The above connection layer can be electrically connected to the second circuit pattern layer.

[0017] The above connecting layer may surround the cavity in an open loop or closed loop.

[0018] The above connecting layer includes a plurality of first sub-connecting layers and second sub-connecting layers adjacent to each other, and the first sub-connecting layer and the second sub-connecting layer can be spaced apart from each other.

[0019] It may include a first extension portion extending in a direction perpendicular to the stacking direction and connecting between the connection layer and the second circuit pattern layer.

[0020] The above first extension portion may be disposed within the second insulating layer.

[0021] It may include a second extension portion extending in the stacking direction and connecting between the connection layer and the first circuit pattern layer.

[0022] The second extension portion may be disposed within the first insulating layer.

[0023] The cavity may include a first cavity and a second cavity spaced apart from the first cavity.

[0024] The above connecting layer may include a first connecting layer surrounding the first cavity and a second connecting layer surrounding the second cavity.

[0025] The first connection layer and the second connection layer may be in contact with or spaced apart from each other.

[0026] A package substrate according to an embodiment includes a circuit board; a semiconductor element connected to the circuit board; and a connection portion connecting the semiconductor element and the circuit board, wherein the circuit board includes a first insulating layer; a first circuit pattern layer disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and the first circuit pattern layer and including a cavity; a second circuit pattern layer disposed on the second insulating layer; and a connection layer penetrating the second insulating layer and disposed along an edge of the cavity; and further includes a shield layer disposed outside the second insulating layer, wherein the connection layer is electrically connected to the shield layer.

[0027] An embodiment of the present invention implements a circuit board and a semiconductor package including the same, which improves the input / output count of the circuit board through a cavity disposed in some insulating layers.

[0028] In addition, the embodiment can implement a circuit board and a semiconductor package including the same that provide electromagnetic shielding by arranging a connection layer adjacent to a cavity and electrically connecting it to an upper shield layer.

[0029] In addition, the embodiment can implement a circuit board and a semiconductor package including the same, which prevent issues of non-formation of the side of the shield layer and reduction in manufacturing speed for forming the side shield layer by performing connection with the shield layer disposed on the upper side through a connection layer on the side of the cavity.

[0030] In addition, the embodiment can implement a circuit board that prevents warpage of the circuit board through a connecting layer and a semiconductor package including the same.

[0031] The various advantageous and beneficial effects of the present invention are not limited to the above-described contents, and will be more easily understood in the course of explaining specific embodiments of the present invention.

[0032] Figure 1 is a diagram illustrating a conceptual diagram of a circuit board according to an embodiment of the present invention.

[0033] Figure 2 is a drawing of a circuit board according to the first embodiment,

[0034] Figure 3 is an enlarged view of a portion of Figure 2,

[0035] Fig. 4 is a modified example of Fig. 3,

[0036] Fig. 5 is a plan view of a circuit board according to the first embodiment;

[0037] Figure 6 is a drawing taken along line AA' in Figure 5.

[0038] Figure 7 is a drawing taken along the line BB' in Figure 5.

[0039] Figures 8 to 9 are flowcharts for a method of manufacturing a circuit board according to the first embodiment.

[0040] Fig. 10 is a plan view of a circuit board according to the second embodiment,

[0041] Figure 11 is a drawing taken along the CC' line in Figure 10.

[0042] Figure 12 is a drawing taken along the line DD' in Figure 10.

[0043] Figure 13 is a drawing taken along the line EE' in Figure 10.

[0044] Fig. 14 is a drawing of a circuit board according to the third embodiment,

[0045] Fig. 15 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0046] Fig. 16 is a flowchart showing a method for manufacturing a semiconductor package according to the first embodiment.

[0047] Fig. 17 is a cross-sectional view showing a semiconductor package according to the second embodiment.

[0048] Fig. 18 is a plan view of a semiconductor package according to the second embodiment.

[0049] Fig. 19 is a cross-sectional view showing a semiconductor package according to the third embodiment.

[0050] Fig. 20 is a plan view of a semiconductor package according to the third embodiment.

[0051] The present invention can be modified in various ways and has various embodiments, and specific embodiments are illustrated and described in the drawings. However, this is not to be construed as a specific embodiment of the present invention.

[0052] It is not intended to be limited to the embodiments, and should be understood to include all modifications, equivalents, or substitutes included in the spirit and technical scope of the present invention.

[0053] Terms that include ordinal numbers, such as "second," "first," etc., may be used to describe various components, but the components are not limited by the terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a second component may be referred to as "first component," and similarly, a first component may also be referred to as "second component." The term "and / or" includes a combination of multiple related items described herein or any of multiple related items described herein.

[0054] When a component is referred to as being "connected" or "connected" to another component, it should be understood that it may be directly connected or connected to that other component, but that there may be other components intervening. Conversely, when a component is referred to as being "directly connected" or "connected" to another component, it should be understood that there are no other components intervening.

[0055] The terminology used in this application is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In this application, it should be understood that the terms "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0056] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined herein.

[0057] Hereinafter, embodiments will be described in detail with reference to the attached drawings. Regardless of the drawing numbers, identical or corresponding components are given the same reference numbers, and redundant descriptions thereof will be omitted.

[0058] Before describing the embodiments, an electronic device to which the circuit board and semiconductor package of the embodiments are applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. The semiconductor package may contain various semiconductor elements.

[0059] The semiconductor device may include active components and / or passive components. The active component may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of components are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chip set including a specific combination of the above-mentioned components.

[0060] The memory chip may be a stacked memory such as HBM. Additionally, the memory chip may include a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), or a flash memory.

[0061] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0062] Additionally, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive device, etc. However, the present invention is not limited thereto, and it is to be understood that the electronic device may be any other electronic device that processes data.

[0063] Figure 1 is a conceptual diagram of a circuit board according to an embodiment.

[0064] First, the circuit board includes an electrode portion (120) for electrical connection and an insulating layer (110) for preventing electrical short-circuiting between the electrode portions (120). Referring to FIG. 1, the insulating layer (110) includes an upper surface for mounting a semiconductor element, and a lower surface (110B) corresponding to the upper surface for connecting the circuit board (CB) to a main board, etc., and may have a structure in which a plurality of insulating layers (111, 112) are laminated between the upper surface and the lower surface. The upper insulating layer (112) constituting the upper surface of the circuit board and the lower insulating layer (112) constituting the lower surface of the circuit board may be referred to as an outer laminated region, and the region laminated between the upper insulating layer and the lower insulating layer may be referred to as an inner laminated region.

[0065] The electrode portion (120) is arranged for electrical connection between the main board, etc. and the semiconductor element (SD), and includes a circuit pattern (or circuit pattern layer), pads, and via electrodes. The circuit pattern can be designed in various forms for signal and / or power transmission with the semiconductor element (SD), and is arranged within each vertically stacked insulating layer (110).

[0066] Via electrodes (121b, 122b) are arranged to penetrate at least a portion of each insulating layer for vertical connection between circuit patterns arranged on each vertically stacked insulating layer. That is, the insulating layer may include a via hole for arrangement of the via electrode. In addition, the via electrode may have a wider width than the circuit pattern for impedance optimization or heat dissipation, but is not limited thereto and may be freely designed.

[0067] The pads (121a, 122a) may include an outer pad (122a) arranged in the outer stacking region and an inner pad (121a) arranged in the inner stacking region. The outer pad (122a) functions to be bonded to a semiconductor device (SD) and / or a main board or substrate (CB). Currently, it can be bonded with solder, wire, conductive adhesive, etc., but may be arranged with a width larger than the width of the circuit pattern to solve problems such as securing yield. However, the present invention is not limited thereto, and may have the same width as the width of the circuit pattern depending on the technical limitations of the bonding process. The inner pad (121a) functions to connect the via electrode and the circuit pattern. When the via electrode is arranged with a width wider than the circuit pattern, a pad with a width wider than the circuit pattern is provided for positional alignment during the manufacturing process of the via electrode to be arranged on each circuit pattern. Accordingly, each via electrode may have an upper surface that is flush with the lower surface of the upper pad that is in direct contact with the via electrode, and a lower surface that is flush with the upper surface of the lower pad that is in direct contact with the lower surface of the via electrode. Here, the lower surface of the upper pad and the upper surface of the lower pad do not necessarily mean flat surfaces, and it should be understood that even concave or convex surfaces that may appear depending on various processes may be present.

[0068] Additionally, depending on the process, the via electrode and the pad may be formed integrally. That is, the pad may have a protrusion for electrical connection between circuit patterns arranged within each laminated insulating layer, and the protrusion may be regarded as a via electrode that electrically connects between adjacent laminated circuit patterns. That is, depending on the process, the via electrode and the pad may be distinguished by different configurations, or may be distinguished by the protrusion of the pad.

[0069] The circuit board may further include a protective layer (113). The protective layer (113) may function to protect the pad from external moisture or contaminants, and may function to prevent short circuits between adjacent conductive bonding members when bonding the semiconductor element and / or the main board and the circuit board. For example, the protective layer (113) may be formed of a solder resist. Specifically, the semiconductor element and / or the main board, etc., have a plurality of terminals for connecting the circuit board. In addition, the plurality of terminals may be arranged at a high density. When the plurality of terminals and the pads of the circuit board are bonded, the conductive bonding member may use solder, for example. When using solder, a solder short circuit problem may occur between terminals having a high density, and thus, a solder resist having poor wettability with the solder may be arranged to solve this short circuit problem. In addition, the protective layer (113) may be formed of a material having insulating properties for electrical connection. Accordingly, the protective layer (113) may be called an ‘insulating layer’ and may be a component of the above-described insulating layer (110).

[0070] And the insulating layer (112) or protective layer (113) located in the outer laminated area of ​​the circuit board may have an opening (OP). It may be electrically connected to other semiconductor elements or a circuit board, etc., through the opening (OP).

[0071] Circuit boards can be divided into package boards and interposers based on their function. The package board serves to mount semiconductor devices and / or interposers. As data increases, the circuit board area expands or the number of insulating layers increases, which can significantly reduce the yield of the circuit board. Therefore, by separating the circuit board into an interposer and a package board, the yield of the circuit board can be improved. In addition, the interposer can act as a buffer between the pad size and / or spacing of the package board and the fine pattern size and / or spacing of the terminals of the semiconductor devices. Specifically, as the spacing and size of the terminals of the semiconductor devices decrease and the terminal density increases, it can be difficult to implement pads of the package board with sizes and / or spacings corresponding to the terminals of the semiconductor devices. Therefore, by arranging an interposer with pad sizes and / or spacings that are between the pad sizes and / or spacings of the package board and the terminals of the semiconductor devices, the electrical connection between the semiconductor devices and the package board can be facilitated.

[0072] The package substrate and interposer described above can be classified into core substrates and coreless substrates, depending on the composition of the insulating layer. In the case of a core substrate, the insulating layer may include a core layer, and the core layer may refer to a layer among the laminated insulating layers that includes a reinforcing member. The reinforcing member may refer to glass fiber. The core layer may have the function of preventing warpage of the circuit board during the process by being arranged thicker than other insulating layers. However, the core layer may cause problems such as voltage drop and signal loss, or may be difficult to thin. Therefore, depending on the application, the insulating layer of the circuit board may use a coreless substrate that does not include a core layer.

[0073] The insulating layer of the circuit board is formed of any insulating resin, such as a thermosetting and / or photocurable resin. As the thermosetting resin, ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., can be used, and a material such as prepreg (PPG) containing glass fiber can be used. As the photocurable resin, any insulating resin, such as PID (Photo Imageable Dielectric) resin, can be used. The aforementioned optional insulating resin may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenol resin, etc., and may include an inorganic filler such as silica. When the insulating resin is used as a core, a reinforcing material such as glass fiber or aramid fiber can be included.

[0074] Fig. 2 is a drawing of a circuit board according to the first embodiment, Fig. 3 is an enlarged view of a portion of Fig. 2, and Fig. 4 is a modified example of Fig. 3.

[0075] Referring to FIGS. 2 and 3, a circuit board (100A) according to an embodiment may include an insulating layer (110), an electrode portion (120), and a connection layer (CL). In each embodiment, the insulating layer and the electrode portion may be applied as described above in FIG. 1, except for the description below.

[0076] A circuit board (100A) according to an embodiment may include a second insulating layer (112) including a cavity (CV). In the circuit board according to an embodiment of the present invention, the circuit pattern layer may be a concept including the circuit pattern and pad described in FIG. 1.

[0077] First, the insulating layer (110) may be formed of an insulating material. The insulating layer (110) may be formed of at least one layer. When the insulating layer (110) has a multi-layer structure, the insulating layers (110) of the multiple layers may include the same insulating material, but are not limited thereto. For example, at least one insulating layer (110) among the multiple layers of insulating layers (110) may include an insulating material different from at least one other insulating layer (110).

[0078] The insulating layer (110) of the circuit board (100A) may be rigid or flexible. For example, the insulating layer (110) of the circuit board (100A) may include glass or plastic. For example, the insulating layer (110) of the circuit board may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass. For example, the insulating layer (110) of the substrate may include a strengthened or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC). For example, the insulating layer (110) of the circuit board may include sapphire. For example, the insulating layer (110) of the substrate may include an optically isotropic film. For example, the insulating layer (110) of the substrate may include COC (Cyclic Olefin Copolymer), COP (Cyclic Olefin Polymer), photoisotropic polycarbonate (PC), or photoisotropic polymethyl methacrylate (PMMA). For example, the insulating layer (110) of the substrate may be formed of a material including a filler and an insulating resin. For example, the insulating layer (110) of the substrate may have a structure in which a filler such as silica or alumina is disposed in a thermosetting resin or a thermoplastic resin.

[0079] The insulating layer (110) may have a structure in which a plurality of different insulating materials are laminated, and an exemplary arrangement structure will be described in more detail as follows.

[0080] In one embodiment, the insulating layer (110) may include a core layer or a coreless layer including a reinforcing member. Here, the core layer may refer to an insulating layer including a reinforcing member and having a thickness in the lamination direction (X-axis direction) exceeding 30 μm. In addition, the insulating layer may include a plurality of layers that are respectively disposed on the upper and lower portions of the core layer and do not include a reinforcing member. In this case, the circuit board may be a core board. The reinforcing member may also be referred to as reinforcing fiber or glass fiber.

[0081] Reinforcing member may mean a glass fiber material extending along the horizontal direction of the insulation layer and may have a different meaning from the spaced filler.

[0082] In another embodiment, the insulating layer (110) of the substrate may be a coreless substrate that does not include a core layer. For example, the insulating layer (110) of the substrate may include an organic material that does not include a reinforcing member that has excellent processability, enables slimming of the substrate, and enables miniaturization of the electrode portion of the substrate. For example, the insulating layer (110) of the substrate may use ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Co., Ltd., and FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc. may be used. For example, the insulating layer (110) may include a plurality of layers composed of ABF.

[0083] As an example, the insulating layer (110) may include a first insulating layer (111) and a second insulating layer (112). The second insulating layer (112) may be disposed on the first insulating layer (111).

[0084] The first insulating layer (111) may be a part of a copper clad laminate (CCL). Alternatively, the first insulating layer (111) may correspond to a copper clad laminate. For example, the first insulating layer (111) and the first electrode portion (121) positioned on the first insulating layer (111) may be a copper clad laminate (CCL). The first insulating layer (111) and the first circuit pattern layer (121a) may be a copper clad laminate (CCL).

[0085] And the first insulating layer (111) may include an insulating material as an inner layer laminated region in the circuit board (100A). The first insulating layer (111) may be formed of a plurality of layers, and the plurality of layers may be formed of the same or different materials. The boundary surface of the upper second insulating layer (112) of the first insulating layer (111) may or may not be distinguished depending on the analysis method. The description of this boundary surface may be equally applied to each insulating layer within the first and second insulating layers. In addition, the first insulating layer (111) may be located between the upper and lower second insulating layers (112). The second insulating layer (112) may be disposed on the upper and lower surfaces of the first insulating layer (111).

[0086] The first insulating layer (111) and the first electrode portion (121) may not be easily removed by etching according to the etching process when forming a cavity. That is, even if a cavity (CV) is formed in the second insulating layer (112), the first insulating layer (111) and the first electrode portion (121) may easily remain.

[0087] Additionally, the second insulating layer (112) may be disposed on the first insulating layer (111) and the first circuit pattern layer (121a). The second insulating layer (112) may correspond to an outer layer lamination area in the circuit board (110A).

[0088] The second insulating layer (112) may be formed of at least one layer. As illustrated, the second insulating layer (112) may be formed of a plurality of layers. In addition, the second insulating layer (112) may include ABF (Ajinomoto Build-up Film) as described above, or prepreg (PPG) including glass fiber.

[0089] The second insulating layer (112) may be positioned on at least one of the upper and lower surfaces of the first insulating layer (111). The following description will be based on the lamination direction (X-axis direction).

[0090] Additionally, as described above, a third insulating layer (not shown) may be further disposed on the second insulating layer (112). The third insulating layer (not shown) may be a resist layer. This resist layer may have a function of preventing solder flow during solder bonding by having low solder wettability characteristics, or may have a function of preventing moisture or contaminants from the outside from penetrating into the circuit board.

[0091] Additionally, the third insulating layer (not shown) may be a solder resist layer containing an organic polymer material. For example, the third insulating layer (not shown) of the circuit board may contain a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. Additionally, the third insulating layer (not shown) may contain any one of a photo solder resist layer, a cover-lay, and a polymer material.

[0092] The electrode portion (120) may include a first electrode portion (121) and a second electrode portion (122). The first electrode portion (121) may be located on the first insulating layer (111). The second electrode portion (122) may be located on the second insulating layer (112).

[0093] The first electrode portion (121) may include a first circuit pattern layer (121a) and a first through-electrode (121b). The second electrode portion (122) may include a second circuit pattern layer (122a) and a second via electrode (122b). As described above, each circuit pattern layer may mean including a pad and / or trace of the electrode portion and a circuit pattern. In addition, the circuit pattern layer may be disposed within each stacked insulating layer, and for electrical connection between the circuit pattern layers disposed within each stacked insulating layer, the via electrode may be disposed between a plurality of circuit pattern layers disposed in different layers. In addition, the through-electrode may electrically connect a plurality of circuit pattern layers disposed in different layers.

[0094] The first circuit pattern layer (121a) may be disposed on the first insulating layer (111). The first circuit pattern layer (121a) may be disposed on the upper and lower surfaces of the first insulating layer (111). The first through-electrode (121b) may penetrate the first insulating layer (111) and be in contact with the first circuit pattern layer (121a).

[0095] The second circuit pattern layer (122a) may be disposed on the second insulating layer (112). The second circuit pattern layer (122a) may be disposed on the upper and lower surfaces of the second insulating layer (112). The second through-electrode (122b) may penetrate the second insulating layer (112) and be in contact with the second circuit pattern layer (122a).

[0096] In this way, the first circuit pattern layer (121a) and the second circuit pattern layer (122a) can be positioned on the first insulating layer (111) and the second insulating layer (112). And as described above, since the circuit pattern layer is a concept including a circuit pattern and a pad, the circuit pattern layer can be positioned within each insulating layer and may not be directly connected to a via electrode or a through-electrode. However, each circuit pattern layer can be electrically connected to any one of the via electrodes.

[0097] In addition, the first insulating layer (111) and the second insulating layer (112) may include vias or through-holes (V1, V2). The through-holes may include a first through-hole (V1) penetrating the first insulating layer (111) and a second through-hole (V2) penetrating the second insulating layer (112). In addition, through-electrodes of the electrode portion may be positioned in the through-holes (V1, V2). For example, a first via electrode (121b) may be positioned in the first through-hole (V1). A second via electrode (122b) may be positioned in the second through-hole (V2).

[0098] As an example, the first through hole (V1) of the first insulating layer (111) and the second through hole (V2) of the second insulating layer (112) may have inclined surfaces along the lamination direction. That is, the adjacent first through holes (V1) and second through holes (V2) may increase or decrease in area in one direction. For example, in the circuit board (100A), the areas of the first through hole (V1) and the second through hole (V2) may increase along the lamination direction based on the upper area. Here, the upper area of ​​the circuit board (100A) corresponds to an area on the lamination direction side among the areas that bisect the first insulating layer (111) in the lamination direction.

[0099] In addition, since the second insulating layer (112) is composed of multiple insulating layers, the second through holes (V2) may also be provided in multiple numbers. Each of the multiple second through holes (V2) may have an area that increases or decreases in one direction. Based on the upper region of the circuit board (100A), the area of ​​the multiple second through holes (V2) may increase along the stacking direction.

[0100] In addition, the second insulating layer (112) may cover at least a portion of the first circuit pattern layer (121a). In addition, the third insulating layer (not shown) may cover at least a portion of the second circuit pattern layer (122a). The third insulating layer (not shown) may include an opening for electrical connection with a semiconductor element, an interposer, etc. The second circuit pattern layer (122a) may be exposed by the opening. A shield layer, which will be described later, may be positioned on the third insulating layer.

[0101] The second insulating layer (112) may include a cavity (CV). The second insulating layer (112) may include the cavity (CV) and an edge portion outside the cavity (CV). The edge portion may correspond to an 'edge portion', a 'wall portion', a 'side wall', etc. Furthermore, a second electrode portion (122) may be positioned in the edge portion. In embodiments of the present invention, the cavity (CV) may be expressed in various ways, such as a 'groove', a 'recess', a hole, a 'via', etc. Furthermore, the cavity (CV) may have various shapes, such as a circle or a square.

[0102] Such a cavity (CV) may be located in the second insulating layer (112). That is, the cavity (CV) may be located on the first insulating layer (111) and the first electrode portion (121).

[0103] The cavity (CV) can have various shapes depending on the shape of the semiconductor device or chip mounted inside. For example, the shape of the semiconductor device or chip can generally be rectangular with respect to the plane perpendicular to the stacking direction. Correspondingly, the cavity (CV) can also have a rectangular shape with respect to the plane perpendicular to the stacking direction.

[0104] In addition, by securing a mounting space for semiconductor elements or chips, etc., within the cavity (CV), and by arranging the second electrode portion (122) on the second insulating layer (112) outside the cavity (CV), a circuit pattern with a small line width can be easily arranged within the second insulating layer (112). As a result, the circuit board according to the embodiment can provide an improved input / output (I / O) count.

[0105] A portion (111E) of the first insulating layer may be exposed by the cavity (CV). A portion (121E) of the first circuit pattern layer (121a) may be exposed by the cavity (CV).

[0106] And at least a portion of the first circuit pattern layer (121a) may be exposed by the cavity (CV).

[0107] The connection layer (CL) can penetrate the second insulating layer (112). The connection layer (CL) is a member for electromagnetic shielding and may include a conductive material. Accordingly, the connection layer may be called a 'shielding member', a 'shielding layer', a 'blocking member', or a 'blocking layer'. Furthermore, the connection layer (CL) may be made of the same material as a via electrode or may have the same / similar shape. In addition, the connection layer (CL) may be connected to the ground as described below or may be in a dummy or floating state at least in part.

[0108] Furthermore, the connection layer (CL) is similar to the via electrode, but may have the same or different heights in the stacking direction depending on the presence of pads. For example, if there is a pad embedded in the second insulating layer, the height of the connection layer (CL) in the stacking direction may be greater than the height of the via electrode in the stacking direction. The height of the connection layer (CL) in the stacking direction may be different from the height of the via electrode in the stacking direction.

[0109] As a variation, the connection layer (CL) may partially penetrate the second insulating layer (112). In addition, the connection layer (CL) may partially penetrate the first insulating layer (111) and also penetrate the second insulating layer (112). For example, the connection layer (CL) may be formed of a plurality of sub-connection layers that are spaced apart from each other. In addition, some of the plurality of sub-connection layers may penetrate the second insulating layer (112), and other parts may penetrate at least a portion of the second insulating layer (112) or at least a portion of the first insulating layer (111). However, considering the ease of the manufacturing process, at least a portion of the connection layer (CL) may penetrate the second insulating layer (112). This will be described below based on this. In addition, the connection layer may be formed simultaneously with the formation of the cavity. Accordingly, the ease of manufacturing may be improved. Alternatively, the connection layer may be formed at a different stage from the cavity.

[0110] The connection layer (CL) may be made of a conductive material similar to the second electrode portion (122). Accordingly, the connection layer (CL) may be electrically connected to a shield layer disposed on the upper portion of the circuit board (100A). Accordingly, the connection layer (CL) may be connected to ground in the package substrate and may serve as a 'shielding layer', a 'shielding layer', or an 'electromagnetic interference (MEI) blocking layer' that performs an electromagnetic interference (MEI) function. Furthermore, the cavity (CV) may be formed as an empty space and may be a space through which electromagnetic waves can easily pass. Accordingly, by arranging the connection layer (CL) that performs a shielding function on the outside of the cavity (CV), electromagnetic interference (EMI) of a semiconductor element or chip within the cavity (CV) may be performed more effectively.

[0111] Furthermore, the second electrode portion disposed on the second insulating layer (112) is a variety of signal lines, and by disposing the connection layer (CL) on the second insulating layer, electromagnetic interference flowing in and out from the signal lines can be effectively blocked.

[0112] The connection layer (CL) may be disposed along the edge of the cavity (CV) while being disposed on the second insulating layer (112). The connection layer (CL) may overlap the second circuit pattern layer (122a) in a direction perpendicular to the lamination direction on the outside of the cavity (CV). That is, the connection layer (CL) may be located in the same layer as the second electrode portion (122) within the second insulating layer (112). Alternatively, the connection layer (CL) may be located in the same layer as at least a portion of the second electrode portion (122) within the second insulating layer (112). Accordingly, at least a portion of the second electrode portion (122) may overlap the connection layer (CL) in a horizontal direction perpendicular to the lamination direction.

[0113] Furthermore, the connection layer (CL) may be positioned between the second electrode portion (122) and the cavity (CV) or on the outside of the second electrode portion (122). Alternatively, the connection layer (CL) may be positioned between the second electrode portions (122) spaced apart within the second insulating layer (112). By applying this structure, the connection layer (CL) can prevent electromagnetic interference generated from the circuit board or from the outside from flowing into or out of the cavity. In addition, noise caused by electromagnetic waves can be reduced through this.

[0114] The connection layer (CL) can block electromagnetic forces applied to semiconductor devices or chips mounted within the cavity (CV). In other words, the shielding function of the connection layer (CL) can be effectively provided.

[0115] And since the connection layer (CL) is located on the outer side of at least a portion of the second electrode portion (122), the electrical reliability of the second electrode portion (122) can also be improved.

[0116] In addition, the connection layer (CL) can penetrate the second insulating layer (112) as described above and come into contact with the upper surface of the first insulating layer (111). Accordingly, the connection layer (CL) can overlap the semiconductor element or chip in the horizontal direction. Accordingly, electromagnetic shielding for the semiconductor element or chip can be effectively performed.

[0117] In addition, the connection layer (CL) may be spaced apart from the side surface (CVS) of the cavity (CV). And since the connection layer (CL) is spaced apart from the side surface (CVS) of the cavity (CV) by a predetermined distance (W1), the occurrence of electrical issues (e.g., short circuit) for semiconductor devices or chips mounted in the cavity (CV) can be suppressed. Here, the predetermined distance (W1) may mean the shortest distance in the horizontal direction between the side surface (CVS) of the cavity (CV) and the connection layer (CL). In the case where the connection layer (CL) is formed of a conductive material and has an inclined side surface, the predetermined distance (W1) for electromagnetic wave shielding is defined as the shortest distance in the horizontal direction between the conductive material and the side surface (CVS) of the cavity (CV), thereby allowing the positional accuracy of the cavity (CV) to be more precisely controlled.

[0118] Furthermore, the bottom surface (CVB) of the cavity (CV) may correspond to the top surface (111E) of the exposed first insulating layer. In addition, the bottom surface (CVB) of the cavity (CV) may correspond to the exposed first electrode portion (121') or the exposed first circuit pattern layer. Accordingly, electrical connection between the semiconductor element or chip mounted within the cavity (CV) and the second electrode portion (122) can be easily achieved.

[0119] The connection layer (CL) may penetrate the second insulating layer (112) so that a portion of the upper portion may be exposed. The upper surface (CLE) of the exposed connection layer (CL) may be spaced apart from the upper surface of the first circuit pattern layer (122a) located on the upper surface of the second insulating layer (112). For example, the upper surface (CLE) of the exposed connection layer (CL) may be spaced apart from the upper surface of the first circuit pattern layer (122a) located on the upper surface of the second insulating layer (112) by a predetermined distance (DH) in the lamination direction. In addition, the upper surface (CLE) of the exposed connection layer (CL) may be located below the upper surface of the first circuit pattern layer (122a) located on the upper surface of the second insulating layer (112). For example, the upper surface (CLE) of the exposed connection layer (CL) may be positioned adjacent to the first insulating layer (111) compared to the upper surface of the first circuit pattern layer (122a) located on the upper surface of the second insulating layer (112).

[0120] Additionally, the connection layer (CL) according to the embodiment may be electrically connected to the second electrode portion (122). For example, the connection layer (CL) may be electrically connected to the second circuit pattern layer (122a). To this end, in the circuit board (100A) according to the embodiment, the connection layer (CL) may be electrically connected to the second electrode portion (122) through an extension portion.

[0121] The circuit board (100A) may include a first extension portion (EP1) for electrical connection. The first extension portion (EP1) may be in contact with the connection layer (CL) and the second electrode portion (122) and may be electrically connected to the connection layer (CL) and the second electrode portion (122).

[0122] The first extension portion (EP1) may be positioned within the second insulating layer (112). The first extension portion (EP1) may extend in a direction perpendicular to the lamination direction. Accordingly, the first extension portion (EP1) may connect between the connection layer (CL) and the second circuit pattern layer (122a). Accordingly, the first extension portion (EP1) may overlap the second electrode portion (122) within the second insulating layer (112) or the connection layer (CL) in a direction perpendicular to the lamination direction.

[0123] For example, the first extension portion (EP1) may include at least one of the first-first extension portion (EP1a), the first-second extension portion (EP1b), and the first-third extension portion (EP1c). Each of the first-first extension portion (EP1a), the first-second extension portion (EP1b), and the first-third extension portion (EP1c) may be positioned within one layer of the second insulating layer (112) composed of multiple layers. As a result, the first extension portion (EP1) may be easily electrically connected to the second electrode portion (122).

[0124] In addition, any one of the first-first extension portion (EP1a), the first-second extension portion (EP1b), and the first-third extension portion (EP1c) may be located in a portion of the second insulating layer (112). In other words, the connection layer (CL) may be in contact with and electrically connected to the second electrode portion (122) through the plurality of contact points, i.e., the first-first extension portion (EP1a), the first-second extension portion (EP1b), and the first-third extension portion (EP1). Accordingly, even if an electrical issue occurs in any one of the first-first extension portion (EP1a), the first-second extension portion (EP1b), and the first-third extension portion (EP1c), the electrical connection between the connection layer (CL) and the second electrode portion (122) may be maintained. And the first-first extension portion (EP1a), the first-second extension portion (EP1b), and the first-third extension portion (EP1c) can also be electrically connected to the first electrode portion (121). For example, the first-first extension portion (EP1a), the first-second extension portion (EP1b), and the first-third extension portion (EP1c) can be electrically connected to any one of the first electrode portions (121). In other words, electromagnetic shielding can be maintained more reliably.

[0125] And the first electrode portion (121) connected to the first extension portion (EP1) can be electrically connected to the ground of the substrate. Accordingly, the connection layer (CL), the first extension portion (EP1), the second electrode portion, and the first electrode portion can be electrically connected (PATH1). Furthermore, the first extension portion (EP1) can also be positioned in the same layer as the second electrode portion (122) within the second insulating layer (112). Accordingly, the first extension portion (EP1) can be in contact with the electrode portion of the second electrode portion (122) that is closest to the first extension portion (EP1). Accordingly, the circuit formation of the second extension portion (EP1) can be easily achieved.

[0126] Additionally, the first extension portion (EP1) may be formed in the same shape as the trace or pad of the electrode portion. Accordingly, the first extension portion (EP1) may be formed in the same layer as the pad or the second circuit pattern layer of the second electrode portion, and may overlap with the pad or the second circuit pattern layer in a direction perpendicular to the stacking direction. In addition, for electrical connection, the first extension portion (EP1) may be formed of a conductive material.

[0127] Referring further to FIG. 4, in a variation, the circuit board may include a second extension portion (EP3). The second extension portion (EP3) may be in contact with the connection layer (CL) and the first electrode portion (121), and may be electrically connected to the connection layer (CL) and the first electrode portion (121).

[0128] The second extension portion (EP3) may be located within the first insulating layer (111). In the present embodiment, the extension portion may be a trace or pad electrically connected to the ground (or ground) of the substrate. In addition, the second extension portion (EP3) may extend in the stacking direction or in a direction perpendicular to the stacking direction. Accordingly, the second extension portion (EP3) may connect between the connection layer (CL) and the first circuit pattern layer (121a). Accordingly, the second extension portion (EP3) may overlap the first electrode portion (121) or the connection layer (CL) within the first insulating layer (111) in a direction perpendicular to the stacking direction.

[0129] For example, at least one second extension portion (EP3) may be present at various locations within the first insulating layer (111). Accordingly, the second extension portion (EP3) can be easily electrically connected to the first electrode portion (121). In addition, a portion of the second extension portion (EP3) may be positioned in a certain area within the first insulating layer (111). In other words, the connection layer (CL) may be connected to the first electrode portion (121) through a plurality of contact points. Accordingly, even if an electrical issue occurs in a portion of the second extension portion (EP3) or a portion of the first electrode portion (121), the electrical connection between the connection layer (CL) and the first electrode portion (121) can be maintained. In other words, the reliability of electromagnetic shielding can be maintained at a higher level.

[0130] And the first electrode portion (121) connected to the second extension portion (EP3) can be electrically connected to the ground of the substrate. Accordingly, the connection layer (CL), the second extension portion (EP3), and the first electrode portion (121) can be electrically connected (PATH2a, 2b). In addition, as described above, a plurality of electrical connection paths (PATH2a, 2b) can be formed by a plurality of contact points. Accordingly, the maintenance power or reliability for electromagnetic shielding can be performed more effectively.

[0131] Additionally, the second extension portion (EP3) may be formed in the same shape as the trace or pad of the electrode portion. Accordingly, the second extension portion (EP3) may be formed in the same layer as the pad or the second circuit pattern layer of the second electrode portion, and may overlap with the pad or the second circuit pattern layer in a direction perpendicular to the stacking direction. In addition, for electrical connection, the second extension portion (EP3) may be formed of a conductive material.

[0132] Additionally, as another example, the connection layer (CL) may be in direct contact with the first electrode portion (121). For example, the connection layer (CL) may overlap at least partially with the first electrode portion (121) in the lamination direction. As a result, contact between the connection layer (CL) and the first electrode portion (121) may be more easily achieved.

[0133] FIG. 5 is a plan view of a circuit board according to the first embodiment, FIG. 6 is a view taken along line AA' in FIG. 5, and FIG. 7 is a view taken along line BB' in FIG. 5.

[0134] Referring to FIGS. 5 to 7, in a circuit board according to an embodiment, a connection layer (CL) may surround a cavity (CV) in an open loop or closed loop form. For example, the connection layer (CL) may surround a cavity (CV) in an open loop form.

[0135] Accordingly, a plurality of connection layers (CL) may be arranged spaced apart from each other. The connection layer (CL) may include a first sub-connection layer (SCL) and a second sub-connection layer (SCL'). The first sub-connection layer (SCL) and the second sub-connection layer (SCL') may be arranged spaced apart from each other by a predetermined distance (gap) in a direction perpendicular to the stacking direction. In addition, both the first sub-connection layer (SCL) and the second sub-connection layer (SCL') may not be in direct contact with the first extension portion or the second electrode portion. However, even if the first sub-connection layer (SCL) and the second sub-connection layer (SCL') are not in direct contact, they may be electrically connected to each other. Accordingly, an electromagnetic shielding function by the connection layer (CL) surrounding the cavity (CV) may be realized.

[0136] In addition, the connection layer (CL) may be located between the second electrode portion (122) and the cavity (CV) or on the outside of the second electrode portion (122). And the connection layer (CL) may be located between the second electrode portions (122) spaced apart within the second insulating layer (112). That is, the connection layer (CL) may be located on the outside of at least a portion of the second electrode portion (122). Furthermore, as described above, the area of ​​the cavity (CV) in a plane or surface perpendicular to the lamination direction may be smaller than the area of ​​the open loop formed by the connection layer (CL).

[0137] Furthermore, since the connection layer (CL) is on the outside of the cavity (CV), the connection layer (CL) can also suppress warping of the circuit board due to thermal expansion, etc.

[0138] Figures 8 to 9 are flowcharts for a method of manufacturing a circuit board according to the first embodiment.

[0139] Referring to Fig. 8, a copper-clad laminate having copper foil on both sides including a first insulating layer (111) is prepared. Then, a via hole or a through hole can be formed in the first insulating layer (111). The through hole or the via hole can be formed by a method such as a laser drilling method, a punching method, an etching method (mechanical drilling, chemical etching, or any suitable mechanism).

[0140] And a first via electrode can be formed within the first through hole. Afterwards, a first circuit pattern layer can be formed on top of the first insulating layer (111) through patterning.

[0141] And a second insulating layer (112) can be laminated on both sides of the first insulating layer (111). And a through hole or a via hole can be formed for the second insulating layer and a second via electrode can be formed. However, one area of ​​the second insulating layer (112) can be formed only by the insulating layer without the second electrode portion. This area can correspond to the area of ​​the cavity described above. Furthermore, the connection layer (CL) can also be positioned on the second insulating layer (112).

[0142] Each circuit pattern layer can be formed by a manufacturing process of a printed circuit board, such as an additive process, a subtractive process, a modified semi-additive process (MSAP), and a semi-additive process (SAP).

[0143] Furthermore, the pattern can be formed by a dry film or the like.

[0144] Referring to FIG. 9, a cavity (CV) may be formed on the inside of the second insulating layer (112) in the above-described region by a method such as a laser method, a punching method, or an etching method. The cavity (CV) may penetrate the central region of the second insulating layer (112). The cavity (CV) may be surrounded by the second electrode portion. In addition, the cavity (CV) may be surrounded by the connection layer (CL). In other words, the cavity (CV) may be located within the connection layer (CL) and the second electrode portion. The first insulating layer (111) and a portion of the first electrode portion (121) may be exposed by the cavity (CV). dd

[0145] FIG. 10 is a plan view of a circuit board according to the second embodiment, FIG. 11 is a view taken along CC' in FIG. 10, FIG. 12 is a view taken along DD' in FIG. 10, and FIG. 13 is a view taken along EE' in FIG. 10.

[0146] Referring to FIGS. 10 to 13, a circuit board (100B) according to the second embodiment may include an insulating layer (110), an electrode portion (120), and a connection layer (CL). Except for the contents described below, the above-described contents may be equally applied.

[0147] In the circuit board (100B) according to the second embodiment, the connection layer (CL) can surround the cavity (CV) in a closed loop. Accordingly, the connection layer (CL) can continuously surround the cavity (CV). At least a portion of the connection layer (CL) can be in direct contact with the first extension portion, the second electrode portion, the first electrode portion, or the second electrode portion. For example, the connection layer (CL) can be electrically connected to the first extension portion, the second electrode portion, and the first electrode portion. Alternatively, the connection layer (CL) can be electrically connected to the second electrode portion. And the connection layer (CL) can be electrically connected to the second electrode portion and the second extension portion. Accordingly, an electromagnetic shielding function can be realized by the connection layer (CL) surrounding the cavity (CV).

[0148] In addition, the connection layer (CL) may be located between the second electrode portion (122) and the cavity (CV) or on the outside of the second electrode portion (122). And the connection layer (CL) may be located between the second electrode portions (122) spaced apart within the second insulating layer (112). That is, the connection layer (CL) may be located on the outside of at least a portion of the second electrode portion (122). Furthermore, as described above, the area of ​​the cavity (CV) in a plane or surface perpendicular to the lamination direction may be smaller than the area of ​​a closed loop formed by the connection layer (CL).

[0149] The connection layer (CL) may maintain its length in the stacking direction, or may vary in some areas. For example, the connection layer (CL) may vary in length at the edges of the closed loop in the stacking direction. For example, the longer the distance between the connection layer (CL) and the cavity (CV), the greater the length of the connection layer (CL) in the stacking direction.

[0150] Fig. 14 is a drawing of a circuit board according to the third embodiment.

[0151] A circuit board (100C) according to the third embodiment may include an insulating layer (110), an electrode portion (120), and a connection layer (CL). Except for the contents described below, the above-described contents may be equally applied.

[0152] In the circuit board (100C) according to the third embodiment, the connection layer (CL) may be located in the second insulating layer (112). The connection layer (CL) may penetrate the second insulating layer (112).

[0153] The connection layer (CL) may have a different shape from the second electrode portion (122) of the second insulating layer (112) composed of multiple layers. In the second electrode portion (122), the through electrode (122b) may be positioned in each layer of the second insulating layer (112). Accordingly, the width (or area) of the through electrode (122b) in each layer may increase or decrease in the stacking direction. For example, the width (or area) of the through electrode (122b) in the lower portion of each layer may be the same. Or, the width (or area) of the through electrode (122b) in the lower portion of each layer may be similar to each other within a range of 20%. And, the width (or area) of the through electrode (122b) in the upper portion of each layer may be the same. Or, the width (or area) of the through electrode (122b) in the upper portion of each layer may be similar to each other within a range of 20%.

[0154] Additionally, the connecting layer (CL) can continuously penetrate at least two layers among each layer of the second insulating layer (112). Accordingly, the minimum width (or area) of the connecting layer (CL) can be smaller than the minimum width (or area) of the through-electrode (122b).

[0155] In addition, the second insulating layer (112) may be composed of multiple layers as described above. For example, the multiple layers of the second insulating layer (112) may include a 2-1 insulating layer (112a), a 2-2 insulating layer (112b), and a 2-3 insulating layer (112c).

[0156] In an embodiment, a groove extending outwardly from the connection layer (CL) may be present at the interface between each insulating layer. This groove may be located at the interface between adjacent insulating layers. This groove may be formed at the interface of adjacent insulating layers when forming a through hole penetrating multiple insulating layers.

[0157] And, in some areas of the boundary surface of adjacent insulating layers, such grooves may not exist. The following description is based on the existence of grooves at the boundary surface between each insulating layer in the second insulating layer (112).

[0158] For example, a first groove (GA1) may be positioned between the 2-1 insulating layer (112a) and the 2-2 insulating layer (112b). And a second groove (GA2) may be positioned between the 2-2 insulating layer (112b) and the 2-3 insulating layer (112c).

[0159] And the connecting layer (CL) may be present at least in a groove formed at the boundary surface of each insulating layer. For example, when forming a through hole penetrating a second insulating layer (112) composed of a plurality of insulating layers, a portion of the through hole extending from the second insulating layer (112) to the boundary surface between adjacent insulating layers may correspond to the groove. After the through hole and the groove are formed, the connecting layer (CL) may be filled up to the groove. For example, the connecting layer (CL) may be positioned within the first groove (GA1). Additionally, the connecting layer (CL) may be positioned within the second groove (GA2).

[0160] In addition, the grooves formed at the boundary surface of adjacent insulating layers may have the same or different widths depending on the location. For example, the width (Wj) of the first groove (GA1) may also vary depending on the location in the plane. Similarly, the width (Wk) of the second groove (GA2) may also vary depending on the location in the plane. Furthermore, the width (Wj) of the first groove (GA1) and the width (Wk) of the second groove (GA2) may be the same or different.

[0161] Additionally, the connection layer (CL) may be located within the groove, but may be located at least in a portion thereof. For example, the connection layer (CL) may fill the entirety of each groove (GA1, GA2). Additionally, the connection layer (CL) may fill at least a portion of each groove (GA1, GA2). Accordingly, a gap may exist between the side of the groove and the connection layer (CL) in each groove (Ga1, GA2). For example, air may be present.

[0162] And the connection layer (CL) can be electrically connected to the first and second electrode parts through the first extension part or the second extension part. And the distance between the connection layer (CL) and the adjacent second electrode part can increase or decrease as it faces one direction (lower). For example, the connection layer (CL) may be formed differently from the number of layers of the second insulating layer. The connection layer (CL) may have a structure in which the area, size, or width decreases toward the lower part of the substrate or the first insulating layer. By this configuration, the problem of disconnection between the electrode part and the connection layer (CL) can be reduced. In addition, the propagation path of electromagnetic waves becomes longer and more energy is absorbed, so that electromagnetic interference can be reduced more effectively. The via hole for arranging the connection layer (CL) can be formed by a machine (e.g., laser cutting) or a chemical method, as described below.

[0163] Fig. 15 is a cross-sectional view showing a semiconductor package according to the first embodiment.

[0164] Referring to FIG. 15, a semiconductor package according to the first embodiment may include a circuit board according to various embodiments described above. Hereinafter, the circuit board is referred to as a first circuit board.

[0165] The semiconductor package includes a first conductive coupling portion (410) disposed on an electrode portion of a first circuit board. The first conductive coupling portion (410) may be disposed on each of a plurality of electrode portions (first electrode portions) of the first circuit board. In particular, the first conductive coupling portion (410) may be disposed on a first circuit pattern layer exposed by a cavity in the first circuit board. In the present specification, the conductive coupling portion may correspond to a 'connection portion', a 'conductive portion', etc. for electrical connection.

[0166] The first conductive joint (410) may have a spherical shape. For example, the cross-section of the first conductive joint (410) may have a circular shape or a semicircular shape. For example, the cross-section of the first conductive joint (410) may have a partially or entirely rounded shape. For example, the cross-sectional shape of the first conductive joint (410) may be flat on one side and curved on the other side. The first conductive joint (410) may be a solder ball, but is not limited thereto.

[0167] A semiconductor package according to an embodiment may include a chip (420) or semiconductor element disposed on a first conductive bonding portion (410). The chip (420) may be a processor chip. For example, the chip (420) may be an application processor (AP) chip selected from among a central processor (e.g., a CPU), a graphics processor (e.g., a GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller.

[0168] At this time, the bottom surface of the chip (420) may include a terminal (425), and the terminal (425) may be electrically connected to the first electrode portion (first circuit pattern layer) of the first circuit board through the first conductive bonding portion (410).

[0169] Meanwhile, the semiconductor package of the embodiment may be configured to have multiple chips arranged on a single circuit board at a predetermined distance from each other. For example, the chip (420) may include a first chip and a second chip that are spaced apart from each other.

[0170] For example, the first circuit board may include a plurality of cavities spaced apart in the width direction or length direction. A first chip and a second chip may be respectively positioned within the plurality of cavities. At this time, at least one terminal of the first chip may be connected to at least one terminal of the second chip. Furthermore, the first chip and the second chip may be different types of application processor (AP) chips.

[0171] Meanwhile, the first chip and the second chip can be spaced apart on the circuit board at a certain distance. This ensures electrical reliability. Furthermore, the distance between the first and second chips can prevent loss in signal transmission between the first and second chips, or in signal transmission to each of the first and second chips.

[0172] Meanwhile, the semiconductor package may include a second conductive bonding portion within an opening or openings in the outermost insulating layer of the first circuit board.

[0173] At this time, the second conductive joint may be a solder ball, but is not limited thereto. In an embodiment, the uppermost portion of the second conductive joint may be positioned higher than the uppermost portion of the chip (420). This configuration can prevent damage to the circuit board. Furthermore, space can be easily secured for a package substrate or circuit board additionally positioned above.

[0174] Additionally, the embodiment may include a third conductive coupling portion (440) positioned within an opening of the protective layer or the second insulating layer. The third conductive coupling portion (440) may be for coupling the semiconductor package and a main board (or motherboard) of an external device.

[0175] Furthermore, the semiconductor package may include a shield layer (SL) positioned on top of the circuit board. The shield layer (SL) may be positioned on the outside of the second insulating layer (112).

[0176] And the connection layer (CL) can be electrically connected to the shield layer (SL). The shield layer (SL) can be spaced apart from the second conductive bonding portion described above. The shield layer (SL) can be electrically isolated from the second conductive bonding portion. As a result, the electrical reliability of the shield layer (SL) can be improved.

[0177] And the shield layer (SL) can be positioned on the semiconductor element (or chip), underfill, and molding layer mounted within the cavity (CV). The shield layer (SL) can be electrically isolated from the semiconductor element (or chip).

[0178] Fig. 16 is a flowchart showing a method for manufacturing a semiconductor package according to the first embodiment.

[0179] Referring to Fig. 16, semiconductor devices can be mounted in each cavity of a plurality of circuit boards. After the semiconductor devices or chips are mounted in the cavities (CVs), underfilling and other operations can be easily performed. Furthermore, molding of the circuit boards can be performed (Fig. 16(a)).

[0180] And a shield layer (SL') can be formed on the circuit board. The shield layer (SL') can be formed on the upper surface of a plurality of circuit boards (Fig. 16(b)). In addition, the shield layer (SL') can also be located on the side surface of a plurality of circuit boards.

[0181] Additionally, the shield layer (SL') can be formed on the upper surface of the circuit board by various methods. For example, the shield layer (SL') can be formed by sputtering. Accordingly, metal particles can be deposited on the upper surface of the package substrate or the upper surface of the circuit board. In addition, they can also be deposited on the side surface of the circuit board.

[0182] Furthermore, multiple package substrates can be separated into individual pieces. The separation described above can be accomplished through various methods. For example, the package substrates can be separated through physical or chemical methods.

[0183] For example, each of the plurality of package substrates may be separated into individual circuit substrates or package substrates by a sawtooth street or scribe, a saw blade, a cutting tool, a laser, or the like, with a circuit substrate having a shield layer bonded thereto. According to an embodiment, even if the shield layer (SL') is formed on the upper surface of the circuit substrate or the upper surface of the package substrate, the connection layer and the shield layer (SL') of each circuit substrate may be electrically connected. Accordingly, even if the shield layer is not formed on the side surface of the circuit substrate at a different deposition rate from the upper surface of the circuit substrate, a shielding structure for electromagnetic interference may be formed within the circuit substrate.

[0184] This eliminates the risk of a shield layer not forming on the side of the circuit board, as the connection layer is formed within the circuit board. Furthermore, this effectively reduces process time due to differences in deposition rates. Furthermore, it also reduces material costs for shield layer formation.

[0185] Fig. 17 is a cross-sectional view showing a semiconductor package according to the second embodiment, and Fig. 18 is a plan view of the semiconductor package according to the second embodiment.

[0186] Referring to FIGS. 17 and 18, a semiconductor package according to the second embodiment may include a circuit board according to the various embodiments described above. In addition, the semiconductor package may include a shield layer (SL), a first conductive bonding portion (410), a chip (420), a third conductive bonding portion (440), and the like. Furthermore, the semiconductor package may be applied with all of the contents described below.

[0187] Furthermore, the circuit board may include a plurality of cavities (CVs). For example, the circuit board may include a first cavity (CV1) and a second cavity (CV2). The first cavity (CV1) and the second cavity (CV2) may be spaced apart from each other.

[0188] Furthermore, a first chip (420a) may be positioned in the first cavity (CV1). Additionally, a second chip (420b) may be positioned in the second cavity (CV2).

[0189] The circuit board may include a connection layer (CL) surrounding each cavity. The connection layer (CL) may be positioned corresponding to the cavity. The connection layer may include a first connection layer (CL1) and a second connection layer (CL2). The first connection layer (CL1) may be arranged to surround the first cavity (CV1). The second connection layer (CL2) may be arranged to surround the second cavity (CV2).

[0190] The first connection layer (CL1) and the second connection layer (CL2) may be in contact with or spaced apart from each other. This configuration allows for more effective electromagnetic shielding of semiconductor devices or chips placed in each of the plurality of cavities.

[0191] Fig. 19 is a cross-sectional view showing a semiconductor package according to the third embodiment, and Fig. 20 is a plan view of the semiconductor package according to the third embodiment.

[0192] Referring to FIGS. 19 and 20, a semiconductor package according to a third embodiment may include a circuit board according to various embodiments described above. In addition, the semiconductor package may include a shield layer (SL), a first conductive bonding portion (410), a chip (420), a third conductive bonding portion (440), and the like. Furthermore, the semiconductor package may be applied with all of the contents described below.

[0193] Furthermore, the circuit board may include a plurality of cavities (CVs). For example, the circuit board may include a first cavity (CV1) and a second cavity (CV2). The first cavity (CV1) and the second cavity (CV2) may be spaced apart from each other.

[0194] A first chip (420a) may be positioned in the first cavity (CV1). Additionally, a second chip (420b) may be positioned in the second cavity (CV2).

[0195] And the circuit board may include a connection layer (CL) surrounding the cavity. For example, the connection layer (CL) may surround a plurality of cavities (CV). That is, a plurality of cavities and a plurality of semiconductor devices (or chips) may be positioned inside the connection layer (CL). In addition, the connection layer (CL) may not exist in an area between a plurality of adjacent cavities. Accordingly, the cavity and the connection layer may not overlap each other in an area between a plurality of adjacent cavities. The connection layer (CL) may be positioned corresponding to the cavity. Accordingly, the cavity (CV) may be formed by only one connection layer (CL).

[0196] The first connection layer (CL1) and the second connection layer (CL2) may be in contact with or spaced apart from each other. This configuration allows for more effective electromagnetic shielding of semiconductor devices or chips placed in each of the plurality of cavities.

[0197] Meanwhile, when a circuit board having the characteristics of the invention described above is used in IT devices such as smartphones, server computers, TVs, or home appliances, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the characteristics of the invention performs a semiconductor package function, it can safely protect semiconductor chips from external moisture or contaminants, and can solve problems such as leakage current or electrical shorts between terminals, or electrical open circuits in terminals supplying semiconductor chips. Furthermore, when it performs a signal transmission function, it can solve noise problems. Through this, the circuit board having the characteristics of the invention described above can maintain the stable function of IT devices or home appliances, thereby enabling the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability with each other.

[0198] When a circuit board having the characteristics of the invention described above is used in a transportation device such as a vehicle, it can solve the problem of signal distortion transmitted to the transportation device, safely protect the semiconductor chip controlling the transportation device from external sources, and solve the problem of leakage current or electrical short circuit between terminals, or electrical open of the terminal supplying the semiconductor chip, thereby further improving the stability of the transportation device. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

[0199] The features, structures, effects, etc. described in the embodiments above are included in at least one embodiment, and are not necessarily limited to just one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by those skilled in the art to which the embodiments pertain. Therefore, the contents related to such combinations and modifications should be construed as being included within the scope of the embodiments.

[0200] Although the above description focuses on examples, these are merely examples and are not intended to limit the examples. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible without departing from the essential characteristics of the present examples. For example, each component specifically shown in the examples can be modified and implemented. In addition, differences related to such modifications and applications should be interpreted as being included within the scope of the embodiments set forth in the appended claims.

Claims

1. First insulation layer; A first circuit pattern layer disposed on the first insulating layer; A second insulating layer disposed on the first insulating layer and the first circuit pattern layer and including a cavity; A second circuit pattern layer disposed on the second insulating layer; and A circuit board comprising a connecting layer penetrating the second insulating layer and arranged along the edge of the cavity.

2. In paragraph 1, A circuit board in which the above-mentioned connecting layer overlaps the second circuit pattern layer in a direction perpendicular to the lamination direction on the outside of the cavity.

3. In paragraph 1, A circuit board wherein the connecting layer is disposed between the second circuit pattern layer and the cavity or on the outside of the second circuit pattern layer.

4. In paragraph 1, The above connecting layer is a circuit board electrically connected to the first circuit pattern layer.

5. In paragraph 1, A circuit board in which the above connecting layer is electrically connected to the second circuit pattern layer.

6. In paragraph 1, The above connecting layer is a circuit board that surrounds the cavity in an open loop or closed loop.

7. In paragraph 1, The above connection layer comprises a plurality of first sub-connection layers and second sub-connection layers that are adjacent to each other, A circuit board in which the first sub-connection layer and the second sub-connection layer are spaced apart from each other.

8. In paragraph 1, A circuit board comprising a first extension portion extending in a direction perpendicular to the stacking direction and connecting between the connection layer and the second circuit pattern layer.

9. In paragraph 8, A circuit board in which the first extension portion is disposed within the second insulating layer.

10. In paragraph 1, A circuit board comprising a second extension portion extending in the stacking direction and connecting between the connection layer and the first circuit pattern layer.

11. In paragraph 10, A circuit board in which the second extension portion is disposed within the first insulating layer.

12. In paragraph 1, A circuit board comprising a first cavity and a second cavity spaced apart from the first cavity.

13. In paragraph 12, A circuit board comprising a first connecting layer surrounding the first cavity and a second connecting layer surrounding the second cavity.

14. In paragraph 13, A circuit board in which the first connection layer and the second connection layer are in contact with or spaced apart from each other.

15. Circuit board; A semiconductor element connected to the circuit board; and A connection portion connecting the semiconductor element and the circuit board; The above circuit board, First insulating layer; A first circuit pattern layer disposed on the first insulating layer; A second insulating layer disposed on the first insulating layer and the first circuit pattern layer and including a cavity; A second circuit pattern layer disposed on the second insulating layer; and a connecting layer penetrating the second insulating layer and arranged along the edge of the cavity; Further comprising a shield layer disposed outside the second insulating layer; The above connecting layer is a package substrate electrically connected to the above shield layer.

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