Display panel and display device

Abstract

The present disclosure relates to a display panel. The display panel comprises a functional layer group; the side of the functional layer group away from a base substrate comprises at least one area where a pattern is to be formed and other areas; the other areas are located on the periphery of said areas; at least some of the other areas are higher than said areas; and the distance between the at least some of the other areas and the base substrate is greater than the distance between said areas and the base substrate. A step is formed between other areas and areas where patterns are to be formed, the areas where patterns are to be formed are not scratched when a fine mask moves, and formation of particle foreign matters in the areas where patterns are to be formed is avoided, improving the recognition accuracy of a test device, and thus improving the vapor deposition yield. The present disclosure further provides a display device comprising the display panel.

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese Patent Application No. 202310735708.0, filed on June 20, 2023, entitled “Display Panel and Display Device,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0004] By monitoring the offset of the center of the region to be patterned relative to the center of the alignment mark, the overall offset of the fine metal mask can be estimated.

[0005] When the fine metal mask plate fluctuates, it is easy to scrape the area to be patterned on the back plate, forming particulate foreign objects in the area to be patterned, reducing the recognition accuracy of the testing device and affecting the evaporation yield.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0007] Summary of the Invention

[0008] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device.

[0009] According to one aspect of this disclosure, a display panel is provided, having a display area and a non-display area located around the display area. The display panel includes a substrate and a functional layer group. The functional layer group is disposed on one side of the substrate. The side of the functional layer group away from the substrate includes at least one area to be patterned and other areas. At least one area to be patterned is located in the non-display area, and the other areas are located around the area to be patterned. At least a portion of the other areas are at a greater distance from the substrate than the distance between the area to be patterned and the substrate.

[0010] In one embodiment of this disclosure, the functional layer group includes a planarization layer group, a first electrode, and a pixel defining layer. The planarization layer group includes a first planarization layer and a second planarization layer. The first planarization layer is disposed on one side of the substrate, and the second planarization layer is located on the side of the first planarization layer away from the substrate. The first electrode is disposed on the side of the planarization layer group away from the substrate. The pixel defining layer is disposed on the side of the first electrode away from the substrate, and the pixel defining layer has a pixel opening that exposes the first electrode.

[0011] In one embodiment of this disclosure, the other regions include a alignment pattern region located in the non-display area and adjacent to the pattern area to be formed. The functional layer group includes an alignment pattern, and the orthographic projection of the alignment pattern on the substrate is at least partially located within the orthographic projection of the alignment pattern region on the substrate.

[0012] In one embodiment of this disclosure, the other regions also include a support region, which is located around the alignment pattern region. The distance between the support region and the substrate is greater than the distance between the pattern to be formed region and the alignment pattern region and the substrate.

[0013] In one embodiment of this disclosure, the alignment pattern is disposed in the same layer and material as the first electrode.

[0014] In one embodiment of this disclosure, the functional layer group further includes a spacer layer located on the side of the pixel defining layer away from the substrate. The spacer layer includes a support portion, the area to be patterned is located on the side of the pixel defining layer away from the substrate, and the support area is located on the side of the support portion away from the substrate.

[0015] In one embodiment of this disclosure, the functional layer group has a first opening in the non-display area, the first opening at least passes through a portion of the pixel defining layer, the pattern area to be formed is located within the first opening, and the alignment pattern area is located on the surface of the pixel defining layer away from the substrate.

[0016] In one embodiment of this disclosure, the first opening includes a first opening segment penetrating the pixel defining layer, or a first opening segment penetrating the pixel defining layer and a second opening segment penetrating the second planarization layer, wherein the orthographic projection of the first opening segment on the substrate coincides with the orthographic projection of the second opening segment on the substrate.

[0017] In one embodiment of this disclosure, the functional layer group has a second opening in the non-display area. The second opening passes through at least a portion of the pixel defining layer. The pattern area to be formed and the alignment pattern area are both located within the second opening. The support area is located on the side of the pixel defining layer away from the substrate.

[0018] In one embodiment of this disclosure, the functional layer group further includes a source / drain metal layer, which is located between the first planarization layer and the substrate, and / or between the first planarization layer and the second planarization layer, and the alignment pattern is disposed in the same layer and with the same material as the source / drain metal layer.

[0019] In one embodiment of this disclosure, the functional layer group has a third opening in the non-display area. The third opening passes through at least a portion of the second planarization layer. The area to be patterned and the alignment pattern area are both located within the third opening. The third opening includes a first sub-opening area and a second sub-opening area. The alignment pattern is located in the first sub-opening area. The pixel defining layer covers the second sub-opening area and also covers the alignment pattern and the side of the second planarization layer away from the substrate. The alignment pattern area overlaps with the orthographic projection of the first sub-opening area on the pixel defining layer, and the area to be patterned overlaps with the orthographic projection of the second sub-opening area on the pixel defining layer.

[0020] In one embodiment of this disclosure, the non-display area includes an identification area, an alignment pattern and a pattern area to be formed constitute a pattern group to be identified, the pattern group to be identified is located within the identification area, and a support is disposed around the pattern group to be identified, the support being located outside or inside the identification area.

[0021] In one embodiment of this disclosure, when the support is located outside the recognition area, the distance between the support and the edge of the recognition area is less than 1 mm.

[0022] In one embodiment of this disclosure, the dimensions of the support portion along the first direction are not equal to the dimensions of the support portion along the second direction. Both the first and second directions are located on the surface of the substrate, and the second direction is perpendicular to the first direction.

[0023] In one embodiment of this disclosure, the dimension of the support portion along the first direction is 50μm to 100μm.

[0024] In one embodiment of this disclosure, the height difference between the support area and the area to be patterned is 1 μm to 2 μm.

[0025] In one embodiment of this disclosure, the support portion is provided with at least one first groove, the extension direction of the first groove being the same as the extension direction of the support portion.

[0026] In one embodiment of this disclosure, the support portion is a continuous and closed structure, and the outline shape of the orthographic projection of the support portion on the substrate is elliptical, circular, or polygonal.

[0027] In one embodiment of this disclosure, the support portion includes at least one set of support segments, and the set of support segments includes two support segments, which are arranged parallel to opposite sides of the identification area.

[0028] In one embodiment of this disclosure, the support portion includes a plurality of support blocks distributed along the contour of the identification area.

[0029] In one embodiment of this disclosure, the shape of the orthographic projection of the support block onto the substrate is rectangular, circular, or polygonal.

[0030] In one embodiment of this disclosure, the area to be patterned includes multiple areas to be patterned, which are arranged sequentially along a first direction. The alignment pattern includes at least one first alignment mark, multiple second alignment marks, and a third alignment mark. The at least one first alignment mark is disposed along the first direction and is located on the same straight line as the multiple areas to be patterned. The multiple second alignment marks are disposed along a second direction, which intersects with the first direction. The multiple second alignment marks are respectively located on the same straight line as the multiple areas to be patterned along the second direction. The third alignment mark is disposed at the intersection of the straight line where the first alignment mark is located and the straight line where the second alignment mark is located.

[0031] In one embodiment of this disclosure, the display panel includes a plurality of patterns to be identified, all of which are located in the display area.

[0032] In one embodiment of this disclosure, each patterned area is provided with a light-emitting functional layer on the side away from the substrate, and at least a portion of the other areas are at a greater distance from the substrate than the distance between the light-emitting functional layer and the substrate.

[0033] According to another aspect of this disclosure, a display device is provided, including a display panel provided in one aspect of this disclosure.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0036] Figure 1 is a planar schematic diagram of the distribution of the pattern group to be identified on the display panel according to an embodiment of the present disclosure.

[0037] Figure 2 is a magnified view of part A in Figure 1.

[0038] Figure 3 is a planar schematic diagram of the positional relationship between the pattern area to be formed and the corresponding pattern in the pattern group to be identified according to an embodiment of this disclosure.

[0039] Figure 4 is a cross-sectional schematic diagram of a case where a fine metal mask plate scrapes against a back plate according to an embodiment of this disclosure.

[0040] Figure 5 is a cross-sectional schematic diagram of another scenario involving the scraping of a fine metal mask plate against a back plate according to an embodiment of this disclosure.

[0041] Figure 6 is a planar schematic diagram of the fine metal mask plate and the back plate scraping against each other according to an embodiment of this disclosure.

[0042] Figure 7 is a cross-sectional schematic diagram of the display panel according to the embodiments of this disclosure when the support is located in the spacer layer and the support area is on the side of the support away from the substrate.

[0043] Figure 8 is a cross-sectional schematic diagram of the display panel according to the embodiments of this disclosure when the support portion is located in the pixel defining layer and the support area is on the side of the support portion away from the substrate.

[0044] Figure 9 is a cross-sectional schematic diagram of the display panel when the first groove is provided on the side of the support portion away from the substrate in Figure 7.

[0045] Figure 10 is a cross-sectional schematic diagram of the display panel when the first groove is provided on the side of the support portion away from the substrate in Figure 8.

[0046] Figure 11 is a plan view of a support portion surrounding a pattern group to be identified according to an embodiment of this disclosure.

[0047] Figure 12 is a plan view of another support portion surrounding the pattern group to be identified according to an embodiment of this disclosure.

[0048] Figure 13 is a plan view of a support part according to an embodiment of the present disclosure, which includes two support segments and the two support segments are arranged along a first direction.

[0049] Figure 14 is a plan view of a support part according to an embodiment of the present disclosure, which includes two support segments and the two support segments are arranged along a second direction.

[0050] Figure 15 is a planar schematic diagram of a support part according to an embodiment of the present disclosure, which includes multiple support blocks, and the support blocks are rectangular in shape.

[0051] Figure 16 is a planar schematic diagram of a support part according to an embodiment of the present disclosure, which includes multiple support blocks, and the support blocks are circular in shape.

[0052] Figure 17 is a cross-sectional schematic diagram of a display panel with a first opening and an alignment pattern disposed on the same layer as the first electrode according to an embodiment of the present disclosure.

[0053] Figure 18 is a cross-sectional schematic diagram of a display panel with a first opening and an alignment pattern disposed on the same layer as the second source electrode according to an embodiment of the present disclosure.

[0054] Figure 19 is a cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure, wherein a third opening is provided and an alignment pattern is located within the third opening.

[0055] Explanation of reference numerals in the attached diagram: 1-Fine metal mask, 2-Display panel, 201-Display area, 202-Non-display area, 2021- Identification area, 203-cofferdam, 2031-first cofferdam, 2032-second cofferdam, 20-substrate, 21-functional layer group, 211-pattern area to be formed, 2111-first pattern area to be formed, 2112-second pattern area to be formed, 2113-third pattern area to be formed, 2114-fourth pattern area to be formed, 2115-fifth pattern area to be formed, 212-alignment pattern area, 213-support area, 214-support portion, 2141-first groove, 2142-support segment, 2143-support block, 215-first opening, 2151-first opening segment, 2152-second opening segment, 216-second opening, 217-third opening, 2171-first sub-opening area, 2172-second sub-opening area, 22-buffer layer, 23-driving circuit layer, 231-thin film transistor, 2311-active layer 2312-Gate insulating layer, 2313-Gate, 2314-Interlayer insulating layer, 2315-Interlayer dielectric layer, 2316-First source, 2317-Drain, 2318-Guard layer, 2319-Second source, 232-Alignment pattern, 2321-First alignment mark, 2322-Second alignment mark, 2323-Third alignment mark, 24-Planarization layer group, 241-First planarization layer, 242-Second alignment layer Two planarization layers, 25-pixel defining layer, 251-pixel opening, 26-pixel layer, 261-first electrode, 262-light-emitting layer group, 2621-patterning layer, 2622-common layer, 263-second electrode, 265-light-emitting functional layer, 27-encapsulation layer, 271-first inorganic encapsulation layer, 272-organic encapsulation layer, 273-second inorganic encapsulation layer, 28-spacer layer, 281-spacer pillar, 29-backplate. Detailed Implementation

[0056] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0057] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0058] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0059] OLED displays are currently primarily fabricated by depositing the light-emitting layer (EL) on a backplane (BP) using a fine metal mask (FMM). To ensure that all luminescent material passes through the openings in the pattern to be formed on the FMM and lands at the corresponding luminescent unit position of the sub-pixel on the backplane after deposition, a pixel position accuracy test element group (PPA Teg) is needed to monitor the alignment accuracy of the deposition process. The PPA Teg is used to mark the difference between the actual and ideal deposition positions of the luminescent functional layer, which can be achieved by identifying the luminescent functional layer.

[0060] As shown in Figures 1 and 2, taking a rectangular display panel as an example, the non-display area 202 of the display panel 2 may include two first sub-non-display areas extending along a first direction and two second sub-non-display areas extending along a second direction. The second sub-non-display area located at the bottom of the display panel has a binding area. The non-display area 202 has multiple recognition areas 2021, each containing a pattern group to be recognized. These recognition areas can be placed within the two first sub-non-display areas, typically within the second sub-non-display area with the binding area. However, in some cases, they may also be placed within the second sub-non-display area. It should be noted that the first direction is the x-direction in Figure 1, and the second direction is the y-direction in Figure 1.

[0061] As shown in Figure 3, the pattern group to be identified includes a pattern area 211 to be formed. The pattern area 211 includes a first pattern area 2111, a second pattern area 2112, a third pattern area 2113, a fourth pattern area 2114, and a fifth pattern area 2115. The third pattern area 2113, the fourth pattern area 2114, the fifth pattern area 2115, the first pattern area 2111, and the second pattern area 2112 can be arranged sequentially along a first direction.

[0062] The pattern group to be identified also includes a alignment pattern 232, which includes at least one first alignment mark 2321, multiple second alignment marks 2322, and a third alignment mark 2323. The first alignment mark 2321 is arranged along a first direction and is located on the same straight line as multiple areas to be formed. The multiple second alignment marks 2322 are arranged along a second direction, which intersects with the first direction. The multiple second alignment marks 2322 are respectively located on the same straight line as multiple areas to be formed along the second direction. The third alignment mark 2323 is located at the intersection of the straight line where the first alignment mark 2321 is located and the straight line where the second alignment mark 2322 is located.

[0063] The alignment pattern 232 can be set to monitor the positional accuracy of various sub-pixel light-emitting layers in the non-display area 202. Multiple alignment marks can mark the ideal position of various areas to be formed. By monitoring the offset between the center of each light-emitting layer and each auxiliary layer and the center of the alignment mark, the overall offset of the fine metal mask can be estimated, thereby re-stretching the fine metal mask or compensating and correcting the evaporation process.

[0064] There is a problem of friction between the fine metal mask and the back plate. As shown in Figure 4, the display panel includes a back plate, which may include a substrate 20, a driving circuit layer 23, a planarization layer group 24, and a pixel defining layer 25. The driving circuit layer 23 is located on one side of the substrate 20, and the planarization layer group 24 is located on the side away from the substrate 20. The pixel defining layer 25 is located on the side of the planarization layer group 24 away from the substrate 20. When the pixel layer is deposited on the pixel defining layer 25, the light-emitting functional layer is formed on the pattern area to be formed on the pixel defining layer. The fine metal mask 1 is located on the side of the spacer pillar 281 of the spacer layer 28 away from the back plate. There is a step difference between the fine metal mask 1 and the pattern area to be formed. The fine metal mask 1 will fluctuate during the evaporation process (displacement in the direction perpendicular to the back plate and in the direction parallel to the back plate), causing friction between the fine metal mask 1 and the back plate, generating particulate foreign matter, which affects the recognition accuracy of the pixel position accuracy test element group 3.

[0065] As shown in Figure 5, to eliminate the step difference between the fine metal mask 1 and the back plate, a spacer layer 28 is provided in the area to be patterned. The light-emitting material layer used to form sub-pixels is formed on the spacer layer 28, so that the side of the fine metal mask 1 near the back plate is flush with the area to be patterned. However, since the fluctuation of the fine metal mask 1 still exists (displacement in the direction perpendicular to the back plate and in the direction parallel to the back plate), the fine metal mask 1 will still be in direct contact with the area to be patterned, and scratch defects will also occur, affecting the recognition accuracy of the pixel position accuracy test element group 3. The scratch defect situation can be seen in Figure 6, where particulate foreign objects are distributed on the back plate 29.

[0066] Based on this, the present disclosure provides a display panel. As shown in Figures 7 to 19, the display panel 2 has a display area 201 and a non-display area 202 located around the display area 201. The display panel 2 includes a substrate 20 and a functional layer group 21. The functional layer group 21 is disposed on one side of the substrate 20. The side of the functional layer group 21 away from the substrate 20 includes at least one pattern-to-be-patterned area 211 and other areas. At least one pattern-to-be-patterned area 211 is located in the non-display area, and the other areas are located around the pattern-to-be-patterned area 211. The distance between at least a portion of the other areas and the substrate 20 is greater than the distance between the pattern-to-be-patterned area 211 and the substrate 20.

[0067] The side of the functional layer group 21 away from the substrate 20 includes at least one patterned area 211 and other areas. The other areas are located outside the patterned area and at least a portion of the other areas are higher than the patterned area 211. The distance between the other areas and the substrate 20 is greater than the distance between the patterned area 211 and the substrate 20. This allows a step difference to be formed between the other areas and the patterned area 211. When the fine mask fluctuates, it will not scratch the patterned area 211, thus avoiding the formation of particulate foreign matter in the patterned area 211, improving the recognition accuracy of the testing device, and thereby improving the evaporation yield.

[0068] It should be noted that other areas refer to the areas of the display panel 2 other than the area 211 where the pattern is to be formed. This may include the area of ​​the non-display area 202 other than the area 211 where the pattern is to be formed, or it may include part of the display area 201.

[0069] The display panel involved in the embodiments of this disclosure will be described in detail below with reference to specific examples.

[0070] As shown in Figures 7 to 10, the display panel 2 includes a substrate 20 and a functional layer group 21 disposed on one side of the substrate 20. The display panel 2 has a display area 201 and a non-display area 202 located around the display area 201. The functional layer group 21 includes a driving circuit layer and a pixel layer. The driving circuit layer is disposed on one side of the substrate 20, and the pixel layer is disposed on the side of the driving circuit layer away from the substrate 20.

[0071] The functional layer group 21 includes a planarization layer group 24, which is disposed between the driving circuit layer and the pixel layer. The planarization layer group 24 may include a first planarization layer, which is disposed on the side of the driving circuit layer away from the substrate 20.

[0072] The driving circuit layer may include multiple thin-film transistors 231. The thin-film transistors 231 may be top-gate or bottom-gate type. Taking a top-gate type thin-film transistor 231 as an example, the thin-film transistor 231 may include an active layer 2311, a gate insulating layer 2312, a gate 2313, and source / drain metal layers, wherein:

[0073] The active layer 2311 is disposed on one side of the substrate 20. Its material can be polycrystalline silicon, amorphous silicon, etc., and the active layer 2311 may include a channel region and two doped regions of different doping types located on both sides of the channel region.

[0074] The gate insulating layer 2312 can cover the active layer 2311 and the substrate 20, and the material of the gate insulating layer 2312 is an insulating material such as silicon oxide.

[0075] The gate 2313 is disposed on the side of the gate insulating layer 2312 away from the substrate 20 and is directly opposite the active layer 2311. That is, the projection of the gate 2313 on the substrate 20 is located within the projection range of the active layer 2311 on the substrate 20. For example, the projection of the gate 2313 on the substrate 20 coincides with the projection of the channel region of the active layer 2311 on the substrate 20.

[0076] The thin-film transistor 231 further includes an interlayer insulating layer 2314, which covers the gate 2313 and the gate insulating layer 2312. The thin-film transistor 231 also includes an interlayer dielectric layer 2315, which is disposed on the side of the interlayer insulating layer 2314 away from the substrate 20. Both the interlayer insulating layer 2314 and the interlayer dielectric layer 2315 are insulating materials, but the materials of the interlayer insulating layer 2314 and the interlayer dielectric layer 2315 may be different.

[0077] The source / drain metal layer may include a first source / drain metal layer disposed on the surface of the interlayer dielectric layer 2315 away from the substrate 20. The first source / drain metal layer includes a first source 2316 and a drain 2317, which are connected to the active layer 2311. For example, the first source 2316 and the drain 2317 are respectively connected to two doped regions of the corresponding active layer 2311 through vias.

[0078] A protective layer 2318 is provided on the side of the first source electrode 2316 away from the substrate 20, and the protective layer 2318 covers the first source electrode 2316 and the drain electrode 2317. A first planarization layer 24 is provided on the side of the first source / drain metal layer away from the substrate 20. The first planarization layer 24 is provided on the side of the protective layer 2318 away from the substrate 20, covers the protective layer 2318, and the surface of the first planarization layer 24 away from the substrate 20 is planar.

[0079] The source / drain metal layer may further include a second source / drain metal layer, which includes a second source 2319. A second planarization layer 242 is provided on the side of the second source 2319 away from the substrate 20. The second planarization layer covers the second source 2319 and the first planarization layer 24. The second source 2319 is connected to the first source 2316 through a via.

[0080] It should be noted that a buffer layer 22 is usually provided between the substrate 20 and the driving circuit layer.

[0081] A pixel defining layer 25 and a pixel layer 26 can be disposed on the side of the driving backplate away from the substrate 20. The pixel defining layer 25 has multiple pixel openings 251, and the pixel layer 26 includes multiple sub-pixels, each disposed within one of the multiple pixel openings 251. The multiple sub-pixel array is distributed on the side of the driving backplate away from the substrate 20. Specific sub-pixels can be located on the side of the first planarization layer 24 or the second planarization layer away from the substrate 20. It should be noted that, depending on the emitted color, the sub-pixels can include red, green, and blue sub-pixels.

[0082] Each sub-pixel may include a first electrode 261, a light-emitting layer group 262, and a second electrode 263. The first electrode 261 is located on the surface of the driving backplate away from the substrate 20, the light-emitting layer group 262 is disposed on the surface of the first electrode 261 away from the substrate 20, and the second electrode 263 is disposed on the surface of the light-emitting layer group 262 away from the substrate 20. The pixel layer can be driven to emit light through the first electrode 261 and the second electrode 263 to display an image.

[0083] The first electrode 261 is connected to either the first source 2316 or the second source 2319. When the thin-film transistor 231 includes only the first source 2316, the first electrode 261 is connected to the first source 2316, and a pixel defining layer 25 covers the first electrode 261 and the first planarization layer 24. When the thin-film transistor 231 also includes the second source 2319, the first electrode 261 is connected to the second source 2319, and a pixel defining layer 25 covers the first electrode 261 and the fourth planarization layer.

[0084] The second electrode 263 can be used as a cathode, and the first electrode 261 can be used as an anode. The light-emitting layer group 262 can be driven to emit light by applying a signal to the first electrode 261. The specific light-emitting principle will not be described in detail here.

[0085] The light-emitting layer group 262 may include an electroluminescent organic light-emitting material. For example, the light-emitting layer group 262 may include a patterned layer 2621 and a common layer 2622 stacked on the first electrode 261. The patterned layer 2621 may include a first patterned portion and a second patterned portion. The first patterned portion is disposed on the side of the first electrode 261 away from the substrate 20, and the second patterned portion is disposed on the side of the pixel defining layer 25 away from the substrate 20. The orthographic projection of the common layer 2622 on the substrate 20 covers the orthographic projection of each first electrode 261 on the substrate 20, as well as the portion of the pixel defining layer 25 located between any two adjacent first electrodes 261.

[0086] The patterned layer 2621 may include an auxiliary layer and a light-emitting layer. The auxiliary layer typically includes a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. The common layer 2622 is typically a charge generation layer. Generally, a patterned area is set on a mask, and auxiliary layers and light-emitting layers of different color sub-pixels are formed using processes such as vapor deposition.

[0087] Furthermore, the display panel 2 of this disclosure may also include an encapsulation layer 27, which is disposed on the side of the pixel layer 26 away from the substrate 20, thereby covering the pixel layer 26 and preventing water and oxygen corrosion. The encapsulation layer 27 may be a single-layer or multi-layer structure, and the material of the encapsulation layer 27 may include organic or inorganic materials, without special limitations herein.

[0088] In this embodiment, the encapsulation layer 27 may include a first inorganic encapsulation layer 271, an organic encapsulation layer 272, and a second inorganic encapsulation layer 273. The first inorganic encapsulation layer 271 is disposed on the side of the pixel layer 26 away from the substrate 20, the organic encapsulation layer 272 is disposed on the side of the first inorganic encapsulation layer 271 away from the substrate 2020, and the second inorganic encapsulation layer 273 is disposed on the side of the organic encapsulation layer 272 away from the substrate 2020. The inorganic encapsulation layer 271 and the second inorganic encapsulation layer 273 can be formed by vapor deposition, and the organic encapsulation layer 272 can be formed by inkjet printing ink leveling.

[0089] Because of the flow of liquid organic encapsulation material, leakage is prone to occur. To prevent leakage, especially at the lower bezel, a dike has always been provided in the non-display area 202 away from the display area 201 to act as a barrier. The cross-sectional shape of the dike can be rectangular as shown in the figure, or it can be trapezoidal. The dike must have at least one side with a slope closer to the display area 201, which is not limited here.

[0090] In the non-display area 202, there are multiple cofferdams 203 that are sequentially moved away from the display area 201. The multiple cofferdams 203 may include a first cofferdam 2031 and a second cofferdam 2032. The first cofferdam 2031 is arranged around the display area 201; the second cofferdam 2032 is arranged around the first cofferdam 2031.

[0091] As shown in Figure 7, the pattern area 211 to be formed is located on the side of the pixel defining layer away from the substrate 20. The side of the functional layer group 21 away from the substrate 20 also includes other areas located around the pattern area 211 to be formed. The other areas include the alignment pattern area 212, which is located in the non-display area 202 and adjacent to the pattern area 211 to be formed. The alignment pattern area 212 is also located on the side of the pixel defining layer away from the substrate 20.

[0092] The alignment pattern region 212 has alignment openings, and each alignment mark of the alignment pattern 232 is disposed within the alignment opening. Referring to the figure, the second alignment mark 2322 and the third alignment mark 2323 are both located within the alignment pattern region 212. It is understood that the orthographic projection of the alignment pattern 232 onto the substrate 20 is at least partially located within the orthographic projection of the alignment pattern region 212 onto the substrate 20. The alignment pattern 232 can be disposed on the side of the second planarization layer away from the substrate 20, and the alignment pattern 232 can be disposed in the same layer and with the same material as the first electrode 261.

[0093] Other areas include a support region 213, which is located around the alignment pattern region 212. The support region 213 has a support portion 214 located in the spacer layer 28. The support portion 214 and the spacer pillar 281 are made of the same layer and material. The support region 213 is located on the side of the support portion 214 furthest from the substrate 20. The distance between the support region 213 and the substrate 20 is greater than the distance between the patterned region 211 and the substrate 20, and also greater than the distance between the alignment pattern region 212 and the substrate 20. When the fine mask contacts the spacer pillar 281, the opening in the patterned region will not scratch the patterned region.

[0094] As shown in Figure 8, the difference from Figure 7 is that the alignment pattern 232 is disposed on the same layer as the first source or the second source 2319. That is, the alignment pattern 232 can be disposed between the interlayer dielectric layer and the first planarization layer, or between the first planarization layer and the second planarization layer. A second opening 216 is provided in the non-display area 202. The second opening 216 penetrates the pixel defining layer and exposes the second planarization layer. The pattern area 211 to be formed and the alignment pattern area 212 are both located within the second opening 216. The remaining portion of the pixel defining layer in the non-display area 202 can serve as a support portion 214.

[0095] It is understood that both the patterned area 211 and the alignment patterned area 212 are located on the side of the second planarization layer away from the substrate 20, and the support area 213 is located on the side of the pixel defining layer away from the substrate 20. Therefore, the distance between the support area 213 and the substrate 20 is greater than the distance between the patterned area and the substrate 20. A step is formed between the support area 213 and the patterned area. When the fine mask contacts the spacer pillar 281, the opening of the patterned area will not scratch the patterned area.

[0096] As shown in Figures 9 and 10, the wider the support portion 214, the greater the support strength. In order to ensure the width of the support portion 214 and minimize the contact area between the support portion 214 and the fine mask plate, a first groove 2141 can be provided on the side of the support portion 214 away from the substrate 20, regardless of whether it is the display panel 2 in Figure 7 or the display panel 2 in Figure 8. The extending direction of the first groove 2141 is the same as the extending direction of the support portion 214. The number of first grooves 2141 on the support portion 214 can be single or multiple.

[0097] The pixel layer 26 located in the display area 201 typically includes multiple red subpixels, multiple green subpixels, and multiple blue subpixels. Blue subpixels may include a blue subpixel emitting layer, red subpixels may include a red subpixel auxiliary layer and a red subpixel emitting layer, and green subpixels may include a green subpixel auxiliary layer and a green subpixel emitting layer.

[0098] The pixel layer 26 of the display area 201 is usually formed by vapor deposition layer by layer on the driving circuit layer through a mask 1. When forming the pixel layer 26 on the driving circuit layer, the blue sub-pixel light-emitting layer is generally deposited first, then the red sub-pixel auxiliary layer is deposited, then the red sub-pixel light-emitting layer is deposited, then the green sub-pixel auxiliary layer is deposited, and then the green sub-pixel light-emitting layer is deposited, thus forming red sub-pixels, green sub-pixels and blue sub-pixels.

[0099] The red pixel auxiliary layer is located on the side of the red pixel emitting layer closest to the driving circuit layer, and it is used to conduct light when the red pixel emits light. The green pixel auxiliary layer is located on the side of the green pixel emitting layer closest to the driving backplane, and it is used to conduct light when the green pixel emits light. Due to the material of the blue pixel, no auxiliary pixel is needed to conduct light when the blue pixel emits light, so no auxiliary blue layer is required.

[0100] Since the red sub-pixel light-emitting layer, green sub-pixel light-emitting layer, blue sub-pixel light-emitting layer, red sub-pixel auxiliary layer, and green sub-pixel auxiliary layer are deposited in different evaporation chambers, it is usually necessary to monitor the evaporation accuracy of these layers. Therefore, a light-emitting functional layer 265 is typically formed in each area of ​​the non-display area 202 where a pattern is to be formed. The light-emitting functional layer 265 can be set in the same layer and with the same material as the patterning layer 2621.

[0101] A light-emitting functional pattern is defined on the side of the driving circuit layer away from the substrate 20 using a fine mask. The light-emitting functional pattern includes multiple light-emitting functional layers 265 spaced apart, and light-emitting layers and auxiliary layers of various sub-pixels are formed in the region of each light-emitting functional layer 265. A spacer layer 28 can be provided between the pixel layer and the pixel defining layer. The spacer layer 28 includes multiple spacer pillars 281, which are located around the pixel opening 251. The spacer pillars 281 are used to support the fine mask during evaporation.

[0102] The light-emitting functional layer 265 may include a first pattern to be formed, a second pattern to be formed, a third pattern to be formed, a fourth pattern to be formed, and a fifth pattern to be formed. The first pattern to be formed may be set in the same layer and with the same material as the red sub-pixel light-emitting layer. The second pattern to be formed may be set in the same layer and with the same material as the green sub-pixel light-emitting layer. The third pattern to be formed may be set in the same layer and with the same material as the blue sub-pixel light-emitting layer. The fourth pattern to be formed may be set in the same layer and with the same material as the red sub-pixel auxiliary layer. The fifth pattern to be formed may be set in the same layer and with the same material as the green sub-pixel auxiliary layer. Furthermore, the first pattern to be formed, the second pattern to be formed, the third pattern to be formed, the fourth pattern to be formed, and the fifth pattern to be formed are set to not overlap with each other.

[0103] As shown in Figures 11 to 16, the regions to be formed are configured in multiple ways, and these regions are arranged sequentially along the first direction. These regions are divided into auxiliary layer regions and light-emitting layer regions. The auxiliary layer regions include the regions to be formed in the red sub-pixel auxiliary layer, the green sub-pixel auxiliary layer, the red sub-pixel light-emitting layer, the green sub-pixel light-emitting layer, and the blue sub-pixel light-emitting layer.

[0104] A red subpixel auxiliary layer is formed in the pattern area to be formed in the red subpixel auxiliary layer, a green subpixel auxiliary layer is formed in the pattern area to be formed in the green subpixel auxiliary layer, a red subpixel emitting layer is formed in the pattern area to be formed in the red subpixel emitting layer, a green subpixel emitting layer is formed in the pattern area to be formed in the green subpixel emitting layer, and a blue subpixel emitting layer is formed in the pattern area to be formed in the blue subpixel emitting layer.

[0105] By monitoring the vapor deposition positions of the red sub-pixel light-emitting layer, green sub-pixel light-emitting layer, blue sub-pixel light-emitting layer, red sub-pixel auxiliary layer, and green sub-pixel auxiliary layer in the non-display area 202, the vapor deposition positions of the red sub-pixel light-emitting layer, green sub-pixel light-emitting layer, blue sub-pixel light-emitting layer, red sub-pixel auxiliary layer, and green sub-pixel auxiliary layer in the display area 201 can be determined.

[0106] Referring to Figure 6, the pattern region to be formed in the red sub-pixel auxiliary layer is the first pattern region to be formed 2111, the pattern region to be formed in the green sub-pixel auxiliary layer is the second pattern region to be formed 2112, the pattern region to be formed in the red sub-pixel emitting layer is the third pattern region to be formed 2113, the pattern region to be formed in the green sub-pixel emitting layer is the fourth pattern region to be formed 2114, and the pattern region to be formed in the blue sub-pixel emitting layer is the fifth pattern region to be formed 2115.

[0107] The alignment mark 234 includes at least one first alignment mark 2321 disposed along a first direction, a second alignment mark 2322 disposed along a second direction and corresponding one-to-one with the five graphic regions to be formed, and a third alignment mark 2323 aligned with the positions of the first alignment mark 2321 and the second alignment mark 2322. The first alignment mark 2321 is located between the fifth graphic region 2115 to be formed and the first graphic region 2111 to be formed. The five second alignment marks 2322 are respectively located on the same side of the first graphic region 2111, the second graphic region 2112, the third graphic region 2113, the fourth graphic region 2114, and the fifth graphic region 2115 along the second direction. The third alignment mark 2323 is located on the same straight line as the five second alignment marks 2322 along the second direction. The third alignment mark 2323 is located between the first alignment mark 2321 corresponding to the fifth graphic region 2115 and the first alignment mark 2321 corresponding to the first graphic region 2111.

[0108] The non-display area 202 includes an identification area 2021, an alignment pattern 232, and a light-emitting functional layer 265 of the pattern-forming area 211, forming a pattern group to be identified. This pattern group is located within the identification area 2021, and a support portion 214 surrounds it. The support portion 214 can be located outside or within the identification area 2021. Referring to Figures 1 and 2, to ensure monitoring accuracy, the display panel 2 includes multiple pattern groups to be identified, which are identified separately using a set of test elements. The distance between the edge of the pattern-forming area 211 and the edge of the display area 201 is less than 2 mm.

[0109] When the support portion 214 is within the recognition area 2021, in order to ensure the support effect while minimizing the impact on the recognition process, the dimensions of the support portion 214 along the first direction are not equal to the dimensions of the support portion 214 along the second direction. The first direction is parallel to the surface of the substrate 20, and the second direction is perpendicular to the surface of the substrate 20. The dimensions of the support portion 214 along the first direction are 50μm to 100μm.

[0110] When the support part 214 is located outside the recognition area 2021, the closer the support part 214 is to the recognition area 2021, the better the support effect. In order to ensure the support effect of the support part 214 on the recognition area 2021, the support part 214 should not be too far away from the recognition area 2021. Generally, the distance between the support part 214 and the edge of the recognition area 2021 is less than 1mm, which can be adjusted according to actual needs.

[0111] The dimensions of the support portion 214 along the first direction are not equal to the dimensions of the support portion 214 along the second direction. The dimension of the support portion 214 along the first direction is 50μm to 100μm. Both the first and second directions are located on the surface of the substrate 20, and the second direction is perpendicular to the first direction.

[0112] It should be emphasized that the distance between the support region 213 and the substrate 20 is greater than the distance between the patterned region 211 and the substrate 20. Understandably, the height difference between the support region 213 and the patterned region 211 is 1μm to 2μm to ensure that the support portion 214 provides protection and support.

[0113] As shown in Figures 11 and 12, the support portion 214 is a continuous and closed structure. The outline shape of the orthographic projection of the support portion 214 on the substrate 20 can be elliptical, circular, or rectangular, or it can be other polygons.

[0114] As shown in Figures 13 and 14, the shape of the support portion 214 can also be a non-closed, fully enclosed structure. The support portion 214 includes at least one set of support segments 2142. The set of support segments 2142 includes two support segments 2142. The two support segments 2142 are arranged parallel to the two opposite sides of the identification area 2021. The two support segments 2142 can be located on the two sides of the identification area 2021 extending along the first direction, or they can be located on the two sides of the identification area 2021 extending along the second direction.

[0115] As shown in Figures 15 and 16, the support portion 214 also includes multiple support blocks 2143 arranged along the contour of the recognition area 2021. The multiple support blocks 2143 form a support effect around the area to be patterned. The larger the area of ​​the support block 2143, the better the support effect. The support block 2143 is a cuboid, cylinder, or prism. The orthographic projection of the support block 2143 on the substrate 20 is rectangular, circular, or polygonal. When the support block 2143 is cuboid, its orthographic projection on the substrate 20 is a 30×30μm rectangle.

[0116] As shown in Figures 17 and 18, the difference from Figure 7 is that the display panel 2 does not have a support portion 214, and the non-display area 202 has a first opening 215. The first opening 215 passes through at least part of the pixel defining layer. The first opening 215 may include a first opening segment 2151 located in the pixel defining layer, or it may be a first opening segment 2151 located in the pixel defining layer and a second opening segment 2152 located in the second planarization layer. The orthographic projection of the first opening segment 2151 on the substrate 20 coincides with the orthographic projection of the second opening segment 2152 on the substrate 20.

[0117] The patterned area 211 is located within the first opening 215, with the bottom of the first opening 215 being the patterned area. Therefore, the patterned area is located on the side of the first or second planarization layer away from the substrate 20. The alignment patterned area 212 is disposed on the surface of the pixel defining layer away from the substrate 20. It is understood that the distance between the alignment patterned area 212 and the substrate 20 is greater than the distance between the patterned area and the substrate 20. A step is formed between the alignment patterned area 212 and the patterned area. When the fine mask contacts the spacer pillar 281, the opening of the patterned area will not scratch the patterned area.

[0118] In Figure 17, the alignment pattern 232 can be disposed on the side of the second planarization layer away from the substrate 20, and the alignment pattern 232 can be disposed in the same layer and with the same material as the first electrode 261. In Figure 18, the alignment pattern 232 is disposed in the same layer and with the same material as the second source electrode 2319, that is, the alignment pattern 232 is disposed between the first planarization layer and the second planarization layer. The alignment pattern 232 can also be disposed in the same layer and with the same material as the first source electrode, that is, the alignment pattern 232 can be disposed between the interlayer dielectric layer and the first planarization layer.

[0119] As shown in Figure 19, the difference from the previous figure is that the second planarization layer has a third opening 217. The third opening 217 passes through the second planarization layer, exposing the first planarization layer. The area of ​​the first planarization layer located in the third opening 217 includes a first sub-opening region 2171 and a second sub-opening region 2172. The alignment pattern 232 is disposed in the first sub-opening region 2171. The pixel defining layer covers the second sub-opening region 2172, and the pixel defining layer covers the second sub-opening region 2172, as well as the side of the second planarization layer away from the substrate 20. The alignment pattern region 212 overlaps with the orthographic projection of the first sub-opening region 2171 on the pixel defining layer, and the pattern-to-be-formed region 211 overlaps with the orthographic projection of the second sub-opening region 2172 on the pixel defining layer. It should be noted that the second sub-opening refers to the area within the first sub-opening region 2171 other than the first sub-opening region 2171 itself.

[0120] It should be noted that the aforementioned identification area 2021 can also be located on the side of the second cofferdam 2032 in the non-display area 202 that is away from the display area 201. It can be understood that the identification area 2021 can be located within the non-display area 202 as long as it is located there.

[0121] As shown in Figures 7 and 9, when the light-emitting functional layer 265 is located on the side of the pixel defining layer away from the substrate, the distance between the side of the light-emitting functional layer 265 away from the substrate and the substrate is less than the distance between the side of the support portion away from the substrate and the substrate. The distance between the side of the light-emitting functional layer 265 away from the substrate and the side of the second patterned portion away from the substrate is 0 mm, and the distance between the side of the light-emitting functional layer 265 away from the substrate and the side of the first patterned portion away from the substrate is 1 to 2 mm.

[0122] As shown in Figures 8 and 10, when the light-emitting functional layer 265 is located within the second opening, the light-emitting functional layer 265 can be located on the side of the second planarization layer away from the substrate. The distance between the side of the light-emitting functional layer 265 away from the substrate and the substrate is less than the distance between the side of the pixel defining layer away from the substrate and the substrate. The thickness of the pixel defining layer is between 1 and 2 mm. Therefore, the distance between the side of the light-emitting functional layer 265 away from the substrate and the side of the second patterned portion away from the substrate is -1 to -2 mm, and the distance between the side of the light-emitting functional layer 265 away from the substrate and the side of the first patterned portion away from the substrate is 0 mm.

[0123] As shown in Figures 17 and 18, when the light-emitting functional layer 265 is to be formed within the first opening, it can be located on the side of the protective layer away from the substrate, on the side of the first planarization layer away from the substrate, or on the side of the second planarization layer away from the substrate. The distance between the side of the light-emitting functional layer 265 away from the substrate and the substrate is less than the distance between the side of the pixel defining layer outside the first opening away from the substrate and the substrate. The thicknesses of the first planarization layer, the second planarization layer, and the pixel defining layer are between 1 and 2 mm. Therefore, the distance between the side of the light-emitting functional layer 265 away from the substrate and the side of the second patterned portion away from the substrate is -1 to -6 mm, and the distance between the side of the light-emitting functional layer 265 away from the substrate and the side of the first patterned portion away from the substrate is -1 to -4 mm.

[0124] As shown in Figure 19, when the light-emitting functional layer 265 is to be formed within the third opening, it is located on the side of the pixel defining layer away from the substrate. The pixel defining layer can be located on the side of the protective layer away from the substrate, the side of the first planarization layer away from the substrate, or the side of the second planarization layer away from the substrate. The distance between the side of the light-emitting functional layer 265 away from the substrate and the substrate is less than the distance between the side of the pixel defining layer outside the third opening away from the substrate and the substrate. The distance between the side of the light-emitting functional layer 265 away from the substrate and the side of the second patterned portion away from the substrate is -1 to -4 mm, and the distance between the side of the light-emitting functional layer 265 away from the substrate and the side of the first patterned portion away from the substrate is -2 to 0 mm.

[0125] This disclosure also provides a display device. This display device may include the display panel described in any of the embodiments of this disclosure above. The specific structure and beneficial effects of the display panel have been described in detail above, and therefore will not be repeated here.

[0126] It should be noted that, in addition to the display panel, the display device also includes other necessary components and parts, such as circuit boards, power cords, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here.

[0127] When the display panel has the structure shown in the figure, the display device can be a traditional electronic device, such as a mobile phone, computer, television and video recorder, or an emerging wearable device, such as virtual reality device and augmented reality device, which will not be listed here.

[0128] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A display panel having a display area and a non-display area located around the periphery of the display area, wherein, The display panel includes: Substrate; A functional layer group is disposed on one side of the substrate. The side of the functional layer group away from the substrate includes at least one pattern-forming area and other areas. The at least one pattern-forming area is located in the non-display area, and the other areas are located outside the pattern-forming area. At least a portion of the other areas are at a greater distance from the substrate than the distance between the pattern-forming area and the substrate.

2. The display panel according to claim 1, wherein, The functional layer group includes: A planarization layer group includes a first planarization layer and a second planarization layer, wherein the first planarization layer is disposed on one side of the substrate, and the second planarization layer is located on the side of the first planarization layer away from the substrate. The first electrode is disposed on the side of the planarization layer group away from the substrate. A pixel defining layer is disposed on the side of the first electrode away from the substrate, and the pixel defining layer has a pixel opening that exposes the first electrode.

3. The display panel according to claim 2, wherein, The other regions include alignment pattern regions located in the non-display area and adjacent to the pattern to be formed region. The functional layer group includes alignment patterns, and the orthographic projection of the alignment patterns on the substrate is at least partially located within the orthographic projection of the alignment pattern regions on the substrate.

4. The display panel according to claim 3, wherein, The other regions also include a support region located around the alignment pattern region. The distance between the support region and the substrate is greater than the distance between the pattern to be formed region and the alignment pattern region and the substrate.

5. The display panel according to claim 3, wherein, The alignment pattern is disposed in the same layer and material as the first electrode.

6. The display panel according to claim 3, wherein, The functional layer group further includes a spacer layer located on the side of the pixel defining layer away from the substrate. The spacer layer includes a support portion, the area to be patterned is located on the side of the pixel defining layer away from the substrate, and the support area is located on the side of the support portion away from the substrate.

7. The display panel according to claim 3, wherein, The functional layer group has a first opening in the non-display area, the first opening at least passes through a portion of the pixel defining layer, the pattern area to be formed is located in the first opening, and the alignment pattern area is located on the surface of the pixel defining layer away from the substrate.

8. The display panel according to claim 7, wherein, The first opening includes a first opening segment penetrating the pixel defining layer, or a first opening segment penetrating the pixel defining layer and a second opening segment penetrating the second planarization layer, wherein the orthographic projection of the first opening segment on the substrate coincides with the orthographic projection of the second opening segment on the substrate.

9. The display panel according to claim 4, wherein, The functional layer group has a second opening in the non-display area, the second opening at least partially passing through the pixel defining layer, the pattern area to be formed and the alignment pattern area are both located within the second opening, and the support area is located on the side of the pixel defining layer away from the substrate.

10. The display panel according to claim 9, wherein, The functional layer group further includes a source / drain metal layer, which is located between the first planarization layer and the substrate, and / or between the first planarization layer and the second planarization layer. The alignment pattern is disposed in the same layer and with the same material as the source / drain metal layer.

11. The display panel according to claim 3, wherein, The functional layer group has a third opening in the non-display area. The third opening passes through at least a portion of the second planarization layer. The area to be patterned and the alignment pattern area are both located within the third opening. The third opening includes a first sub-opening area and a second sub-opening area. The alignment pattern is disposed in the first sub-opening area. The pixel defining layer covers the second sub-opening area and covers the alignment pattern and the side of the second planarization layer away from the substrate. The alignment pattern area overlaps with the orthographic projection of the first sub-opening area on the pixel defining layer. The area to be patterned overlaps with the orthographic projection of the second sub-opening area on the pixel defining layer.

12. The display panel according to claim 6, wherein, The non-display area includes an identification area. The alignment pattern and the area to be formed form a pattern group to be identified. The pattern group to be identified is located within the identification area. The support portion is arranged around the pattern group to be identified. The support portion is located outside or inside the identification area.

13. The display panel according to claim 12, wherein, When the support is located outside the recognition area, the distance between the support and the edge of the recognition area is less than 1 mm.

14. The display panel according to claim 6, wherein, The dimensions of the support portion along the first direction are not equal to the dimensions of the support portion along the second direction. Both the first direction and the second direction are located on the surface of the substrate, and the second direction is perpendicular to the first direction.

15. The display panel according to claim 14, wherein, The dimension of the support portion along the first direction is 50μm to 100μm.

16. The display panel according to claim 6, wherein, The height difference between the support area and the area to be patterned is 1μm to 2μm.

17. The display panel according to claim 12, wherein, The support portion is provided with at least one first groove, and the extending direction of the first groove is the same as the extending direction of the support portion.

18. The display panel according to claim 12, wherein, The support portion is a continuous and closed structure, and the outline shape of the orthographic projection of the support portion on the substrate is elliptical, circular, or polygonal.

19. The display panel according to claim 12, wherein, The support portion includes at least one set of support segments, and the set of support segments includes two support segments, which are arranged parallel to the two opposite sides of the identification area.

20. The display panel according to claim 12, wherein, The support portion includes multiple support blocks, which are distributed along the contour of the identification area.

21. The display panel according to claim 20, wherein, The shape of the orthographic projection of the support block onto the substrate is rectangular, circular, or polygonal.

22. The display panel according to claim 3, wherein, The area to be patterned includes multiple areas to be patterned, which are arranged sequentially along a first direction. The alignment pattern includes: At least one first alignment mark is set along the first direction and is located on the same straight line as multiple regions of the graphic to be formed; Multiple second alignment marks are set along a second direction, which intersects with the first direction, and the multiple second alignment marks are respectively located on the same straight line along the second direction with multiple graphic regions to be formed; The third alignment mark is located at the intersection of the line containing the first alignment mark and the line containing the second alignment mark.

23. The display panel according to claim 12, wherein, The display panel includes multiple groups of patterns to be identified, and all of the multiple groups of patterns to be identified are located in the display area.

24. The display panel according to claim 1, wherein, Each of the areas to be patterned has a light-emitting functional layer on the side away from the substrate, and at least a portion of the other areas are at a greater distance from the substrate than the distance between the light-emitting functional layer and the substrate.

25. A display device, wherein, Includes the display panel as described in any one of claims 1 to 24.

Images